diff options
author | Sujith Manoharan <c_manoha@qualcomm.com> | 2012-09-09 23:50:03 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2012-09-11 15:31:37 -0400 |
commit | a4a2954ff49e72ce3fa1f78a156b2492a023c89d (patch) | |
tree | 677798b1d03f9e692443b2041ae0fd1f552a4d78 /drivers/net/wireless/ath | |
parent | aaa53ee97dab2b4c98ea2765e4f16af62d8694bb (diff) |
ath9k_hw: Add AR9565 HW support
Various parts of the code require AR9565 checks,
this patch adds them.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/ani.c | 2 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_eeprom.c | 10 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_mac.c | 2 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_phy.c | 10 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_phy.h | 14 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/eeprom.h | 2 | ||||
-rw-r--r-- | drivers/net/wireless/ath/ath9k/hw.c | 20 |
7 files changed, 31 insertions, 29 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c index ff007f500feb..e09ec40ce71a 100644 --- a/drivers/net/wireless/ath/ath9k/ani.c +++ b/drivers/net/wireless/ath/ath9k/ani.c | |||
@@ -237,7 +237,7 @@ static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel, | |||
237 | entry_cck->fir_step_level); | 237 | entry_cck->fir_step_level); |
238 | 238 | ||
239 | /* Skip MRC CCK for pre AR9003 families */ | 239 | /* Skip MRC CCK for pre AR9003 families */ |
240 | if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah)) | 240 | if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) |
241 | return; | 241 | return; |
242 | 242 | ||
243 | if (aniState->mrcCCK != entry_cck->mrc_cck_on) | 243 | if (aniState->mrcCCK != entry_cck->mrc_cck_on) |
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c index e9466f0291d3..185c990353d2 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c | |||
@@ -3520,7 +3520,7 @@ static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz) | |||
3520 | 3520 | ||
3521 | if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah)) | 3521 | if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah)) |
3522 | REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias); | 3522 | REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias); |
3523 | else if (AR_SREV_9462(ah) || AR_SREV_9550(ah)) | 3523 | else if (AR_SREV_9462(ah) || AR_SREV_9550(ah) || AR_SREV_9565(ah)) |
3524 | REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); | 3524 | REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); |
3525 | else { | 3525 | else { |
3526 | REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); | 3526 | REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); |
@@ -3568,7 +3568,7 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) | |||
3568 | 3568 | ||
3569 | u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz); | 3569 | u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz); |
3570 | 3570 | ||
3571 | if (AR_SREV_9462(ah)) { | 3571 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { |
3572 | REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, | 3572 | REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, |
3573 | AR_SWITCH_TABLE_COM_AR9462_ALL, value); | 3573 | AR_SWITCH_TABLE_COM_AR9462_ALL, value); |
3574 | } else if (AR_SREV_9550(ah)) { | 3574 | } else if (AR_SREV_9550(ah)) { |
@@ -3612,7 +3612,7 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) | |||
3612 | } | 3612 | } |
3613 | } | 3613 | } |
3614 | 3614 | ||
3615 | if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { | 3615 | if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { |
3616 | value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1); | 3616 | value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1); |
3617 | /* | 3617 | /* |
3618 | * main_lnaconf, alt_lnaconf, main_tb, alt_tb | 3618 | * main_lnaconf, alt_lnaconf, main_tb, alt_tb |
@@ -3843,7 +3843,7 @@ void ar9003_hw_internal_regulator_apply(struct ath_hw *ah) | |||
3843 | REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); | 3843 | REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); |
3844 | if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) | 3844 | if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) |
3845 | return; | 3845 | return; |
3846 | } else if (AR_SREV_9462(ah)) { | 3846 | } else if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { |
3847 | reg_val = le32_to_cpu(pBase->swreg); | 3847 | reg_val = le32_to_cpu(pBase->swreg); |
3848 | REG_WRITE(ah, AR_PHY_PMU1, reg_val); | 3848 | REG_WRITE(ah, AR_PHY_PMU1, reg_val); |
3849 | } else { | 3849 | } else { |
@@ -3874,7 +3874,7 @@ void ar9003_hw_internal_regulator_apply(struct ath_hw *ah) | |||
3874 | while (!REG_READ_FIELD(ah, AR_PHY_PMU2, | 3874 | while (!REG_READ_FIELD(ah, AR_PHY_PMU2, |
3875 | AR_PHY_PMU2_PGM)) | 3875 | AR_PHY_PMU2_PGM)) |
3876 | udelay(10); | 3876 | udelay(10); |
3877 | } else if (AR_SREV_9462(ah)) | 3877 | } else if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) |
3878 | REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1); | 3878 | REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1); |
3879 | else { | 3879 | else { |
3880 | reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) | | 3880 | reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) | |
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c index 5d55724ca4fe..d5b2e0ecc21c 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c | |||
@@ -31,7 +31,7 @@ ar9003_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i) | |||
31 | u32 val, ctl12, ctl17; | 31 | u32 val, ctl12, ctl17; |
32 | u8 desc_len; | 32 | u8 desc_len; |
33 | 33 | ||
34 | desc_len = (AR_SREV_9462(ah) ? 0x18 : 0x17); | 34 | desc_len = ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x18 : 0x17); |
35 | 35 | ||
36 | val = (ATHEROS_VENDOR_ID << AR_DescId_S) | | 36 | val = (ATHEROS_VENDOR_ID << AR_DescId_S) | |
37 | (1 << AR_TxRxDesc_S) | | 37 | (1 << AR_TxRxDesc_S) | |
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c index c3ebf8728d43..78665b29296d 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c | |||
@@ -88,7 +88,7 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) | |||
88 | channelSel = (freq * 4) / div; | 88 | channelSel = (freq * 4) / div; |
89 | chan_frac = (((freq * 4) % div) * 0x20000) / div; | 89 | chan_frac = (((freq * 4) % div) * 0x20000) / div; |
90 | channelSel = (channelSel << 17) | chan_frac; | 90 | channelSel = (channelSel << 17) | chan_frac; |
91 | } else if (AR_SREV_9485(ah)) { | 91 | } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { |
92 | u32 chan_frac; | 92 | u32 chan_frac; |
93 | 93 | ||
94 | /* | 94 | /* |
@@ -736,7 +736,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah, | |||
736 | if (chan->channel == 2484) | 736 | if (chan->channel == 2484) |
737 | ar9003_hw_prog_ini(ah, &ah->ini_japan2484, 1); | 737 | ar9003_hw_prog_ini(ah, &ah->ini_japan2484, 1); |
738 | 738 | ||
739 | if (AR_SREV_9462(ah)) | 739 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) |
740 | REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE, | 740 | REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE, |
741 | AR_GLB_SWREG_DISCONT_EN_BT_WLAN); | 741 | AR_GLB_SWREG_DISCONT_EN_BT_WLAN); |
742 | 742 | ||
@@ -746,9 +746,9 @@ static int ar9003_hw_process_ini(struct ath_hw *ah, | |||
746 | ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); | 746 | ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); |
747 | ath9k_hw_apply_txpower(ah, chan, false); | 747 | ath9k_hw_apply_txpower(ah, chan, false); |
748 | 748 | ||
749 | if (AR_SREV_9462(ah)) { | 749 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { |
750 | if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0, | 750 | if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0, |
751 | AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL)) | 751 | AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL)) |
752 | ah->enabled_cals |= TX_IQ_CAL; | 752 | ah->enabled_cals |= TX_IQ_CAL; |
753 | else | 753 | else |
754 | ah->enabled_cals &= ~TX_IQ_CAL; | 754 | ah->enabled_cals &= ~TX_IQ_CAL; |
@@ -1111,7 +1111,7 @@ static void ar9003_hw_set_nf_limits(struct ath_hw *ah) | |||
1111 | if (AR_SREV_9330(ah)) | 1111 | if (AR_SREV_9330(ah)) |
1112 | ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ; | 1112 | ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ; |
1113 | 1113 | ||
1114 | if (AR_SREV_9462(ah)) { | 1114 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { |
1115 | ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ; | 1115 | ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ; |
1116 | ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ; | 1116 | ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ; |
1117 | ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ; | 1117 | ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ; |
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h index e8bfb4125e86..f092f8cf6c6c 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h | |||
@@ -636,8 +636,8 @@ | |||
636 | #define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G_S 1 | 636 | #define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G_S 1 |
637 | 637 | ||
638 | #define AR_PHY_65NM_CH0_SYNTH4 0x1608c | 638 | #define AR_PHY_65NM_CH0_SYNTH4 0x1608c |
639 | #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT (AR_SREV_9462(ah) ? 0x00000001 : 0x00000002) | 639 | #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00000001 : 0x00000002) |
640 | #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S (AR_SREV_9462(ah) ? 0 : 1) | 640 | #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0 : 1) |
641 | #define AR_PHY_65NM_CH0_SYNTH7 0x16098 | 641 | #define AR_PHY_65NM_CH0_SYNTH7 0x16098 |
642 | #define AR_PHY_65NM_CH0_BIAS1 0x160c0 | 642 | #define AR_PHY_65NM_CH0_BIAS1 0x160c0 |
643 | #define AR_PHY_65NM_CH0_BIAS2 0x160c4 | 643 | #define AR_PHY_65NM_CH0_BIAS2 0x160c4 |
@@ -647,7 +647,7 @@ | |||
647 | #define AR_PHY_65NM_CH2_RXTX4 0x1690c | 647 | #define AR_PHY_65NM_CH2_RXTX4 0x1690c |
648 | 648 | ||
649 | #define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \ | 649 | #define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \ |
650 | ((AR_SREV_9462(ah) ? 0x1628c : 0x16280))) | 650 | (((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x1628c : 0x16280))) |
651 | #define AR_CH0_TOP_XPABIASLVL (AR_SREV_9550(ah) ? 0x3c0 : 0x300) | 651 | #define AR_CH0_TOP_XPABIASLVL (AR_SREV_9550(ah) ? 0x3c0 : 0x300) |
652 | #define AR_CH0_TOP_XPABIASLVL_S (AR_SREV_9550(ah) ? 6 : 8) | 652 | #define AR_CH0_TOP_XPABIASLVL_S (AR_SREV_9550(ah) ? 6 : 8) |
653 | 653 | ||
@@ -675,7 +675,7 @@ | |||
675 | #define AR_SWITCH_TABLE_ALL_S (0) | 675 | #define AR_SWITCH_TABLE_ALL_S (0) |
676 | 676 | ||
677 | #define AR_PHY_65NM_CH0_THERM (AR_SREV_9300(ah) ? 0x16290 :\ | 677 | #define AR_PHY_65NM_CH0_THERM (AR_SREV_9300(ah) ? 0x16290 :\ |
678 | (AR_SREV_9462(ah) ? 0x16294 : 0x1628c)) | 678 | ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16294 : 0x1628c)) |
679 | 679 | ||
680 | #define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000 | 680 | #define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000 |
681 | #define AR_PHY_65NM_CH0_THERM_LOCAL_S 31 | 681 | #define AR_PHY_65NM_CH0_THERM_LOCAL_S 31 |
@@ -697,17 +697,17 @@ | |||
697 | #define AR_CH0_TOP2_XPABIASLVL_S 12 | 697 | #define AR_CH0_TOP2_XPABIASLVL_S 12 |
698 | 698 | ||
699 | #define AR_CH0_XTAL (AR_SREV_9300(ah) ? 0x16294 : \ | 699 | #define AR_CH0_XTAL (AR_SREV_9300(ah) ? 0x16294 : \ |
700 | (AR_SREV_9462(ah) ? 0x16298 : 0x16290)) | 700 | ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16298 : 0x16290)) |
701 | #define AR_CH0_XTAL_CAPINDAC 0x7f000000 | 701 | #define AR_CH0_XTAL_CAPINDAC 0x7f000000 |
702 | #define AR_CH0_XTAL_CAPINDAC_S 24 | 702 | #define AR_CH0_XTAL_CAPINDAC_S 24 |
703 | #define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000 | 703 | #define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000 |
704 | #define AR_CH0_XTAL_CAPOUTDAC_S 17 | 704 | #define AR_CH0_XTAL_CAPOUTDAC_S 17 |
705 | 705 | ||
706 | #define AR_PHY_PMU1 (AR_SREV_9462(ah) ? 0x16340 : 0x16c40) | 706 | #define AR_PHY_PMU1 ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16340 : 0x16c40) |
707 | #define AR_PHY_PMU1_PWD 0x1 | 707 | #define AR_PHY_PMU1_PWD 0x1 |
708 | #define AR_PHY_PMU1_PWD_S 0 | 708 | #define AR_PHY_PMU1_PWD_S 0 |
709 | 709 | ||
710 | #define AR_PHY_PMU2 (AR_SREV_9462(ah) ? 0x16344 : 0x16c44) | 710 | #define AR_PHY_PMU2 ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16344 : 0x16c44) |
711 | #define AR_PHY_PMU2_PGM 0x00200000 | 711 | #define AR_PHY_PMU2_PGM 0x00200000 |
712 | #define AR_PHY_PMU2_PGM_S 21 | 712 | #define AR_PHY_PMU2_PGM_S 21 |
713 | 713 | ||
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.h b/drivers/net/wireless/ath/ath9k/eeprom.h index 484b31305906..7e1da18d09df 100644 --- a/drivers/net/wireless/ath/ath9k/eeprom.h +++ b/drivers/net/wireless/ath/ath9k/eeprom.h | |||
@@ -108,7 +108,7 @@ | |||
108 | #define EEP_RFSILENT_ENABLED_S 0 | 108 | #define EEP_RFSILENT_ENABLED_S 0 |
109 | #define EEP_RFSILENT_POLARITY 0x0002 | 109 | #define EEP_RFSILENT_POLARITY 0x0002 |
110 | #define EEP_RFSILENT_POLARITY_S 1 | 110 | #define EEP_RFSILENT_POLARITY_S 1 |
111 | #define EEP_RFSILENT_GPIO_SEL (AR_SREV_9462(ah) ? 0x00fc : 0x001c) | 111 | #define EEP_RFSILENT_GPIO_SEL ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00fc : 0x001c) |
112 | #define EEP_RFSILENT_GPIO_SEL_S 2 | 112 | #define EEP_RFSILENT_GPIO_SEL_S 2 |
113 | 113 | ||
114 | #define AR5416_OPFLAGS_11A 0x01 | 114 | #define AR5416_OPFLAGS_11A 0x01 |
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c index 36386265b8ab..6539d2acb5e8 100644 --- a/drivers/net/wireless/ath/ath9k/hw.c +++ b/drivers/net/wireless/ath/ath9k/hw.c | |||
@@ -602,6 +602,11 @@ static int __ath9k_hw_init(struct ath_hw *ah) | |||
602 | if (AR_SREV_9462(ah)) | 602 | if (AR_SREV_9462(ah)) |
603 | ah->WARegVal &= ~AR_WA_D3_L1_DISABLE; | 603 | ah->WARegVal &= ~AR_WA_D3_L1_DISABLE; |
604 | 604 | ||
605 | if (AR_SREV_9565(ah)) { | ||
606 | ah->WARegVal |= AR_WA_BIT22; | ||
607 | REG_WRITE(ah, AR_WA, ah->WARegVal); | ||
608 | } | ||
609 | |||
605 | ath9k_hw_init_defaults(ah); | 610 | ath9k_hw_init_defaults(ah); |
606 | ath9k_hw_init_config(ah); | 611 | ath9k_hw_init_config(ah); |
607 | 612 | ||
@@ -802,8 +807,7 @@ static void ath9k_hw_init_pll(struct ath_hw *ah, | |||
802 | { | 807 | { |
803 | u32 pll; | 808 | u32 pll; |
804 | 809 | ||
805 | if (AR_SREV_9485(ah)) { | 810 | if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { |
806 | |||
807 | /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ | 811 | /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ |
808 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | 812 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, |
809 | AR_CH0_BB_DPLL2_PLL_PWD, 0x1); | 813 | AR_CH0_BB_DPLL2_PLL_PWD, 0x1); |
@@ -2036,7 +2040,7 @@ static void ath9k_set_power_sleep(struct ath_hw *ah) | |||
2036 | { | 2040 | { |
2037 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); | 2041 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
2038 | 2042 | ||
2039 | if (AR_SREV_9462(ah)) { | 2043 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { |
2040 | REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); | 2044 | REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); |
2041 | REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); | 2045 | REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); |
2042 | REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); | 2046 | REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); |
@@ -2491,7 +2495,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah) | |||
2491 | 2495 | ||
2492 | if (AR_SREV_9300_20_OR_LATER(ah)) { | 2496 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
2493 | pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; | 2497 | pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; |
2494 | if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah)) | 2498 | if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah)) |
2495 | pCap->hw_caps |= ATH9K_HW_CAP_LDPC; | 2499 | pCap->hw_caps |= ATH9K_HW_CAP_LDPC; |
2496 | 2500 | ||
2497 | pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; | 2501 | pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; |
@@ -2574,14 +2578,12 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah) | |||
2574 | ah->enabled_cals |= TX_IQ_ON_AGC_CAL; | 2578 | ah->enabled_cals |= TX_IQ_ON_AGC_CAL; |
2575 | } | 2579 | } |
2576 | 2580 | ||
2577 | if (AR_SREV_9462(ah)) { | 2581 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { |
2578 | |||
2579 | if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) | 2582 | if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) |
2580 | pCap->hw_caps |= ATH9K_HW_CAP_MCI; | 2583 | pCap->hw_caps |= ATH9K_HW_CAP_MCI; |
2581 | 2584 | ||
2582 | if (AR_SREV_9462_20(ah)) | 2585 | if (AR_SREV_9462_20(ah)) |
2583 | pCap->hw_caps |= ATH9K_HW_CAP_RTT; | 2586 | pCap->hw_caps |= ATH9K_HW_CAP_RTT; |
2584 | |||
2585 | } | 2587 | } |
2586 | 2588 | ||
2587 | 2589 | ||
@@ -2747,7 +2749,7 @@ void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) | |||
2747 | 2749 | ||
2748 | ENABLE_REGWRITE_BUFFER(ah); | 2750 | ENABLE_REGWRITE_BUFFER(ah); |
2749 | 2751 | ||
2750 | if (AR_SREV_9462(ah)) | 2752 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) |
2751 | bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; | 2753 | bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; |
2752 | 2754 | ||
2753 | REG_WRITE(ah, AR_RX_FILTER, bits); | 2755 | REG_WRITE(ah, AR_RX_FILTER, bits); |
@@ -3044,7 +3046,7 @@ void ath9k_hw_gen_timer_start(struct ath_hw *ah, | |||
3044 | REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, | 3046 | REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, |
3045 | gen_tmr_configuration[timer->index].mode_mask); | 3047 | gen_tmr_configuration[timer->index].mode_mask); |
3046 | 3048 | ||
3047 | if (AR_SREV_9462(ah)) { | 3049 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { |
3048 | /* | 3050 | /* |
3049 | * Starting from AR9462, each generic timer can select which tsf | 3051 | * Starting from AR9462, each generic timer can select which tsf |
3050 | * to use. But we still follow the old rule, 0 - 7 use tsf and | 3052 | * to use. But we still follow the old rule, 0 - 7 use tsf and |