ath9k_hw: fix and clean up PHY activation delay

The delay calculation is the same for all chips, however some parts of the
code missed the extra delay factor for half/quarter.
Clean up the code and move the delay calculation to a common place.

Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

1 files changed, 2 insertions, 18 deletions

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index 4c8d0d770945..a1c0879a5d4e 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -526,22 +526,10 @@ static void ar9003_hw_init_bb(struct ath_hw *ah,
          * Value is in 100ns increments.
          */
         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
-        if (IS_CHAN_B(chan))
-                synthDelay = (4 * synthDelay) / 22;
-        else
-                synthDelay /= 10;
 
         /* Activate the PHY (includes baseband activate + synthesizer on) */
         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
-
-        /*
-         * There is an issue if the AP starts the calibration before
-         * the base band timeout completes.  This could result in the
-         * rx_clear false triggering.  As a workaround we add delay an
-         * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
-         * does not happen.
-         */
-        udelay(synthDelay + BASE_ACTIVATE_DELAY);
+        ath9k_hw_synth_delay(ah, chan, synthDelay);
 }
 
 static void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
@@ -801,12 +789,8 @@ static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
 {
         u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
-        if (IS_CHAN_B(ah->curchan))
-                synthDelay = (4 * synthDelay) / 22;
-        else
-                synthDelay /= 10;
 
-        udelay(synthDelay + BASE_ACTIVATE_DELAY);
+        ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
 
         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
 }