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authorDavid S. Miller <davem@davemloft.net>2012-12-01 11:27:31 -0500
committerDavid S. Miller <davem@davemloft.net>2012-12-01 11:27:31 -0500
commita20da984fb5ddedb9e8e699c04e10fe0ca609440 (patch)
tree3b1e17c43777a3ecd488e89859cb5be201729494 /drivers/net/ethernet
parentce43b03e8889475817d427b1f3724c7e294b76eb (diff)
parented83da12ee742da8cefa784def3af64e4e195462 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next
Jeff Kirsher says: ==================== This series contains updates to ixgbe, igb and e1000e. Majority of the changes are against igb. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet')
-rw-r--r--drivers/net/ethernet/intel/e1000e/80003es2lan.c66
-rw-r--r--drivers/net/ethernet/intel/e1000e/82571.c115
-rw-r--r--drivers/net/ethernet/intel/e1000e/defines.h27
-rw-r--r--drivers/net/ethernet/intel/e1000e/e1000.h17
-rw-r--r--drivers/net/ethernet/intel/e1000e/ethtool.c69
-rw-r--r--drivers/net/ethernet/intel/e1000e/hw.h6
-rw-r--r--drivers/net/ethernet/intel/e1000e/ich8lan.c243
-rw-r--r--drivers/net/ethernet/intel/e1000e/mac.c135
-rw-r--r--drivers/net/ethernet/intel/e1000e/manage.c9
-rw-r--r--drivers/net/ethernet/intel/e1000e/netdev.c313
-rw-r--r--drivers/net/ethernet/intel/e1000e/nvm.c15
-rw-r--r--drivers/net/ethernet/intel/e1000e/param.c50
-rw-r--r--drivers/net/ethernet/intel/e1000e/phy.c141
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_82575.c49
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_defines.h7
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_i210.c275
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_i210.h6
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_mac.c124
-rw-r--r--drivers/net/ethernet/intel/igb/e1000_nvm.c28
-rw-r--r--drivers/net/ethernet/intel/igb/igb.h2
-rw-r--r--drivers/net/ethernet/intel/igb/igb_ethtool.c14
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c83
-rw-r--r--drivers/net/ethernet/intel/ixgbe/ixgbe_main.c13
23 files changed, 823 insertions, 984 deletions
diff --git a/drivers/net/ethernet/intel/e1000e/80003es2lan.c b/drivers/net/ethernet/intel/e1000e/80003es2lan.c
index 4dd18a1f45d2..e73c2c355993 100644
--- a/drivers/net/ethernet/intel/e1000e/80003es2lan.c
+++ b/drivers/net/ethernet/intel/e1000e/80003es2lan.c
@@ -26,8 +26,7 @@
26 26
27*******************************************************************************/ 27*******************************************************************************/
28 28
29/* 29/* 80003ES2LAN Gigabit Ethernet Controller (Copper)
30 * 80003ES2LAN Gigabit Ethernet Controller (Copper)
31 * 80003ES2LAN Gigabit Ethernet Controller (Serdes) 30 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
32 */ 31 */
33 32
@@ -80,7 +79,8 @@
80 1 = 50-80M 79 1 = 50-80M
81 2 = 80-110M 80 2 = 80-110M
82 3 = 110-140M 81 3 = 110-140M
83 4 = >140M */ 82 4 = >140M
83 */
84 84
85/* Kumeran Mode Control Register (Page 193, Register 16) */ 85/* Kumeran Mode Control Register (Page 193, Register 16) */
86#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 86#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
@@ -95,8 +95,7 @@
95/* In-Band Control Register (Page 194, Register 18) */ 95/* In-Band Control Register (Page 194, Register 18) */
96#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */ 96#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */
97 97
98/* 98/* A table for the GG82563 cable length where the range is defined
99 * A table for the GG82563 cable length where the range is defined
100 * with a lower bound at "index" and the upper bound at 99 * with a lower bound at "index" and the upper bound at
101 * "index + 5". 100 * "index + 5".
102 */ 101 */
@@ -183,8 +182,7 @@ static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
183 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 182 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
184 E1000_EECD_SIZE_EX_SHIFT); 183 E1000_EECD_SIZE_EX_SHIFT);
185 184
186 /* 185 /* Added to a constant, "size" becomes the left-shift value
187 * Added to a constant, "size" becomes the left-shift value
188 * for setting word_size. 186 * for setting word_size.
189 */ 187 */
190 size += NVM_WORD_SIZE_BASE_SHIFT; 188 size += NVM_WORD_SIZE_BASE_SHIFT;
@@ -375,8 +373,7 @@ static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
375 if (!(swfw_sync & (fwmask | swmask))) 373 if (!(swfw_sync & (fwmask | swmask)))
376 break; 374 break;
377 375
378 /* 376 /* Firmware currently using resource (fwmask)
379 * Firmware currently using resource (fwmask)
380 * or other software thread using resource (swmask) 377 * or other software thread using resource (swmask)
381 */ 378 */
382 e1000e_put_hw_semaphore(hw); 379 e1000e_put_hw_semaphore(hw);
@@ -442,8 +439,7 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
442 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 439 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
443 page_select = GG82563_PHY_PAGE_SELECT; 440 page_select = GG82563_PHY_PAGE_SELECT;
444 } else { 441 } else {
445 /* 442 /* Use Alternative Page Select register to access
446 * Use Alternative Page Select register to access
447 * registers 30 and 31 443 * registers 30 and 31
448 */ 444 */
449 page_select = GG82563_PHY_PAGE_SELECT_ALT; 445 page_select = GG82563_PHY_PAGE_SELECT_ALT;
@@ -457,8 +453,7 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
457 } 453 }
458 454
459 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) { 455 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
460 /* 456 /* The "ready" bit in the MDIC register may be incorrectly set
461 * The "ready" bit in the MDIC register may be incorrectly set
462 * before the device has completed the "Page Select" MDI 457 * before the device has completed the "Page Select" MDI
463 * transaction. So we wait 200us after each MDI command... 458 * transaction. So we wait 200us after each MDI command...
464 */ 459 */
@@ -513,8 +508,7 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
513 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 508 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
514 page_select = GG82563_PHY_PAGE_SELECT; 509 page_select = GG82563_PHY_PAGE_SELECT;
515 } else { 510 } else {
516 /* 511 /* Use Alternative Page Select register to access
517 * Use Alternative Page Select register to access
518 * registers 30 and 31 512 * registers 30 and 31
519 */ 513 */
520 page_select = GG82563_PHY_PAGE_SELECT_ALT; 514 page_select = GG82563_PHY_PAGE_SELECT_ALT;
@@ -528,8 +522,7 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
528 } 522 }
529 523
530 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) { 524 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
531 /* 525 /* The "ready" bit in the MDIC register may be incorrectly set
532 * The "ready" bit in the MDIC register may be incorrectly set
533 * before the device has completed the "Page Select" MDI 526 * before the device has completed the "Page Select" MDI
534 * transaction. So we wait 200us after each MDI command... 527 * transaction. So we wait 200us after each MDI command...
535 */ 528 */
@@ -618,8 +611,7 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
618 u16 phy_data; 611 u16 phy_data;
619 bool link; 612 bool link;
620 613
621 /* 614 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
622 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
623 * forced whenever speed and duplex are forced. 615 * forced whenever speed and duplex are forced.
624 */ 616 */
625 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 617 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
@@ -657,8 +649,7 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
657 return ret_val; 649 return ret_val;
658 650
659 if (!link) { 651 if (!link) {
660 /* 652 /* We didn't get link.
661 * We didn't get link.
662 * Reset the DSP and cross our fingers. 653 * Reset the DSP and cross our fingers.
663 */ 654 */
664 ret_val = e1000e_phy_reset_dsp(hw); 655 ret_val = e1000e_phy_reset_dsp(hw);
@@ -677,8 +668,7 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
677 if (ret_val) 668 if (ret_val)
678 return ret_val; 669 return ret_val;
679 670
680 /* 671 /* Resetting the phy means we need to verify the TX_CLK corresponds
681 * Resetting the phy means we need to verify the TX_CLK corresponds
682 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. 672 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
683 */ 673 */
684 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 674 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
@@ -687,8 +677,7 @@ static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
687 else 677 else
688 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; 678 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
689 679
690 /* 680 /* In addition, we must re-enable CRS on Tx for both half and full
691 * In addition, we must re-enable CRS on Tx for both half and full
692 * duplex. 681 * duplex.
693 */ 682 */
694 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 683 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
@@ -766,8 +755,7 @@ static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
766 s32 ret_val; 755 s32 ret_val;
767 u16 kum_reg_data; 756 u16 kum_reg_data;
768 757
769 /* 758 /* Prevent the PCI-E bus from sticking if there is no TLP connection
770 * Prevent the PCI-E bus from sticking if there is no TLP connection
771 * on the last TLP read/write transaction when MAC is reset. 759 * on the last TLP read/write transaction when MAC is reset.
772 */ 760 */
773 ret_val = e1000e_disable_pcie_master(hw); 761 ret_val = e1000e_disable_pcie_master(hw);
@@ -899,8 +887,7 @@ static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
899 hw->dev_spec.e80003es2lan.mdic_wa_enable = false; 887 hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
900 } 888 }
901 889
902 /* 890 /* Clear all of the statistics registers (clear on read). It is
903 * Clear all of the statistics registers (clear on read). It is
904 * important that we do this after we have tried to establish link 891 * important that we do this after we have tried to establish link
905 * because the symbol error count will increment wildly if there 892 * because the symbol error count will increment wildly if there
906 * is no link. 893 * is no link.
@@ -945,8 +932,7 @@ static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
945 reg |= (1 << 28); 932 reg |= (1 << 28);
946 ew32(TARC(1), reg); 933 ew32(TARC(1), reg);
947 934
948 /* 935 /* Disable IPv6 extension header parsing because some malformed
949 * Disable IPv6 extension header parsing because some malformed
950 * IPv6 headers can hang the Rx. 936 * IPv6 headers can hang the Rx.
951 */ 937 */
952 reg = er32(RFCTL); 938 reg = er32(RFCTL);
@@ -979,8 +965,7 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
979 if (ret_val) 965 if (ret_val)
980 return ret_val; 966 return ret_val;
981 967
982 /* 968 /* Options:
983 * Options:
984 * MDI/MDI-X = 0 (default) 969 * MDI/MDI-X = 0 (default)
985 * 0 - Auto for all speeds 970 * 0 - Auto for all speeds
986 * 1 - MDI mode 971 * 1 - MDI mode
@@ -1006,8 +991,7 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
1006 break; 991 break;
1007 } 992 }
1008 993
1009 /* 994 /* Options:
1010 * Options:
1011 * disable_polarity_correction = 0 (default) 995 * disable_polarity_correction = 0 (default)
1012 * Automatic Correction for Reversed Cable Polarity 996 * Automatic Correction for Reversed Cable Polarity
1013 * 0 - Disabled 997 * 0 - Disabled
@@ -1065,8 +1049,7 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
1065 if (ret_val) 1049 if (ret_val)
1066 return ret_val; 1050 return ret_val;
1067 1051
1068 /* 1052 /* Do not init these registers when the HW is in IAMT mode, since the
1069 * Do not init these registers when the HW is in IAMT mode, since the
1070 * firmware will have already initialized them. We only initialize 1053 * firmware will have already initialized them. We only initialize
1071 * them if the HW is not in IAMT mode. 1054 * them if the HW is not in IAMT mode.
1072 */ 1055 */
@@ -1087,8 +1070,7 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
1087 return ret_val; 1070 return ret_val;
1088 } 1071 }
1089 1072
1090 /* 1073 /* Workaround: Disable padding in Kumeran interface in the MAC
1091 * Workaround: Disable padding in Kumeran interface in the MAC
1092 * and in the PHY to avoid CRC errors. 1074 * and in the PHY to avoid CRC errors.
1093 */ 1075 */
1094 ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data); 1076 ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
@@ -1121,8 +1103,7 @@ static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1121 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1103 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1122 ew32(CTRL, ctrl); 1104 ew32(CTRL, ctrl);
1123 1105
1124 /* 1106 /* Set the mac to wait the maximum time between each
1125 * Set the mac to wait the maximum time between each
1126 * iteration and increase the max iterations when 1107 * iteration and increase the max iterations when
1127 * polling the phy; this fixes erroneous timeouts at 10Mbps. 1108 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1128 */ 1109 */
@@ -1352,8 +1333,7 @@ static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1352{ 1333{
1353 s32 ret_val = 0; 1334 s32 ret_val = 0;
1354 1335
1355 /* 1336 /* If there's an alternate MAC address place it in RAR0
1356 * If there's an alternate MAC address place it in RAR0
1357 * so that it will override the Si installed default perm 1337 * so that it will override the Si installed default perm
1358 * address. 1338 * address.
1359 */ 1339 */
diff --git a/drivers/net/ethernet/intel/e1000e/82571.c b/drivers/net/ethernet/intel/e1000e/82571.c
index c98586408005..c77d010d5c59 100644
--- a/drivers/net/ethernet/intel/e1000e/82571.c
+++ b/drivers/net/ethernet/intel/e1000e/82571.c
@@ -26,8 +26,7 @@
26 26
27*******************************************************************************/ 27*******************************************************************************/
28 28
29/* 29/* 82571EB Gigabit Ethernet Controller
30 * 82571EB Gigabit Ethernet Controller
31 * 82571EB Gigabit Ethernet Controller (Copper) 30 * 82571EB Gigabit Ethernet Controller (Copper)
32 * 82571EB Gigabit Ethernet Controller (Fiber) 31 * 82571EB Gigabit Ethernet Controller (Fiber)
33 * 82571EB Dual Port Gigabit Mezzanine Adapter 32 * 82571EB Dual Port Gigabit Mezzanine Adapter
@@ -191,8 +190,7 @@ static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
191 if (((eecd >> 15) & 0x3) == 0x3) { 190 if (((eecd >> 15) & 0x3) == 0x3) {
192 nvm->type = e1000_nvm_flash_hw; 191 nvm->type = e1000_nvm_flash_hw;
193 nvm->word_size = 2048; 192 nvm->word_size = 2048;
194 /* 193 /* Autonomous Flash update bit must be cleared due
195 * Autonomous Flash update bit must be cleared due
196 * to Flash update issue. 194 * to Flash update issue.
197 */ 195 */
198 eecd &= ~E1000_EECD_AUPDEN; 196 eecd &= ~E1000_EECD_AUPDEN;
@@ -204,8 +202,7 @@ static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
204 nvm->type = e1000_nvm_eeprom_spi; 202 nvm->type = e1000_nvm_eeprom_spi;
205 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 203 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
206 E1000_EECD_SIZE_EX_SHIFT); 204 E1000_EECD_SIZE_EX_SHIFT);
207 /* 205 /* Added to a constant, "size" becomes the left-shift value
208 * Added to a constant, "size" becomes the left-shift value
209 * for setting word_size. 206 * for setting word_size.
210 */ 207 */
211 size += NVM_WORD_SIZE_BASE_SHIFT; 208 size += NVM_WORD_SIZE_BASE_SHIFT;
@@ -291,8 +288,7 @@ static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
291 288
292 /* FWSM register */ 289 /* FWSM register */
293 mac->has_fwsm = true; 290 mac->has_fwsm = true;
294 /* 291 /* ARC supported; valid only if manageability features are
295 * ARC supported; valid only if manageability features are
296 * enabled. 292 * enabled.
297 */ 293 */
298 mac->arc_subsystem_valid = !!(er32(FWSM) & 294 mac->arc_subsystem_valid = !!(er32(FWSM) &
@@ -314,8 +310,7 @@ static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
314 break; 310 break;
315 } 311 }
316 312
317 /* 313 /* Ensure that the inter-port SWSM.SMBI lock bit is clear before
318 * Ensure that the inter-port SWSM.SMBI lock bit is clear before
319 * first NVM or PHY access. This should be done for single-port 314 * first NVM or PHY access. This should be done for single-port
320 * devices, and for one port only on dual-port devices so that 315 * devices, and for one port only on dual-port devices so that
321 * for those devices we can still use the SMBI lock to synchronize 316 * for those devices we can still use the SMBI lock to synchronize
@@ -352,11 +347,8 @@ static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
352 ew32(SWSM, swsm & ~E1000_SWSM_SMBI); 347 ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
353 } 348 }
354 349
355 /* 350 /* Initialize device specific counter of SMBI acquisition timeouts. */
356 * Initialize device specific counter of SMBI acquisition 351 hw->dev_spec.e82571.smb_counter = 0;
357 * timeouts.
358 */
359 hw->dev_spec.e82571.smb_counter = 0;
360 352
361 return 0; 353 return 0;
362} 354}
@@ -445,8 +437,7 @@ static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
445 switch (hw->mac.type) { 437 switch (hw->mac.type) {
446 case e1000_82571: 438 case e1000_82571:
447 case e1000_82572: 439 case e1000_82572:
448 /* 440 /* The 82571 firmware may still be configuring the PHY.
449 * The 82571 firmware may still be configuring the PHY.
450 * In this case, we cannot access the PHY until the 441 * In this case, we cannot access the PHY until the
451 * configuration is done. So we explicitly set the 442 * configuration is done. So we explicitly set the
452 * PHY ID. 443 * PHY ID.
@@ -492,8 +483,7 @@ static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
492 s32 fw_timeout = hw->nvm.word_size + 1; 483 s32 fw_timeout = hw->nvm.word_size + 1;
493 s32 i = 0; 484 s32 i = 0;
494 485
495 /* 486 /* If we have timedout 3 times on trying to acquire
496 * If we have timedout 3 times on trying to acquire
497 * the inter-port SMBI semaphore, there is old code 487 * the inter-port SMBI semaphore, there is old code
498 * operating on the other port, and it is not 488 * operating on the other port, and it is not
499 * releasing SMBI. Modify the number of times that 489 * releasing SMBI. Modify the number of times that
@@ -787,8 +777,7 @@ static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
787 if (ret_val) 777 if (ret_val)
788 return ret_val; 778 return ret_val;
789 779
790 /* 780 /* If our nvm is an EEPROM, then we're done
791 * If our nvm is an EEPROM, then we're done
792 * otherwise, commit the checksum to the flash NVM. 781 * otherwise, commit the checksum to the flash NVM.
793 */ 782 */
794 if (hw->nvm.type != e1000_nvm_flash_hw) 783 if (hw->nvm.type != e1000_nvm_flash_hw)
@@ -806,8 +795,7 @@ static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
806 795
807 /* Reset the firmware if using STM opcode. */ 796 /* Reset the firmware if using STM opcode. */
808 if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { 797 if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
809 /* 798 /* The enabling of and the actual reset must be done
810 * The enabling of and the actual reset must be done
811 * in two write cycles. 799 * in two write cycles.
812 */ 800 */
813 ew32(HICR, E1000_HICR_FW_RESET_ENABLE); 801 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
@@ -867,8 +855,7 @@ static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
867 u32 i, eewr = 0; 855 u32 i, eewr = 0;
868 s32 ret_val = 0; 856 s32 ret_val = 0;
869 857
870 /* 858 /* A check for invalid values: offset too large, too many words,
871 * A check for invalid values: offset too large, too many words,
872 * and not enough words. 859 * and not enough words.
873 */ 860 */
874 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 861 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
@@ -957,8 +944,7 @@ static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
957 } else { 944 } else {
958 data &= ~IGP02E1000_PM_D0_LPLU; 945 data &= ~IGP02E1000_PM_D0_LPLU;
959 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); 946 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
960 /* 947 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
961 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
962 * during Dx states where the power conservation is most 948 * during Dx states where the power conservation is most
963 * important. During driver activity we should enable 949 * important. During driver activity we should enable
964 * SmartSpeed, so performance is maintained. 950 * SmartSpeed, so performance is maintained.
@@ -1002,8 +988,7 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1002 u32 ctrl, ctrl_ext, eecd, tctl; 988 u32 ctrl, ctrl_ext, eecd, tctl;
1003 s32 ret_val; 989 s32 ret_val;
1004 990
1005 /* 991 /* Prevent the PCI-E bus from sticking if there is no TLP connection
1006 * Prevent the PCI-E bus from sticking if there is no TLP connection
1007 * on the last TLP read/write transaction when MAC is reset. 992 * on the last TLP read/write transaction when MAC is reset.
1008 */ 993 */
1009 ret_val = e1000e_disable_pcie_master(hw); 994 ret_val = e1000e_disable_pcie_master(hw);
@@ -1021,8 +1006,7 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1021 1006
1022 usleep_range(10000, 20000); 1007 usleep_range(10000, 20000);
1023 1008
1024 /* 1009 /* Must acquire the MDIO ownership before MAC reset.
1025 * Must acquire the MDIO ownership before MAC reset.
1026 * Ownership defaults to firmware after a reset. 1010 * Ownership defaults to firmware after a reset.
1027 */ 1011 */
1028 switch (hw->mac.type) { 1012 switch (hw->mac.type) {
@@ -1067,8 +1051,7 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1067 /* We don't want to continue accessing MAC registers. */ 1051 /* We don't want to continue accessing MAC registers. */
1068 return ret_val; 1052 return ret_val;
1069 1053
1070 /* 1054 /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1071 * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1072 * Need to wait for Phy configuration completion before accessing 1055 * Need to wait for Phy configuration completion before accessing
1073 * NVM and Phy. 1056 * NVM and Phy.
1074 */ 1057 */
@@ -1076,8 +1059,7 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1076 switch (hw->mac.type) { 1059 switch (hw->mac.type) {
1077 case e1000_82571: 1060 case e1000_82571:
1078 case e1000_82572: 1061 case e1000_82572:
1079 /* 1062 /* REQ and GNT bits need to be cleared when using AUTO_RD
1080 * REQ and GNT bits need to be cleared when using AUTO_RD
1081 * to access the EEPROM. 1063 * to access the EEPROM.
1082 */ 1064 */
1083 eecd = er32(EECD); 1065 eecd = er32(EECD);
@@ -1138,8 +1120,7 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1138 e_dbg("Initializing the IEEE VLAN\n"); 1120 e_dbg("Initializing the IEEE VLAN\n");
1139 mac->ops.clear_vfta(hw); 1121 mac->ops.clear_vfta(hw);
1140 1122
1141 /* Setup the receive address. */ 1123 /* Setup the receive address.
1142 /*
1143 * If, however, a locally administered address was assigned to the 1124 * If, however, a locally administered address was assigned to the
1144 * 82571, we must reserve a RAR for it to work around an issue where 1125 * 82571, we must reserve a RAR for it to work around an issue where
1145 * resetting one port will reload the MAC on the other port. 1126 * resetting one port will reload the MAC on the other port.
@@ -1183,8 +1164,7 @@ static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1183 break; 1164 break;
1184 } 1165 }
1185 1166
1186 /* 1167 /* Clear all of the statistics registers (clear on read). It is
1187 * Clear all of the statistics registers (clear on read). It is
1188 * important that we do this after we have tried to establish link 1168 * important that we do this after we have tried to establish link
1189 * because the symbol error count will increment wildly if there 1169 * because the symbol error count will increment wildly if there
1190 * is no link. 1170 * is no link.
@@ -1281,8 +1261,7 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1281 ew32(PBA_ECC, reg); 1261 ew32(PBA_ECC, reg);
1282 } 1262 }
1283 1263
1284 /* 1264 /* Workaround for hardware errata.
1285 * Workaround for hardware errata.
1286 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 1265 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1287 */ 1266 */
1288 if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) { 1267 if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) {
@@ -1291,8 +1270,7 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1291 ew32(CTRL_EXT, reg); 1270 ew32(CTRL_EXT, reg);
1292 } 1271 }
1293 1272
1294 /* 1273 /* Disable IPv6 extension header parsing because some malformed
1295 * Disable IPv6 extension header parsing because some malformed
1296 * IPv6 headers can hang the Rx. 1274 * IPv6 headers can hang the Rx.
1297 */ 1275 */
1298 if (hw->mac.type <= e1000_82573) { 1276 if (hw->mac.type <= e1000_82573) {
@@ -1309,8 +1287,7 @@ static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1309 reg |= (1 << 22); 1287 reg |= (1 << 22);
1310 ew32(GCR, reg); 1288 ew32(GCR, reg);
1311 1289
1312 /* 1290 /* Workaround for hardware errata.
1313 * Workaround for hardware errata.
1314 * apply workaround for hardware errata documented in errata 1291 * apply workaround for hardware errata documented in errata
1315 * docs Fixes issue where some error prone or unreliable PCIe 1292 * docs Fixes issue where some error prone or unreliable PCIe
1316 * completions are occurring, particularly with ASPM enabled. 1293 * completions are occurring, particularly with ASPM enabled.
@@ -1344,8 +1321,7 @@ static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1344 case e1000_82574: 1321 case e1000_82574:
1345 case e1000_82583: 1322 case e1000_82583:
1346 if (hw->mng_cookie.vlan_id != 0) { 1323 if (hw->mng_cookie.vlan_id != 0) {
1347 /* 1324 /* The VFTA is a 4096b bit-field, each identifying
1348 * The VFTA is a 4096b bit-field, each identifying
1349 * a single VLAN ID. The following operations 1325 * a single VLAN ID. The following operations
1350 * determine which 32b entry (i.e. offset) into the 1326 * determine which 32b entry (i.e. offset) into the
1351 * array we want to set the VLAN ID (i.e. bit) of 1327 * array we want to set the VLAN ID (i.e. bit) of
@@ -1362,8 +1338,7 @@ static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1362 break; 1338 break;
1363 } 1339 }
1364 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 1340 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1365 /* 1341 /* If the offset we want to clear is the same offset of the
1366 * If the offset we want to clear is the same offset of the
1367 * manageability VLAN ID, then clear all bits except that of 1342 * manageability VLAN ID, then clear all bits except that of
1368 * the manageability unit. 1343 * the manageability unit.
1369 */ 1344 */
@@ -1401,8 +1376,7 @@ static s32 e1000_led_on_82574(struct e1000_hw *hw)
1401 1376
1402 ctrl = hw->mac.ledctl_mode2; 1377 ctrl = hw->mac.ledctl_mode2;
1403 if (!(E1000_STATUS_LU & er32(STATUS))) { 1378 if (!(E1000_STATUS_LU & er32(STATUS))) {
1404 /* 1379 /* If no link, then turn LED on by setting the invert bit
1405 * If no link, then turn LED on by setting the invert bit
1406 * for each LED that's "on" (0x0E) in ledctl_mode2. 1380 * for each LED that's "on" (0x0E) in ledctl_mode2.
1407 */ 1381 */
1408 for (i = 0; i < 4; i++) 1382 for (i = 0; i < 4; i++)
@@ -1427,8 +1401,7 @@ bool e1000_check_phy_82574(struct e1000_hw *hw)
1427 u16 receive_errors = 0; 1401 u16 receive_errors = 0;
1428 s32 ret_val = 0; 1402 s32 ret_val = 0;
1429 1403
1430 /* 1404 /* Read PHY Receive Error counter first, if its is max - all F's then
1431 * Read PHY Receive Error counter first, if its is max - all F's then
1432 * read the Base1000T status register If both are max then PHY is hung. 1405 * read the Base1000T status register If both are max then PHY is hung.
1433 */ 1406 */
1434 ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors); 1407 ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors);
@@ -1458,8 +1431,7 @@ bool e1000_check_phy_82574(struct e1000_hw *hw)
1458 **/ 1431 **/
1459static s32 e1000_setup_link_82571(struct e1000_hw *hw) 1432static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1460{ 1433{
1461 /* 1434 /* 82573 does not have a word in the NVM to determine
1462 * 82573 does not have a word in the NVM to determine
1463 * the default flow control setting, so we explicitly 1435 * the default flow control setting, so we explicitly
1464 * set it to full. 1436 * set it to full.
1465 */ 1437 */
@@ -1526,8 +1498,7 @@ static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1526 switch (hw->mac.type) { 1498 switch (hw->mac.type) {
1527 case e1000_82571: 1499 case e1000_82571:
1528 case e1000_82572: 1500 case e1000_82572:
1529 /* 1501 /* If SerDes loopback mode is entered, there is no form
1530 * If SerDes loopback mode is entered, there is no form
1531 * of reset to take the adapter out of that mode. So we 1502 * of reset to take the adapter out of that mode. So we
1532 * have to explicitly take the adapter out of loopback 1503 * have to explicitly take the adapter out of loopback
1533 * mode. This prevents drivers from twiddling their thumbs 1504 * mode. This prevents drivers from twiddling their thumbs
@@ -1584,8 +1555,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1584 switch (mac->serdes_link_state) { 1555 switch (mac->serdes_link_state) {
1585 case e1000_serdes_link_autoneg_complete: 1556 case e1000_serdes_link_autoneg_complete:
1586 if (!(status & E1000_STATUS_LU)) { 1557 if (!(status & E1000_STATUS_LU)) {
1587 /* 1558 /* We have lost link, retry autoneg before
1588 * We have lost link, retry autoneg before
1589 * reporting link failure 1559 * reporting link failure
1590 */ 1560 */
1591 mac->serdes_link_state = 1561 mac->serdes_link_state =
@@ -1598,8 +1568,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1598 break; 1568 break;
1599 1569
1600 case e1000_serdes_link_forced_up: 1570 case e1000_serdes_link_forced_up:
1601 /* 1571 /* If we are receiving /C/ ordered sets, re-enable
1602 * If we are receiving /C/ ordered sets, re-enable
1603 * auto-negotiation in the TXCW register and disable 1572 * auto-negotiation in the TXCW register and disable
1604 * forced link in the Device Control register in an 1573 * forced link in the Device Control register in an
1605 * attempt to auto-negotiate with our link partner. 1574 * attempt to auto-negotiate with our link partner.
@@ -1619,8 +1588,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1619 1588
1620 case e1000_serdes_link_autoneg_progress: 1589 case e1000_serdes_link_autoneg_progress:
1621 if (rxcw & E1000_RXCW_C) { 1590 if (rxcw & E1000_RXCW_C) {
1622 /* 1591 /* We received /C/ ordered sets, meaning the
1623 * We received /C/ ordered sets, meaning the
1624 * link partner has autonegotiated, and we can 1592 * link partner has autonegotiated, and we can
1625 * trust the Link Up (LU) status bit. 1593 * trust the Link Up (LU) status bit.
1626 */ 1594 */
@@ -1636,8 +1604,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1636 e_dbg("AN_PROG -> DOWN\n"); 1604 e_dbg("AN_PROG -> DOWN\n");
1637 } 1605 }
1638 } else { 1606 } else {
1639 /* 1607 /* The link partner did not autoneg.
1640 * The link partner did not autoneg.
1641 * Force link up and full duplex, and change 1608 * Force link up and full duplex, and change
1642 * state to forced. 1609 * state to forced.
1643 */ 1610 */
@@ -1660,8 +1627,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1660 1627
1661 case e1000_serdes_link_down: 1628 case e1000_serdes_link_down:
1662 default: 1629 default:
1663 /* 1630 /* The link was down but the receiver has now gained
1664 * The link was down but the receiver has now gained
1665 * valid sync, so lets see if we can bring the link 1631 * valid sync, so lets see if we can bring the link
1666 * up. 1632 * up.
1667 */ 1633 */
@@ -1679,8 +1645,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1679 mac->serdes_link_state = e1000_serdes_link_down; 1645 mac->serdes_link_state = e1000_serdes_link_down;
1680 e_dbg("ANYSTATE -> DOWN\n"); 1646 e_dbg("ANYSTATE -> DOWN\n");
1681 } else { 1647 } else {
1682 /* 1648 /* Check several times, if SYNCH bit and CONFIG
1683 * Check several times, if SYNCH bit and CONFIG
1684 * bit both are consistently 1 then simply ignore 1649 * bit both are consistently 1 then simply ignore
1685 * the IV bit and restart Autoneg 1650 * the IV bit and restart Autoneg
1686 */ 1651 */
@@ -1780,8 +1745,7 @@ void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1780 1745
1781 /* If workaround is activated... */ 1746 /* If workaround is activated... */
1782 if (state) 1747 if (state)
1783 /* 1748 /* Hold a copy of the LAA in RAR[14] This is done so that
1784 * Hold a copy of the LAA in RAR[14] This is done so that
1785 * between the time RAR[0] gets clobbered and the time it 1749 * between the time RAR[0] gets clobbered and the time it
1786 * gets fixed, the actual LAA is in one of the RARs and no 1750 * gets fixed, the actual LAA is in one of the RARs and no
1787 * incoming packets directed to this port are dropped. 1751 * incoming packets directed to this port are dropped.
@@ -1810,8 +1774,7 @@ static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1810 if (nvm->type != e1000_nvm_flash_hw) 1774 if (nvm->type != e1000_nvm_flash_hw)
1811 return 0; 1775 return 0;
1812 1776
1813 /* 1777 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
1814 * Check bit 4 of word 10h. If it is 0, firmware is done updating
1815 * 10h-12h. Checksum may need to be fixed. 1778 * 10h-12h. Checksum may need to be fixed.
1816 */ 1779 */
1817 ret_val = e1000_read_nvm(hw, 0x10, 1, &data); 1780 ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
@@ -1819,8 +1782,7 @@ static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1819 return ret_val; 1782 return ret_val;
1820 1783
1821 if (!(data & 0x10)) { 1784 if (!(data & 0x10)) {
1822 /* 1785 /* Read 0x23 and check bit 15. This bit is a 1
1823 * Read 0x23 and check bit 15. This bit is a 1
1824 * when the checksum has already been fixed. If 1786 * when the checksum has already been fixed. If
1825 * the checksum is still wrong and this bit is a 1787 * the checksum is still wrong and this bit is a
1826 * 1, we need to return bad checksum. Otherwise, 1788 * 1, we need to return bad checksum. Otherwise,
@@ -1852,8 +1814,7 @@ static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1852 if (hw->mac.type == e1000_82571) { 1814 if (hw->mac.type == e1000_82571) {
1853 s32 ret_val = 0; 1815 s32 ret_val = 0;
1854 1816
1855 /* 1817 /* If there's an alternate MAC address place it in RAR0
1856 * If there's an alternate MAC address place it in RAR0
1857 * so that it will override the Si installed default perm 1818 * so that it will override the Si installed default perm
1858 * address. 1819 * address.
1859 */ 1820 */
diff --git a/drivers/net/ethernet/intel/e1000e/defines.h b/drivers/net/ethernet/intel/e1000e/defines.h
index 76edbc1be33b..02a12b69555f 100644
--- a/drivers/net/ethernet/intel/e1000e/defines.h
+++ b/drivers/net/ethernet/intel/e1000e/defines.h
@@ -185,8 +185,7 @@
185#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 185#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
186#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 186#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
187 187
188/* 188/* Use byte values for the following shift parameters
189 * Use byte values for the following shift parameters
190 * Usage: 189 * Usage:
191 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 190 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
192 * E1000_PSRCTL_BSIZE0_MASK) | 191 * E1000_PSRCTL_BSIZE0_MASK) |
@@ -242,8 +241,7 @@
242#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 241#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
243#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 242#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
244 243
245/* 244/* Bit definitions for the Management Data IO (MDIO) and Management Data
246 * Bit definitions for the Management Data IO (MDIO) and Management Data
247 * Clock (MDC) pins in the Device Control Register. 245 * Clock (MDC) pins in the Device Control Register.
248 */ 246 */
249 247
@@ -424,8 +422,7 @@
424#define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ 422#define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */
425#define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 for ECC */ 423#define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 for ECC */
426 424
427/* 425/* This defines the bits that are set in the Interrupt Mask
428 * This defines the bits that are set in the Interrupt Mask
429 * Set/Read Register. Each bit is documented below: 426 * Set/Read Register. Each bit is documented below:
430 * o RXT0 = Receiver Timer Interrupt (ring 0) 427 * o RXT0 = Receiver Timer Interrupt (ring 0)
431 * o TXDW = Transmit Descriptor Written Back 428 * o TXDW = Transmit Descriptor Written Back
@@ -475,8 +472,7 @@
475/* 802.1q VLAN Packet Size */ 472/* 802.1q VLAN Packet Size */
476#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 473#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
477 474
478/* Receive Address */ 475/* Receive Address
479/*
480 * Number of high/low register pairs in the RAR. The RAR (Receive Address 476 * Number of high/low register pairs in the RAR. The RAR (Receive Address
481 * Registers) holds the directed and multicast addresses that we monitor. 477 * Registers) holds the directed and multicast addresses that we monitor.
482 * Technically, we have 16 spots. However, we reserve one of these spots 478 * Technically, we have 16 spots. However, we reserve one of these spots
@@ -723,8 +719,7 @@
723#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 719#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
724#define MAX_PHY_MULTI_PAGE_REG 0xF 720#define MAX_PHY_MULTI_PAGE_REG 0xF
725 721
726/* Bit definitions for valid PHY IDs. */ 722/* Bit definitions for valid PHY IDs.
727/*
728 * I = Integrated 723 * I = Integrated
729 * E = External 724 * E = External
730 */ 725 */
@@ -762,8 +757,7 @@
762#define M88E1000_PSCR_AUTO_X_1000T 0x0040 757#define M88E1000_PSCR_AUTO_X_1000T 0x0040
763/* Auto crossover enabled all speeds */ 758/* Auto crossover enabled all speeds */
764#define M88E1000_PSCR_AUTO_X_MODE 0x0060 759#define M88E1000_PSCR_AUTO_X_MODE 0x0060
765/* 760/* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold)
766 * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold)
767 * 0=Normal 10BASE-T Rx Threshold 761 * 0=Normal 10BASE-T Rx Threshold
768 */ 762 */
769#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 763#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
@@ -779,14 +773,12 @@
779 773
780#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 774#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
781 775
782/* 776/* Number of times we will attempt to autonegotiate before downshifting if we
783 * Number of times we will attempt to autonegotiate before downshifting if we
784 * are the master 777 * are the master
785 */ 778 */
786#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 779#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
787#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 780#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
788/* 781/* Number of times we will attempt to autonegotiate before downshifting if we
789 * Number of times we will attempt to autonegotiate before downshifting if we
790 * are the slave 782 * are the slave
791 */ 783 */
792#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 784#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
@@ -808,8 +800,7 @@
808#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ 800#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
809 ((reg) & MAX_PHY_REG_ADDRESS)) 801 ((reg) & MAX_PHY_REG_ADDRESS))
810 802
811/* 803/* Bits...
812 * Bits...
813 * 15-5: page 804 * 15-5: page
814 * 4-0: register offset 805 * 4-0: register offset
815 */ 806 */
diff --git a/drivers/net/ethernet/intel/e1000e/e1000.h b/drivers/net/ethernet/intel/e1000e/e1000.h
index 04668b47a1df..6782a2eea1bc 100644
--- a/drivers/net/ethernet/intel/e1000e/e1000.h
+++ b/drivers/net/ethernet/intel/e1000e/e1000.h
@@ -161,8 +161,7 @@ struct e1000_info;
161/* Time to wait before putting the device into D3 if there's no link (in ms). */ 161/* Time to wait before putting the device into D3 if there's no link (in ms). */
162#define LINK_TIMEOUT 100 162#define LINK_TIMEOUT 100
163 163
164/* 164/* Count for polling __E1000_RESET condition every 10-20msec.
165 * Count for polling __E1000_RESET condition every 10-20msec.
166 * Experimentation has shown the reset can take approximately 210msec. 165 * Experimentation has shown the reset can take approximately 210msec.
167 */ 166 */
168#define E1000_CHECK_RESET_COUNT 25 167#define E1000_CHECK_RESET_COUNT 25
@@ -172,8 +171,7 @@ struct e1000_info;
172#define BURST_RDTR 0x20 171#define BURST_RDTR 0x20
173#define BURST_RADV 0x20 172#define BURST_RADV 0x20
174 173
175/* 174/* in the case of WTHRESH, it appears at least the 82571/2 hardware
176 * in the case of WTHRESH, it appears at least the 82571/2 hardware
177 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when 175 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
178 * WTHRESH=4, so a setting of 5 gives the most efficient bus 176 * WTHRESH=4, so a setting of 5 gives the most efficient bus
179 * utilization but to avoid possible Tx stalls, set it to 1 177 * utilization but to avoid possible Tx stalls, set it to 1
@@ -214,8 +212,7 @@ struct e1000_ps_page {
214 u64 dma; /* must be u64 - written to hw */ 212 u64 dma; /* must be u64 - written to hw */
215}; 213};
216 214
217/* 215/* wrappers around a pointer to a socket buffer,
218 * wrappers around a pointer to a socket buffer,
219 * so a DMA handle can be stored along with the buffer 216 * so a DMA handle can be stored along with the buffer
220 */ 217 */
221struct e1000_buffer { 218struct e1000_buffer {
@@ -305,9 +302,7 @@ struct e1000_adapter {
305 u16 tx_itr; 302 u16 tx_itr;
306 u16 rx_itr; 303 u16 rx_itr;
307 304
308 /* 305 /* Tx */
309 * Tx
310 */
311 struct e1000_ring *tx_ring /* One per active queue */ 306 struct e1000_ring *tx_ring /* One per active queue */
312 ____cacheline_aligned_in_smp; 307 ____cacheline_aligned_in_smp;
313 u32 tx_fifo_limit; 308 u32 tx_fifo_limit;
@@ -340,9 +335,7 @@ struct e1000_adapter {
340 u32 tx_fifo_size; 335 u32 tx_fifo_size;
341 u32 tx_dma_failed; 336 u32 tx_dma_failed;
342 337
343 /* 338 /* Rx */
344 * Rx
345 */
346 bool (*clean_rx) (struct e1000_ring *ring, int *work_done, 339 bool (*clean_rx) (struct e1000_ring *ring, int *work_done,
347 int work_to_do) ____cacheline_aligned_in_smp; 340 int work_to_do) ____cacheline_aligned_in_smp;
348 void (*alloc_rx_buf) (struct e1000_ring *ring, int cleaned_count, 341 void (*alloc_rx_buf) (struct e1000_ring *ring, int cleaned_count,
diff --git a/drivers/net/ethernet/intel/e1000e/ethtool.c b/drivers/net/ethernet/intel/e1000e/ethtool.c
index c11ac2756667..f95bc6ee1c22 100644
--- a/drivers/net/ethernet/intel/e1000e/ethtool.c
+++ b/drivers/net/ethernet/intel/e1000e/ethtool.c
@@ -214,7 +214,8 @@ static int e1000_set_spd_dplx(struct e1000_adapter *adapter, u32 spd, u8 dplx)
214 mac->autoneg = 0; 214 mac->autoneg = 0;
215 215
216 /* Make sure dplx is at most 1 bit and lsb of speed is not set 216 /* Make sure dplx is at most 1 bit and lsb of speed is not set
217 * for the switch() below to work */ 217 * for the switch() below to work
218 */
218 if ((spd & 1) || (dplx & ~1)) 219 if ((spd & 1) || (dplx & ~1))
219 goto err_inval; 220 goto err_inval;
220 221
@@ -263,8 +264,7 @@ static int e1000_set_settings(struct net_device *netdev,
263 struct e1000_adapter *adapter = netdev_priv(netdev); 264 struct e1000_adapter *adapter = netdev_priv(netdev);
264 struct e1000_hw *hw = &adapter->hw; 265 struct e1000_hw *hw = &adapter->hw;
265 266
266 /* 267 /* When SoL/IDER sessions are active, autoneg/speed/duplex
267 * When SoL/IDER sessions are active, autoneg/speed/duplex
268 * cannot be changed 268 * cannot be changed
269 */ 269 */
270 if (hw->phy.ops.check_reset_block && 270 if (hw->phy.ops.check_reset_block &&
@@ -273,8 +273,7 @@ static int e1000_set_settings(struct net_device *netdev,
273 return -EINVAL; 273 return -EINVAL;
274 } 274 }
275 275
276 /* 276 /* MDI setting is only allowed when autoneg enabled because
277 * MDI setting is only allowed when autoneg enabled because
278 * some hardware doesn't allow MDI setting when speed or 277 * some hardware doesn't allow MDI setting when speed or
279 * duplex is forced. 278 * duplex is forced.
280 */ 279 */
@@ -316,8 +315,7 @@ static int e1000_set_settings(struct net_device *netdev,
316 315
317 /* MDI-X => 2; MDI => 1; Auto => 3 */ 316 /* MDI-X => 2; MDI => 1; Auto => 3 */
318 if (ecmd->eth_tp_mdix_ctrl) { 317 if (ecmd->eth_tp_mdix_ctrl) {
319 /* 318 /* fix up the value for auto (3 => 0) as zero is mapped
320 * fix up the value for auto (3 => 0) as zero is mapped
321 * internally to auto 319 * internally to auto
322 */ 320 */
323 if (ecmd->eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO) 321 if (ecmd->eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO)
@@ -454,8 +452,8 @@ static void e1000_get_regs(struct net_device *netdev,
454 regs_buff[12] = adapter->hw.phy.type; /* PHY type (IGP=1, M88=0) */ 452 regs_buff[12] = adapter->hw.phy.type; /* PHY type (IGP=1, M88=0) */
455 453
456 /* ethtool doesn't use anything past this point, so all this 454 /* ethtool doesn't use anything past this point, so all this
457 * code is likely legacy junk for apps that may or may not 455 * code is likely legacy junk for apps that may or may not exist
458 * exist */ 456 */
459 if (hw->phy.type == e1000_phy_m88) { 457 if (hw->phy.type == e1000_phy_m88) {
460 e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 458 e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
461 regs_buff[13] = (u32)phy_data; /* cable length */ 459 regs_buff[13] = (u32)phy_data; /* cable length */
@@ -598,8 +596,7 @@ static int e1000_set_eeprom(struct net_device *netdev,
598 if (ret_val) 596 if (ret_val)
599 goto out; 597 goto out;
600 598
601 /* 599 /* Update the checksum over the first part of the EEPROM if needed
602 * Update the checksum over the first part of the EEPROM if needed
603 * and flush shadow RAM for applicable controllers 600 * and flush shadow RAM for applicable controllers
604 */ 601 */
605 if ((first_word <= NVM_CHECKSUM_REG) || 602 if ((first_word <= NVM_CHECKSUM_REG) ||
@@ -623,8 +620,7 @@ static void e1000_get_drvinfo(struct net_device *netdev,
623 strlcpy(drvinfo->version, e1000e_driver_version, 620 strlcpy(drvinfo->version, e1000e_driver_version,
624 sizeof(drvinfo->version)); 621 sizeof(drvinfo->version));
625 622
626 /* 623 /* EEPROM image version # is reported as firmware version # for
627 * EEPROM image version # is reported as firmware version # for
628 * PCI-E controllers 624 * PCI-E controllers
629 */ 625 */
630 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), 626 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
@@ -708,8 +704,7 @@ static int e1000_set_ringparam(struct net_device *netdev,
708 704
709 e1000e_down(adapter); 705 e1000e_down(adapter);
710 706
711 /* 707 /* We can't just free everything and then setup again, because the
712 * We can't just free everything and then setup again, because the
713 * ISRs in MSI-X mode get passed pointers to the Tx and Rx ring 708 * ISRs in MSI-X mode get passed pointers to the Tx and Rx ring
714 * structs. First, attempt to allocate new resources... 709 * structs. First, attempt to allocate new resources...
715 */ 710 */
@@ -813,8 +808,7 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
813 u32 mask; 808 u32 mask;
814 u32 wlock_mac = 0; 809 u32 wlock_mac = 0;
815 810
816 /* 811 /* The status register is Read Only, so a write should fail.
817 * The status register is Read Only, so a write should fail.
818 * Some bits that get toggled are ignored. 812 * Some bits that get toggled are ignored.
819 */ 813 */
820 switch (mac->type) { 814 switch (mac->type) {
@@ -996,8 +990,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
996 } 990 }
997 991
998 if (!shared_int) { 992 if (!shared_int) {
999 /* 993 /* Disable the interrupt to be reported in
1000 * Disable the interrupt to be reported in
1001 * the cause register and then force the same 994 * the cause register and then force the same
1002 * interrupt and see if one gets posted. If 995 * interrupt and see if one gets posted. If
1003 * an interrupt was posted to the bus, the 996 * an interrupt was posted to the bus, the
@@ -1015,8 +1008,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
1015 } 1008 }
1016 } 1009 }
1017 1010
1018 /* 1011 /* Enable the interrupt to be reported in
1019 * Enable the interrupt to be reported in
1020 * the cause register and then force the same 1012 * the cause register and then force the same
1021 * interrupt and see if one gets posted. If 1013 * interrupt and see if one gets posted. If
1022 * an interrupt was not posted to the bus, the 1014 * an interrupt was not posted to the bus, the
@@ -1034,8 +1026,7 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
1034 } 1026 }
1035 1027
1036 if (!shared_int) { 1028 if (!shared_int) {
1037 /* 1029 /* Disable the other interrupts to be reported in
1038 * Disable the other interrupts to be reported in
1039 * the cause register and then force the other 1030 * the cause register and then force the other
1040 * interrupts and see if any get posted. If 1031 * interrupts and see if any get posted. If
1041 * an interrupt was posted to the bus, the 1032 * an interrupt was posted to the bus, the
@@ -1378,8 +1369,7 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
1378 hw->phy.type == e1000_phy_m88) { 1369 hw->phy.type == e1000_phy_m88) {
1379 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */ 1370 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1380 } else { 1371 } else {
1381 /* 1372 /* Set the ILOS bit on the fiber Nic if half duplex link is
1382 * Set the ILOS bit on the fiber Nic if half duplex link is
1383 * detected. 1373 * detected.
1384 */ 1374 */
1385 if ((er32(STATUS) & E1000_STATUS_FD) == 0) 1375 if ((er32(STATUS) & E1000_STATUS_FD) == 0)
@@ -1388,8 +1378,7 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
1388 1378
1389 ew32(CTRL, ctrl_reg); 1379 ew32(CTRL, ctrl_reg);
1390 1380
1391 /* 1381 /* Disable the receiver on the PHY so when a cable is plugged in, the
1392 * Disable the receiver on the PHY so when a cable is plugged in, the
1393 * PHY does not begin to autoneg when a cable is reconnected to the NIC. 1382 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1394 */ 1383 */
1395 if (hw->phy.type == e1000_phy_m88) 1384 if (hw->phy.type == e1000_phy_m88)
@@ -1408,8 +1397,7 @@ static int e1000_set_82571_fiber_loopback(struct e1000_adapter *adapter)
1408 1397
1409 /* special requirements for 82571/82572 fiber adapters */ 1398 /* special requirements for 82571/82572 fiber adapters */
1410 1399
1411 /* 1400 /* jump through hoops to make sure link is up because serdes
1412 * jump through hoops to make sure link is up because serdes
1413 * link is hardwired up 1401 * link is hardwired up
1414 */ 1402 */
1415 ctrl |= E1000_CTRL_SLU; 1403 ctrl |= E1000_CTRL_SLU;
@@ -1429,8 +1417,7 @@ static int e1000_set_82571_fiber_loopback(struct e1000_adapter *adapter)
1429 ew32(CTRL, ctrl); 1417 ew32(CTRL, ctrl);
1430 } 1418 }
1431 1419
1432 /* 1420 /* special write to serdes control register to enable SerDes analog
1433 * special write to serdes control register to enable SerDes analog
1434 * loopback 1421 * loopback
1435 */ 1422 */
1436#define E1000_SERDES_LB_ON 0x410 1423#define E1000_SERDES_LB_ON 0x410
@@ -1448,8 +1435,7 @@ static int e1000_set_es2lan_mac_loopback(struct e1000_adapter *adapter)
1448 u32 ctrlext = er32(CTRL_EXT); 1435 u32 ctrlext = er32(CTRL_EXT);
1449 u32 ctrl = er32(CTRL); 1436 u32 ctrl = er32(CTRL);
1450 1437
1451 /* 1438 /* save CTRL_EXT to restore later, reuse an empty variable (unused
1452 * save CTRL_EXT to restore later, reuse an empty variable (unused
1453 * on mac_type 80003es2lan) 1439 * on mac_type 80003es2lan)
1454 */ 1440 */
1455 adapter->tx_fifo_head = ctrlext; 1441 adapter->tx_fifo_head = ctrlext;
@@ -1585,8 +1571,7 @@ static int e1000_run_loopback_test(struct e1000_adapter *adapter)
1585 1571
1586 ew32(RDT(0), rx_ring->count - 1); 1572 ew32(RDT(0), rx_ring->count - 1);
1587 1573
1588 /* 1574 /* Calculate the loop count based on the largest descriptor ring
1589 * Calculate the loop count based on the largest descriptor ring
1590 * The idea is to wrap the largest ring a number of times using 64 1575 * The idea is to wrap the largest ring a number of times using 64
1591 * send/receive pairs during each loop 1576 * send/receive pairs during each loop
1592 */ 1577 */
@@ -1627,8 +1612,7 @@ static int e1000_run_loopback_test(struct e1000_adapter *adapter)
1627 l++; 1612 l++;
1628 if (l == rx_ring->count) 1613 if (l == rx_ring->count)
1629 l = 0; 1614 l = 0;
1630 /* 1615 /* time + 20 msecs (200 msecs on 2.4) is more than
1631 * time + 20 msecs (200 msecs on 2.4) is more than
1632 * enough time to complete the receives, if it's 1616 * enough time to complete the receives, if it's
1633 * exceeded, break and error off 1617 * exceeded, break and error off
1634 */ 1618 */
@@ -1649,10 +1633,7 @@ static int e1000_loopback_test(struct e1000_adapter *adapter, u64 *data)
1649{ 1633{
1650 struct e1000_hw *hw = &adapter->hw; 1634 struct e1000_hw *hw = &adapter->hw;
1651 1635
1652 /* 1636 /* PHY loopback cannot be performed if SoL/IDER sessions are active */
1653 * PHY loopback cannot be performed if SoL/IDER
1654 * sessions are active
1655 */
1656 if (hw->phy.ops.check_reset_block && 1637 if (hw->phy.ops.check_reset_block &&
1657 hw->phy.ops.check_reset_block(hw)) { 1638 hw->phy.ops.check_reset_block(hw)) {
1658 e_err("Cannot do PHY loopback test when SoL/IDER is active.\n"); 1639 e_err("Cannot do PHY loopback test when SoL/IDER is active.\n");
@@ -1686,8 +1667,7 @@ static int e1000_link_test(struct e1000_adapter *adapter, u64 *data)
1686 int i = 0; 1667 int i = 0;
1687 hw->mac.serdes_has_link = false; 1668 hw->mac.serdes_has_link = false;
1688 1669
1689 /* 1670 /* On some blade server designs, link establishment
1690 * On some blade server designs, link establishment
1691 * could take as long as 2-3 minutes 1671 * could take as long as 2-3 minutes
1692 */ 1672 */
1693 do { 1673 do {
@@ -1701,8 +1681,7 @@ static int e1000_link_test(struct e1000_adapter *adapter, u64 *data)
1701 } else { 1681 } else {
1702 hw->mac.ops.check_for_link(hw); 1682 hw->mac.ops.check_for_link(hw);
1703 if (hw->mac.autoneg) 1683 if (hw->mac.autoneg)
1704 /* 1684 /* On some Phy/switch combinations, link establishment
1705 * On some Phy/switch combinations, link establishment
1706 * can take a few seconds more than expected. 1685 * can take a few seconds more than expected.
1707 */ 1686 */
1708 msleep(5000); 1687 msleep(5000);
diff --git a/drivers/net/ethernet/intel/e1000e/hw.h b/drivers/net/ethernet/intel/e1000e/hw.h
index d37bfd96c987..cf217777586c 100644
--- a/drivers/net/ethernet/intel/e1000e/hw.h
+++ b/drivers/net/ethernet/intel/e1000e/hw.h
@@ -85,8 +85,7 @@ enum e1e_registers {
85 E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */ 85 E1000_FCRTL = 0x02160, /* Flow Control Receive Threshold Low - RW */
86 E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */ 86 E1000_FCRTH = 0x02168, /* Flow Control Receive Threshold High - RW */
87 E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */ 87 E1000_PSRCTL = 0x02170, /* Packet Split Receive Control - RW */
88/* 88/* Convenience macros
89 * Convenience macros
90 * 89 *
91 * Note: "_n" is the queue number of the register to be written to. 90 * Note: "_n" is the queue number of the register to be written to.
92 * 91 *
@@ -800,8 +799,7 @@ struct e1000_mac_operations {
800 s32 (*read_mac_addr)(struct e1000_hw *); 799 s32 (*read_mac_addr)(struct e1000_hw *);
801}; 800};
802 801
803/* 802/* When to use various PHY register access functions:
804 * When to use various PHY register access functions:
805 * 803 *
806 * Func Caller 804 * Func Caller
807 * Function Does Does When to use 805 * Function Does Does When to use
diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.c b/drivers/net/ethernet/intel/e1000e/ich8lan.c
index e3a7b07df629..976336547607 100644
--- a/drivers/net/ethernet/intel/e1000e/ich8lan.c
+++ b/drivers/net/ethernet/intel/e1000e/ich8lan.c
@@ -26,8 +26,7 @@
26 26
27*******************************************************************************/ 27*******************************************************************************/
28 28
29/* 29/* 82562G 10/100 Network Connection
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection 30 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection 31 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection 32 * 82562GT-2 10/100 Network Connection
@@ -354,8 +353,7 @@ static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
354 return true; 353 return true;
355 } 354 }
356 355
357 /* 356 /* In case the PHY needs to be in mdio slow mode,
358 * In case the PHY needs to be in mdio slow mode,
359 * set slow mode and try to get the PHY id again. 357 * set slow mode and try to get the PHY id again.
360 */ 358 */
361 hw->phy.ops.release(hw); 359 hw->phy.ops.release(hw);
@@ -386,8 +384,7 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
386 return ret_val; 384 return ret_val;
387 } 385 }
388 386
389 /* 387 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
390 * The MAC-PHY interconnect may be in SMBus mode. If the PHY is
391 * inaccessible and resetting the PHY is not blocked, toggle the 388 * inaccessible and resetting the PHY is not blocked, toggle the
392 * LANPHYPC Value bit to force the interconnect to PCIe mode. 389 * LANPHYPC Value bit to force the interconnect to PCIe mode.
393 */ 390 */
@@ -396,8 +393,7 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
396 if (e1000_phy_is_accessible_pchlan(hw)) 393 if (e1000_phy_is_accessible_pchlan(hw))
397 break; 394 break;
398 395
399 /* 396 /* Before toggling LANPHYPC, see if PHY is accessible by
400 * Before toggling LANPHYPC, see if PHY is accessible by
401 * forcing MAC to SMBus mode first. 397 * forcing MAC to SMBus mode first.
402 */ 398 */
403 mac_reg = er32(CTRL_EXT); 399 mac_reg = er32(CTRL_EXT);
@@ -406,8 +402,7 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
406 402
407 /* fall-through */ 403 /* fall-through */
408 case e1000_pch2lan: 404 case e1000_pch2lan:
409 /* 405 /* Gate automatic PHY configuration by hardware on
410 * Gate automatic PHY configuration by hardware on
411 * non-managed 82579 406 * non-managed 82579
412 */ 407 */
413 if ((hw->mac.type == e1000_pch2lan) && 408 if ((hw->mac.type == e1000_pch2lan) &&
@@ -474,8 +469,7 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
474 469
475 hw->phy.ops.release(hw); 470 hw->phy.ops.release(hw);
476 471
477 /* 472 /* Reset the PHY before any access to it. Doing so, ensures
478 * Reset the PHY before any access to it. Doing so, ensures
479 * that the PHY is in a known good state before we read/write 473 * that the PHY is in a known good state before we read/write
480 * PHY registers. The generic reset is sufficient here, 474 * PHY registers. The generic reset is sufficient here,
481 * because we haven't determined the PHY type yet. 475 * because we haven't determined the PHY type yet.
@@ -536,8 +530,7 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
536 /* fall-through */ 530 /* fall-through */
537 case e1000_pch2lan: 531 case e1000_pch2lan:
538 case e1000_pch_lpt: 532 case e1000_pch_lpt:
539 /* 533 /* In case the PHY needs to be in mdio slow mode,
540 * In case the PHY needs to be in mdio slow mode,
541 * set slow mode and try to get the PHY id again. 534 * set slow mode and try to get the PHY id again.
542 */ 535 */
543 ret_val = e1000_set_mdio_slow_mode_hv(hw); 536 ret_val = e1000_set_mdio_slow_mode_hv(hw);
@@ -593,8 +586,7 @@ static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
593 phy->ops.power_up = e1000_power_up_phy_copper; 586 phy->ops.power_up = e1000_power_up_phy_copper;
594 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 587 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
595 588
596 /* 589 /* We may need to do this twice - once for IGP and if that fails,
597 * We may need to do this twice - once for IGP and if that fails,
598 * we'll set BM func pointers and try again 590 * we'll set BM func pointers and try again
599 */ 591 */
600 ret_val = e1000e_determine_phy_address(hw); 592 ret_val = e1000e_determine_phy_address(hw);
@@ -679,8 +671,7 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
679 671
680 gfpreg = er32flash(ICH_FLASH_GFPREG); 672 gfpreg = er32flash(ICH_FLASH_GFPREG);
681 673
682 /* 674 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
683 * sector_X_addr is a "sector"-aligned address (4096 bytes)
684 * Add 1 to sector_end_addr since this sector is included in 675 * Add 1 to sector_end_addr since this sector is included in
685 * the overall size. 676 * the overall size.
686 */ 677 */
@@ -690,8 +681,7 @@ static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
690 /* flash_base_addr is byte-aligned */ 681 /* flash_base_addr is byte-aligned */
691 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; 682 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
692 683
693 /* 684 /* find total size of the NVM, then cut in half since the total
694 * find total size of the NVM, then cut in half since the total
695 * size represents two separate NVM banks. 685 * size represents two separate NVM banks.
696 */ 686 */
697 nvm->flash_bank_size = (sector_end_addr - sector_base_addr) 687 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
@@ -788,8 +778,7 @@ static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
788 if (mac->type == e1000_ich8lan) 778 if (mac->type == e1000_ich8lan)
789 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); 779 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
790 780
791 /* 781 /* Gate automatic PHY configuration by hardware on managed
792 * Gate automatic PHY configuration by hardware on managed
793 * 82579 and i217 782 * 82579 and i217
794 */ 783 */
795 if ((mac->type == e1000_pch2lan || mac->type == e1000_pch_lpt) && 784 if ((mac->type == e1000_pch2lan || mac->type == e1000_pch_lpt) &&
@@ -840,8 +829,7 @@ static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
840 goto release; 829 goto release;
841 e1e_rphy_locked(hw, I82579_EMI_DATA, &dev_spec->eee_lp_ability); 830 e1e_rphy_locked(hw, I82579_EMI_DATA, &dev_spec->eee_lp_ability);
842 831
843 /* 832 /* EEE is not supported in 100Half, so ignore partner's EEE
844 * EEE is not supported in 100Half, so ignore partner's EEE
845 * in 100 ability if full-duplex is not advertised. 833 * in 100 ability if full-duplex is not advertised.
846 */ 834 */
847 e1e_rphy_locked(hw, PHY_LP_ABILITY, &phy_reg); 835 e1e_rphy_locked(hw, PHY_LP_ABILITY, &phy_reg);
@@ -869,8 +857,7 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
869 bool link; 857 bool link;
870 u16 phy_reg; 858 u16 phy_reg;
871 859
872 /* 860 /* We only want to go out to the PHY registers to see if Auto-Neg
873 * We only want to go out to the PHY registers to see if Auto-Neg
874 * has completed and/or if our link status has changed. The 861 * has completed and/or if our link status has changed. The
875 * get_link_status flag is set upon receiving a Link Status 862 * get_link_status flag is set upon receiving a Link Status
876 * Change or Rx Sequence Error interrupt. 863 * Change or Rx Sequence Error interrupt.
@@ -878,8 +865,7 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
878 if (!mac->get_link_status) 865 if (!mac->get_link_status)
879 return 0; 866 return 0;
880 867
881 /* 868 /* First we want to see if the MII Status Register reports
882 * First we want to see if the MII Status Register reports
883 * link. If so, then we want to get the current speed/duplex 869 * link. If so, then we want to get the current speed/duplex
884 * of the PHY. 870 * of the PHY.
885 */ 871 */
@@ -914,8 +900,7 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
914 return ret_val; 900 return ret_val;
915 } 901 }
916 902
917 /* 903 /* Workaround for PCHx parts in half-duplex:
918 * Workaround for PCHx parts in half-duplex:
919 * Set the number of preambles removed from the packet 904 * Set the number of preambles removed from the packet
920 * when it is passed from the PHY to the MAC to prevent 905 * when it is passed from the PHY to the MAC to prevent
921 * the MAC from misinterpreting the packet type. 906 * the MAC from misinterpreting the packet type.
@@ -932,8 +917,7 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
932 break; 917 break;
933 } 918 }
934 919
935 /* 920 /* Check if there was DownShift, must be checked
936 * Check if there was DownShift, must be checked
937 * immediately after link-up 921 * immediately after link-up
938 */ 922 */
939 e1000e_check_downshift(hw); 923 e1000e_check_downshift(hw);
@@ -943,22 +927,19 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
943 if (ret_val) 927 if (ret_val)
944 return ret_val; 928 return ret_val;
945 929
946 /* 930 /* If we are forcing speed/duplex, then we simply return since
947 * If we are forcing speed/duplex, then we simply return since
948 * we have already determined whether we have link or not. 931 * we have already determined whether we have link or not.
949 */ 932 */
950 if (!mac->autoneg) 933 if (!mac->autoneg)
951 return -E1000_ERR_CONFIG; 934 return -E1000_ERR_CONFIG;
952 935
953 /* 936 /* Auto-Neg is enabled. Auto Speed Detection takes care
954 * Auto-Neg is enabled. Auto Speed Detection takes care
955 * of MAC speed/duplex configuration. So we only need to 937 * of MAC speed/duplex configuration. So we only need to
956 * configure Collision Distance in the MAC. 938 * configure Collision Distance in the MAC.
957 */ 939 */
958 mac->ops.config_collision_dist(hw); 940 mac->ops.config_collision_dist(hw);
959 941
960 /* 942 /* Configure Flow Control now that Auto-Neg has completed.
961 * Configure Flow Control now that Auto-Neg has completed.
962 * First, we need to restore the desired flow control 943 * First, we need to restore the desired flow control
963 * settings because we may have had to re-autoneg with a 944 * settings because we may have had to re-autoneg with a
964 * different link partner. 945 * different link partner.
@@ -1000,8 +981,7 @@ static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1000 if (rc) 981 if (rc)
1001 return rc; 982 return rc;
1002 983
1003 /* 984 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1004 * Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1005 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT). 985 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1006 */ 986 */
1007 if ((adapter->hw.phy.type == e1000_phy_ife) || 987 if ((adapter->hw.phy.type == e1000_phy_ife) ||
@@ -1191,8 +1171,7 @@ static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1191{ 1171{
1192 u32 rar_low, rar_high; 1172 u32 rar_low, rar_high;
1193 1173
1194 /* 1174 /* HW expects these in little endian so we reverse the byte order
1195 * HW expects these in little endian so we reverse the byte order
1196 * from network order (big endian) to little endian 1175 * from network order (big endian) to little endian
1197 */ 1176 */
1198 rar_low = ((u32)addr[0] | 1177 rar_low = ((u32)addr[0] |
@@ -1256,8 +1235,7 @@ static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1256 u32 rar_low, rar_high; 1235 u32 rar_low, rar_high;
1257 u32 wlock_mac; 1236 u32 wlock_mac;
1258 1237
1259 /* 1238 /* HW expects these in little endian so we reverse the byte order
1260 * HW expects these in little endian so we reverse the byte order
1261 * from network order (big endian) to little endian 1239 * from network order (big endian) to little endian
1262 */ 1240 */
1263 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 1241 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
@@ -1277,8 +1255,7 @@ static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1277 return; 1255 return;
1278 } 1256 }
1279 1257
1280 /* 1258 /* The manageability engine (ME) can lock certain SHRAR registers that
1281 * The manageability engine (ME) can lock certain SHRAR registers that
1282 * it is using - those registers are unavailable for use. 1259 * it is using - those registers are unavailable for use.
1283 */ 1260 */
1284 if (index < hw->mac.rar_entry_count) { 1261 if (index < hw->mac.rar_entry_count) {
@@ -1387,8 +1364,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1387 s32 ret_val = 0; 1364 s32 ret_val = 0;
1388 u16 word_addr, reg_data, reg_addr, phy_page = 0; 1365 u16 word_addr, reg_data, reg_addr, phy_page = 0;
1389 1366
1390 /* 1367 /* Initialize the PHY from the NVM on ICH platforms. This
1391 * Initialize the PHY from the NVM on ICH platforms. This
1392 * is needed due to an issue where the NVM configuration is 1368 * is needed due to an issue where the NVM configuration is
1393 * not properly autoloaded after power transitions. 1369 * not properly autoloaded after power transitions.
1394 * Therefore, after each PHY reset, we will load the 1370 * Therefore, after each PHY reset, we will load the
@@ -1422,8 +1398,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1422 if (!(data & sw_cfg_mask)) 1398 if (!(data & sw_cfg_mask))
1423 goto release; 1399 goto release;
1424 1400
1425 /* 1401 /* Make sure HW does not configure LCD from PHY
1426 * Make sure HW does not configure LCD from PHY
1427 * extended configuration before SW configuration 1402 * extended configuration before SW configuration
1428 */ 1403 */
1429 data = er32(EXTCNF_CTRL); 1404 data = er32(EXTCNF_CTRL);
@@ -1443,8 +1418,7 @@ static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1443 if (((hw->mac.type == e1000_pchlan) && 1418 if (((hw->mac.type == e1000_pchlan) &&
1444 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || 1419 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
1445 (hw->mac.type > e1000_pchlan)) { 1420 (hw->mac.type > e1000_pchlan)) {
1446 /* 1421 /* HW configures the SMBus address and LEDs when the
1447 * HW configures the SMBus address and LEDs when the
1448 * OEM and LCD Write Enable bits are set in the NVM. 1422 * OEM and LCD Write Enable bits are set in the NVM.
1449 * When both NVM bits are cleared, SW will configure 1423 * When both NVM bits are cleared, SW will configure
1450 * them instead. 1424 * them instead.
@@ -1748,8 +1722,7 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1748 } 1722 }
1749 1723
1750 if (hw->phy.type == e1000_phy_82578) { 1724 if (hw->phy.type == e1000_phy_82578) {
1751 /* 1725 /* Return registers to default by doing a soft reset then
1752 * Return registers to default by doing a soft reset then
1753 * writing 0x3140 to the control register. 1726 * writing 0x3140 to the control register.
1754 */ 1727 */
1755 if (hw->phy.revision < 2) { 1728 if (hw->phy.revision < 2) {
@@ -1769,8 +1742,7 @@ static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1769 if (ret_val) 1742 if (ret_val)
1770 return ret_val; 1743 return ret_val;
1771 1744
1772 /* 1745 /* Configure the K1 Si workaround during phy reset assuming there is
1773 * Configure the K1 Si workaround during phy reset assuming there is
1774 * link so that it disables K1 if link is in 1Gbps. 1746 * link so that it disables K1 if link is in 1Gbps.
1775 */ 1747 */
1776 ret_val = e1000_k1_gig_workaround_hv(hw, true); 1748 ret_val = e1000_k1_gig_workaround_hv(hw, true);
@@ -1853,8 +1825,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1853 return ret_val; 1825 return ret_val;
1854 1826
1855 if (enable) { 1827 if (enable) {
1856 /* 1828 /* Write Rx addresses (rar_entry_count for RAL/H, +4 for
1857 * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1858 * SHRAL/H) and initial CRC values to the MAC 1829 * SHRAL/H) and initial CRC values to the MAC
1859 */ 1830 */
1860 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) { 1831 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
@@ -2131,8 +2102,7 @@ static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2131 udelay(100); 2102 udelay(100);
2132 } while ((!data) && --loop); 2103 } while ((!data) && --loop);
2133 2104
2134 /* 2105 /* If basic configuration is incomplete before the above loop
2135 * If basic configuration is incomplete before the above loop
2136 * count reaches 0, loading the configuration from NVM will 2106 * count reaches 0, loading the configuration from NVM will
2137 * leave the PHY in a bad state possibly resulting in no link. 2107 * leave the PHY in a bad state possibly resulting in no link.
2138 */ 2108 */
@@ -2299,8 +2269,7 @@ static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2299 if (phy->type != e1000_phy_igp_3) 2269 if (phy->type != e1000_phy_igp_3)
2300 return 0; 2270 return 0;
2301 2271
2302 /* 2272 /* Call gig speed drop workaround on LPLU before accessing
2303 * Call gig speed drop workaround on LPLU before accessing
2304 * any PHY registers 2273 * any PHY registers
2305 */ 2274 */
2306 if (hw->mac.type == e1000_ich8lan) 2275 if (hw->mac.type == e1000_ich8lan)
@@ -2319,8 +2288,7 @@ static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2319 if (phy->type != e1000_phy_igp_3) 2288 if (phy->type != e1000_phy_igp_3)
2320 return 0; 2289 return 0;
2321 2290
2322 /* 2291 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2323 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
2324 * during Dx states where the power conservation is most 2292 * during Dx states where the power conservation is most
2325 * important. During driver activity we should enable 2293 * important. During driver activity we should enable
2326 * SmartSpeed, so performance is maintained. 2294 * SmartSpeed, so performance is maintained.
@@ -2382,8 +2350,7 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2382 if (phy->type != e1000_phy_igp_3) 2350 if (phy->type != e1000_phy_igp_3)
2383 return 0; 2351 return 0;
2384 2352
2385 /* 2353 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2386 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
2387 * during Dx states where the power conservation is most 2354 * during Dx states where the power conservation is most
2388 * important. During driver activity we should enable 2355 * important. During driver activity we should enable
2389 * SmartSpeed, so performance is maintained. 2356 * SmartSpeed, so performance is maintained.
@@ -2420,8 +2387,7 @@ static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2420 if (phy->type != e1000_phy_igp_3) 2387 if (phy->type != e1000_phy_igp_3)
2421 return 0; 2388 return 0;
2422 2389
2423 /* 2390 /* Call gig speed drop workaround on LPLU before accessing
2424 * Call gig speed drop workaround on LPLU before accessing
2425 * any PHY registers 2391 * any PHY registers
2426 */ 2392 */
2427 if (hw->mac.type == e1000_ich8lan) 2393 if (hw->mac.type == e1000_ich8lan)
@@ -2589,8 +2555,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2589 2555
2590 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 2556 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2591 2557
2592 /* 2558 /* Either we should have a hardware SPI cycle in progress
2593 * Either we should have a hardware SPI cycle in progress
2594 * bit to check against, in order to start a new cycle or 2559 * bit to check against, in order to start a new cycle or
2595 * FDONE bit should be changed in the hardware so that it 2560 * FDONE bit should be changed in the hardware so that it
2596 * is 1 after hardware reset, which can then be used as an 2561 * is 1 after hardware reset, which can then be used as an
@@ -2599,8 +2564,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2599 */ 2564 */
2600 2565
2601 if (!hsfsts.hsf_status.flcinprog) { 2566 if (!hsfsts.hsf_status.flcinprog) {
2602 /* 2567 /* There is no cycle running at present,
2603 * There is no cycle running at present,
2604 * so we can start a cycle. 2568 * so we can start a cycle.
2605 * Begin by setting Flash Cycle Done. 2569 * Begin by setting Flash Cycle Done.
2606 */ 2570 */
@@ -2610,8 +2574,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2610 } else { 2574 } else {
2611 s32 i; 2575 s32 i;
2612 2576
2613 /* 2577 /* Otherwise poll for sometime so the current
2614 * Otherwise poll for sometime so the current
2615 * cycle has a chance to end before giving up. 2578 * cycle has a chance to end before giving up.
2616 */ 2579 */
2617 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 2580 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
@@ -2623,8 +2586,7 @@ static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2623 udelay(1); 2586 udelay(1);
2624 } 2587 }
2625 if (!ret_val) { 2588 if (!ret_val) {
2626 /* 2589 /* Successful in waiting for previous cycle to timeout,
2627 * Successful in waiting for previous cycle to timeout,
2628 * now set the Flash Cycle Done. 2590 * now set the Flash Cycle Done.
2629 */ 2591 */
2630 hsfsts.hsf_status.flcdone = 1; 2592 hsfsts.hsf_status.flcdone = 1;
@@ -2753,8 +2715,7 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2753 ret_val = e1000_flash_cycle_ich8lan(hw, 2715 ret_val = e1000_flash_cycle_ich8lan(hw,
2754 ICH_FLASH_READ_COMMAND_TIMEOUT); 2716 ICH_FLASH_READ_COMMAND_TIMEOUT);
2755 2717
2756 /* 2718 /* Check if FCERR is set to 1, if set to 1, clear it
2757 * Check if FCERR is set to 1, if set to 1, clear it
2758 * and try the whole sequence a few more times, else 2719 * and try the whole sequence a few more times, else
2759 * read in (shift in) the Flash Data0, the order is 2720 * read in (shift in) the Flash Data0, the order is
2760 * least significant byte first msb to lsb 2721 * least significant byte first msb to lsb
@@ -2767,8 +2728,7 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2767 *data = (u16)(flash_data & 0x0000FFFF); 2728 *data = (u16)(flash_data & 0x0000FFFF);
2768 break; 2729 break;
2769 } else { 2730 } else {
2770 /* 2731 /* If we've gotten here, then things are probably
2771 * If we've gotten here, then things are probably
2772 * completely hosed, but if the error condition is 2732 * completely hosed, but if the error condition is
2773 * detected, it won't hurt to give it another try... 2733 * detected, it won't hurt to give it another try...
2774 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 2734 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
@@ -2849,8 +2809,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2849 2809
2850 nvm->ops.acquire(hw); 2810 nvm->ops.acquire(hw);
2851 2811
2852 /* 2812 /* We're writing to the opposite bank so if we're on bank 1,
2853 * We're writing to the opposite bank so if we're on bank 1,
2854 * write to bank 0 etc. We also need to erase the segment that 2813 * write to bank 0 etc. We also need to erase the segment that
2855 * is going to be written 2814 * is going to be written
2856 */ 2815 */
@@ -2875,8 +2834,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2875 } 2834 }
2876 2835
2877 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 2836 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2878 /* 2837 /* Determine whether to write the value stored
2879 * Determine whether to write the value stored
2880 * in the other NVM bank or a modified value stored 2838 * in the other NVM bank or a modified value stored
2881 * in the shadow RAM 2839 * in the shadow RAM
2882 */ 2840 */
@@ -2890,8 +2848,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2890 break; 2848 break;
2891 } 2849 }
2892 2850
2893 /* 2851 /* If the word is 0x13, then make sure the signature bits
2894 * If the word is 0x13, then make sure the signature bits
2895 * (15:14) are 11b until the commit has completed. 2852 * (15:14) are 11b until the commit has completed.
2896 * This will allow us to write 10b which indicates the 2853 * This will allow us to write 10b which indicates the
2897 * signature is valid. We want to do this after the write 2854 * signature is valid. We want to do this after the write
@@ -2920,8 +2877,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2920 break; 2877 break;
2921 } 2878 }
2922 2879
2923 /* 2880 /* Don't bother writing the segment valid bits if sector
2924 * Don't bother writing the segment valid bits if sector
2925 * programming failed. 2881 * programming failed.
2926 */ 2882 */
2927 if (ret_val) { 2883 if (ret_val) {
@@ -2930,8 +2886,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2930 goto release; 2886 goto release;
2931 } 2887 }
2932 2888
2933 /* 2889 /* Finally validate the new segment by setting bit 15:14
2934 * Finally validate the new segment by setting bit 15:14
2935 * to 10b in word 0x13 , this can be done without an 2890 * to 10b in word 0x13 , this can be done without an
2936 * erase as well since these bits are 11 to start with 2891 * erase as well since these bits are 11 to start with
2937 * and we need to change bit 14 to 0b 2892 * and we need to change bit 14 to 0b
@@ -2948,8 +2903,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2948 if (ret_val) 2903 if (ret_val)
2949 goto release; 2904 goto release;
2950 2905
2951 /* 2906 /* And invalidate the previously valid segment by setting
2952 * And invalidate the previously valid segment by setting
2953 * its signature word (0x13) high_byte to 0b. This can be 2907 * its signature word (0x13) high_byte to 0b. This can be
2954 * done without an erase because flash erase sets all bits 2908 * done without an erase because flash erase sets all bits
2955 * to 1's. We can write 1's to 0's without an erase 2909 * to 1's. We can write 1's to 0's without an erase
@@ -2968,8 +2922,7 @@ static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2968release: 2922release:
2969 nvm->ops.release(hw); 2923 nvm->ops.release(hw);
2970 2924
2971 /* 2925 /* Reload the EEPROM, or else modifications will not appear
2972 * Reload the EEPROM, or else modifications will not appear
2973 * until after the next adapter reset. 2926 * until after the next adapter reset.
2974 */ 2927 */
2975 if (!ret_val) { 2928 if (!ret_val) {
@@ -2997,8 +2950,7 @@ static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2997 s32 ret_val; 2950 s32 ret_val;
2998 u16 data; 2951 u16 data;
2999 2952
3000 /* 2953 /* Read 0x19 and check bit 6. If this bit is 0, the checksum
3001 * Read 0x19 and check bit 6. If this bit is 0, the checksum
3002 * needs to be fixed. This bit is an indication that the NVM 2954 * needs to be fixed. This bit is an indication that the NVM
3003 * was prepared by OEM software and did not calculate the 2955 * was prepared by OEM software and did not calculate the
3004 * checksum...a likely scenario. 2956 * checksum...a likely scenario.
@@ -3048,8 +3000,7 @@ void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
3048 pr0.range.wpe = true; 3000 pr0.range.wpe = true;
3049 ew32flash(ICH_FLASH_PR0, pr0.regval); 3001 ew32flash(ICH_FLASH_PR0, pr0.regval);
3050 3002
3051 /* 3003 /* Lock down a subset of GbE Flash Control Registers, e.g.
3052 * Lock down a subset of GbE Flash Control Registers, e.g.
3053 * PR0 to prevent the write-protection from being lifted. 3004 * PR0 to prevent the write-protection from being lifted.
3054 * Once FLOCKDN is set, the registers protected by it cannot 3005 * Once FLOCKDN is set, the registers protected by it cannot
3055 * be written until FLOCKDN is cleared by a hardware reset. 3006 * be written until FLOCKDN is cleared by a hardware reset.
@@ -3109,8 +3060,7 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3109 3060
3110 ew32flash(ICH_FLASH_FDATA0, flash_data); 3061 ew32flash(ICH_FLASH_FDATA0, flash_data);
3111 3062
3112 /* 3063 /* check if FCERR is set to 1 , if set to 1, clear it
3113 * check if FCERR is set to 1 , if set to 1, clear it
3114 * and try the whole sequence a few more times else done 3064 * and try the whole sequence a few more times else done
3115 */ 3065 */
3116 ret_val = e1000_flash_cycle_ich8lan(hw, 3066 ret_val = e1000_flash_cycle_ich8lan(hw,
@@ -3118,8 +3068,7 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3118 if (!ret_val) 3068 if (!ret_val)
3119 break; 3069 break;
3120 3070
3121 /* 3071 /* If we're here, then things are most likely
3122 * If we're here, then things are most likely
3123 * completely hosed, but if the error condition 3072 * completely hosed, but if the error condition
3124 * is detected, it won't hurt to give it another 3073 * is detected, it won't hurt to give it another
3125 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 3074 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
@@ -3207,8 +3156,7 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3207 3156
3208 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3157 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3209 3158
3210 /* 3159 /* Determine HW Sector size: Read BERASE bits of hw flash status
3211 * Determine HW Sector size: Read BERASE bits of hw flash status
3212 * register 3160 * register
3213 * 00: The Hw sector is 256 bytes, hence we need to erase 16 3161 * 00: The Hw sector is 256 bytes, hence we need to erase 16
3214 * consecutive sectors. The start index for the nth Hw sector 3162 * consecutive sectors. The start index for the nth Hw sector
@@ -3253,16 +3201,14 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3253 if (ret_val) 3201 if (ret_val)
3254 return ret_val; 3202 return ret_val;
3255 3203
3256 /* 3204 /* Write a value 11 (block Erase) in Flash
3257 * Write a value 11 (block Erase) in Flash
3258 * Cycle field in hw flash control 3205 * Cycle field in hw flash control
3259 */ 3206 */
3260 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3207 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3261 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 3208 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3262 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3209 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3263 3210
3264 /* 3211 /* Write the last 24 bits of an index within the
3265 * Write the last 24 bits of an index within the
3266 * block into Flash Linear address field in Flash 3212 * block into Flash Linear address field in Flash
3267 * Address. 3213 * Address.
3268 */ 3214 */
@@ -3274,8 +3220,7 @@ static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3274 if (!ret_val) 3220 if (!ret_val)
3275 break; 3221 break;
3276 3222
3277 /* 3223 /* Check if FCERR is set to 1. If 1,
3278 * Check if FCERR is set to 1. If 1,
3279 * clear it and try the whole sequence 3224 * clear it and try the whole sequence
3280 * a few more times else Done 3225 * a few more times else Done
3281 */ 3226 */
@@ -3403,8 +3348,7 @@ static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3403 3348
3404 ret_val = e1000e_get_bus_info_pcie(hw); 3349 ret_val = e1000e_get_bus_info_pcie(hw);
3405 3350
3406 /* 3351 /* ICH devices are "PCI Express"-ish. They have
3407 * ICH devices are "PCI Express"-ish. They have
3408 * a configuration space, but do not contain 3352 * a configuration space, but do not contain
3409 * PCI Express Capability registers, so bus width 3353 * PCI Express Capability registers, so bus width
3410 * must be hardcoded. 3354 * must be hardcoded.
@@ -3429,8 +3373,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3429 u32 ctrl, reg; 3373 u32 ctrl, reg;
3430 s32 ret_val; 3374 s32 ret_val;
3431 3375
3432 /* 3376 /* Prevent the PCI-E bus from sticking if there is no TLP connection
3433 * Prevent the PCI-E bus from sticking if there is no TLP connection
3434 * on the last TLP read/write transaction when MAC is reset. 3377 * on the last TLP read/write transaction when MAC is reset.
3435 */ 3378 */
3436 ret_val = e1000e_disable_pcie_master(hw); 3379 ret_val = e1000e_disable_pcie_master(hw);
@@ -3440,8 +3383,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3440 e_dbg("Masking off all interrupts\n"); 3383 e_dbg("Masking off all interrupts\n");
3441 ew32(IMC, 0xffffffff); 3384 ew32(IMC, 0xffffffff);
3442 3385
3443 /* 3386 /* Disable the Transmit and Receive units. Then delay to allow
3444 * Disable the Transmit and Receive units. Then delay to allow
3445 * any pending transactions to complete before we hit the MAC 3387 * any pending transactions to complete before we hit the MAC
3446 * with the global reset. 3388 * with the global reset.
3447 */ 3389 */
@@ -3474,15 +3416,13 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3474 ctrl = er32(CTRL); 3416 ctrl = er32(CTRL);
3475 3417
3476 if (!hw->phy.ops.check_reset_block(hw)) { 3418 if (!hw->phy.ops.check_reset_block(hw)) {
3477 /* 3419 /* Full-chip reset requires MAC and PHY reset at the same
3478 * Full-chip reset requires MAC and PHY reset at the same
3479 * time to make sure the interface between MAC and the 3420 * time to make sure the interface between MAC and the
3480 * external PHY is reset. 3421 * external PHY is reset.
3481 */ 3422 */
3482 ctrl |= E1000_CTRL_PHY_RST; 3423 ctrl |= E1000_CTRL_PHY_RST;
3483 3424
3484 /* 3425 /* Gate automatic PHY configuration by hardware on
3485 * Gate automatic PHY configuration by hardware on
3486 * non-managed 82579 3426 * non-managed 82579
3487 */ 3427 */
3488 if ((hw->mac.type == e1000_pch2lan) && 3428 if ((hw->mac.type == e1000_pch2lan) &&
@@ -3516,8 +3456,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3516 return ret_val; 3456 return ret_val;
3517 } 3457 }
3518 3458
3519 /* 3459 /* For PCH, this write will make sure that any noise
3520 * For PCH, this write will make sure that any noise
3521 * will be detected as a CRC error and be dropped rather than show up 3460 * will be detected as a CRC error and be dropped rather than show up
3522 * as a bad packet to the DMA engine. 3461 * as a bad packet to the DMA engine.
3523 */ 3462 */
@@ -3569,8 +3508,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3569 for (i = 0; i < mac->mta_reg_count; i++) 3508 for (i = 0; i < mac->mta_reg_count; i++)
3570 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 3509 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3571 3510
3572 /* 3511 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
3573 * The 82578 Rx buffer will stall if wakeup is enabled in host and
3574 * the ME. Disable wakeup by clearing the host wakeup bit. 3512 * the ME. Disable wakeup by clearing the host wakeup bit.
3575 * Reset the phy after disabling host wakeup to reset the Rx buffer. 3513 * Reset the phy after disabling host wakeup to reset the Rx buffer.
3576 */ 3514 */
@@ -3600,8 +3538,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3600 E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 3538 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3601 ew32(TXDCTL(1), txdctl); 3539 ew32(TXDCTL(1), txdctl);
3602 3540
3603 /* 3541 /* ICH8 has opposite polarity of no_snoop bits.
3604 * ICH8 has opposite polarity of no_snoop bits.
3605 * By default, we should use snoop behavior. 3542 * By default, we should use snoop behavior.
3606 */ 3543 */
3607 if (mac->type == e1000_ich8lan) 3544 if (mac->type == e1000_ich8lan)
@@ -3614,8 +3551,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3614 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 3551 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3615 ew32(CTRL_EXT, ctrl_ext); 3552 ew32(CTRL_EXT, ctrl_ext);
3616 3553
3617 /* 3554 /* Clear all of the statistics registers (clear on read). It is
3618 * Clear all of the statistics registers (clear on read). It is
3619 * important that we do this after we have tried to establish link 3555 * important that we do this after we have tried to establish link
3620 * because the symbol error count will increment wildly if there 3556 * because the symbol error count will increment wildly if there
3621 * is no link. 3557 * is no link.
@@ -3676,15 +3612,13 @@ static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3676 ew32(STATUS, reg); 3612 ew32(STATUS, reg);
3677 } 3613 }
3678 3614
3679 /* 3615 /* work-around descriptor data corruption issue during nfs v2 udp
3680 * work-around descriptor data corruption issue during nfs v2 udp
3681 * traffic, just disable the nfs filtering capability 3616 * traffic, just disable the nfs filtering capability
3682 */ 3617 */
3683 reg = er32(RFCTL); 3618 reg = er32(RFCTL);
3684 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); 3619 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3685 3620
3686 /* 3621 /* Disable IPv6 extension header parsing because some malformed
3687 * Disable IPv6 extension header parsing because some malformed
3688 * IPv6 headers can hang the Rx. 3622 * IPv6 headers can hang the Rx.
3689 */ 3623 */
3690 if (hw->mac.type == e1000_ich8lan) 3624 if (hw->mac.type == e1000_ich8lan)
@@ -3709,8 +3643,7 @@ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3709 if (hw->phy.ops.check_reset_block(hw)) 3643 if (hw->phy.ops.check_reset_block(hw))
3710 return 0; 3644 return 0;
3711 3645
3712 /* 3646 /* ICH parts do not have a word in the NVM to determine
3713 * ICH parts do not have a word in the NVM to determine
3714 * the default flow control setting, so we explicitly 3647 * the default flow control setting, so we explicitly
3715 * set it to full. 3648 * set it to full.
3716 */ 3649 */
@@ -3722,8 +3655,7 @@ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3722 hw->fc.requested_mode = e1000_fc_full; 3655 hw->fc.requested_mode = e1000_fc_full;
3723 } 3656 }
3724 3657
3725 /* 3658 /* Save off the requested flow control mode for use later. Depending
3726 * Save off the requested flow control mode for use later. Depending
3727 * on the link partner's capabilities, we may or may not use this mode. 3659 * on the link partner's capabilities, we may or may not use this mode.
3728 */ 3660 */
3729 hw->fc.current_mode = hw->fc.requested_mode; 3661 hw->fc.current_mode = hw->fc.requested_mode;
@@ -3771,8 +3703,7 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3771 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 3703 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3772 ew32(CTRL, ctrl); 3704 ew32(CTRL, ctrl);
3773 3705
3774 /* 3706 /* Set the mac to wait the maximum time between each iteration
3775 * Set the mac to wait the maximum time between each iteration
3776 * and increase the max iterations when polling the phy; 3707 * and increase the max iterations when polling the phy;
3777 * this fixes erroneous timeouts at 10Mbps. 3708 * this fixes erroneous timeouts at 10Mbps.
3778 */ 3709 */
@@ -3892,8 +3823,7 @@ static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3892 if (!dev_spec->kmrn_lock_loss_workaround_enabled) 3823 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3893 return 0; 3824 return 0;
3894 3825
3895 /* 3826 /* Make sure link is up before proceeding. If not just return.
3896 * Make sure link is up before proceeding. If not just return.
3897 * Attempting this while link is negotiating fouled up link 3827 * Attempting this while link is negotiating fouled up link
3898 * stability 3828 * stability
3899 */ 3829 */
@@ -3925,8 +3855,7 @@ static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3925 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 3855 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3926 ew32(PHY_CTRL, phy_ctrl); 3856 ew32(PHY_CTRL, phy_ctrl);
3927 3857
3928 /* 3858 /* Call gig speed drop workaround on Gig disable before accessing
3929 * Call gig speed drop workaround on Gig disable before accessing
3930 * any PHY registers 3859 * any PHY registers
3931 */ 3860 */
3932 e1000e_gig_downshift_workaround_ich8lan(hw); 3861 e1000e_gig_downshift_workaround_ich8lan(hw);
@@ -3983,8 +3912,7 @@ void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3983 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 3912 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3984 ew32(PHY_CTRL, reg); 3913 ew32(PHY_CTRL, reg);
3985 3914
3986 /* 3915 /* Call gig speed drop workaround on Gig disable before
3987 * Call gig speed drop workaround on Gig disable before
3988 * accessing any PHY registers 3916 * accessing any PHY registers
3989 */ 3917 */
3990 if (hw->mac.type == e1000_ich8lan) 3918 if (hw->mac.type == e1000_ich8lan)
@@ -4078,8 +4006,7 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4078 goto release; 4006 goto release;
4079 e1e_rphy_locked(hw, I82579_EMI_DATA, &eee_advert); 4007 e1e_rphy_locked(hw, I82579_EMI_DATA, &eee_advert);
4080 4008
4081 /* 4009 /* Disable LPLU if both link partners support 100BaseT
4082 * Disable LPLU if both link partners support 100BaseT
4083 * EEE and 100Full is advertised on both ends of the 4010 * EEE and 100Full is advertised on both ends of the
4084 * link. 4011 * link.
4085 */ 4012 */
@@ -4091,8 +4018,7 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4091 E1000_PHY_CTRL_NOND0A_LPLU); 4018 E1000_PHY_CTRL_NOND0A_LPLU);
4092 } 4019 }
4093 4020
4094 /* 4021 /* For i217 Intel Rapid Start Technology support,
4095 * For i217 Intel Rapid Start Technology support,
4096 * when the system is going into Sx and no manageability engine 4022 * when the system is going into Sx and no manageability engine
4097 * is present, the driver must configure proxy to reset only on 4023 * is present, the driver must configure proxy to reset only on
4098 * power good. LPI (Low Power Idle) state must also reset only 4024 * power good. LPI (Low Power Idle) state must also reset only
@@ -4106,8 +4032,7 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4106 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; 4032 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4107 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg); 4033 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
4108 4034
4109 /* 4035 /* Set bit enable LPI (EEE) to reset only on
4110 * Set bit enable LPI (EEE) to reset only on
4111 * power good. 4036 * power good.
4112 */ 4037 */
4113 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg); 4038 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
@@ -4120,8 +4045,7 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4120 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 4045 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4121 } 4046 }
4122 4047
4123 /* 4048 /* Enable MTA to reset for Intel Rapid Start Technology
4124 * Enable MTA to reset for Intel Rapid Start Technology
4125 * Support 4049 * Support
4126 */ 4050 */
4127 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 4051 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
@@ -4175,8 +4099,7 @@ void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4175 return; 4099 return;
4176 } 4100 }
4177 4101
4178 /* 4102 /* For i217 Intel Rapid Start Technology support when the system
4179 * For i217 Intel Rapid Start Technology support when the system
4180 * is transitioning from Sx and no manageability engine is present 4103 * is transitioning from Sx and no manageability engine is present
4181 * configure SMBus to restore on reset, disable proxy, and enable 4104 * configure SMBus to restore on reset, disable proxy, and enable
4182 * the reset on MTA (Multicast table array). 4105 * the reset on MTA (Multicast table array).
@@ -4191,8 +4114,7 @@ void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4191 } 4114 }
4192 4115
4193 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 4116 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4194 /* 4117 /* Restore clear on SMB if no manageability engine
4195 * Restore clear on SMB if no manageability engine
4196 * is present 4118 * is present
4197 */ 4119 */
4198 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 4120 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
@@ -4298,8 +4220,7 @@ static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
4298 u16 data = (u16)hw->mac.ledctl_mode2; 4220 u16 data = (u16)hw->mac.ledctl_mode2;
4299 u32 i, led; 4221 u32 i, led;
4300 4222
4301 /* 4223 /* If no link, then turn LED on by setting the invert bit
4302 * If no link, then turn LED on by setting the invert bit
4303 * for each LED that's mode is "link_up" in ledctl_mode2. 4224 * for each LED that's mode is "link_up" in ledctl_mode2.
4304 */ 4225 */
4305 if (!(er32(STATUS) & E1000_STATUS_LU)) { 4226 if (!(er32(STATUS) & E1000_STATUS_LU)) {
@@ -4329,8 +4250,7 @@ static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
4329 u16 data = (u16)hw->mac.ledctl_mode1; 4250 u16 data = (u16)hw->mac.ledctl_mode1;
4330 u32 i, led; 4251 u32 i, led;
4331 4252
4332 /* 4253 /* If no link, then turn LED off by clearing the invert bit
4333 * If no link, then turn LED off by clearing the invert bit
4334 * for each LED that's mode is "link_up" in ledctl_mode1. 4254 * for each LED that's mode is "link_up" in ledctl_mode1.
4335 */ 4255 */
4336 if (!(er32(STATUS) & E1000_STATUS_LU)) { 4256 if (!(er32(STATUS) & E1000_STATUS_LU)) {
@@ -4375,8 +4295,7 @@ static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
4375 } else { 4295 } else {
4376 ret_val = e1000e_get_auto_rd_done(hw); 4296 ret_val = e1000e_get_auto_rd_done(hw);
4377 if (ret_val) { 4297 if (ret_val) {
4378 /* 4298 /* When auto config read does not complete, do not
4379 * When auto config read does not complete, do not
4380 * return with an error. This can happen in situations 4299 * return with an error. This can happen in situations
4381 * where there is no eeprom and prevents getting link. 4300 * where there is no eeprom and prevents getting link.
4382 */ 4301 */
diff --git a/drivers/net/ethernet/intel/e1000e/mac.c b/drivers/net/ethernet/intel/e1000e/mac.c
index a13439928488..54d9dafaf126 100644
--- a/drivers/net/ethernet/intel/e1000e/mac.c
+++ b/drivers/net/ethernet/intel/e1000e/mac.c
@@ -73,8 +73,7 @@ void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
73 struct e1000_bus_info *bus = &hw->bus; 73 struct e1000_bus_info *bus = &hw->bus;
74 u32 reg; 74 u32 reg;
75 75
76 /* 76 /* The status register reports the correct function number
77 * The status register reports the correct function number
78 * for the device regardless of function swap state. 77 * for the device regardless of function swap state.
79 */ 78 */
80 reg = er32(STATUS); 79 reg = er32(STATUS);
@@ -210,8 +209,7 @@ s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
210 return 0; 209 return 0;
211 } 210 }
212 211
213 /* 212 /* We have a valid alternate MAC address, and we want to treat it the
214 * We have a valid alternate MAC address, and we want to treat it the
215 * same as the normal permanent MAC address stored by the HW into the 213 * same as the normal permanent MAC address stored by the HW into the
216 * RAR. Do this by mapping this address into RAR0. 214 * RAR. Do this by mapping this address into RAR0.
217 */ 215 */
@@ -233,8 +231,7 @@ void e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
233{ 231{
234 u32 rar_low, rar_high; 232 u32 rar_low, rar_high;
235 233
236 /* 234 /* HW expects these in little endian so we reverse the byte order
237 * HW expects these in little endian so we reverse the byte order
238 * from network order (big endian) to little endian 235 * from network order (big endian) to little endian
239 */ 236 */
240 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 237 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
@@ -246,8 +243,7 @@ void e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
246 if (rar_low || rar_high) 243 if (rar_low || rar_high)
247 rar_high |= E1000_RAH_AV; 244 rar_high |= E1000_RAH_AV;
248 245
249 /* 246 /* Some bridges will combine consecutive 32-bit writes into
250 * Some bridges will combine consecutive 32-bit writes into
251 * a single burst write, which will malfunction on some parts. 247 * a single burst write, which will malfunction on some parts.
252 * The flushes avoid this. 248 * The flushes avoid this.
253 */ 249 */
@@ -273,15 +269,13 @@ static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
273 /* Register count multiplied by bits per register */ 269 /* Register count multiplied by bits per register */
274 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 270 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
275 271
276 /* 272 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
277 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
278 * where 0xFF would still fall within the hash mask. 273 * where 0xFF would still fall within the hash mask.
279 */ 274 */
280 while (hash_mask >> bit_shift != 0xFF) 275 while (hash_mask >> bit_shift != 0xFF)
281 bit_shift++; 276 bit_shift++;
282 277
283 /* 278 /* The portion of the address that is used for the hash table
284 * The portion of the address that is used for the hash table
285 * is determined by the mc_filter_type setting. 279 * is determined by the mc_filter_type setting.
286 * The algorithm is such that there is a total of 8 bits of shifting. 280 * The algorithm is such that there is a total of 8 bits of shifting.
287 * The bit_shift for a mc_filter_type of 0 represents the number of 281 * The bit_shift for a mc_filter_type of 0 represents the number of
@@ -423,8 +417,7 @@ s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
423 s32 ret_val; 417 s32 ret_val;
424 bool link; 418 bool link;
425 419
426 /* 420 /* We only want to go out to the PHY registers to see if Auto-Neg
427 * We only want to go out to the PHY registers to see if Auto-Neg
428 * has completed and/or if our link status has changed. The 421 * has completed and/or if our link status has changed. The
429 * get_link_status flag is set upon receiving a Link Status 422 * get_link_status flag is set upon receiving a Link Status
430 * Change or Rx Sequence Error interrupt. 423 * Change or Rx Sequence Error interrupt.
@@ -432,8 +425,7 @@ s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
432 if (!mac->get_link_status) 425 if (!mac->get_link_status)
433 return 0; 426 return 0;
434 427
435 /* 428 /* First we want to see if the MII Status Register reports
436 * First we want to see if the MII Status Register reports
437 * link. If so, then we want to get the current speed/duplex 429 * link. If so, then we want to get the current speed/duplex
438 * of the PHY. 430 * of the PHY.
439 */ 431 */
@@ -446,28 +438,24 @@ s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
446 438
447 mac->get_link_status = false; 439 mac->get_link_status = false;
448 440
449 /* 441 /* Check if there was DownShift, must be checked
450 * Check if there was DownShift, must be checked
451 * immediately after link-up 442 * immediately after link-up
452 */ 443 */
453 e1000e_check_downshift(hw); 444 e1000e_check_downshift(hw);
454 445
455 /* 446 /* If we are forcing speed/duplex, then we simply return since
456 * If we are forcing speed/duplex, then we simply return since
457 * we have already determined whether we have link or not. 447 * we have already determined whether we have link or not.
458 */ 448 */
459 if (!mac->autoneg) 449 if (!mac->autoneg)
460 return -E1000_ERR_CONFIG; 450 return -E1000_ERR_CONFIG;
461 451
462 /* 452 /* Auto-Neg is enabled. Auto Speed Detection takes care
463 * Auto-Neg is enabled. Auto Speed Detection takes care
464 * of MAC speed/duplex configuration. So we only need to 453 * of MAC speed/duplex configuration. So we only need to
465 * configure Collision Distance in the MAC. 454 * configure Collision Distance in the MAC.
466 */ 455 */
467 mac->ops.config_collision_dist(hw); 456 mac->ops.config_collision_dist(hw);
468 457
469 /* 458 /* Configure Flow Control now that Auto-Neg has completed.
470 * Configure Flow Control now that Auto-Neg has completed.
471 * First, we need to restore the desired flow control 459 * First, we need to restore the desired flow control
472 * settings because we may have had to re-autoneg with a 460 * settings because we may have had to re-autoneg with a
473 * different link partner. 461 * different link partner.
@@ -498,8 +486,7 @@ s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
498 status = er32(STATUS); 486 status = er32(STATUS);
499 rxcw = er32(RXCW); 487 rxcw = er32(RXCW);
500 488
501 /* 489 /* If we don't have link (auto-negotiation failed or link partner
502 * If we don't have link (auto-negotiation failed or link partner
503 * cannot auto-negotiate), the cable is plugged in (we have signal), 490 * cannot auto-negotiate), the cable is plugged in (we have signal),
504 * and our link partner is not trying to auto-negotiate with us (we 491 * and our link partner is not trying to auto-negotiate with us (we
505 * are receiving idles or data), we need to force link up. We also 492 * are receiving idles or data), we need to force link up. We also
@@ -530,8 +517,7 @@ s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
530 return ret_val; 517 return ret_val;
531 } 518 }
532 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 519 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
533 /* 520 /* If we are forcing link and we are receiving /C/ ordered
534 * If we are forcing link and we are receiving /C/ ordered
535 * sets, re-enable auto-negotiation in the TXCW register 521 * sets, re-enable auto-negotiation in the TXCW register
536 * and disable forced link in the Device Control register 522 * and disable forced link in the Device Control register
537 * in an attempt to auto-negotiate with our link partner. 523 * in an attempt to auto-negotiate with our link partner.
@@ -565,8 +551,7 @@ s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
565 status = er32(STATUS); 551 status = er32(STATUS);
566 rxcw = er32(RXCW); 552 rxcw = er32(RXCW);
567 553
568 /* 554 /* If we don't have link (auto-negotiation failed or link partner
569 * If we don't have link (auto-negotiation failed or link partner
570 * cannot auto-negotiate), and our link partner is not trying to 555 * cannot auto-negotiate), and our link partner is not trying to
571 * auto-negotiate with us (we are receiving idles or data), 556 * auto-negotiate with us (we are receiving idles or data),
572 * we need to force link up. We also need to give auto-negotiation 557 * we need to force link up. We also need to give auto-negotiation
@@ -595,8 +580,7 @@ s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
595 return ret_val; 580 return ret_val;
596 } 581 }
597 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 582 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
598 /* 583 /* If we are forcing link and we are receiving /C/ ordered
599 * If we are forcing link and we are receiving /C/ ordered
600 * sets, re-enable auto-negotiation in the TXCW register 584 * sets, re-enable auto-negotiation in the TXCW register
601 * and disable forced link in the Device Control register 585 * and disable forced link in the Device Control register
602 * in an attempt to auto-negotiate with our link partner. 586 * in an attempt to auto-negotiate with our link partner.
@@ -607,8 +591,7 @@ s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
607 591
608 mac->serdes_has_link = true; 592 mac->serdes_has_link = true;
609 } else if (!(E1000_TXCW_ANE & er32(TXCW))) { 593 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
610 /* 594 /* If we force link for non-auto-negotiation switch, check
611 * If we force link for non-auto-negotiation switch, check
612 * link status based on MAC synchronization for internal 595 * link status based on MAC synchronization for internal
613 * serdes media type. 596 * serdes media type.
614 */ 597 */
@@ -665,8 +648,7 @@ static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
665 s32 ret_val; 648 s32 ret_val;
666 u16 nvm_data; 649 u16 nvm_data;
667 650
668 /* 651 /* Read and store word 0x0F of the EEPROM. This word contains bits
669 * Read and store word 0x0F of the EEPROM. This word contains bits
670 * that determine the hardware's default PAUSE (flow control) mode, 652 * that determine the hardware's default PAUSE (flow control) mode,
671 * a bit that determines whether the HW defaults to enabling or 653 * a bit that determines whether the HW defaults to enabling or
672 * disabling auto-negotiation, and the direction of the 654 * disabling auto-negotiation, and the direction of the
@@ -705,15 +687,13 @@ s32 e1000e_setup_link_generic(struct e1000_hw *hw)
705{ 687{
706 s32 ret_val; 688 s32 ret_val;
707 689
708 /* 690 /* In the case of the phy reset being blocked, we already have a link.
709 * In the case of the phy reset being blocked, we already have a link.
710 * We do not need to set it up again. 691 * We do not need to set it up again.
711 */ 692 */
712 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) 693 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
713 return 0; 694 return 0;
714 695
715 /* 696 /* If requested flow control is set to default, set flow control
716 * If requested flow control is set to default, set flow control
717 * based on the EEPROM flow control settings. 697 * based on the EEPROM flow control settings.
718 */ 698 */
719 if (hw->fc.requested_mode == e1000_fc_default) { 699 if (hw->fc.requested_mode == e1000_fc_default) {
@@ -722,8 +702,7 @@ s32 e1000e_setup_link_generic(struct e1000_hw *hw)
722 return ret_val; 702 return ret_val;
723 } 703 }
724 704
725 /* 705 /* Save off the requested flow control mode for use later. Depending
726 * Save off the requested flow control mode for use later. Depending
727 * on the link partner's capabilities, we may or may not use this mode. 706 * on the link partner's capabilities, we may or may not use this mode.
728 */ 707 */
729 hw->fc.current_mode = hw->fc.requested_mode; 708 hw->fc.current_mode = hw->fc.requested_mode;
@@ -735,8 +714,7 @@ s32 e1000e_setup_link_generic(struct e1000_hw *hw)
735 if (ret_val) 714 if (ret_val)
736 return ret_val; 715 return ret_val;
737 716
738 /* 717 /* Initialize the flow control address, type, and PAUSE timer
739 * Initialize the flow control address, type, and PAUSE timer
740 * registers to their default values. This is done even if flow 718 * registers to their default values. This is done even if flow
741 * control is disabled, because it does not hurt anything to 719 * control is disabled, because it does not hurt anything to
742 * initialize these registers. 720 * initialize these registers.
@@ -763,8 +741,7 @@ static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
763 struct e1000_mac_info *mac = &hw->mac; 741 struct e1000_mac_info *mac = &hw->mac;
764 u32 txcw; 742 u32 txcw;
765 743
766 /* 744 /* Check for a software override of the flow control settings, and
767 * Check for a software override of the flow control settings, and
768 * setup the device accordingly. If auto-negotiation is enabled, then 745 * setup the device accordingly. If auto-negotiation is enabled, then
769 * software will have to set the "PAUSE" bits to the correct value in 746 * software will have to set the "PAUSE" bits to the correct value in
770 * the Transmit Config Word Register (TXCW) and re-start auto- 747 * the Transmit Config Word Register (TXCW) and re-start auto-
@@ -786,8 +763,7 @@ static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
786 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 763 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
787 break; 764 break;
788 case e1000_fc_rx_pause: 765 case e1000_fc_rx_pause:
789 /* 766 /* Rx Flow control is enabled and Tx Flow control is disabled
790 * Rx Flow control is enabled and Tx Flow control is disabled
791 * by a software over-ride. Since there really isn't a way to 767 * by a software over-ride. Since there really isn't a way to
792 * advertise that we are capable of Rx Pause ONLY, we will 768 * advertise that we are capable of Rx Pause ONLY, we will
793 * advertise that we support both symmetric and asymmetric Rx 769 * advertise that we support both symmetric and asymmetric Rx
@@ -797,15 +773,13 @@ static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
797 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 773 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
798 break; 774 break;
799 case e1000_fc_tx_pause: 775 case e1000_fc_tx_pause:
800 /* 776 /* Tx Flow control is enabled, and Rx Flow control is disabled,
801 * Tx Flow control is enabled, and Rx Flow control is disabled,
802 * by a software over-ride. 777 * by a software over-ride.
803 */ 778 */
804 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 779 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
805 break; 780 break;
806 case e1000_fc_full: 781 case e1000_fc_full:
807 /* 782 /* Flow control (both Rx and Tx) is enabled by a software
808 * Flow control (both Rx and Tx) is enabled by a software
809 * over-ride. 783 * over-ride.
810 */ 784 */
811 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 785 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
@@ -835,8 +809,7 @@ static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
835 u32 i, status; 809 u32 i, status;
836 s32 ret_val; 810 s32 ret_val;
837 811
838 /* 812 /* If we have a signal (the cable is plugged in, or assumed true for
839 * If we have a signal (the cable is plugged in, or assumed true for
840 * serdes media) then poll for a "Link-Up" indication in the Device 813 * serdes media) then poll for a "Link-Up" indication in the Device
841 * Status Register. Time-out if a link isn't seen in 500 milliseconds 814 * Status Register. Time-out if a link isn't seen in 500 milliseconds
842 * seconds (Auto-negotiation should complete in less than 500 815 * seconds (Auto-negotiation should complete in less than 500
@@ -851,8 +824,7 @@ static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
851 if (i == FIBER_LINK_UP_LIMIT) { 824 if (i == FIBER_LINK_UP_LIMIT) {
852 e_dbg("Never got a valid link from auto-neg!!!\n"); 825 e_dbg("Never got a valid link from auto-neg!!!\n");
853 mac->autoneg_failed = true; 826 mac->autoneg_failed = true;
854 /* 827 /* AutoNeg failed to achieve a link, so we'll call
855 * AutoNeg failed to achieve a link, so we'll call
856 * mac->check_for_link. This routine will force the 828 * mac->check_for_link. This routine will force the
857 * link up if we detect a signal. This will allow us to 829 * link up if we detect a signal. This will allow us to
858 * communicate with non-autonegotiating link partners. 830 * communicate with non-autonegotiating link partners.
@@ -894,8 +866,7 @@ s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
894 if (ret_val) 866 if (ret_val)
895 return ret_val; 867 return ret_val;
896 868
897 /* 869 /* Since auto-negotiation is enabled, take the link out of reset (the
898 * Since auto-negotiation is enabled, take the link out of reset (the
899 * link will be in reset, because we previously reset the chip). This 870 * link will be in reset, because we previously reset the chip). This
900 * will restart auto-negotiation. If auto-negotiation is successful 871 * will restart auto-negotiation. If auto-negotiation is successful
901 * then the link-up status bit will be set and the flow control enable 872 * then the link-up status bit will be set and the flow control enable
@@ -907,8 +878,7 @@ s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
907 e1e_flush(); 878 e1e_flush();
908 usleep_range(1000, 2000); 879 usleep_range(1000, 2000);
909 880
910 /* 881 /* For these adapters, the SW definable pin 1 is set when the optics
911 * For these adapters, the SW definable pin 1 is set when the optics
912 * detect a signal. If we have a signal, then poll for a "Link-Up" 882 * detect a signal. If we have a signal, then poll for a "Link-Up"
913 * indication. 883 * indication.
914 */ 884 */
@@ -954,16 +924,14 @@ s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
954{ 924{
955 u32 fcrtl = 0, fcrth = 0; 925 u32 fcrtl = 0, fcrth = 0;
956 926
957 /* 927 /* Set the flow control receive threshold registers. Normally,
958 * Set the flow control receive threshold registers. Normally,
959 * these registers will be set to a default threshold that may be 928 * these registers will be set to a default threshold that may be
960 * adjusted later by the driver's runtime code. However, if the 929 * adjusted later by the driver's runtime code. However, if the
961 * ability to transmit pause frames is not enabled, then these 930 * ability to transmit pause frames is not enabled, then these
962 * registers will be set to 0. 931 * registers will be set to 0.
963 */ 932 */
964 if (hw->fc.current_mode & e1000_fc_tx_pause) { 933 if (hw->fc.current_mode & e1000_fc_tx_pause) {
965 /* 934 /* We need to set up the Receive Threshold high and low water
966 * We need to set up the Receive Threshold high and low water
967 * marks as well as (optionally) enabling the transmission of 935 * marks as well as (optionally) enabling the transmission of
968 * XON frames. 936 * XON frames.
969 */ 937 */
@@ -995,8 +963,7 @@ s32 e1000e_force_mac_fc(struct e1000_hw *hw)
995 963
996 ctrl = er32(CTRL); 964 ctrl = er32(CTRL);
997 965
998 /* 966 /* Because we didn't get link via the internal auto-negotiation
999 * Because we didn't get link via the internal auto-negotiation
1000 * mechanism (we either forced link or we got link via PHY 967 * mechanism (we either forced link or we got link via PHY
1001 * auto-neg), we have to manually enable/disable transmit an 968 * auto-neg), we have to manually enable/disable transmit an
1002 * receive flow control. 969 * receive flow control.
@@ -1057,8 +1024,7 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1057 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1024 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1058 u16 speed, duplex; 1025 u16 speed, duplex;
1059 1026
1060 /* 1027 /* Check for the case where we have fiber media and auto-neg failed
1061 * Check for the case where we have fiber media and auto-neg failed
1062 * so we had to force link. In this case, we need to force the 1028 * so we had to force link. In this case, we need to force the
1063 * configuration of the MAC to match the "fc" parameter. 1029 * configuration of the MAC to match the "fc" parameter.
1064 */ 1030 */
@@ -1076,15 +1042,13 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1076 return ret_val; 1042 return ret_val;
1077 } 1043 }
1078 1044
1079 /* 1045 /* Check for the case where we have copper media and auto-neg is
1080 * Check for the case where we have copper media and auto-neg is
1081 * enabled. In this case, we need to check and see if Auto-Neg 1046 * enabled. In this case, we need to check and see if Auto-Neg
1082 * has completed, and if so, how the PHY and link partner has 1047 * has completed, and if so, how the PHY and link partner has
1083 * flow control configured. 1048 * flow control configured.
1084 */ 1049 */
1085 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1050 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1086 /* 1051 /* Read the MII Status Register and check to see if AutoNeg
1087 * Read the MII Status Register and check to see if AutoNeg
1088 * has completed. We read this twice because this reg has 1052 * has completed. We read this twice because this reg has
1089 * some "sticky" (latched) bits. 1053 * some "sticky" (latched) bits.
1090 */ 1054 */
@@ -1100,8 +1064,7 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1100 return ret_val; 1064 return ret_val;
1101 } 1065 }
1102 1066
1103 /* 1067 /* The AutoNeg process has completed, so we now need to
1104 * The AutoNeg process has completed, so we now need to
1105 * read both the Auto Negotiation Advertisement 1068 * read both the Auto Negotiation Advertisement
1106 * Register (Address 4) and the Auto_Negotiation Base 1069 * Register (Address 4) and the Auto_Negotiation Base
1107 * Page Ability Register (Address 5) to determine how 1070 * Page Ability Register (Address 5) to determine how
@@ -1115,8 +1078,7 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1115 if (ret_val) 1078 if (ret_val)
1116 return ret_val; 1079 return ret_val;
1117 1080
1118 /* 1081 /* Two bits in the Auto Negotiation Advertisement Register
1119 * Two bits in the Auto Negotiation Advertisement Register
1120 * (Address 4) and two bits in the Auto Negotiation Base 1082 * (Address 4) and two bits in the Auto Negotiation Base
1121 * Page Ability Register (Address 5) determine flow control 1083 * Page Ability Register (Address 5) determine flow control
1122 * for both the PHY and the link partner. The following 1084 * for both the PHY and the link partner. The following
@@ -1151,8 +1113,7 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1151 */ 1113 */
1152 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1114 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1153 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1115 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1154 /* 1116 /* Now we need to check if the user selected Rx ONLY
1155 * Now we need to check if the user selected Rx ONLY
1156 * of pause frames. In this case, we had to advertise 1117 * of pause frames. In this case, we had to advertise
1157 * FULL flow control because we could not advertise Rx 1118 * FULL flow control because we could not advertise Rx
1158 * ONLY. Hence, we must now check to see if we need to 1119 * ONLY. Hence, we must now check to see if we need to
@@ -1166,8 +1127,7 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1166 e_dbg("Flow Control = Rx PAUSE frames only.\n"); 1127 e_dbg("Flow Control = Rx PAUSE frames only.\n");
1167 } 1128 }
1168 } 1129 }
1169 /* 1130 /* For receiving PAUSE frames ONLY.
1170 * For receiving PAUSE frames ONLY.
1171 * 1131 *
1172 * LOCAL DEVICE | LINK PARTNER 1132 * LOCAL DEVICE | LINK PARTNER
1173 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1133 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
@@ -1181,8 +1141,7 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1181 hw->fc.current_mode = e1000_fc_tx_pause; 1141 hw->fc.current_mode = e1000_fc_tx_pause;
1182 e_dbg("Flow Control = Tx PAUSE frames only.\n"); 1142 e_dbg("Flow Control = Tx PAUSE frames only.\n");
1183 } 1143 }
1184 /* 1144 /* For transmitting PAUSE frames ONLY.
1185 * For transmitting PAUSE frames ONLY.
1186 * 1145 *
1187 * LOCAL DEVICE | LINK PARTNER 1146 * LOCAL DEVICE | LINK PARTNER
1188 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1147 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
@@ -1196,16 +1155,14 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1196 hw->fc.current_mode = e1000_fc_rx_pause; 1155 hw->fc.current_mode = e1000_fc_rx_pause;
1197 e_dbg("Flow Control = Rx PAUSE frames only.\n"); 1156 e_dbg("Flow Control = Rx PAUSE frames only.\n");
1198 } else { 1157 } else {
1199 /* 1158 /* Per the IEEE spec, at this point flow control
1200 * Per the IEEE spec, at this point flow control
1201 * should be disabled. 1159 * should be disabled.
1202 */ 1160 */
1203 hw->fc.current_mode = e1000_fc_none; 1161 hw->fc.current_mode = e1000_fc_none;
1204 e_dbg("Flow Control = NONE.\n"); 1162 e_dbg("Flow Control = NONE.\n");
1205 } 1163 }
1206 1164
1207 /* 1165 /* Now we need to do one last check... If we auto-
1208 * Now we need to do one last check... If we auto-
1209 * negotiated to HALF DUPLEX, flow control should not be 1166 * negotiated to HALF DUPLEX, flow control should not be
1210 * enabled per IEEE 802.3 spec. 1167 * enabled per IEEE 802.3 spec.
1211 */ 1168 */
@@ -1218,8 +1175,7 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1218 if (duplex == HALF_DUPLEX) 1175 if (duplex == HALF_DUPLEX)
1219 hw->fc.current_mode = e1000_fc_none; 1176 hw->fc.current_mode = e1000_fc_none;
1220 1177
1221 /* 1178 /* Now we call a subroutine to actually force the MAC
1222 * Now we call a subroutine to actually force the MAC
1223 * controller to use the correct flow control settings. 1179 * controller to use the correct flow control settings.
1224 */ 1180 */
1225 ret_val = e1000e_force_mac_fc(hw); 1181 ret_val = e1000e_force_mac_fc(hw);
@@ -1520,8 +1476,7 @@ s32 e1000e_blink_led_generic(struct e1000_hw *hw)
1520 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1476 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1521 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1477 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1522 } else { 1478 } else {
1523 /* 1479 /* set the blink bit for each LED that's "on" (0x0E)
1524 * set the blink bit for each LED that's "on" (0x0E)
1525 * in ledctl_mode2 1480 * in ledctl_mode2
1526 */ 1481 */
1527 ledctl_blink = hw->mac.ledctl_mode2; 1482 ledctl_blink = hw->mac.ledctl_mode2;
diff --git a/drivers/net/ethernet/intel/e1000e/manage.c b/drivers/net/ethernet/intel/e1000e/manage.c
index bacc950fc684..6dc47beb3adc 100644
--- a/drivers/net/ethernet/intel/e1000e/manage.c
+++ b/drivers/net/ethernet/intel/e1000e/manage.c
@@ -143,8 +143,7 @@ bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
143 return hw->mac.tx_pkt_filtering; 143 return hw->mac.tx_pkt_filtering;
144 } 144 }
145 145
146 /* 146 /* If we can't read from the host interface for whatever
147 * If we can't read from the host interface for whatever
148 * reason, disable filtering. 147 * reason, disable filtering.
149 */ 148 */
150 ret_val = e1000_mng_enable_host_if(hw); 149 ret_val = e1000_mng_enable_host_if(hw);
@@ -163,8 +162,7 @@ bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
163 hdr->checksum = 0; 162 hdr->checksum = 0;
164 csum = e1000_calculate_checksum((u8 *)hdr, 163 csum = e1000_calculate_checksum((u8 *)hdr,
165 E1000_MNG_DHCP_COOKIE_LENGTH); 164 E1000_MNG_DHCP_COOKIE_LENGTH);
166 /* 165 /* If either the checksums or signature don't match, then
167 * If either the checksums or signature don't match, then
168 * the cookie area isn't considered valid, in which case we 166 * the cookie area isn't considered valid, in which case we
169 * take the safe route of assuming Tx filtering is enabled. 167 * take the safe route of assuming Tx filtering is enabled.
170 */ 168 */
@@ -252,8 +250,7 @@ static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer,
252 /* Calculate length in DWORDs */ 250 /* Calculate length in DWORDs */
253 length >>= 2; 251 length >>= 2;
254 252
255 /* 253 /* The device driver writes the relevant command block into the
256 * The device driver writes the relevant command block into the
257 * ram area. 254 * ram area.
258 */ 255 */
259 for (i = 0; i < length; i++) { 256 for (i = 0; i < length; i++) {
diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c
index dadb13be479a..6d06ed4e34b1 100644
--- a/drivers/net/ethernet/intel/e1000e/netdev.c
+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
@@ -146,9 +146,11 @@ static const struct e1000_reg_info e1000_reg_info_tbl[] = {
146 {0, NULL} 146 {0, NULL}
147}; 147};
148 148
149/* 149/**
150 * e1000_regdump - register printout routine 150 * e1000_regdump - register printout routine
151 */ 151 * @hw: pointer to the HW structure
152 * @reginfo: pointer to the register info table
153 **/
152static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo) 154static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
153{ 155{
154 int n = 0; 156 int n = 0;
@@ -196,9 +198,10 @@ static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
196 } 198 }
197} 199}
198 200
199/* 201/**
200 * e1000e_dump - Print registers, Tx-ring and Rx-ring 202 * e1000e_dump - Print registers, Tx-ring and Rx-ring
201 */ 203 * @adapter: board private structure
204 **/
202static void e1000e_dump(struct e1000_adapter *adapter) 205static void e1000e_dump(struct e1000_adapter *adapter)
203{ 206{
204 struct net_device *netdev = adapter->netdev; 207 struct net_device *netdev = adapter->netdev;
@@ -623,8 +626,7 @@ map_skb:
623 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); 626 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
624 627
625 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 628 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
626 /* 629 /* Force memory writes to complete before letting h/w
627 * Force memory writes to complete before letting h/w
628 * know there are new descriptors to fetch. (Only 630 * know there are new descriptors to fetch. (Only
629 * applicable for weak-ordered memory model archs, 631 * applicable for weak-ordered memory model archs,
630 * such as IA-64). 632 * such as IA-64).
@@ -692,8 +694,7 @@ static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
692 goto no_buffers; 694 goto no_buffers;
693 } 695 }
694 } 696 }
695 /* 697 /* Refresh the desc even if buffer_addrs
696 * Refresh the desc even if buffer_addrs
697 * didn't change because each write-back 698 * didn't change because each write-back
698 * erases this info. 699 * erases this info.
699 */ 700 */
@@ -726,8 +727,7 @@ static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
726 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); 727 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
727 728
728 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { 729 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
729 /* 730 /* Force memory writes to complete before letting h/w
730 * Force memory writes to complete before letting h/w
731 * know there are new descriptors to fetch. (Only 731 * know there are new descriptors to fetch. (Only
732 * applicable for weak-ordered memory model archs, 732 * applicable for weak-ordered memory model archs,
733 * such as IA-64). 733 * such as IA-64).
@@ -817,7 +817,8 @@ check_page:
817 /* Force memory writes to complete before letting h/w 817 /* Force memory writes to complete before letting h/w
818 * know there are new descriptors to fetch. (Only 818 * know there are new descriptors to fetch. (Only
819 * applicable for weak-ordered memory model archs, 819 * applicable for weak-ordered memory model archs,
820 * such as IA-64). */ 820 * such as IA-64).
821 */
821 wmb(); 822 wmb();
822 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) 823 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
823 e1000e_update_rdt_wa(rx_ring, i); 824 e1000e_update_rdt_wa(rx_ring, i);
@@ -891,8 +892,7 @@ static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
891 892
892 length = le16_to_cpu(rx_desc->wb.upper.length); 893 length = le16_to_cpu(rx_desc->wb.upper.length);
893 894
894 /* 895 /* !EOP means multiple descriptors were used to store a single
895 * !EOP means multiple descriptors were used to store a single
896 * packet, if that's the case we need to toss it. In fact, we 896 * packet, if that's the case we need to toss it. In fact, we
897 * need to toss every packet with the EOP bit clear and the 897 * need to toss every packet with the EOP bit clear and the
898 * next frame that _does_ have the EOP bit set, as it is by 898 * next frame that _does_ have the EOP bit set, as it is by
@@ -933,8 +933,7 @@ static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
933 total_rx_bytes += length; 933 total_rx_bytes += length;
934 total_rx_packets++; 934 total_rx_packets++;
935 935
936 /* 936 /* code added for copybreak, this should improve
937 * code added for copybreak, this should improve
938 * performance for small packets with large amounts 937 * performance for small packets with large amounts
939 * of reassembly being done in the stack 938 * of reassembly being done in the stack
940 */ 939 */
@@ -1032,15 +1031,13 @@ static void e1000_print_hw_hang(struct work_struct *work)
1032 1031
1033 if (!adapter->tx_hang_recheck && 1032 if (!adapter->tx_hang_recheck &&
1034 (adapter->flags2 & FLAG2_DMA_BURST)) { 1033 (adapter->flags2 & FLAG2_DMA_BURST)) {
1035 /* 1034 /* May be block on write-back, flush and detect again
1036 * May be block on write-back, flush and detect again
1037 * flush pending descriptor writebacks to memory 1035 * flush pending descriptor writebacks to memory
1038 */ 1036 */
1039 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1037 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1040 /* execute the writes immediately */ 1038 /* execute the writes immediately */
1041 e1e_flush(); 1039 e1e_flush();
1042 /* 1040 /* Due to rare timing issues, write to TIDV again to ensure
1043 * Due to rare timing issues, write to TIDV again to ensure
1044 * the write is successful 1041 * the write is successful
1045 */ 1042 */
1046 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 1043 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
@@ -1169,8 +1166,7 @@ static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
1169 } 1166 }
1170 1167
1171 if (adapter->detect_tx_hung) { 1168 if (adapter->detect_tx_hung) {
1172 /* 1169 /* Detect a transmit hang in hardware, this serializes the
1173 * Detect a transmit hang in hardware, this serializes the
1174 * check with the clearing of time_stamp and movement of i 1170 * check with the clearing of time_stamp and movement of i
1175 */ 1171 */
1176 adapter->detect_tx_hung = false; 1172 adapter->detect_tx_hung = false;
@@ -1270,14 +1266,12 @@ static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1270 skb_put(skb, length); 1266 skb_put(skb, length);
1271 1267
1272 { 1268 {
1273 /* 1269 /* this looks ugly, but it seems compiler issues make
1274 * this looks ugly, but it seems compiler issues make
1275 * it more efficient than reusing j 1270 * it more efficient than reusing j
1276 */ 1271 */
1277 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]); 1272 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
1278 1273
1279 /* 1274 /* page alloc/put takes too long and effects small
1280 * page alloc/put takes too long and effects small
1281 * packet throughput, so unsplit small packets and 1275 * packet throughput, so unsplit small packets and
1282 * save the alloc/put only valid in softirq (napi) 1276 * save the alloc/put only valid in softirq (napi)
1283 * context to call kmap_* 1277 * context to call kmap_*
@@ -1288,8 +1282,7 @@ static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1288 1282
1289 ps_page = &buffer_info->ps_pages[0]; 1283 ps_page = &buffer_info->ps_pages[0];
1290 1284
1291 /* 1285 /* there is no documentation about how to call
1292 * there is no documentation about how to call
1293 * kmap_atomic, so we can't hold the mapping 1286 * kmap_atomic, so we can't hold the mapping
1294 * very long 1287 * very long
1295 */ 1288 */
@@ -1486,14 +1479,16 @@ static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1486 skb_shinfo(rxtop)->nr_frags, 1479 skb_shinfo(rxtop)->nr_frags,
1487 buffer_info->page, 0, length); 1480 buffer_info->page, 0, length);
1488 /* re-use the current skb, we only consumed the 1481 /* re-use the current skb, we only consumed the
1489 * page */ 1482 * page
1483 */
1490 buffer_info->skb = skb; 1484 buffer_info->skb = skb;
1491 skb = rxtop; 1485 skb = rxtop;
1492 rxtop = NULL; 1486 rxtop = NULL;
1493 e1000_consume_page(buffer_info, skb, length); 1487 e1000_consume_page(buffer_info, skb, length);
1494 } else { 1488 } else {
1495 /* no chain, got EOP, this buf is the packet 1489 /* no chain, got EOP, this buf is the packet
1496 * copybreak to save the put_page/alloc_page */ 1490 * copybreak to save the put_page/alloc_page
1491 */
1497 if (length <= copybreak && 1492 if (length <= copybreak &&
1498 skb_tailroom(skb) >= length) { 1493 skb_tailroom(skb) >= length) {
1499 u8 *vaddr; 1494 u8 *vaddr;
@@ -1502,7 +1497,8 @@ static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1502 length); 1497 length);
1503 kunmap_atomic(vaddr); 1498 kunmap_atomic(vaddr);
1504 /* re-use the page, so don't erase 1499 /* re-use the page, so don't erase
1505 * buffer_info->page */ 1500 * buffer_info->page
1501 */
1506 skb_put(skb, length); 1502 skb_put(skb, length);
1507 } else { 1503 } else {
1508 skb_fill_page_desc(skb, 0, 1504 skb_fill_page_desc(skb, 0,
@@ -1656,22 +1652,17 @@ static irqreturn_t e1000_intr_msi(int irq, void *data)
1656 struct e1000_hw *hw = &adapter->hw; 1652 struct e1000_hw *hw = &adapter->hw;
1657 u32 icr = er32(ICR); 1653 u32 icr = er32(ICR);
1658 1654
1659 /* 1655 /* read ICR disables interrupts using IAM */
1660 * read ICR disables interrupts using IAM
1661 */
1662
1663 if (icr & E1000_ICR_LSC) { 1656 if (icr & E1000_ICR_LSC) {
1664 hw->mac.get_link_status = true; 1657 hw->mac.get_link_status = true;
1665 /* 1658 /* ICH8 workaround-- Call gig speed drop workaround on cable
1666 * ICH8 workaround-- Call gig speed drop workaround on cable
1667 * disconnect (LSC) before accessing any PHY registers 1659 * disconnect (LSC) before accessing any PHY registers
1668 */ 1660 */
1669 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1661 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1670 (!(er32(STATUS) & E1000_STATUS_LU))) 1662 (!(er32(STATUS) & E1000_STATUS_LU)))
1671 schedule_work(&adapter->downshift_task); 1663 schedule_work(&adapter->downshift_task);
1672 1664
1673 /* 1665 /* 80003ES2LAN workaround-- For packet buffer work-around on
1674 * 80003ES2LAN workaround-- For packet buffer work-around on
1675 * link down event; disable receives here in the ISR and reset 1666 * link down event; disable receives here in the ISR and reset
1676 * adapter in watchdog 1667 * adapter in watchdog
1677 */ 1668 */
@@ -1713,31 +1704,27 @@ static irqreturn_t e1000_intr(int irq, void *data)
1713 if (!icr || test_bit(__E1000_DOWN, &adapter->state)) 1704 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
1714 return IRQ_NONE; /* Not our interrupt */ 1705 return IRQ_NONE; /* Not our interrupt */
1715 1706
1716 /* 1707 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1717 * IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1718 * not set, then the adapter didn't send an interrupt 1708 * not set, then the adapter didn't send an interrupt
1719 */ 1709 */
1720 if (!(icr & E1000_ICR_INT_ASSERTED)) 1710 if (!(icr & E1000_ICR_INT_ASSERTED))
1721 return IRQ_NONE; 1711 return IRQ_NONE;
1722 1712
1723 /* 1713 /* Interrupt Auto-Mask...upon reading ICR,
1724 * Interrupt Auto-Mask...upon reading ICR,
1725 * interrupts are masked. No need for the 1714 * interrupts are masked. No need for the
1726 * IMC write 1715 * IMC write
1727 */ 1716 */
1728 1717
1729 if (icr & E1000_ICR_LSC) { 1718 if (icr & E1000_ICR_LSC) {
1730 hw->mac.get_link_status = true; 1719 hw->mac.get_link_status = true;
1731 /* 1720 /* ICH8 workaround-- Call gig speed drop workaround on cable
1732 * ICH8 workaround-- Call gig speed drop workaround on cable
1733 * disconnect (LSC) before accessing any PHY registers 1721 * disconnect (LSC) before accessing any PHY registers
1734 */ 1722 */
1735 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && 1723 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1736 (!(er32(STATUS) & E1000_STATUS_LU))) 1724 (!(er32(STATUS) & E1000_STATUS_LU)))
1737 schedule_work(&adapter->downshift_task); 1725 schedule_work(&adapter->downshift_task);
1738 1726
1739 /* 1727 /* 80003ES2LAN workaround--
1740 * 80003ES2LAN workaround--
1741 * For packet buffer work-around on link down event; 1728 * For packet buffer work-around on link down event;
1742 * disable receives here in the ISR and 1729 * disable receives here in the ISR and
1743 * reset adapter in watchdog 1730 * reset adapter in watchdog
@@ -2469,8 +2456,7 @@ static void e1000_set_itr(struct e1000_adapter *adapter)
2469 2456
2470set_itr_now: 2457set_itr_now:
2471 if (new_itr != adapter->itr) { 2458 if (new_itr != adapter->itr) {
2472 /* 2459 /* this attempts to bias the interrupt rate towards Bulk
2473 * this attempts to bias the interrupt rate towards Bulk
2474 * by adding intermediate steps when interrupt rate is 2460 * by adding intermediate steps when interrupt rate is
2475 * increasing 2461 * increasing
2476 */ 2462 */
@@ -2740,8 +2726,7 @@ static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
2740 2726
2741 manc = er32(MANC); 2727 manc = er32(MANC);
2742 2728
2743 /* 2729 /* enable receiving management packets to the host. this will probably
2744 * enable receiving management packets to the host. this will probably
2745 * generate destination unreachable messages from the host OS, but 2730 * generate destination unreachable messages from the host OS, but
2746 * the packets will be handled on SMBUS 2731 * the packets will be handled on SMBUS
2747 */ 2732 */
@@ -2754,8 +2739,7 @@ static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
2754 break; 2739 break;
2755 case e1000_82574: 2740 case e1000_82574:
2756 case e1000_82583: 2741 case e1000_82583:
2757 /* 2742 /* Check if IPMI pass-through decision filter already exists;
2758 * Check if IPMI pass-through decision filter already exists;
2759 * if so, enable it. 2743 * if so, enable it.
2760 */ 2744 */
2761 for (i = 0, j = 0; i < 8; i++) { 2745 for (i = 0, j = 0; i < 8; i++) {
@@ -2827,8 +2811,7 @@ static void e1000_configure_tx(struct e1000_adapter *adapter)
2827 u32 txdctl = er32(TXDCTL(0)); 2811 u32 txdctl = er32(TXDCTL(0));
2828 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH | 2812 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2829 E1000_TXDCTL_WTHRESH); 2813 E1000_TXDCTL_WTHRESH);
2830 /* 2814 /* set up some performance related parameters to encourage the
2831 * set up some performance related parameters to encourage the
2832 * hardware to use the bus more efficiently in bursts, depends 2815 * hardware to use the bus more efficiently in bursts, depends
2833 * on the tx_int_delay to be enabled, 2816 * on the tx_int_delay to be enabled,
2834 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls 2817 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
@@ -2845,8 +2828,7 @@ static void e1000_configure_tx(struct e1000_adapter *adapter)
2845 2828
2846 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) { 2829 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
2847 tarc = er32(TARC(0)); 2830 tarc = er32(TARC(0));
2848 /* 2831 /* set the speed mode bit, we'll clear it if we're not at
2849 * set the speed mode bit, we'll clear it if we're not at
2850 * gigabit link later 2832 * gigabit link later
2851 */ 2833 */
2852#define SPEED_MODE_BIT (1 << 21) 2834#define SPEED_MODE_BIT (1 << 21)
@@ -2967,8 +2949,7 @@ static void e1000_setup_rctl(struct e1000_adapter *adapter)
2967 rfctl |= E1000_RFCTL_EXTEN; 2949 rfctl |= E1000_RFCTL_EXTEN;
2968 ew32(RFCTL, rfctl); 2950 ew32(RFCTL, rfctl);
2969 2951
2970 /* 2952 /* 82571 and greater support packet-split where the protocol
2971 * 82571 and greater support packet-split where the protocol
2972 * header is placed in skb->data and the packet data is 2953 * header is placed in skb->data and the packet data is
2973 * placed in pages hanging off of skb_shinfo(skb)->nr_frags. 2954 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2974 * In the case of a non-split, skb->data is linearly filled, 2955 * In the case of a non-split, skb->data is linearly filled,
@@ -3016,7 +2997,8 @@ static void e1000_setup_rctl(struct e1000_adapter *adapter)
3016 /* This is useful for sniffing bad packets. */ 2997 /* This is useful for sniffing bad packets. */
3017 if (adapter->netdev->features & NETIF_F_RXALL) { 2998 if (adapter->netdev->features & NETIF_F_RXALL) {
3018 /* UPE and MPE will be handled by normal PROMISC logic 2999 /* UPE and MPE will be handled by normal PROMISC logic
3019 * in e1000e_set_rx_mode */ 3000 * in e1000e_set_rx_mode
3001 */
3020 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3002 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3021 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3003 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3022 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3004 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
@@ -3071,8 +3053,7 @@ static void e1000_configure_rx(struct e1000_adapter *adapter)
3071 usleep_range(10000, 20000); 3053 usleep_range(10000, 20000);
3072 3054
3073 if (adapter->flags2 & FLAG2_DMA_BURST) { 3055 if (adapter->flags2 & FLAG2_DMA_BURST) {
3074 /* 3056 /* set the writeback threshold (only takes effect if the RDTR
3075 * set the writeback threshold (only takes effect if the RDTR
3076 * is set). set GRAN=1 and write back up to 0x4 worth, and 3057 * is set). set GRAN=1 and write back up to 0x4 worth, and
3077 * enable prefetching of 0x20 Rx descriptors 3058 * enable prefetching of 0x20 Rx descriptors
3078 * granularity = 01 3059 * granularity = 01
@@ -3083,8 +3064,7 @@ static void e1000_configure_rx(struct e1000_adapter *adapter)
3083 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE); 3064 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3084 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE); 3065 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3085 3066
3086 /* 3067 /* override the delay timers for enabling bursting, only if
3087 * override the delay timers for enabling bursting, only if
3088 * the value was not set by the user via module options 3068 * the value was not set by the user via module options
3089 */ 3069 */
3090 if (adapter->rx_int_delay == DEFAULT_RDTR) 3070 if (adapter->rx_int_delay == DEFAULT_RDTR)
@@ -3108,8 +3088,7 @@ static void e1000_configure_rx(struct e1000_adapter *adapter)
3108 ew32(CTRL_EXT, ctrl_ext); 3088 ew32(CTRL_EXT, ctrl_ext);
3109 e1e_flush(); 3089 e1e_flush();
3110 3090
3111 /* 3091 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3112 * Setup the HW Rx Head and Tail Descriptor Pointers and
3113 * the Base and Length of the Rx Descriptor Ring 3092 * the Base and Length of the Rx Descriptor Ring
3114 */ 3093 */
3115 rdba = rx_ring->dma; 3094 rdba = rx_ring->dma;
@@ -3130,8 +3109,7 @@ static void e1000_configure_rx(struct e1000_adapter *adapter)
3130 ew32(RXCSUM, rxcsum); 3109 ew32(RXCSUM, rxcsum);
3131 3110
3132 if (adapter->hw.mac.type == e1000_pch2lan) { 3111 if (adapter->hw.mac.type == e1000_pch2lan) {
3133 /* 3112 /* With jumbo frames, excessive C-state transition
3134 * With jumbo frames, excessive C-state transition
3135 * latencies result in dropped transactions. 3113 * latencies result in dropped transactions.
3136 */ 3114 */
3137 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3115 if (adapter->netdev->mtu > ETH_DATA_LEN) {
@@ -3216,8 +3194,7 @@ static int e1000e_write_uc_addr_list(struct net_device *netdev)
3216 if (!netdev_uc_empty(netdev) && rar_entries) { 3194 if (!netdev_uc_empty(netdev) && rar_entries) {
3217 struct netdev_hw_addr *ha; 3195 struct netdev_hw_addr *ha;
3218 3196
3219 /* 3197 /* write the addresses in reverse order to avoid write
3220 * write the addresses in reverse order to avoid write
3221 * combining 3198 * combining
3222 */ 3199 */
3223 netdev_for_each_uc_addr(ha, netdev) { 3200 netdev_for_each_uc_addr(ha, netdev) {
@@ -3269,8 +3246,7 @@ static void e1000e_set_rx_mode(struct net_device *netdev)
3269 if (netdev->flags & IFF_ALLMULTI) { 3246 if (netdev->flags & IFF_ALLMULTI) {
3270 rctl |= E1000_RCTL_MPE; 3247 rctl |= E1000_RCTL_MPE;
3271 } else { 3248 } else {
3272 /* 3249 /* Write addresses to the MTA, if the attempt fails
3273 * Write addresses to the MTA, if the attempt fails
3274 * then we should just turn on promiscuous mode so 3250 * then we should just turn on promiscuous mode so
3275 * that we can at least receive multicast traffic 3251 * that we can at least receive multicast traffic
3276 */ 3252 */
@@ -3279,8 +3255,7 @@ static void e1000e_set_rx_mode(struct net_device *netdev)
3279 rctl |= E1000_RCTL_MPE; 3255 rctl |= E1000_RCTL_MPE;
3280 } 3256 }
3281 e1000e_vlan_filter_enable(adapter); 3257 e1000e_vlan_filter_enable(adapter);
3282 /* 3258 /* Write addresses to available RAR registers, if there is not
3283 * Write addresses to available RAR registers, if there is not
3284 * sufficient space to store all the addresses then enable 3259 * sufficient space to store all the addresses then enable
3285 * unicast promiscuous mode 3260 * unicast promiscuous mode
3286 */ 3261 */
@@ -3315,8 +3290,7 @@ static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3315 for (i = 0; i < 32; i++) 3290 for (i = 0; i < 32; i++)
3316 ew32(RETA(i), 0); 3291 ew32(RETA(i), 0);
3317 3292
3318 /* 3293 /* Disable raw packet checksumming so that RSS hash is placed in
3319 * Disable raw packet checksumming so that RSS hash is placed in
3320 * descriptor on writeback. 3294 * descriptor on writeback.
3321 */ 3295 */
3322 rxcsum = er32(RXCSUM); 3296 rxcsum = er32(RXCSUM);
@@ -3408,8 +3382,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
3408 ew32(PBA, pba); 3382 ew32(PBA, pba);
3409 3383
3410 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) { 3384 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
3411 /* 3385 /* To maintain wire speed transmits, the Tx FIFO should be
3412 * To maintain wire speed transmits, the Tx FIFO should be
3413 * large enough to accommodate two full transmit packets, 3386 * large enough to accommodate two full transmit packets,
3414 * rounded up to the next 1KB and expressed in KB. Likewise, 3387 * rounded up to the next 1KB and expressed in KB. Likewise,
3415 * the Rx FIFO should be large enough to accommodate at least 3388 * the Rx FIFO should be large enough to accommodate at least
@@ -3421,8 +3394,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
3421 tx_space = pba >> 16; 3394 tx_space = pba >> 16;
3422 /* lower 16 bits has Rx packet buffer allocation size in KB */ 3395 /* lower 16 bits has Rx packet buffer allocation size in KB */
3423 pba &= 0xffff; 3396 pba &= 0xffff;
3424 /* 3397 /* the Tx fifo also stores 16 bytes of information about the Tx
3425 * the Tx fifo also stores 16 bytes of information about the Tx
3426 * but don't include ethernet FCS because hardware appends it 3398 * but don't include ethernet FCS because hardware appends it
3427 */ 3399 */
3428 min_tx_space = (adapter->max_frame_size + 3400 min_tx_space = (adapter->max_frame_size +
@@ -3435,8 +3407,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
3435 min_rx_space = ALIGN(min_rx_space, 1024); 3407 min_rx_space = ALIGN(min_rx_space, 1024);
3436 min_rx_space >>= 10; 3408 min_rx_space >>= 10;
3437 3409
3438 /* 3410 /* If current Tx allocation is less than the min Tx FIFO size,
3439 * If current Tx allocation is less than the min Tx FIFO size,
3440 * and the min Tx FIFO size is less than the current Rx FIFO 3411 * and the min Tx FIFO size is less than the current Rx FIFO
3441 * allocation, take space away from current Rx allocation 3412 * allocation, take space away from current Rx allocation
3442 */ 3413 */
@@ -3444,8 +3415,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
3444 ((min_tx_space - tx_space) < pba)) { 3415 ((min_tx_space - tx_space) < pba)) {
3445 pba -= min_tx_space - tx_space; 3416 pba -= min_tx_space - tx_space;
3446 3417
3447 /* 3418 /* if short on Rx space, Rx wins and must trump Tx
3448 * if short on Rx space, Rx wins and must trump Tx
3449 * adjustment 3419 * adjustment
3450 */ 3420 */
3451 if (pba < min_rx_space) 3421 if (pba < min_rx_space)
@@ -3455,8 +3425,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
3455 ew32(PBA, pba); 3425 ew32(PBA, pba);
3456 } 3426 }
3457 3427
3458 /* 3428 /* flow control settings
3459 * flow control settings
3460 * 3429 *
3461 * The high water mark must be low enough to fit one full frame 3430 * The high water mark must be low enough to fit one full frame
3462 * (or the size used for early receive) above it in the Rx FIFO. 3431 * (or the size used for early receive) above it in the Rx FIFO.
@@ -3490,8 +3459,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
3490 fc->low_water = fc->high_water - 8; 3459 fc->low_water = fc->high_water - 8;
3491 break; 3460 break;
3492 case e1000_pchlan: 3461 case e1000_pchlan:
3493 /* 3462 /* Workaround PCH LOM adapter hangs with certain network
3494 * Workaround PCH LOM adapter hangs with certain network
3495 * loads. If hangs persist, try disabling Tx flow control. 3463 * loads. If hangs persist, try disabling Tx flow control.
3496 */ 3464 */
3497 if (adapter->netdev->mtu > ETH_DATA_LEN) { 3465 if (adapter->netdev->mtu > ETH_DATA_LEN) {
@@ -3516,8 +3484,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
3516 break; 3484 break;
3517 } 3485 }
3518 3486
3519 /* 3487 /* Alignment of Tx data is on an arbitrary byte boundary with the
3520 * Alignment of Tx data is on an arbitrary byte boundary with the
3521 * maximum size per Tx descriptor limited only to the transmit 3488 * maximum size per Tx descriptor limited only to the transmit
3522 * allocation of the packet buffer minus 96 bytes with an upper 3489 * allocation of the packet buffer minus 96 bytes with an upper
3523 * limit of 24KB due to receive synchronization limitations. 3490 * limit of 24KB due to receive synchronization limitations.
@@ -3525,8 +3492,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
3525 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96, 3492 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
3526 24 << 10); 3493 24 << 10);
3527 3494
3528 /* 3495 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
3529 * Disable Adaptive Interrupt Moderation if 2 full packets cannot
3530 * fit in receive buffer. 3496 * fit in receive buffer.
3531 */ 3497 */
3532 if (adapter->itr_setting & 0x3) { 3498 if (adapter->itr_setting & 0x3) {
@@ -3549,8 +3515,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
3549 /* Allow time for pending master requests to run */ 3515 /* Allow time for pending master requests to run */
3550 mac->ops.reset_hw(hw); 3516 mac->ops.reset_hw(hw);
3551 3517
3552 /* 3518 /* For parts with AMT enabled, let the firmware know
3553 * For parts with AMT enabled, let the firmware know
3554 * that the network interface is in control 3519 * that the network interface is in control
3555 */ 3520 */
3556 if (adapter->flags & FLAG_HAS_AMT) 3521 if (adapter->flags & FLAG_HAS_AMT)
@@ -3579,8 +3544,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
3579 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && 3544 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3580 !(adapter->flags & FLAG_SMART_POWER_DOWN)) { 3545 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
3581 u16 phy_data = 0; 3546 u16 phy_data = 0;
3582 /* 3547 /* speed up time to link by disabling smart power down, ignore
3583 * speed up time to link by disabling smart power down, ignore
3584 * the return value of this function because there is nothing 3548 * the return value of this function because there is nothing
3585 * different we would do if it failed 3549 * different we would do if it failed
3586 */ 3550 */
@@ -3628,8 +3592,7 @@ static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3628 /* execute the writes immediately */ 3592 /* execute the writes immediately */
3629 e1e_flush(); 3593 e1e_flush();
3630 3594
3631 /* 3595 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
3632 * due to rare timing issues, write to TIDV/RDTR again to ensure the
3633 * write is successful 3596 * write is successful
3634 */ 3597 */
3635 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); 3598 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
@@ -3647,8 +3610,7 @@ void e1000e_down(struct e1000_adapter *adapter)
3647 struct e1000_hw *hw = &adapter->hw; 3610 struct e1000_hw *hw = &adapter->hw;
3648 u32 tctl, rctl; 3611 u32 tctl, rctl;
3649 3612
3650 /* 3613 /* signal that we're down so the interrupt handler does not
3651 * signal that we're down so the interrupt handler does not
3652 * reschedule our watchdog timer 3614 * reschedule our watchdog timer
3653 */ 3615 */
3654 set_bit(__E1000_DOWN, &adapter->state); 3616 set_bit(__E1000_DOWN, &adapter->state);
@@ -3691,8 +3653,7 @@ void e1000e_down(struct e1000_adapter *adapter)
3691 if (!pci_channel_offline(adapter->pdev)) 3653 if (!pci_channel_offline(adapter->pdev))
3692 e1000e_reset(adapter); 3654 e1000e_reset(adapter);
3693 3655
3694 /* 3656 /* TODO: for power management, we could drop the link and
3695 * TODO: for power management, we could drop the link and
3696 * pci_disable_device here. 3657 * pci_disable_device here.
3697 */ 3658 */
3698} 3659}
@@ -3755,8 +3716,7 @@ static irqreturn_t e1000_intr_msi_test(int irq, void *data)
3755 e_dbg("icr is %08X\n", icr); 3716 e_dbg("icr is %08X\n", icr);
3756 if (icr & E1000_ICR_RXSEQ) { 3717 if (icr & E1000_ICR_RXSEQ) {
3757 adapter->flags &= ~FLAG_MSI_TEST_FAILED; 3718 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
3758 /* 3719 /* Force memory writes to complete before acknowledging the
3759 * Force memory writes to complete before acknowledging the
3760 * interrupt is handled. 3720 * interrupt is handled.
3761 */ 3721 */
3762 wmb(); 3722 wmb();
@@ -3786,7 +3746,8 @@ static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
3786 e1000e_reset_interrupt_capability(adapter); 3746 e1000e_reset_interrupt_capability(adapter);
3787 3747
3788 /* Assume that the test fails, if it succeeds then the test 3748 /* Assume that the test fails, if it succeeds then the test
3789 * MSI irq handler will unset this flag */ 3749 * MSI irq handler will unset this flag
3750 */
3790 adapter->flags |= FLAG_MSI_TEST_FAILED; 3751 adapter->flags |= FLAG_MSI_TEST_FAILED;
3791 3752
3792 err = pci_enable_msi(adapter->pdev); 3753 err = pci_enable_msi(adapter->pdev);
@@ -3800,8 +3761,7 @@ static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
3800 goto msi_test_failed; 3761 goto msi_test_failed;
3801 } 3762 }
3802 3763
3803 /* 3764 /* Force memory writes to complete before enabling and firing an
3804 * Force memory writes to complete before enabling and firing an
3805 * interrupt. 3765 * interrupt.
3806 */ 3766 */
3807 wmb(); 3767 wmb();
@@ -3901,8 +3861,7 @@ static int e1000_open(struct net_device *netdev)
3901 if (err) 3861 if (err)
3902 goto err_setup_rx; 3862 goto err_setup_rx;
3903 3863
3904 /* 3864 /* If AMT is enabled, let the firmware know that the network
3905 * If AMT is enabled, let the firmware know that the network
3906 * interface is now open and reset the part to a known state. 3865 * interface is now open and reset the part to a known state.
3907 */ 3866 */
3908 if (adapter->flags & FLAG_HAS_AMT) { 3867 if (adapter->flags & FLAG_HAS_AMT) {
@@ -3923,8 +3882,7 @@ static int e1000_open(struct net_device *netdev)
3923 PM_QOS_CPU_DMA_LATENCY, 3882 PM_QOS_CPU_DMA_LATENCY,
3924 PM_QOS_DEFAULT_VALUE); 3883 PM_QOS_DEFAULT_VALUE);
3925 3884
3926 /* 3885 /* before we allocate an interrupt, we must be ready to handle it.
3927 * before we allocate an interrupt, we must be ready to handle it.
3928 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3886 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3929 * as soon as we call pci_request_irq, so we have to setup our 3887 * as soon as we call pci_request_irq, so we have to setup our
3930 * clean_rx handler before we do so. 3888 * clean_rx handler before we do so.
@@ -3935,8 +3893,7 @@ static int e1000_open(struct net_device *netdev)
3935 if (err) 3893 if (err)
3936 goto err_req_irq; 3894 goto err_req_irq;
3937 3895
3938 /* 3896 /* Work around PCIe errata with MSI interrupts causing some chipsets to
3939 * Work around PCIe errata with MSI interrupts causing some chipsets to
3940 * ignore e1000e MSI messages, which means we need to test our MSI 3897 * ignore e1000e MSI messages, which means we need to test our MSI
3941 * interrupt now 3898 * interrupt now
3942 */ 3899 */
@@ -4017,16 +3974,14 @@ static int e1000_close(struct net_device *netdev)
4017 e1000e_free_tx_resources(adapter->tx_ring); 3974 e1000e_free_tx_resources(adapter->tx_ring);
4018 e1000e_free_rx_resources(adapter->rx_ring); 3975 e1000e_free_rx_resources(adapter->rx_ring);
4019 3976
4020 /* 3977 /* kill manageability vlan ID if supported, but not if a vlan with
4021 * kill manageability vlan ID if supported, but not if a vlan with
4022 * the same ID is registered on the host OS (let 8021q kill it) 3978 * the same ID is registered on the host OS (let 8021q kill it)
4023 */ 3979 */
4024 if (adapter->hw.mng_cookie.status & 3980 if (adapter->hw.mng_cookie.status &
4025 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) 3981 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
4026 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id); 3982 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4027 3983
4028 /* 3984 /* If AMT is enabled, let the firmware know that the network
4029 * If AMT is enabled, let the firmware know that the network
4030 * interface is now closed 3985 * interface is now closed
4031 */ 3986 */
4032 if ((adapter->flags & FLAG_HAS_AMT) && 3987 if ((adapter->flags & FLAG_HAS_AMT) &&
@@ -4065,8 +4020,7 @@ static int e1000_set_mac(struct net_device *netdev, void *p)
4065 /* activate the work around */ 4020 /* activate the work around */
4066 e1000e_set_laa_state_82571(&adapter->hw, 1); 4021 e1000e_set_laa_state_82571(&adapter->hw, 1);
4067 4022
4068 /* 4023 /* Hold a copy of the LAA in RAR[14] This is done so that
4069 * Hold a copy of the LAA in RAR[14] This is done so that
4070 * between the time RAR[0] gets clobbered and the time it 4024 * between the time RAR[0] gets clobbered and the time it
4071 * gets fixed (in e1000_watchdog), the actual LAA is in one 4025 * gets fixed (in e1000_watchdog), the actual LAA is in one
4072 * of the RARs and no incoming packets directed to this port 4026 * of the RARs and no incoming packets directed to this port
@@ -4099,10 +4053,13 @@ static void e1000e_update_phy_task(struct work_struct *work)
4099 e1000_get_phy_info(&adapter->hw); 4053 e1000_get_phy_info(&adapter->hw);
4100} 4054}
4101 4055
4102/* 4056/**
4057 * e1000_update_phy_info - timre call-back to update PHY info
4058 * @data: pointer to adapter cast into an unsigned long
4059 *
4103 * Need to wait a few seconds after link up to get diagnostic information from 4060 * Need to wait a few seconds after link up to get diagnostic information from
4104 * the phy 4061 * the phy
4105 */ 4062 **/
4106static void e1000_update_phy_info(unsigned long data) 4063static void e1000_update_phy_info(unsigned long data)
4107{ 4064{
4108 struct e1000_adapter *adapter = (struct e1000_adapter *) data; 4065 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
@@ -4129,8 +4086,7 @@ static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4129 if (ret_val) 4086 if (ret_val)
4130 return; 4087 return;
4131 4088
4132 /* 4089 /* A page set is expensive so check if already on desired page.
4133 * A page set is expensive so check if already on desired page.
4134 * If not, set to the page with the PHY status registers. 4090 * If not, set to the page with the PHY status registers.
4135 */ 4091 */
4136 hw->phy.addr = 1; 4092 hw->phy.addr = 1;
@@ -4201,8 +4157,7 @@ static void e1000e_update_stats(struct e1000_adapter *adapter)
4201 struct e1000_hw *hw = &adapter->hw; 4157 struct e1000_hw *hw = &adapter->hw;
4202 struct pci_dev *pdev = adapter->pdev; 4158 struct pci_dev *pdev = adapter->pdev;
4203 4159
4204 /* 4160 /* Prevent stats update while adapter is being reset, or if the pci
4205 * Prevent stats update while adapter is being reset, or if the pci
4206 * connection is down. 4161 * connection is down.
4207 */ 4162 */
4208 if (adapter->link_speed == 0) 4163 if (adapter->link_speed == 0)
@@ -4270,8 +4225,7 @@ static void e1000e_update_stats(struct e1000_adapter *adapter)
4270 4225
4271 /* Rx Errors */ 4226 /* Rx Errors */
4272 4227
4273 /* 4228 /* RLEC on some newer hardware can be incorrect so build
4274 * RLEC on some newer hardware can be incorrect so build
4275 * our own version based on RUC and ROC 4229 * our own version based on RUC and ROC
4276 */ 4230 */
4277 netdev->stats.rx_errors = adapter->stats.rxerrc + 4231 netdev->stats.rx_errors = adapter->stats.rxerrc +
@@ -4323,8 +4277,7 @@ static void e1000_phy_read_status(struct e1000_adapter *adapter)
4323 if (ret_val) 4277 if (ret_val)
4324 e_warn("Error reading PHY register\n"); 4278 e_warn("Error reading PHY register\n");
4325 } else { 4279 } else {
4326 /* 4280 /* Do not read PHY registers if link is not up
4327 * Do not read PHY registers if link is not up
4328 * Set values to typical power-on defaults 4281 * Set values to typical power-on defaults
4329 */ 4282 */
4330 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX); 4283 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
@@ -4362,8 +4315,7 @@ static bool e1000e_has_link(struct e1000_adapter *adapter)
4362 bool link_active = false; 4315 bool link_active = false;
4363 s32 ret_val = 0; 4316 s32 ret_val = 0;
4364 4317
4365 /* 4318 /* get_link_status is set on LSC (link status) interrupt or
4366 * get_link_status is set on LSC (link status) interrupt or
4367 * Rx sequence error interrupt. get_link_status will stay 4319 * Rx sequence error interrupt. get_link_status will stay
4368 * false until the check_for_link establishes link 4320 * false until the check_for_link establishes link
4369 * for copper adapters ONLY 4321 * for copper adapters ONLY
@@ -4415,8 +4367,7 @@ static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4415{ 4367{
4416 struct e1000_hw *hw = &adapter->hw; 4368 struct e1000_hw *hw = &adapter->hw;
4417 4369
4418 /* 4370 /* With 82574 controllers, PHY needs to be checked periodically
4419 * With 82574 controllers, PHY needs to be checked periodically
4420 * for hung state and reset, if two calls return true 4371 * for hung state and reset, if two calls return true
4421 */ 4372 */
4422 if (e1000_check_phy_82574(hw)) 4373 if (e1000_check_phy_82574(hw))
@@ -4484,8 +4435,7 @@ static void e1000_watchdog_task(struct work_struct *work)
4484 &adapter->link_speed, 4435 &adapter->link_speed,
4485 &adapter->link_duplex); 4436 &adapter->link_duplex);
4486 e1000_print_link_info(adapter); 4437 e1000_print_link_info(adapter);
4487 /* 4438 /* On supported PHYs, check for duplex mismatch only
4488 * On supported PHYs, check for duplex mismatch only
4489 * if link has autonegotiated at 10/100 half 4439 * if link has autonegotiated at 10/100 half
4490 */ 4440 */
4491 if ((hw->phy.type == e1000_phy_igp_3 || 4441 if ((hw->phy.type == e1000_phy_igp_3 ||
@@ -4515,8 +4465,7 @@ static void e1000_watchdog_task(struct work_struct *work)
4515 break; 4465 break;
4516 } 4466 }
4517 4467
4518 /* 4468 /* workaround: re-program speed mode bit after
4519 * workaround: re-program speed mode bit after
4520 * link-up event 4469 * link-up event
4521 */ 4470 */
4522 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) && 4471 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
@@ -4527,8 +4476,7 @@ static void e1000_watchdog_task(struct work_struct *work)
4527 ew32(TARC(0), tarc0); 4476 ew32(TARC(0), tarc0);
4528 } 4477 }
4529 4478
4530 /* 4479 /* disable TSO for pcie and 10/100 speeds, to avoid
4531 * disable TSO for pcie and 10/100 speeds, to avoid
4532 * some hardware issues 4480 * some hardware issues
4533 */ 4481 */
4534 if (!(adapter->flags & FLAG_TSO_FORCE)) { 4482 if (!(adapter->flags & FLAG_TSO_FORCE)) {
@@ -4549,16 +4497,14 @@ static void e1000_watchdog_task(struct work_struct *work)
4549 } 4497 }
4550 } 4498 }
4551 4499
4552 /* 4500 /* enable transmits in the hardware, need to do this
4553 * enable transmits in the hardware, need to do this
4554 * after setting TARC(0) 4501 * after setting TARC(0)
4555 */ 4502 */
4556 tctl = er32(TCTL); 4503 tctl = er32(TCTL);
4557 tctl |= E1000_TCTL_EN; 4504 tctl |= E1000_TCTL_EN;
4558 ew32(TCTL, tctl); 4505 ew32(TCTL, tctl);
4559 4506
4560 /* 4507 /* Perform any post-link-up configuration before
4561 * Perform any post-link-up configuration before
4562 * reporting link up. 4508 * reporting link up.
4563 */ 4509 */
4564 if (phy->ops.cfg_on_link_up) 4510 if (phy->ops.cfg_on_link_up)
@@ -4609,8 +4555,7 @@ link_up:
4609 4555
4610 if (!netif_carrier_ok(netdev) && 4556 if (!netif_carrier_ok(netdev) &&
4611 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) { 4557 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) {
4612 /* 4558 /* We've lost link, so the controller stops DMA,
4613 * We've lost link, so the controller stops DMA,
4614 * but we've got queued Tx work that's never going 4559 * but we've got queued Tx work that's never going
4615 * to get done, so reset controller to flush Tx. 4560 * to get done, so reset controller to flush Tx.
4616 * (Do the reset outside of interrupt context). 4561 * (Do the reset outside of interrupt context).
@@ -4622,8 +4567,7 @@ link_up:
4622 4567
4623 /* Simple mode for Interrupt Throttle Rate (ITR) */ 4568 /* Simple mode for Interrupt Throttle Rate (ITR) */
4624 if (adapter->itr_setting == 4) { 4569 if (adapter->itr_setting == 4) {
4625 /* 4570 /* Symmetric Tx/Rx gets a reduced ITR=2000;
4626 * Symmetric Tx/Rx gets a reduced ITR=2000;
4627 * Total asymmetrical Tx or Rx gets ITR=8000; 4571 * Total asymmetrical Tx or Rx gets ITR=8000;
4628 * everyone else is between 2000-8000. 4572 * everyone else is between 2000-8000.
4629 */ 4573 */
@@ -4648,8 +4592,7 @@ link_up:
4648 /* Force detection of hung controller every watchdog period */ 4592 /* Force detection of hung controller every watchdog period */
4649 adapter->detect_tx_hung = true; 4593 adapter->detect_tx_hung = true;
4650 4594
4651 /* 4595 /* With 82571 controllers, LAA may be overwritten due to controller
4652 * With 82571 controllers, LAA may be overwritten due to controller
4653 * reset from the other port. Set the appropriate LAA in RAR[0] 4596 * reset from the other port. Set the appropriate LAA in RAR[0]
4654 */ 4597 */
4655 if (e1000e_get_laa_state_82571(hw)) 4598 if (e1000e_get_laa_state_82571(hw))
@@ -4948,8 +4891,7 @@ static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
4948 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) 4891 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
4949 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS)); 4892 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
4950 4893
4951 /* 4894 /* Force memory writes to complete before letting h/w
4952 * Force memory writes to complete before letting h/w
4953 * know there are new descriptors to fetch. (Only 4895 * know there are new descriptors to fetch. (Only
4954 * applicable for weak-ordered memory model archs, 4896 * applicable for weak-ordered memory model archs,
4955 * such as IA-64). 4897 * such as IA-64).
@@ -4963,8 +4905,7 @@ static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
4963 else 4905 else
4964 writel(i, tx_ring->tail); 4906 writel(i, tx_ring->tail);
4965 4907
4966 /* 4908 /* we need this if more than one processor can write to our tail
4967 * we need this if more than one processor can write to our tail
4968 * at a time, it synchronizes IO on IA64/Altix systems 4909 * at a time, it synchronizes IO on IA64/Altix systems
4969 */ 4910 */
4970 mmiowb(); 4911 mmiowb();
@@ -5014,15 +4955,13 @@ static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5014 struct e1000_adapter *adapter = tx_ring->adapter; 4955 struct e1000_adapter *adapter = tx_ring->adapter;
5015 4956
5016 netif_stop_queue(adapter->netdev); 4957 netif_stop_queue(adapter->netdev);
5017 /* 4958 /* Herbert's original patch had:
5018 * Herbert's original patch had:
5019 * smp_mb__after_netif_stop_queue(); 4959 * smp_mb__after_netif_stop_queue();
5020 * but since that doesn't exist yet, just open code it. 4960 * but since that doesn't exist yet, just open code it.
5021 */ 4961 */
5022 smp_mb(); 4962 smp_mb();
5023 4963
5024 /* 4964 /* We need to check again in a case another CPU has just
5025 * We need to check again in a case another CPU has just
5026 * made room available. 4965 * made room available.
5027 */ 4966 */
5028 if (e1000_desc_unused(tx_ring) < size) 4967 if (e1000_desc_unused(tx_ring) < size)
@@ -5067,8 +5006,7 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5067 return NETDEV_TX_OK; 5006 return NETDEV_TX_OK;
5068 } 5007 }
5069 5008
5070 /* 5009 /* The minimum packet size with TCTL.PSP set is 17 bytes so
5071 * The minimum packet size with TCTL.PSP set is 17 bytes so
5072 * pad skb in order to meet this minimum size requirement 5010 * pad skb in order to meet this minimum size requirement
5073 */ 5011 */
5074 if (unlikely(skb->len < 17)) { 5012 if (unlikely(skb->len < 17)) {
@@ -5082,14 +5020,12 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5082 if (mss) { 5020 if (mss) {
5083 u8 hdr_len; 5021 u8 hdr_len;
5084 5022
5085 /* 5023 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5086 * TSO Workaround for 82571/2/3 Controllers -- if skb->data
5087 * points to just header, pull a few bytes of payload from 5024 * points to just header, pull a few bytes of payload from
5088 * frags into skb->data 5025 * frags into skb->data
5089 */ 5026 */
5090 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 5027 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5091 /* 5028 /* we do this workaround for ES2LAN, but it is un-necessary,
5092 * we do this workaround for ES2LAN, but it is un-necessary,
5093 * avoiding it could save a lot of cycles 5029 * avoiding it could save a lot of cycles
5094 */ 5030 */
5095 if (skb->data_len && (hdr_len == len)) { 5031 if (skb->data_len && (hdr_len == len)) {
@@ -5120,8 +5056,7 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5120 if (adapter->hw.mac.tx_pkt_filtering) 5056 if (adapter->hw.mac.tx_pkt_filtering)
5121 e1000_transfer_dhcp_info(adapter, skb); 5057 e1000_transfer_dhcp_info(adapter, skb);
5122 5058
5123 /* 5059 /* need: count + 2 desc gap to keep tail from touching
5124 * need: count + 2 desc gap to keep tail from touching
5125 * head, otherwise try next time 5060 * head, otherwise try next time
5126 */ 5061 */
5127 if (e1000_maybe_stop_tx(tx_ring, count + 2)) 5062 if (e1000_maybe_stop_tx(tx_ring, count + 2))
@@ -5145,8 +5080,7 @@ static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5145 else if (e1000_tx_csum(tx_ring, skb)) 5080 else if (e1000_tx_csum(tx_ring, skb))
5146 tx_flags |= E1000_TX_FLAGS_CSUM; 5081 tx_flags |= E1000_TX_FLAGS_CSUM;
5147 5082
5148 /* 5083 /* Old method was to assume IPv4 packet by default if TSO was enabled.
5149 * Old method was to assume IPv4 packet by default if TSO was enabled.
5150 * 82571 hardware supports TSO capabilities for IPv6 as well... 5084 * 82571 hardware supports TSO capabilities for IPv6 as well...
5151 * no longer assume, we must. 5085 * no longer assume, we must.
5152 */ 5086 */
@@ -5233,8 +5167,7 @@ struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
5233 5167
5234 /* Rx Errors */ 5168 /* Rx Errors */
5235 5169
5236 /* 5170 /* RLEC on some newer hardware can be incorrect so build
5237 * RLEC on some newer hardware can be incorrect so build
5238 * our own version based on RUC and ROC 5171 * our own version based on RUC and ROC
5239 */ 5172 */
5240 stats->rx_errors = adapter->stats.rxerrc + 5173 stats->rx_errors = adapter->stats.rxerrc +
@@ -5303,8 +5236,7 @@ static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5303 if (netif_running(netdev)) 5236 if (netif_running(netdev))
5304 e1000e_down(adapter); 5237 e1000e_down(adapter);
5305 5238
5306 /* 5239 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
5307 * NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
5308 * means we reserve 2 more, this pushes us to allocate from the next 5240 * means we reserve 2 more, this pushes us to allocate from the next
5309 * larger slab size. 5241 * larger slab size.
5310 * i.e. RXBUFFER_2048 --> size-4096 slab 5242 * i.e. RXBUFFER_2048 --> size-4096 slab
@@ -5566,8 +5498,7 @@ static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
5566 if (adapter->hw.phy.type == e1000_phy_igp_3) 5498 if (adapter->hw.phy.type == e1000_phy_igp_3)
5567 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); 5499 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
5568 5500
5569 /* 5501 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5570 * Release control of h/w to f/w. If f/w is AMT enabled, this
5571 * would have already happened in close and is redundant. 5502 * would have already happened in close and is redundant.
5572 */ 5503 */
5573 e1000e_release_hw_control(adapter); 5504 e1000e_release_hw_control(adapter);
@@ -5594,8 +5525,7 @@ static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep,
5594 struct net_device *netdev = pci_get_drvdata(pdev); 5525 struct net_device *netdev = pci_get_drvdata(pdev);
5595 struct e1000_adapter *adapter = netdev_priv(netdev); 5526 struct e1000_adapter *adapter = netdev_priv(netdev);
5596 5527
5597 /* 5528 /* The pci-e switch on some quad port adapters will report a
5598 * The pci-e switch on some quad port adapters will report a
5599 * correctable error when the MAC transitions from D0 to D3. To 5529 * correctable error when the MAC transitions from D0 to D3. To
5600 * prevent this we need to mask off the correctable errors on the 5530 * prevent this we need to mask off the correctable errors on the
5601 * downstream port of the pci-e switch. 5531 * downstream port of the pci-e switch.
@@ -5624,8 +5554,7 @@ static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
5624#else 5554#else
5625static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state) 5555static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
5626{ 5556{
5627 /* 5557 /* Both device and parent should have the same ASPM setting.
5628 * Both device and parent should have the same ASPM setting.
5629 * Disable ASPM in downstream component first and then upstream. 5558 * Disable ASPM in downstream component first and then upstream.
5630 */ 5559 */
5631 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, state); 5560 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, state);
@@ -5719,8 +5648,7 @@ static int __e1000_resume(struct pci_dev *pdev)
5719 5648
5720 netif_device_attach(netdev); 5649 netif_device_attach(netdev);
5721 5650
5722 /* 5651 /* If the controller has AMT, do not set DRV_LOAD until the interface
5723 * If the controller has AMT, do not set DRV_LOAD until the interface
5724 * is up. For all other cases, let the f/w know that the h/w is now 5652 * is up. For all other cases, let the f/w know that the h/w is now
5725 * under the control of the driver. 5653 * under the control of the driver.
5726 */ 5654 */
@@ -5848,7 +5776,10 @@ static irqreturn_t e1000_intr_msix(int irq, void *data)
5848 return IRQ_HANDLED; 5776 return IRQ_HANDLED;
5849} 5777}
5850 5778
5851/* 5779/**
5780 * e1000_netpoll
5781 * @netdev: network interface device structure
5782 *
5852 * Polling 'interrupt' - used by things like netconsole to send skbs 5783 * Polling 'interrupt' - used by things like netconsole to send skbs
5853 * without having to re-enable interrupts. It's not called while 5784 * without having to re-enable interrupts. It's not called while
5854 * the interrupt routine is executing. 5785 * the interrupt routine is executing.
@@ -5973,8 +5904,7 @@ static void e1000_io_resume(struct pci_dev *pdev)
5973 5904
5974 netif_device_attach(netdev); 5905 netif_device_attach(netdev);
5975 5906
5976 /* 5907 /* If the controller has AMT, do not set DRV_LOAD until the interface
5977 * If the controller has AMT, do not set DRV_LOAD until the interface
5978 * is up. For all other cases, let the f/w know that the h/w is now 5908 * is up. For all other cases, let the f/w know that the h/w is now
5979 * under the control of the driver. 5909 * under the control of the driver.
5980 */ 5910 */
@@ -6273,14 +6203,12 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
6273 if (e1000e_enable_mng_pass_thru(&adapter->hw)) 6203 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6274 adapter->flags |= FLAG_MNG_PT_ENABLED; 6204 adapter->flags |= FLAG_MNG_PT_ENABLED;
6275 6205
6276 /* 6206 /* before reading the NVM, reset the controller to
6277 * before reading the NVM, reset the controller to
6278 * put the device in a known good starting state 6207 * put the device in a known good starting state
6279 */ 6208 */
6280 adapter->hw.mac.ops.reset_hw(&adapter->hw); 6209 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6281 6210
6282 /* 6211 /* systems with ASPM and others may see the checksum fail on the first
6283 * systems with ASPM and others may see the checksum fail on the first
6284 * attempt. Let's give it a few tries 6212 * attempt. Let's give it a few tries
6285 */ 6213 */
6286 for (i = 0;; i++) { 6214 for (i = 0;; i++) {
@@ -6335,8 +6263,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
6335 adapter->rx_ring->count = E1000_DEFAULT_RXD; 6263 adapter->rx_ring->count = E1000_DEFAULT_RXD;
6336 adapter->tx_ring->count = E1000_DEFAULT_TXD; 6264 adapter->tx_ring->count = E1000_DEFAULT_TXD;
6337 6265
6338 /* 6266 /* Initial Wake on LAN setting - If APM wake is enabled in
6339 * Initial Wake on LAN setting - If APM wake is enabled in
6340 * the EEPROM, enable the ACPI Magic Packet filter 6267 * the EEPROM, enable the ACPI Magic Packet filter
6341 */ 6268 */
6342 if (adapter->flags & FLAG_APME_IN_WUC) { 6269 if (adapter->flags & FLAG_APME_IN_WUC) {
@@ -6360,8 +6287,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
6360 if (eeprom_data & eeprom_apme_mask) 6287 if (eeprom_data & eeprom_apme_mask)
6361 adapter->eeprom_wol |= E1000_WUFC_MAG; 6288 adapter->eeprom_wol |= E1000_WUFC_MAG;
6362 6289
6363 /* 6290 /* now that we have the eeprom settings, apply the special cases
6364 * now that we have the eeprom settings, apply the special cases
6365 * where the eeprom may be wrong or the board simply won't support 6291 * where the eeprom may be wrong or the board simply won't support
6366 * wake on lan on a particular port 6292 * wake on lan on a particular port
6367 */ 6293 */
@@ -6378,8 +6304,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
6378 /* reset the hardware with the new settings */ 6304 /* reset the hardware with the new settings */
6379 e1000e_reset(adapter); 6305 e1000e_reset(adapter);
6380 6306
6381 /* 6307 /* If the controller has AMT, do not set DRV_LOAD until the interface
6382 * If the controller has AMT, do not set DRV_LOAD until the interface
6383 * is up. For all other cases, let the f/w know that the h/w is now 6308 * is up. For all other cases, let the f/w know that the h/w is now
6384 * under the control of the driver. 6309 * under the control of the driver.
6385 */ 6310 */
@@ -6442,8 +6367,7 @@ static void __devexit e1000_remove(struct pci_dev *pdev)
6442 struct e1000_adapter *adapter = netdev_priv(netdev); 6367 struct e1000_adapter *adapter = netdev_priv(netdev);
6443 bool down = test_bit(__E1000_DOWN, &adapter->state); 6368 bool down = test_bit(__E1000_DOWN, &adapter->state);
6444 6369
6445 /* 6370 /* The timers may be rescheduled, so explicitly disable them
6446 * The timers may be rescheduled, so explicitly disable them
6447 * from being rescheduled. 6371 * from being rescheduled.
6448 */ 6372 */
6449 if (!down) 6373 if (!down)
@@ -6468,8 +6392,7 @@ static void __devexit e1000_remove(struct pci_dev *pdev)
6468 if (pci_dev_run_wake(pdev)) 6392 if (pci_dev_run_wake(pdev))
6469 pm_runtime_get_noresume(&pdev->dev); 6393 pm_runtime_get_noresume(&pdev->dev);
6470 6394
6471 /* 6395 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6472 * Release control of h/w to f/w. If f/w is AMT enabled, this
6473 * would have already happened in close and is redundant. 6396 * would have already happened in close and is redundant.
6474 */ 6397 */
6475 e1000e_release_hw_control(adapter); 6398 e1000e_release_hw_control(adapter);
diff --git a/drivers/net/ethernet/intel/e1000e/nvm.c b/drivers/net/ethernet/intel/e1000e/nvm.c
index a969f1af1b4e..b6468804cb2e 100644
--- a/drivers/net/ethernet/intel/e1000e/nvm.c
+++ b/drivers/net/ethernet/intel/e1000e/nvm.c
@@ -279,8 +279,7 @@ static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
279 e1e_flush(); 279 e1e_flush();
280 udelay(1); 280 udelay(1);
281 281
282 /* 282 /* Read "Status Register" repeatedly until the LSB is cleared.
283 * Read "Status Register" repeatedly until the LSB is cleared.
284 * The EEPROM will signal that the command has been completed 283 * The EEPROM will signal that the command has been completed
285 * by clearing bit 0 of the internal status register. If it's 284 * by clearing bit 0 of the internal status register. If it's
286 * not cleared within 'timeout', then error out. 285 * not cleared within 'timeout', then error out.
@@ -321,8 +320,7 @@ s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
321 u32 i, eerd = 0; 320 u32 i, eerd = 0;
322 s32 ret_val = 0; 321 s32 ret_val = 0;
323 322
324 /* 323 /* A check for invalid values: offset too large, too many words,
325 * A check for invalid values: offset too large, too many words,
326 * too many words for the offset, and not enough words. 324 * too many words for the offset, and not enough words.
327 */ 325 */
328 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 326 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
@@ -364,8 +362,7 @@ s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
364 s32 ret_val; 362 s32 ret_val;
365 u16 widx = 0; 363 u16 widx = 0;
366 364
367 /* 365 /* A check for invalid values: offset too large, too many words,
368 * A check for invalid values: offset too large, too many words,
369 * and not enough words. 366 * and not enough words.
370 */ 367 */
371 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 368 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
@@ -393,8 +390,7 @@ s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
393 390
394 e1000_standby_nvm(hw); 391 e1000_standby_nvm(hw);
395 392
396 /* 393 /* Some SPI eeproms use the 8th address bit embedded in the
397 * Some SPI eeproms use the 8th address bit embedded in the
398 * opcode 394 * opcode
399 */ 395 */
400 if ((nvm->address_bits == 8) && (offset >= 128)) 396 if ((nvm->address_bits == 8) && (offset >= 128))
@@ -461,8 +457,7 @@ s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
461 return ret_val; 457 return ret_val;
462 } 458 }
463 459
464 /* 460 /* if nvm_data is not ptr guard the PBA must be in legacy format which
465 * if nvm_data is not ptr guard the PBA must be in legacy format which
466 * means pba_ptr is actually our second data word for the PBA number 461 * means pba_ptr is actually our second data word for the PBA number
467 * and we can decode it into an ascii string 462 * and we can decode it into an ascii string
468 */ 463 */
diff --git a/drivers/net/ethernet/intel/e1000e/param.c b/drivers/net/ethernet/intel/e1000e/param.c
index dfbfa7fd98c3..1fbb31554e4d 100644
--- a/drivers/net/ethernet/intel/e1000e/param.c
+++ b/drivers/net/ethernet/intel/e1000e/param.c
@@ -32,11 +32,9 @@
32 32
33#include "e1000.h" 33#include "e1000.h"
34 34
35/* 35/* This is the only thing that needs to be changed to adjust the
36 * This is the only thing that needs to be changed to adjust the
37 * maximum number of ports that the driver can manage. 36 * maximum number of ports that the driver can manage.
38 */ 37 */
39
40#define E1000_MAX_NIC 32 38#define E1000_MAX_NIC 32
41 39
42#define OPTION_UNSET -1 40#define OPTION_UNSET -1
@@ -49,12 +47,10 @@ module_param(copybreak, uint, 0644);
49MODULE_PARM_DESC(copybreak, 47MODULE_PARM_DESC(copybreak,
50 "Maximum size of packet that is copied to a new buffer on receive"); 48 "Maximum size of packet that is copied to a new buffer on receive");
51 49
52/* 50/* All parameters are treated the same, as an integer array of values.
53 * All parameters are treated the same, as an integer array of values.
54 * This macro just reduces the need to repeat the same declaration code 51 * This macro just reduces the need to repeat the same declaration code
55 * over and over (plus this helps to avoid typo bugs). 52 * over and over (plus this helps to avoid typo bugs).
56 */ 53 */
57
58#define E1000_PARAM_INIT { [0 ... E1000_MAX_NIC] = OPTION_UNSET } 54#define E1000_PARAM_INIT { [0 ... E1000_MAX_NIC] = OPTION_UNSET }
59#define E1000_PARAM(X, desc) \ 55#define E1000_PARAM(X, desc) \
60 static int __devinitdata X[E1000_MAX_NIC+1] \ 56 static int __devinitdata X[E1000_MAX_NIC+1] \
@@ -63,8 +59,7 @@ MODULE_PARM_DESC(copybreak,
63 module_param_array_named(X, X, int, &num_##X, 0); \ 59 module_param_array_named(X, X, int, &num_##X, 0); \
64 MODULE_PARM_DESC(X, desc); 60 MODULE_PARM_DESC(X, desc);
65 61
66/* 62/* Transmit Interrupt Delay in units of 1.024 microseconds
67 * Transmit Interrupt Delay in units of 1.024 microseconds
68 * Tx interrupt delay needs to typically be set to something non-zero 63 * Tx interrupt delay needs to typically be set to something non-zero
69 * 64 *
70 * Valid Range: 0-65535 65 * Valid Range: 0-65535
@@ -74,8 +69,7 @@ E1000_PARAM(TxIntDelay, "Transmit Interrupt Delay");
74#define MAX_TXDELAY 0xFFFF 69#define MAX_TXDELAY 0xFFFF
75#define MIN_TXDELAY 0 70#define MIN_TXDELAY 0
76 71
77/* 72/* Transmit Absolute Interrupt Delay in units of 1.024 microseconds
78 * Transmit Absolute Interrupt Delay in units of 1.024 microseconds
79 * 73 *
80 * Valid Range: 0-65535 74 * Valid Range: 0-65535
81 */ 75 */
@@ -84,8 +78,7 @@ E1000_PARAM(TxAbsIntDelay, "Transmit Absolute Interrupt Delay");
84#define MAX_TXABSDELAY 0xFFFF 78#define MAX_TXABSDELAY 0xFFFF
85#define MIN_TXABSDELAY 0 79#define MIN_TXABSDELAY 0
86 80
87/* 81/* Receive Interrupt Delay in units of 1.024 microseconds
88 * Receive Interrupt Delay in units of 1.024 microseconds
89 * hardware will likely hang if you set this to anything but zero. 82 * hardware will likely hang if you set this to anything but zero.
90 * 83 *
91 * Valid Range: 0-65535 84 * Valid Range: 0-65535
@@ -94,8 +87,7 @@ E1000_PARAM(RxIntDelay, "Receive Interrupt Delay");
94#define MAX_RXDELAY 0xFFFF 87#define MAX_RXDELAY 0xFFFF
95#define MIN_RXDELAY 0 88#define MIN_RXDELAY 0
96 89
97/* 90/* Receive Absolute Interrupt Delay in units of 1.024 microseconds
98 * Receive Absolute Interrupt Delay in units of 1.024 microseconds
99 * 91 *
100 * Valid Range: 0-65535 92 * Valid Range: 0-65535
101 */ 93 */
@@ -103,8 +95,7 @@ E1000_PARAM(RxAbsIntDelay, "Receive Absolute Interrupt Delay");
103#define MAX_RXABSDELAY 0xFFFF 95#define MAX_RXABSDELAY 0xFFFF
104#define MIN_RXABSDELAY 0 96#define MIN_RXABSDELAY 0
105 97
106/* 98/* Interrupt Throttle Rate (interrupts/sec)
107 * Interrupt Throttle Rate (interrupts/sec)
108 * 99 *
109 * Valid Range: 100-100000 or one of: 0=off, 1=dynamic, 3=dynamic conservative 100 * Valid Range: 100-100000 or one of: 0=off, 1=dynamic, 3=dynamic conservative
110 */ 101 */
@@ -113,8 +104,7 @@ E1000_PARAM(InterruptThrottleRate, "Interrupt Throttling Rate");
113#define MAX_ITR 100000 104#define MAX_ITR 100000
114#define MIN_ITR 100 105#define MIN_ITR 100
115 106
116/* 107/* IntMode (Interrupt Mode)
117 * IntMode (Interrupt Mode)
118 * 108 *
119 * Valid Range: varies depending on kernel configuration & hardware support 109 * Valid Range: varies depending on kernel configuration & hardware support
120 * 110 *
@@ -132,8 +122,7 @@ E1000_PARAM(IntMode, "Interrupt Mode");
132#define MAX_INTMODE 2 122#define MAX_INTMODE 2
133#define MIN_INTMODE 0 123#define MIN_INTMODE 0
134 124
135/* 125/* Enable Smart Power Down of the PHY
136 * Enable Smart Power Down of the PHY
137 * 126 *
138 * Valid Range: 0, 1 127 * Valid Range: 0, 1
139 * 128 *
@@ -141,8 +130,7 @@ E1000_PARAM(IntMode, "Interrupt Mode");
141 */ 130 */
142E1000_PARAM(SmartPowerDownEnable, "Enable PHY smart power down"); 131E1000_PARAM(SmartPowerDownEnable, "Enable PHY smart power down");
143 132
144/* 133/* Enable Kumeran Lock Loss workaround
145 * Enable Kumeran Lock Loss workaround
146 * 134 *
147 * Valid Range: 0, 1 135 * Valid Range: 0, 1
148 * 136 *
@@ -150,8 +138,7 @@ E1000_PARAM(SmartPowerDownEnable, "Enable PHY smart power down");
150 */ 138 */
151E1000_PARAM(KumeranLockLoss, "Enable Kumeran lock loss workaround"); 139E1000_PARAM(KumeranLockLoss, "Enable Kumeran lock loss workaround");
152 140
153/* 141/* Write Protect NVM
154 * Write Protect NVM
155 * 142 *
156 * Valid Range: 0, 1 143 * Valid Range: 0, 1
157 * 144 *
@@ -159,8 +146,7 @@ E1000_PARAM(KumeranLockLoss, "Enable Kumeran lock loss workaround");
159 */ 146 */
160E1000_PARAM(WriteProtectNVM, "Write-protect NVM [WARNING: disabling this can lead to corrupted NVM]"); 147E1000_PARAM(WriteProtectNVM, "Write-protect NVM [WARNING: disabling this can lead to corrupted NVM]");
161 148
162/* 149/* Enable CRC Stripping
163 * Enable CRC Stripping
164 * 150 *
165 * Valid Range: 0, 1 151 * Valid Range: 0, 1
166 * 152 *
@@ -351,8 +337,7 @@ void __devinit e1000e_check_options(struct e1000_adapter *adapter)
351 if (num_InterruptThrottleRate > bd) { 337 if (num_InterruptThrottleRate > bd) {
352 adapter->itr = InterruptThrottleRate[bd]; 338 adapter->itr = InterruptThrottleRate[bd];
353 339
354 /* 340 /* Make sure a message is printed for non-special
355 * Make sure a message is printed for non-special
356 * values. And in case of an invalid option, display 341 * values. And in case of an invalid option, display
357 * warning, use default and go through itr/itr_setting 342 * warning, use default and go through itr/itr_setting
358 * adjustment logic below 343 * adjustment logic below
@@ -361,14 +346,12 @@ void __devinit e1000e_check_options(struct e1000_adapter *adapter)
361 e1000_validate_option(&adapter->itr, &opt, adapter)) 346 e1000_validate_option(&adapter->itr, &opt, adapter))
362 adapter->itr = opt.def; 347 adapter->itr = opt.def;
363 } else { 348 } else {
364 /* 349 /* If no option specified, use default value and go
365 * If no option specified, use default value and go
366 * through the logic below to adjust itr/itr_setting 350 * through the logic below to adjust itr/itr_setting
367 */ 351 */
368 adapter->itr = opt.def; 352 adapter->itr = opt.def;
369 353
370 /* 354 /* Make sure a message is printed for non-special
371 * Make sure a message is printed for non-special
372 * default values 355 * default values
373 */ 356 */
374 if (adapter->itr > 4) 357 if (adapter->itr > 4)
@@ -400,8 +383,7 @@ void __devinit e1000e_check_options(struct e1000_adapter *adapter)
400 opt.name); 383 opt.name);
401 break; 384 break;
402 default: 385 default:
403 /* 386 /* Save the setting, because the dynamic bits
404 * Save the setting, because the dynamic bits
405 * change itr. 387 * change itr.
406 * 388 *
407 * Clear the lower two bits because 389 * Clear the lower two bits because
diff --git a/drivers/net/ethernet/intel/e1000e/phy.c b/drivers/net/ethernet/intel/e1000e/phy.c
index fc62a3f3a5be..28b38ff37e84 100644
--- a/drivers/net/ethernet/intel/e1000e/phy.c
+++ b/drivers/net/ethernet/intel/e1000e/phy.c
@@ -193,8 +193,7 @@ s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
193 return -E1000_ERR_PARAM; 193 return -E1000_ERR_PARAM;
194 } 194 }
195 195
196 /* 196 /* Set up Op-code, Phy Address, and register offset in the MDI
197 * Set up Op-code, Phy Address, and register offset in the MDI
198 * Control register. The MAC will take care of interfacing with the 197 * Control register. The MAC will take care of interfacing with the
199 * PHY to retrieve the desired data. 198 * PHY to retrieve the desired data.
200 */ 199 */
@@ -204,8 +203,7 @@ s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
204 203
205 ew32(MDIC, mdic); 204 ew32(MDIC, mdic);
206 205
207 /* 206 /* Poll the ready bit to see if the MDI read completed
208 * Poll the ready bit to see if the MDI read completed
209 * Increasing the time out as testing showed failures with 207 * Increasing the time out as testing showed failures with
210 * the lower time out 208 * the lower time out
211 */ 209 */
@@ -225,8 +223,7 @@ s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
225 } 223 }
226 *data = (u16) mdic; 224 *data = (u16) mdic;
227 225
228 /* 226 /* Allow some time after each MDIC transaction to avoid
229 * Allow some time after each MDIC transaction to avoid
230 * reading duplicate data in the next MDIC transaction. 227 * reading duplicate data in the next MDIC transaction.
231 */ 228 */
232 if (hw->mac.type == e1000_pch2lan) 229 if (hw->mac.type == e1000_pch2lan)
@@ -253,8 +250,7 @@ s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
253 return -E1000_ERR_PARAM; 250 return -E1000_ERR_PARAM;
254 } 251 }
255 252
256 /* 253 /* Set up Op-code, Phy Address, and register offset in the MDI
257 * Set up Op-code, Phy Address, and register offset in the MDI
258 * Control register. The MAC will take care of interfacing with the 254 * Control register. The MAC will take care of interfacing with the
259 * PHY to retrieve the desired data. 255 * PHY to retrieve the desired data.
260 */ 256 */
@@ -265,8 +261,7 @@ s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
265 261
266 ew32(MDIC, mdic); 262 ew32(MDIC, mdic);
267 263
268 /* 264 /* Poll the ready bit to see if the MDI read completed
269 * Poll the ready bit to see if the MDI read completed
270 * Increasing the time out as testing showed failures with 265 * Increasing the time out as testing showed failures with
271 * the lower time out 266 * the lower time out
272 */ 267 */
@@ -285,8 +280,7 @@ s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
285 return -E1000_ERR_PHY; 280 return -E1000_ERR_PHY;
286 } 281 }
287 282
288 /* 283 /* Allow some time after each MDIC transaction to avoid
289 * Allow some time after each MDIC transaction to avoid
290 * reading duplicate data in the next MDIC transaction. 284 * reading duplicate data in the next MDIC transaction.
291 */ 285 */
292 if (hw->mac.type == e1000_pch2lan) 286 if (hw->mac.type == e1000_pch2lan)
@@ -708,8 +702,7 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
708 if (ret_val) 702 if (ret_val)
709 return ret_val; 703 return ret_val;
710 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK; 704 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
711 /* 705 /* Options:
712 * Options:
713 * 0 - Auto (default) 706 * 0 - Auto (default)
714 * 1 - MDI mode 707 * 1 - MDI mode
715 * 2 - MDI-X mode 708 * 2 - MDI-X mode
@@ -754,8 +747,7 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
754 if (phy->type != e1000_phy_bm) 747 if (phy->type != e1000_phy_bm)
755 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 748 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
756 749
757 /* 750 /* Options:
758 * Options:
759 * MDI/MDI-X = 0 (default) 751 * MDI/MDI-X = 0 (default)
760 * 0 - Auto for all speeds 752 * 0 - Auto for all speeds
761 * 1 - MDI mode 753 * 1 - MDI mode
@@ -780,8 +772,7 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
780 break; 772 break;
781 } 773 }
782 774
783 /* 775 /* Options:
784 * Options:
785 * disable_polarity_correction = 0 (default) 776 * disable_polarity_correction = 0 (default)
786 * Automatic Correction for Reversed Cable Polarity 777 * Automatic Correction for Reversed Cable Polarity
787 * 0 - Disabled 778 * 0 - Disabled
@@ -818,8 +809,7 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
818 if ((phy->type == e1000_phy_m88) && 809 if ((phy->type == e1000_phy_m88) &&
819 (phy->revision < E1000_REVISION_4) && 810 (phy->revision < E1000_REVISION_4) &&
820 (phy->id != BME1000_E_PHY_ID_R2)) { 811 (phy->id != BME1000_E_PHY_ID_R2)) {
821 /* 812 /* Force TX_CLK in the Extended PHY Specific Control Register
822 * Force TX_CLK in the Extended PHY Specific Control Register
823 * to 25MHz clock. 813 * to 25MHz clock.
824 */ 814 */
825 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 815 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
@@ -899,8 +889,7 @@ s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
899 return ret_val; 889 return ret_val;
900 } 890 }
901 891
902 /* 892 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
903 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
904 * timeout issues when LFS is enabled. 893 * timeout issues when LFS is enabled.
905 */ 894 */
906 msleep(100); 895 msleep(100);
@@ -936,8 +925,7 @@ s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
936 925
937 /* set auto-master slave resolution settings */ 926 /* set auto-master slave resolution settings */
938 if (hw->mac.autoneg) { 927 if (hw->mac.autoneg) {
939 /* 928 /* when autonegotiation advertisement is only 1000Mbps then we
940 * when autonegotiation advertisement is only 1000Mbps then we
941 * should disable SmartSpeed and enable Auto MasterSlave 929 * should disable SmartSpeed and enable Auto MasterSlave
942 * resolution as hardware default. 930 * resolution as hardware default.
943 */ 931 */
@@ -1001,16 +989,14 @@ static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1001 return ret_val; 989 return ret_val;
1002 } 990 }
1003 991
1004 /* 992 /* Need to parse both autoneg_advertised and fc and set up
1005 * Need to parse both autoneg_advertised and fc and set up
1006 * the appropriate PHY registers. First we will parse for 993 * the appropriate PHY registers. First we will parse for
1007 * autoneg_advertised software override. Since we can advertise 994 * autoneg_advertised software override. Since we can advertise
1008 * a plethora of combinations, we need to check each bit 995 * a plethora of combinations, we need to check each bit
1009 * individually. 996 * individually.
1010 */ 997 */
1011 998
1012 /* 999 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1013 * First we clear all the 10/100 mb speed bits in the Auto-Neg
1014 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1000 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1015 * the 1000Base-T Control Register (Address 9). 1001 * the 1000Base-T Control Register (Address 9).
1016 */ 1002 */
@@ -1056,8 +1042,7 @@ static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1056 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1042 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1057 } 1043 }
1058 1044
1059 /* 1045 /* Check for a software override of the flow control settings, and
1060 * Check for a software override of the flow control settings, and
1061 * setup the PHY advertisement registers accordingly. If 1046 * setup the PHY advertisement registers accordingly. If
1062 * auto-negotiation is enabled, then software will have to set the 1047 * auto-negotiation is enabled, then software will have to set the
1063 * "PAUSE" bits to the correct value in the Auto-Negotiation 1048 * "PAUSE" bits to the correct value in the Auto-Negotiation
@@ -1076,15 +1061,13 @@ static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1076 */ 1061 */
1077 switch (hw->fc.current_mode) { 1062 switch (hw->fc.current_mode) {
1078 case e1000_fc_none: 1063 case e1000_fc_none:
1079 /* 1064 /* Flow control (Rx & Tx) is completely disabled by a
1080 * Flow control (Rx & Tx) is completely disabled by a
1081 * software over-ride. 1065 * software over-ride.
1082 */ 1066 */
1083 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1067 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1084 break; 1068 break;
1085 case e1000_fc_rx_pause: 1069 case e1000_fc_rx_pause:
1086 /* 1070 /* Rx Flow control is enabled, and Tx Flow control is
1087 * Rx Flow control is enabled, and Tx Flow control is
1088 * disabled, by a software over-ride. 1071 * disabled, by a software over-ride.
1089 * 1072 *
1090 * Since there really isn't a way to advertise that we are 1073 * Since there really isn't a way to advertise that we are
@@ -1096,16 +1079,14 @@ static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1096 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1079 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1097 break; 1080 break;
1098 case e1000_fc_tx_pause: 1081 case e1000_fc_tx_pause:
1099 /* 1082 /* Tx Flow control is enabled, and Rx Flow control is
1100 * Tx Flow control is enabled, and Rx Flow control is
1101 * disabled, by a software over-ride. 1083 * disabled, by a software over-ride.
1102 */ 1084 */
1103 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1085 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1104 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1086 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1105 break; 1087 break;
1106 case e1000_fc_full: 1088 case e1000_fc_full:
1107 /* 1089 /* Flow control (both Rx and Tx) is enabled by a software
1108 * Flow control (both Rx and Tx) is enabled by a software
1109 * over-ride. 1090 * over-ride.
1110 */ 1091 */
1111 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1092 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
@@ -1142,14 +1123,12 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1142 s32 ret_val; 1123 s32 ret_val;
1143 u16 phy_ctrl; 1124 u16 phy_ctrl;
1144 1125
1145 /* 1126 /* Perform some bounds checking on the autoneg advertisement
1146 * Perform some bounds checking on the autoneg advertisement
1147 * parameter. 1127 * parameter.
1148 */ 1128 */
1149 phy->autoneg_advertised &= phy->autoneg_mask; 1129 phy->autoneg_advertised &= phy->autoneg_mask;
1150 1130
1151 /* 1131 /* If autoneg_advertised is zero, we assume it was not defaulted
1152 * If autoneg_advertised is zero, we assume it was not defaulted
1153 * by the calling code so we set to advertise full capability. 1132 * by the calling code so we set to advertise full capability.
1154 */ 1133 */
1155 if (!phy->autoneg_advertised) 1134 if (!phy->autoneg_advertised)
@@ -1163,8 +1142,7 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1163 } 1142 }
1164 e_dbg("Restarting Auto-Neg\n"); 1143 e_dbg("Restarting Auto-Neg\n");
1165 1144
1166 /* 1145 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1167 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1168 * the Auto Neg Restart bit in the PHY control register. 1146 * the Auto Neg Restart bit in the PHY control register.
1169 */ 1147 */
1170 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); 1148 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
@@ -1176,8 +1154,7 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1176 if (ret_val) 1154 if (ret_val)
1177 return ret_val; 1155 return ret_val;
1178 1156
1179 /* 1157 /* Does the user want to wait for Auto-Neg to complete here, or
1180 * Does the user want to wait for Auto-Neg to complete here, or
1181 * check at a later time (for example, callback routine). 1158 * check at a later time (for example, callback routine).
1182 */ 1159 */
1183 if (phy->autoneg_wait_to_complete) { 1160 if (phy->autoneg_wait_to_complete) {
@@ -1208,16 +1185,14 @@ s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1208 bool link; 1185 bool link;
1209 1186
1210 if (hw->mac.autoneg) { 1187 if (hw->mac.autoneg) {
1211 /* 1188 /* Setup autoneg and flow control advertisement and perform
1212 * Setup autoneg and flow control advertisement and perform
1213 * autonegotiation. 1189 * autonegotiation.
1214 */ 1190 */
1215 ret_val = e1000_copper_link_autoneg(hw); 1191 ret_val = e1000_copper_link_autoneg(hw);
1216 if (ret_val) 1192 if (ret_val)
1217 return ret_val; 1193 return ret_val;
1218 } else { 1194 } else {
1219 /* 1195 /* PHY will be set to 10H, 10F, 100H or 100F
1220 * PHY will be set to 10H, 10F, 100H or 100F
1221 * depending on user settings. 1196 * depending on user settings.
1222 */ 1197 */
1223 e_dbg("Forcing Speed and Duplex\n"); 1198 e_dbg("Forcing Speed and Duplex\n");
@@ -1228,8 +1203,7 @@ s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1228 } 1203 }
1229 } 1204 }
1230 1205
1231 /* 1206 /* Check link status. Wait up to 100 microseconds for link to become
1232 * Check link status. Wait up to 100 microseconds for link to become
1233 * valid. 1207 * valid.
1234 */ 1208 */
1235 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, 1209 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
@@ -1273,8 +1247,7 @@ s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1273 if (ret_val) 1247 if (ret_val)
1274 return ret_val; 1248 return ret_val;
1275 1249
1276 /* 1250 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1277 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1278 * forced whenever speed and duplex are forced. 1251 * forced whenever speed and duplex are forced.
1279 */ 1252 */
1280 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1253 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
@@ -1328,8 +1301,7 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1328 u16 phy_data; 1301 u16 phy_data;
1329 bool link; 1302 bool link;
1330 1303
1331 /* 1304 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1332 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1333 * forced whenever speed and duplex are forced. 1305 * forced whenever speed and duplex are forced.
1334 */ 1306 */
1335 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1307 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
@@ -1370,8 +1342,7 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1370 if (hw->phy.type != e1000_phy_m88) { 1342 if (hw->phy.type != e1000_phy_m88) {
1371 e_dbg("Link taking longer than expected.\n"); 1343 e_dbg("Link taking longer than expected.\n");
1372 } else { 1344 } else {
1373 /* 1345 /* We didn't get link.
1374 * We didn't get link.
1375 * Reset the DSP and cross our fingers. 1346 * Reset the DSP and cross our fingers.
1376 */ 1347 */
1377 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, 1348 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
@@ -1398,8 +1369,7 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1398 if (ret_val) 1369 if (ret_val)
1399 return ret_val; 1370 return ret_val;
1400 1371
1401 /* 1372 /* Resetting the phy means we need to re-force TX_CLK in the
1402 * Resetting the phy means we need to re-force TX_CLK in the
1403 * Extended PHY Specific Control Register to 25MHz clock from 1373 * Extended PHY Specific Control Register to 25MHz clock from
1404 * the reset value of 2.5MHz. 1374 * the reset value of 2.5MHz.
1405 */ 1375 */
@@ -1408,8 +1378,7 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1408 if (ret_val) 1378 if (ret_val)
1409 return ret_val; 1379 return ret_val;
1410 1380
1411 /* 1381 /* In addition, we must re-enable CRS on Tx for both half and full
1412 * In addition, we must re-enable CRS on Tx for both half and full
1413 * duplex. 1382 * duplex.
1414 */ 1383 */
1415 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1384 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
@@ -1573,8 +1542,7 @@ s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1573 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); 1542 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1574 if (ret_val) 1543 if (ret_val)
1575 return ret_val; 1544 return ret_val;
1576 /* 1545 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1577 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1578 * during Dx states where the power conservation is most 1546 * during Dx states where the power conservation is most
1579 * important. During driver activity we should enable 1547 * important. During driver activity we should enable
1580 * SmartSpeed, so performance is maintained. 1548 * SmartSpeed, so performance is maintained.
@@ -1702,8 +1670,7 @@ s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1702 s32 ret_val; 1670 s32 ret_val;
1703 u16 data, offset, mask; 1671 u16 data, offset, mask;
1704 1672
1705 /* 1673 /* Polarity is determined based on the speed of
1706 * Polarity is determined based on the speed of
1707 * our connection. 1674 * our connection.
1708 */ 1675 */
1709 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1676 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
@@ -1715,8 +1682,7 @@ s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1715 offset = IGP01E1000_PHY_PCS_INIT_REG; 1682 offset = IGP01E1000_PHY_PCS_INIT_REG;
1716 mask = IGP01E1000_PHY_POLARITY_MASK; 1683 mask = IGP01E1000_PHY_POLARITY_MASK;
1717 } else { 1684 } else {
1718 /* 1685 /* This really only applies to 10Mbps since
1719 * This really only applies to 10Mbps since
1720 * there is no polarity for 100Mbps (always 0). 1686 * there is no polarity for 100Mbps (always 0).
1721 */ 1687 */
1722 offset = IGP01E1000_PHY_PORT_STATUS; 1688 offset = IGP01E1000_PHY_PORT_STATUS;
@@ -1745,8 +1711,7 @@ s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1745 s32 ret_val; 1711 s32 ret_val;
1746 u16 phy_data, offset, mask; 1712 u16 phy_data, offset, mask;
1747 1713
1748 /* 1714 /* Polarity is determined based on the reversal feature being enabled.
1749 * Polarity is determined based on the reversal feature being enabled.
1750 */ 1715 */
1751 if (phy->polarity_correction) { 1716 if (phy->polarity_correction) {
1752 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 1717 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
@@ -1791,8 +1756,7 @@ static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1791 msleep(100); 1756 msleep(100);
1792 } 1757 }
1793 1758
1794 /* 1759 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1795 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1796 * has completed. 1760 * has completed.
1797 */ 1761 */
1798 return ret_val; 1762 return ret_val;
@@ -1814,15 +1778,13 @@ s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1814 u16 i, phy_status; 1778 u16 i, phy_status;
1815 1779
1816 for (i = 0; i < iterations; i++) { 1780 for (i = 0; i < iterations; i++) {
1817 /* 1781 /* Some PHYs require the PHY_STATUS register to be read
1818 * Some PHYs require the PHY_STATUS register to be read
1819 * twice due to the link bit being sticky. No harm doing 1782 * twice due to the link bit being sticky. No harm doing
1820 * it across the board. 1783 * it across the board.
1821 */ 1784 */
1822 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); 1785 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1823 if (ret_val) 1786 if (ret_val)
1824 /* 1787 /* If the first read fails, another entity may have
1825 * If the first read fails, another entity may have
1826 * ownership of the resources, wait and try again to 1788 * ownership of the resources, wait and try again to
1827 * see if they have relinquished the resources yet. 1789 * see if they have relinquished the resources yet.
1828 */ 1790 */
@@ -1913,8 +1875,7 @@ s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1913 if (ret_val) 1875 if (ret_val)
1914 return ret_val; 1876 return ret_val;
1915 1877
1916 /* 1878 /* Getting bits 15:9, which represent the combination of
1917 * Getting bits 15:9, which represent the combination of
1918 * coarse and fine gain values. The result is a number 1879 * coarse and fine gain values. The result is a number
1919 * that can be put into the lookup table to obtain the 1880 * that can be put into the lookup table to obtain the
1920 * approximate cable length. 1881 * approximate cable length.
@@ -2285,15 +2246,13 @@ s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2285 e1e_wphy(hw, 0x1796, 0x0008); 2246 e1e_wphy(hw, 0x1796, 0x0008);
2286 /* Change cg_icount + enable integbp for channels BCD */ 2247 /* Change cg_icount + enable integbp for channels BCD */
2287 e1e_wphy(hw, 0x1798, 0xD008); 2248 e1e_wphy(hw, 0x1798, 0xD008);
2288 /* 2249 /* Change cg_icount + enable integbp + change prop_factor_master
2289 * Change cg_icount + enable integbp + change prop_factor_master
2290 * to 8 for channel A 2250 * to 8 for channel A
2291 */ 2251 */
2292 e1e_wphy(hw, 0x1898, 0xD918); 2252 e1e_wphy(hw, 0x1898, 0xD918);
2293 /* Disable AHT in Slave mode on channel A */ 2253 /* Disable AHT in Slave mode on channel A */
2294 e1e_wphy(hw, 0x187A, 0x0800); 2254 e1e_wphy(hw, 0x187A, 0x0800);
2295 /* 2255 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2296 * Enable LPLU and disable AN to 1000 in non-D0a states,
2297 * Enable SPD+B2B 2256 * Enable SPD+B2B
2298 */ 2257 */
2299 e1e_wphy(hw, 0x0019, 0x008D); 2258 e1e_wphy(hw, 0x0019, 0x008D);
@@ -2417,8 +2376,7 @@ s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2417 e1000e_get_phy_id(hw); 2376 e1000e_get_phy_id(hw);
2418 phy_type = e1000e_get_phy_type_from_id(hw->phy.id); 2377 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2419 2378
2420 /* 2379 /* If phy_type is valid, break - we found our
2421 * If phy_type is valid, break - we found our
2422 * PHY address 2380 * PHY address
2423 */ 2381 */
2424 if (phy_type != e1000_phy_unknown) 2382 if (phy_type != e1000_phy_unknown)
@@ -2478,8 +2436,7 @@ s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2478 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2436 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2479 u32 page_shift, page_select; 2437 u32 page_shift, page_select;
2480 2438
2481 /* 2439 /* Page select is register 31 for phy address 1 and 22 for
2482 * Page select is register 31 for phy address 1 and 22 for
2483 * phy address 2 and 3. Page select is shifted only for 2440 * phy address 2 and 3. Page select is shifted only for
2484 * phy address 1. 2441 * phy address 1.
2485 */ 2442 */
@@ -2537,8 +2494,7 @@ s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2537 if (offset > MAX_PHY_MULTI_PAGE_REG) { 2494 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2538 u32 page_shift, page_select; 2495 u32 page_shift, page_select;
2539 2496
2540 /* 2497 /* Page select is register 31 for phy address 1 and 22 for
2541 * Page select is register 31 for phy address 1 and 22 for
2542 * phy address 2 and 3. Page select is shifted only for 2498 * phy address 2 and 3. Page select is shifted only for
2543 * phy address 1. 2499 * phy address 1.
2544 */ 2500 */
@@ -2683,8 +2639,7 @@ s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2683 return ret_val; 2639 return ret_val;
2684 } 2640 }
2685 2641
2686 /* 2642 /* Enable both PHY wakeup mode and Wakeup register page writes.
2687 * Enable both PHY wakeup mode and Wakeup register page writes.
2688 * Prevent a power state change by disabling ME and Host PHY wakeup. 2643 * Prevent a power state change by disabling ME and Host PHY wakeup.
2689 */ 2644 */
2690 temp = *phy_reg; 2645 temp = *phy_reg;
@@ -2698,8 +2653,7 @@ s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2698 return ret_val; 2653 return ret_val;
2699 } 2654 }
2700 2655
2701 /* 2656 /* Select Host Wakeup Registers page - caller now able to write
2702 * Select Host Wakeup Registers page - caller now able to write
2703 * registers on the Wakeup registers page 2657 * registers on the Wakeup registers page
2704 */ 2658 */
2705 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 2659 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
@@ -3038,8 +2992,7 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3038 if (page == HV_INTC_FC_PAGE_START) 2992 if (page == HV_INTC_FC_PAGE_START)
3039 page = 0; 2993 page = 0;
3040 2994
3041 /* 2995 /* Workaround MDIO accesses being disabled after entering IEEE
3042 * Workaround MDIO accesses being disabled after entering IEEE
3043 * Power Down (when bit 11 of the PHY Control register is set) 2996 * Power Down (when bit 11 of the PHY Control register is set)
3044 */ 2997 */
3045 if ((hw->phy.type == e1000_phy_82578) && 2998 if ((hw->phy.type == e1000_phy_82578) &&
diff --git a/drivers/net/ethernet/intel/igb/e1000_82575.c b/drivers/net/ethernet/intel/igb/e1000_82575.c
index 8c12dbd0d6ce..fdaaf2709d0a 100644
--- a/drivers/net/ethernet/intel/igb/e1000_82575.c
+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c
@@ -1028,6 +1028,15 @@ static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1028 * continue to check for link. 1028 * continue to check for link.
1029 */ 1029 */
1030 hw->mac.get_link_status = !hw->mac.serdes_has_link; 1030 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1031
1032 /* Configure Flow Control now that Auto-Neg has completed.
1033 * First, we need to restore the desired flow control
1034 * settings because we may have had to re-autoneg with a
1035 * different link partner.
1036 */
1037 ret_val = igb_config_fc_after_link_up(hw);
1038 if (ret_val)
1039 hw_dbg("Error configuring flow control\n");
1031 } else { 1040 } else {
1032 ret_val = igb_check_for_copper_link(hw); 1041 ret_val = igb_check_for_copper_link(hw);
1033 } 1042 }
@@ -1345,7 +1354,7 @@ out:
1345 **/ 1354 **/
1346static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw) 1355static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1347{ 1356{
1348 u32 ctrl_ext, ctrl_reg, reg; 1357 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1349 bool pcs_autoneg; 1358 bool pcs_autoneg;
1350 s32 ret_val = E1000_SUCCESS; 1359 s32 ret_val = E1000_SUCCESS;
1351 u16 data; 1360 u16 data;
@@ -1433,27 +1442,45 @@ static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1433 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1442 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1434 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1443 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1435 1444
1436 /*
1437 * We force flow control to prevent the CTRL register values from being
1438 * overwritten by the autonegotiated flow control values
1439 */
1440 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1441
1442 if (pcs_autoneg) { 1445 if (pcs_autoneg) {
1443 /* Set PCS register for autoneg */ 1446 /* Set PCS register for autoneg */
1444 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1447 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1445 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1448 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1449
1450 /* Disable force flow control for autoneg */
1451 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1452
1453 /* Configure flow control advertisement for autoneg */
1454 anadv_reg = rd32(E1000_PCS_ANADV);
1455 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1456 switch (hw->fc.requested_mode) {
1457 case e1000_fc_full:
1458 case e1000_fc_rx_pause:
1459 anadv_reg |= E1000_TXCW_ASM_DIR;
1460 anadv_reg |= E1000_TXCW_PAUSE;
1461 break;
1462 case e1000_fc_tx_pause:
1463 anadv_reg |= E1000_TXCW_ASM_DIR;
1464 break;
1465 default:
1466 break;
1467 }
1468 wr32(E1000_PCS_ANADV, anadv_reg);
1469
1446 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); 1470 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1447 } else { 1471 } else {
1448 /* Set PCS register for forced link */ 1472 /* Set PCS register for forced link */
1449 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1473 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1450 1474
1475 /* Force flow control for forced link */
1476 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1477
1451 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); 1478 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1452 } 1479 }
1453 1480
1454 wr32(E1000_PCS_LCTL, reg); 1481 wr32(E1000_PCS_LCTL, reg);
1455 1482
1456 if (!igb_sgmii_active_82575(hw)) 1483 if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
1457 igb_force_mac_fc(hw); 1484 igb_force_mac_fc(hw);
1458 1485
1459 return ret_val; 1486 return ret_val;
@@ -1927,6 +1954,12 @@ static s32 igb_reset_hw_82580(struct e1000_hw *hw)
1927 1954
1928 hw->dev_spec._82575.global_device_reset = false; 1955 hw->dev_spec._82575.global_device_reset = false;
1929 1956
1957 /* due to hw errata, global device reset doesn't always
1958 * work on 82580
1959 */
1960 if (hw->mac.type == e1000_82580)
1961 global_device_reset = false;
1962
1930 /* Get current control state. */ 1963 /* Get current control state. */
1931 ctrl = rd32(E1000_CTRL); 1964 ctrl = rd32(E1000_CTRL);
1932 1965
diff --git a/drivers/net/ethernet/intel/igb/e1000_defines.h b/drivers/net/ethernet/intel/igb/e1000_defines.h
index 198d14848820..45dce06eff26 100644
--- a/drivers/net/ethernet/intel/igb/e1000_defines.h
+++ b/drivers/net/ethernet/intel/igb/e1000_defines.h
@@ -431,6 +431,10 @@
431#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 431#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
432#define FLOW_CONTROL_TYPE 0x8808 432#define FLOW_CONTROL_TYPE 0x8808
433 433
434/* Transmit Config Word */
435#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
436#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
437
434/* 802.1q VLAN Packet Size */ 438/* 802.1q VLAN Packet Size */
435#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ 439#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
436#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 440#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
@@ -539,6 +543,9 @@
539/* mPHY Near End Digital Loopback Override Bit */ 543/* mPHY Near End Digital Loopback Override Bit */
540#define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10 544#define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10
541 545
546#define E1000_PCS_LCTL_FORCE_FCTRL 0x80
547#define E1000_PCS_LSTS_AN_COMPLETE 0x10000
548
542/* PHY Control Register */ 549/* PHY Control Register */
543#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 550#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
544#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 551#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
diff --git a/drivers/net/ethernet/intel/igb/e1000_i210.c b/drivers/net/ethernet/intel/igb/e1000_i210.c
index 41474298d365..fbcdbebb0b5f 100644
--- a/drivers/net/ethernet/intel/igb/e1000_i210.c
+++ b/drivers/net/ethernet/intel/igb/e1000_i210.c
@@ -35,11 +35,42 @@
35#include "e1000_hw.h" 35#include "e1000_hw.h"
36#include "e1000_i210.h" 36#include "e1000_i210.h"
37 37
38static s32 igb_get_hw_semaphore_i210(struct e1000_hw *hw); 38/**
39static void igb_put_hw_semaphore_i210(struct e1000_hw *hw); 39 * igb_get_hw_semaphore_i210 - Acquire hardware semaphore
40static s32 igb_write_nvm_srwr(struct e1000_hw *hw, u16 offset, u16 words, 40 * @hw: pointer to the HW structure
41 u16 *data); 41 *
42static s32 igb_pool_flash_update_done_i210(struct e1000_hw *hw); 42 * Acquire the HW semaphore to access the PHY or NVM
43 */
44static s32 igb_get_hw_semaphore_i210(struct e1000_hw *hw)
45{
46 u32 swsm;
47 s32 ret_val = E1000_SUCCESS;
48 s32 timeout = hw->nvm.word_size + 1;
49 s32 i = 0;
50
51 /* Get the FW semaphore. */
52 for (i = 0; i < timeout; i++) {
53 swsm = rd32(E1000_SWSM);
54 wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
55
56 /* Semaphore acquired if bit latched */
57 if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI)
58 break;
59
60 udelay(50);
61 }
62
63 if (i == timeout) {
64 /* Release semaphores */
65 igb_put_hw_semaphore(hw);
66 hw_dbg("Driver can't access the NVM\n");
67 ret_val = -E1000_ERR_NVM;
68 goto out;
69 }
70
71out:
72 return ret_val;
73}
43 74
44/** 75/**
45 * igb_acquire_nvm_i210 - Request for access to EEPROM 76 * igb_acquire_nvm_i210 - Request for access to EEPROM
@@ -68,6 +99,23 @@ void igb_release_nvm_i210(struct e1000_hw *hw)
68} 99}
69 100
70/** 101/**
102 * igb_put_hw_semaphore_i210 - Release hardware semaphore
103 * @hw: pointer to the HW structure
104 *
105 * Release hardware semaphore used to access the PHY or NVM
106 */
107static void igb_put_hw_semaphore_i210(struct e1000_hw *hw)
108{
109 u32 swsm;
110
111 swsm = rd32(E1000_SWSM);
112
113 swsm &= ~E1000_SWSM_SWESMBI;
114
115 wr32(E1000_SWSM, swsm);
116}
117
118/**
71 * igb_acquire_swfw_sync_i210 - Acquire SW/FW semaphore 119 * igb_acquire_swfw_sync_i210 - Acquire SW/FW semaphore
72 * @hw: pointer to the HW structure 120 * @hw: pointer to the HW structure
73 * @mask: specifies which semaphore to acquire 121 * @mask: specifies which semaphore to acquire
@@ -138,60 +186,6 @@ void igb_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask)
138} 186}
139 187
140/** 188/**
141 * igb_get_hw_semaphore_i210 - Acquire hardware semaphore
142 * @hw: pointer to the HW structure
143 *
144 * Acquire the HW semaphore to access the PHY or NVM
145 **/
146static s32 igb_get_hw_semaphore_i210(struct e1000_hw *hw)
147{
148 u32 swsm;
149 s32 ret_val = E1000_SUCCESS;
150 s32 timeout = hw->nvm.word_size + 1;
151 s32 i = 0;
152
153 /* Get the FW semaphore. */
154 for (i = 0; i < timeout; i++) {
155 swsm = rd32(E1000_SWSM);
156 wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
157
158 /* Semaphore acquired if bit latched */
159 if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI)
160 break;
161
162 udelay(50);
163 }
164
165 if (i == timeout) {
166 /* Release semaphores */
167 igb_put_hw_semaphore(hw);
168 hw_dbg("Driver can't access the NVM\n");
169 ret_val = -E1000_ERR_NVM;
170 goto out;
171 }
172
173out:
174 return ret_val;
175}
176
177/**
178 * igb_put_hw_semaphore_i210 - Release hardware semaphore
179 * @hw: pointer to the HW structure
180 *
181 * Release hardware semaphore used to access the PHY or NVM
182 **/
183static void igb_put_hw_semaphore_i210(struct e1000_hw *hw)
184{
185 u32 swsm;
186
187 swsm = rd32(E1000_SWSM);
188
189 swsm &= ~E1000_SWSM_SWESMBI;
190
191 wr32(E1000_SWSM, swsm);
192}
193
194/**
195 * igb_read_nvm_srrd_i210 - Reads Shadow Ram using EERD register 189 * igb_read_nvm_srrd_i210 - Reads Shadow Ram using EERD register
196 * @hw: pointer to the HW structure 190 * @hw: pointer to the HW structure
197 * @offset: offset of word in the Shadow Ram to read 191 * @offset: offset of word in the Shadow Ram to read
@@ -229,49 +223,6 @@ s32 igb_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset, u16 words,
229} 223}
230 224
231/** 225/**
232 * igb_write_nvm_srwr_i210 - Write to Shadow RAM using EEWR
233 * @hw: pointer to the HW structure
234 * @offset: offset within the Shadow RAM to be written to
235 * @words: number of words to write
236 * @data: 16 bit word(s) to be written to the Shadow RAM
237 *
238 * Writes data to Shadow RAM at offset using EEWR register.
239 *
240 * If e1000_update_nvm_checksum is not called after this function , the
241 * data will not be committed to FLASH and also Shadow RAM will most likely
242 * contain an invalid checksum.
243 *
244 * If error code is returned, data and Shadow RAM may be inconsistent - buffer
245 * partially written.
246 **/
247s32 igb_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words,
248 u16 *data)
249{
250 s32 status = E1000_SUCCESS;
251 u16 i, count;
252
253 /* We cannot hold synchronization semaphores for too long,
254 * because of forceful takeover procedure. However it is more efficient
255 * to write in bursts than synchronizing access for each word. */
256 for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {
257 count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?
258 E1000_EERD_EEWR_MAX_COUNT : (words - i);
259 if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
260 status = igb_write_nvm_srwr(hw, offset, count,
261 data + i);
262 hw->nvm.ops.release(hw);
263 } else {
264 status = E1000_ERR_SWFW_SYNC;
265 }
266
267 if (status != E1000_SUCCESS)
268 break;
269 }
270
271 return status;
272}
273
274/**
275 * igb_write_nvm_srwr - Write to Shadow Ram using EEWR 226 * igb_write_nvm_srwr - Write to Shadow Ram using EEWR
276 * @hw: pointer to the HW structure 227 * @hw: pointer to the HW structure
277 * @offset: offset within the Shadow Ram to be written to 228 * @offset: offset within the Shadow Ram to be written to
@@ -329,6 +280,50 @@ out:
329} 280}
330 281
331/** 282/**
283 * igb_write_nvm_srwr_i210 - Write to Shadow RAM using EEWR
284 * @hw: pointer to the HW structure
285 * @offset: offset within the Shadow RAM to be written to
286 * @words: number of words to write
287 * @data: 16 bit word(s) to be written to the Shadow RAM
288 *
289 * Writes data to Shadow RAM at offset using EEWR register.
290 *
291 * If e1000_update_nvm_checksum is not called after this function , the
292 * data will not be committed to FLASH and also Shadow RAM will most likely
293 * contain an invalid checksum.
294 *
295 * If error code is returned, data and Shadow RAM may be inconsistent - buffer
296 * partially written.
297 */
298s32 igb_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset, u16 words,
299 u16 *data)
300{
301 s32 status = E1000_SUCCESS;
302 u16 i, count;
303
304 /* We cannot hold synchronization semaphores for too long,
305 * because of forceful takeover procedure. However it is more efficient
306 * to write in bursts than synchronizing access for each word.
307 */
308 for (i = 0; i < words; i += E1000_EERD_EEWR_MAX_COUNT) {
309 count = (words - i) / E1000_EERD_EEWR_MAX_COUNT > 0 ?
310 E1000_EERD_EEWR_MAX_COUNT : (words - i);
311 if (hw->nvm.ops.acquire(hw) == E1000_SUCCESS) {
312 status = igb_write_nvm_srwr(hw, offset, count,
313 data + i);
314 hw->nvm.ops.release(hw);
315 } else {
316 status = E1000_ERR_SWFW_SYNC;
317 }
318
319 if (status != E1000_SUCCESS)
320 break;
321 }
322
323 return status;
324}
325
326/**
332 * igb_read_nvm_i211 - Read NVM wrapper function for I211 327 * igb_read_nvm_i211 - Read NVM wrapper function for I211
333 * @hw: pointer to the HW structure 328 * @hw: pointer to the HW structure
334 * @address: the word address (aka eeprom offset) to read 329 * @address: the word address (aka eeprom offset) to read
@@ -350,16 +345,40 @@ s32 igb_read_nvm_i211(struct e1000_hw *hw, u16 offset, u16 words,
350 if (ret_val != E1000_SUCCESS) 345 if (ret_val != E1000_SUCCESS)
351 hw_dbg("MAC Addr not found in iNVM\n"); 346 hw_dbg("MAC Addr not found in iNVM\n");
352 break; 347 break;
353 case NVM_ID_LED_SETTINGS:
354 case NVM_INIT_CTRL_2: 348 case NVM_INIT_CTRL_2:
349 ret_val = igb_read_invm_i211(hw, (u8)offset, data);
350 if (ret_val != E1000_SUCCESS) {
351 *data = NVM_INIT_CTRL_2_DEFAULT_I211;
352 ret_val = E1000_SUCCESS;
353 }
354 break;
355 case NVM_INIT_CTRL_4: 355 case NVM_INIT_CTRL_4:
356 ret_val = igb_read_invm_i211(hw, (u8)offset, data);
357 if (ret_val != E1000_SUCCESS) {
358 *data = NVM_INIT_CTRL_4_DEFAULT_I211;
359 ret_val = E1000_SUCCESS;
360 }
361 break;
356 case NVM_LED_1_CFG: 362 case NVM_LED_1_CFG:
363 ret_val = igb_read_invm_i211(hw, (u8)offset, data);
364 if (ret_val != E1000_SUCCESS) {
365 *data = NVM_LED_1_CFG_DEFAULT_I211;
366 ret_val = E1000_SUCCESS;
367 }
368 break;
357 case NVM_LED_0_2_CFG: 369 case NVM_LED_0_2_CFG:
358 igb_read_invm_i211(hw, offset, data); 370 igb_read_invm_i211(hw, offset, data);
371 if (ret_val != E1000_SUCCESS) {
372 *data = NVM_LED_0_2_CFG_DEFAULT_I211;
373 ret_val = E1000_SUCCESS;
374 }
359 break; 375 break;
360 case NVM_COMPAT: 376 case NVM_ID_LED_SETTINGS:
361 *data = ID_LED_DEFAULT_I210; 377 ret_val = igb_read_invm_i211(hw, (u8)offset, data);
362 break; 378 if (ret_val != E1000_SUCCESS) {
379 *data = ID_LED_RESERVED_FFFF;
380 ret_val = E1000_SUCCESS;
381 }
363 case NVM_SUB_DEV_ID: 382 case NVM_SUB_DEV_ID:
364 *data = hw->subsystem_device_id; 383 *data = hw->subsystem_device_id;
365 break; 384 break;
@@ -613,6 +632,28 @@ out:
613} 632}
614 633
615/** 634/**
635 * igb_pool_flash_update_done_i210 - Pool FLUDONE status.
636 * @hw: pointer to the HW structure
637 *
638 */
639static s32 igb_pool_flash_update_done_i210(struct e1000_hw *hw)
640{
641 s32 ret_val = -E1000_ERR_NVM;
642 u32 i, reg;
643
644 for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
645 reg = rd32(E1000_EECD);
646 if (reg & E1000_EECD_FLUDONE_I210) {
647 ret_val = E1000_SUCCESS;
648 break;
649 }
650 udelay(5);
651 }
652
653 return ret_val;
654}
655
656/**
616 * igb_update_flash_i210 - Commit EEPROM to the flash 657 * igb_update_flash_i210 - Commit EEPROM to the flash
617 * @hw: pointer to the HW structure 658 * @hw: pointer to the HW structure
618 * 659 *
@@ -642,28 +683,6 @@ out:
642} 683}
643 684
644/** 685/**
645 * igb_pool_flash_update_done_i210 - Pool FLUDONE status.
646 * @hw: pointer to the HW structure
647 *
648 **/
649s32 igb_pool_flash_update_done_i210(struct e1000_hw *hw)
650{
651 s32 ret_val = -E1000_ERR_NVM;
652 u32 i, reg;
653
654 for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
655 reg = rd32(E1000_EECD);
656 if (reg & E1000_EECD_FLUDONE_I210) {
657 ret_val = E1000_SUCCESS;
658 break;
659 }
660 udelay(5);
661 }
662
663 return ret_val;
664}
665
666/**
667 * igb_valid_led_default_i210 - Verify a valid default LED config 686 * igb_valid_led_default_i210 - Verify a valid default LED config
668 * @hw: pointer to the HW structure 687 * @hw: pointer to the HW structure
669 * @data: pointer to the NVM (EEPROM) 688 * @data: pointer to the NVM (EEPROM)
diff --git a/drivers/net/ethernet/intel/igb/e1000_i210.h b/drivers/net/ethernet/intel/igb/e1000_i210.h
index 974d23584d70..1c89358a99ab 100644
--- a/drivers/net/ethernet/intel/igb/e1000_i210.h
+++ b/drivers/net/ethernet/intel/igb/e1000_i210.h
@@ -84,4 +84,10 @@ enum E1000_INVM_STRUCTURE_TYPE {
84 (ID_LED_DEF1_DEF2 << 4) | \ 84 (ID_LED_DEF1_DEF2 << 4) | \
85 (ID_LED_DEF1_DEF2)) 85 (ID_LED_DEF1_DEF2))
86 86
87/* NVM offset defaults for i211 device */
88#define NVM_INIT_CTRL_2_DEFAULT_I211 0X7243
89#define NVM_INIT_CTRL_4_DEFAULT_I211 0x00C1
90#define NVM_LED_1_CFG_DEFAULT_I211 0x0184
91#define NVM_LED_0_2_CFG_DEFAULT_I211 0x200C
92
87#endif 93#endif
diff --git a/drivers/net/ethernet/intel/igb/e1000_mac.c b/drivers/net/ethernet/intel/igb/e1000_mac.c
index 7acddfe9e6d5..101e6e4da97f 100644
--- a/drivers/net/ethernet/intel/igb/e1000_mac.c
+++ b/drivers/net/ethernet/intel/igb/e1000_mac.c
@@ -839,6 +839,7 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
839{ 839{
840 struct e1000_mac_info *mac = &hw->mac; 840 struct e1000_mac_info *mac = &hw->mac;
841 s32 ret_val = 0; 841 s32 ret_val = 0;
842 u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
842 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 843 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
843 u16 speed, duplex; 844 u16 speed, duplex;
844 845
@@ -1040,6 +1041,129 @@ s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
1040 goto out; 1041 goto out;
1041 } 1042 }
1042 } 1043 }
1044 /* Check for the case where we have SerDes media and auto-neg is
1045 * enabled. In this case, we need to check and see if Auto-Neg
1046 * has completed, and if so, how the PHY and link partner has
1047 * flow control configured.
1048 */
1049 if ((hw->phy.media_type == e1000_media_type_internal_serdes)
1050 && mac->autoneg) {
1051 /* Read the PCS_LSTS and check to see if AutoNeg
1052 * has completed.
1053 */
1054 pcs_status_reg = rd32(E1000_PCS_LSTAT);
1055
1056 if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
1057 hw_dbg("PCS Auto Neg has not completed.\n");
1058 return ret_val;
1059 }
1060
1061 /* The AutoNeg process has completed, so we now need to
1062 * read both the Auto Negotiation Advertisement
1063 * Register (PCS_ANADV) and the Auto_Negotiation Base
1064 * Page Ability Register (PCS_LPAB) to determine how
1065 * flow control was negotiated.
1066 */
1067 pcs_adv_reg = rd32(E1000_PCS_ANADV);
1068 pcs_lp_ability_reg = rd32(E1000_PCS_LPAB);
1069
1070 /* Two bits in the Auto Negotiation Advertisement Register
1071 * (PCS_ANADV) and two bits in the Auto Negotiation Base
1072 * Page Ability Register (PCS_LPAB) determine flow control
1073 * for both the PHY and the link partner. The following
1074 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1075 * 1999, describes these PAUSE resolution bits and how flow
1076 * control is determined based upon these settings.
1077 * NOTE: DC = Don't Care
1078 *
1079 * LOCAL DEVICE | LINK PARTNER
1080 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1081 *-------|---------|-------|---------|--------------------
1082 * 0 | 0 | DC | DC | e1000_fc_none
1083 * 0 | 1 | 0 | DC | e1000_fc_none
1084 * 0 | 1 | 1 | 0 | e1000_fc_none
1085 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1086 * 1 | 0 | 0 | DC | e1000_fc_none
1087 * 1 | DC | 1 | DC | e1000_fc_full
1088 * 1 | 1 | 0 | 0 | e1000_fc_none
1089 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1090 *
1091 * Are both PAUSE bits set to 1? If so, this implies
1092 * Symmetric Flow Control is enabled at both ends. The
1093 * ASM_DIR bits are irrelevant per the spec.
1094 *
1095 * For Symmetric Flow Control:
1096 *
1097 * LOCAL DEVICE | LINK PARTNER
1098 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1099 *-------|---------|-------|---------|--------------------
1100 * 1 | DC | 1 | DC | e1000_fc_full
1101 *
1102 */
1103 if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1104 (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
1105 /* Now we need to check if the user selected Rx ONLY
1106 * of pause frames. In this case, we had to advertise
1107 * FULL flow control because we could not advertise Rx
1108 * ONLY. Hence, we must now check to see if we need to
1109 * turn OFF the TRANSMISSION of PAUSE frames.
1110 */
1111 if (hw->fc.requested_mode == e1000_fc_full) {
1112 hw->fc.current_mode = e1000_fc_full;
1113 hw_dbg("Flow Control = FULL.\n");
1114 } else {
1115 hw->fc.current_mode = e1000_fc_rx_pause;
1116 hw_dbg("Flow Control = Rx PAUSE frames only.\n");
1117 }
1118 }
1119 /* For receiving PAUSE frames ONLY.
1120 *
1121 * LOCAL DEVICE | LINK PARTNER
1122 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1123 *-------|---------|-------|---------|--------------------
1124 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1125 */
1126 else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
1127 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1128 (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1129 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1130 hw->fc.current_mode = e1000_fc_tx_pause;
1131 hw_dbg("Flow Control = Tx PAUSE frames only.\n");
1132 }
1133 /* For transmitting PAUSE frames ONLY.
1134 *
1135 * LOCAL DEVICE | LINK PARTNER
1136 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1137 *-------|---------|-------|---------|--------------------
1138 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1139 */
1140 else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1141 (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1142 !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1143 (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1144 hw->fc.current_mode = e1000_fc_rx_pause;
1145 hw_dbg("Flow Control = Rx PAUSE frames only.\n");
1146 } else {
1147 /* Per the IEEE spec, at this point flow control
1148 * should be disabled.
1149 */
1150 hw->fc.current_mode = e1000_fc_none;
1151 hw_dbg("Flow Control = NONE.\n");
1152 }
1153
1154 /* Now we call a subroutine to actually force the MAC
1155 * controller to use the correct flow control settings.
1156 */
1157 pcs_ctrl_reg = rd32(E1000_PCS_LCTL);
1158 pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1159 wr32(E1000_PCS_LCTL, pcs_ctrl_reg);
1160
1161 ret_val = igb_force_mac_fc(hw);
1162 if (ret_val) {
1163 hw_dbg("Error forcing flow control settings\n");
1164 return ret_val;
1165 }
1166 }
1043 1167
1044out: 1168out:
1045 return ret_val; 1169 return ret_val;
diff --git a/drivers/net/ethernet/intel/igb/e1000_nvm.c b/drivers/net/ethernet/intel/igb/e1000_nvm.c
index 7db3f80bcd57..fbb7604db364 100644
--- a/drivers/net/ethernet/intel/igb/e1000_nvm.c
+++ b/drivers/net/ethernet/intel/igb/e1000_nvm.c
@@ -438,7 +438,7 @@ out:
438s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 438s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
439{ 439{
440 struct e1000_nvm_info *nvm = &hw->nvm; 440 struct e1000_nvm_info *nvm = &hw->nvm;
441 s32 ret_val; 441 s32 ret_val = -E1000_ERR_NVM;
442 u16 widx = 0; 442 u16 widx = 0;
443 443
444 /* 444 /*
@@ -448,22 +448,21 @@ s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
448 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 448 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
449 (words == 0)) { 449 (words == 0)) {
450 hw_dbg("nvm parameter(s) out of bounds\n"); 450 hw_dbg("nvm parameter(s) out of bounds\n");
451 ret_val = -E1000_ERR_NVM; 451 return ret_val;
452 goto out;
453 } 452 }
454 453
455 ret_val = hw->nvm.ops.acquire(hw);
456 if (ret_val)
457 goto out;
458
459 msleep(10);
460
461 while (widx < words) { 454 while (widx < words) {
462 u8 write_opcode = NVM_WRITE_OPCODE_SPI; 455 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
463 456
464 ret_val = igb_ready_nvm_eeprom(hw); 457 ret_val = nvm->ops.acquire(hw);
465 if (ret_val) 458 if (ret_val)
466 goto release; 459 return ret_val;
460
461 ret_val = igb_ready_nvm_eeprom(hw);
462 if (ret_val) {
463 nvm->ops.release(hw);
464 return ret_val;
465 }
467 466
468 igb_standby_nvm(hw); 467 igb_standby_nvm(hw);
469 468
@@ -497,13 +496,10 @@ s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
497 break; 496 break;
498 } 497 }
499 } 498 }
499 usleep_range(1000, 2000);
500 nvm->ops.release(hw);
500 } 501 }
501 502
502 msleep(10);
503release:
504 hw->nvm.ops.release(hw);
505
506out:
507 return ret_val; 503 return ret_val;
508} 504}
509 505
diff --git a/drivers/net/ethernet/intel/igb/igb.h b/drivers/net/ethernet/intel/igb/igb.h
index c15a4811b476..17f1686ee411 100644
--- a/drivers/net/ethernet/intel/igb/igb.h
+++ b/drivers/net/ethernet/intel/igb/igb.h
@@ -42,6 +42,8 @@
42 42
43struct igb_adapter; 43struct igb_adapter;
44 44
45#define E1000_PCS_CFG_IGN_SD 1
46
45/* Interrupt defines */ 47/* Interrupt defines */
46#define IGB_START_ITR 648 /* ~6000 ints/sec */ 48#define IGB_START_ITR 648 /* ~6000 ints/sec */
47#define IGB_4K_ITR 980 49#define IGB_4K_ITR 980
diff --git a/drivers/net/ethernet/intel/igb/igb_ethtool.c b/drivers/net/ethernet/intel/igb/igb_ethtool.c
index e2288b5a9caa..bfe9208c4b18 100644
--- a/drivers/net/ethernet/intel/igb/igb_ethtool.c
+++ b/drivers/net/ethernet/intel/igb/igb_ethtool.c
@@ -1624,6 +1624,20 @@ static int igb_setup_loopback_test(struct igb_adapter *adapter)
1624 reg &= ~E1000_CONNSW_ENRGSRC; 1624 reg &= ~E1000_CONNSW_ENRGSRC;
1625 wr32(E1000_CONNSW, reg); 1625 wr32(E1000_CONNSW, reg);
1626 1626
1627 /* Unset sigdetect for SERDES loopback on
1628 * 82580 and i350 devices.
1629 */
1630 switch (hw->mac.type) {
1631 case e1000_82580:
1632 case e1000_i350:
1633 reg = rd32(E1000_PCS_CFG0);
1634 reg |= E1000_PCS_CFG_IGN_SD;
1635 wr32(E1000_PCS_CFG0, reg);
1636 break;
1637 default:
1638 break;
1639 }
1640
1627 /* Set PCS register for forced speed */ 1641 /* Set PCS register for forced speed */
1628 reg = rd32(E1000_PCS_LCTL); 1642 reg = rd32(E1000_PCS_LCTL);
1629 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/ 1643 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c
index efaf9a73cc79..50aa546b8c7a 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.c
@@ -47,23 +47,27 @@ static ssize_t ixgbe_dbg_reg_ops_read(struct file *filp, char __user *buffer,
47 size_t count, loff_t *ppos) 47 size_t count, loff_t *ppos)
48{ 48{
49 struct ixgbe_adapter *adapter = filp->private_data; 49 struct ixgbe_adapter *adapter = filp->private_data;
50 char buf[256]; 50 char *buf;
51 int bytes_not_copied;
52 int len; 51 int len;
53 52
54 /* don't allow partial reads */ 53 /* don't allow partial reads */
55 if (*ppos != 0) 54 if (*ppos != 0)
56 return 0; 55 return 0;
57 56
58 len = snprintf(buf, sizeof(buf), "%s: %s\n", 57 buf = kasprintf(GFP_KERNEL, "%s: %s\n",
59 adapter->netdev->name, ixgbe_dbg_reg_ops_buf); 58 adapter->netdev->name,
60 if (count < len) 59 ixgbe_dbg_reg_ops_buf);
60 if (!buf)
61 return -ENOMEM;
62
63 if (count < strlen(buf)) {
64 kfree(buf);
61 return -ENOSPC; 65 return -ENOSPC;
62 bytes_not_copied = copy_to_user(buffer, buf, len); 66 }
63 if (bytes_not_copied < 0) 67
64 return bytes_not_copied; 68 len = simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf));
65 69
66 *ppos = len; 70 kfree(buf);
67 return len; 71 return len;
68} 72}
69 73
@@ -79,7 +83,7 @@ static ssize_t ixgbe_dbg_reg_ops_write(struct file *filp,
79 size_t count, loff_t *ppos) 83 size_t count, loff_t *ppos)
80{ 84{
81 struct ixgbe_adapter *adapter = filp->private_data; 85 struct ixgbe_adapter *adapter = filp->private_data;
82 int bytes_not_copied; 86 int len;
83 87
84 /* don't allow partial writes */ 88 /* don't allow partial writes */
85 if (*ppos != 0) 89 if (*ppos != 0)
@@ -87,14 +91,15 @@ static ssize_t ixgbe_dbg_reg_ops_write(struct file *filp,
87 if (count >= sizeof(ixgbe_dbg_reg_ops_buf)) 91 if (count >= sizeof(ixgbe_dbg_reg_ops_buf))
88 return -ENOSPC; 92 return -ENOSPC;
89 93
90 bytes_not_copied = copy_from_user(ixgbe_dbg_reg_ops_buf, buffer, count); 94 len = simple_write_to_buffer(ixgbe_dbg_reg_ops_buf,
91 if (bytes_not_copied < 0) 95 sizeof(ixgbe_dbg_reg_ops_buf)-1,
92 return bytes_not_copied; 96 ppos,
93 else if (bytes_not_copied < count) 97 buffer,
94 count -= bytes_not_copied; 98 count);
95 else 99 if (len < 0)
96 return -ENOSPC; 100 return len;
97 ixgbe_dbg_reg_ops_buf[count] = '\0'; 101
102 ixgbe_dbg_reg_ops_buf[len] = '\0';
98 103
99 if (strncmp(ixgbe_dbg_reg_ops_buf, "write", 5) == 0) { 104 if (strncmp(ixgbe_dbg_reg_ops_buf, "write", 5) == 0) {
100 u32 reg, value; 105 u32 reg, value;
@@ -147,23 +152,27 @@ static ssize_t ixgbe_dbg_netdev_ops_read(struct file *filp,
147 size_t count, loff_t *ppos) 152 size_t count, loff_t *ppos)
148{ 153{
149 struct ixgbe_adapter *adapter = filp->private_data; 154 struct ixgbe_adapter *adapter = filp->private_data;
150 char buf[256]; 155 char *buf;
151 int bytes_not_copied;
152 int len; 156 int len;
153 157
154 /* don't allow partial reads */ 158 /* don't allow partial reads */
155 if (*ppos != 0) 159 if (*ppos != 0)
156 return 0; 160 return 0;
157 161
158 len = snprintf(buf, sizeof(buf), "%s: %s\n", 162 buf = kasprintf(GFP_KERNEL, "%s: %s\n",
159 adapter->netdev->name, ixgbe_dbg_netdev_ops_buf); 163 adapter->netdev->name,
160 if (count < len) 164 ixgbe_dbg_netdev_ops_buf);
165 if (!buf)
166 return -ENOMEM;
167
168 if (count < strlen(buf)) {
169 kfree(buf);
161 return -ENOSPC; 170 return -ENOSPC;
162 bytes_not_copied = copy_to_user(buffer, buf, len); 171 }
163 if (bytes_not_copied < 0) 172
164 return bytes_not_copied; 173 len = simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf));
165 174
166 *ppos = len; 175 kfree(buf);
167 return len; 176 return len;
168} 177}
169 178
@@ -179,7 +188,7 @@ static ssize_t ixgbe_dbg_netdev_ops_write(struct file *filp,
179 size_t count, loff_t *ppos) 188 size_t count, loff_t *ppos)
180{ 189{
181 struct ixgbe_adapter *adapter = filp->private_data; 190 struct ixgbe_adapter *adapter = filp->private_data;
182 int bytes_not_copied; 191 int len;
183 192
184 /* don't allow partial writes */ 193 /* don't allow partial writes */
185 if (*ppos != 0) 194 if (*ppos != 0)
@@ -187,15 +196,15 @@ static ssize_t ixgbe_dbg_netdev_ops_write(struct file *filp,
187 if (count >= sizeof(ixgbe_dbg_netdev_ops_buf)) 196 if (count >= sizeof(ixgbe_dbg_netdev_ops_buf))
188 return -ENOSPC; 197 return -ENOSPC;
189 198
190 bytes_not_copied = copy_from_user(ixgbe_dbg_netdev_ops_buf, 199 len = simple_write_to_buffer(ixgbe_dbg_netdev_ops_buf,
191 buffer, count); 200 sizeof(ixgbe_dbg_netdev_ops_buf)-1,
192 if (bytes_not_copied < 0) 201 ppos,
193 return bytes_not_copied; 202 buffer,
194 else if (bytes_not_copied < count) 203 count);
195 count -= bytes_not_copied; 204 if (len < 0)
196 else 205 return len;
197 return -ENOSPC; 206
198 ixgbe_dbg_netdev_ops_buf[count] = '\0'; 207 ixgbe_dbg_netdev_ops_buf[len] = '\0';
199 208
200 if (strncmp(ixgbe_dbg_netdev_ops_buf, "tx_timeout", 10) == 0) { 209 if (strncmp(ixgbe_dbg_netdev_ops_buf, "tx_timeout", 10) == 0) {
201 adapter->netdev->netdev_ops->ndo_tx_timeout(adapter->netdev); 210 adapter->netdev->netdev_ops->ndo_tx_timeout(adapter->netdev);
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
index 484bbedffe2a..79b834583188 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
@@ -1338,26 +1338,29 @@ static unsigned int ixgbe_get_headlen(unsigned char *data,
1338 if (hlen < sizeof(struct iphdr)) 1338 if (hlen < sizeof(struct iphdr))
1339 return hdr.network - data; 1339 return hdr.network - data;
1340 1340
1341 /* record next protocol */ 1341 /* record next protocol if header is present */
1342 nexthdr = hdr.ipv4->protocol; 1342 if (!hdr.ipv4->frag_off)
1343 hdr.network += hlen; 1343 nexthdr = hdr.ipv4->protocol;
1344 } else if (protocol == __constant_htons(ETH_P_IPV6)) { 1344 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1345 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr))) 1345 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1346 return max_len; 1346 return max_len;
1347 1347
1348 /* record next protocol */ 1348 /* record next protocol */
1349 nexthdr = hdr.ipv6->nexthdr; 1349 nexthdr = hdr.ipv6->nexthdr;
1350 hdr.network += sizeof(struct ipv6hdr); 1350 hlen = sizeof(struct ipv6hdr);
1351#ifdef IXGBE_FCOE 1351#ifdef IXGBE_FCOE
1352 } else if (protocol == __constant_htons(ETH_P_FCOE)) { 1352 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1353 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN)) 1353 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1354 return max_len; 1354 return max_len;
1355 hdr.network += FCOE_HEADER_LEN; 1355 hlen = FCOE_HEADER_LEN;
1356#endif 1356#endif
1357 } else { 1357 } else {
1358 return hdr.network - data; 1358 return hdr.network - data;
1359 } 1359 }
1360 1360
1361 /* relocate pointer to start of L4 header */
1362 hdr.network += hlen;
1363
1361 /* finally sort out TCP/UDP */ 1364 /* finally sort out TCP/UDP */
1362 if (nexthdr == IPPROTO_TCP) { 1365 if (nexthdr == IPPROTO_TCP) {
1363 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) 1366 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 03:51:31 -0500