diff options
Diffstat (limited to 'drivers/net/ethernet/intel/igb/e1000_82575.c')
-rw-r--r-- | drivers/net/ethernet/intel/igb/e1000_82575.c | 49 |
1 files changed, 41 insertions, 8 deletions
diff --git a/drivers/net/ethernet/intel/igb/e1000_82575.c b/drivers/net/ethernet/intel/igb/e1000_82575.c index 8c12dbd0d6ce..fdaaf2709d0a 100644 --- a/drivers/net/ethernet/intel/igb/e1000_82575.c +++ b/drivers/net/ethernet/intel/igb/e1000_82575.c | |||
@@ -1028,6 +1028,15 @@ static s32 igb_check_for_link_82575(struct e1000_hw *hw) | |||
1028 | * continue to check for link. | 1028 | * continue to check for link. |
1029 | */ | 1029 | */ |
1030 | hw->mac.get_link_status = !hw->mac.serdes_has_link; | 1030 | hw->mac.get_link_status = !hw->mac.serdes_has_link; |
1031 | |||
1032 | /* Configure Flow Control now that Auto-Neg has completed. | ||
1033 | * First, we need to restore the desired flow control | ||
1034 | * settings because we may have had to re-autoneg with a | ||
1035 | * different link partner. | ||
1036 | */ | ||
1037 | ret_val = igb_config_fc_after_link_up(hw); | ||
1038 | if (ret_val) | ||
1039 | hw_dbg("Error configuring flow control\n"); | ||
1031 | } else { | 1040 | } else { |
1032 | ret_val = igb_check_for_copper_link(hw); | 1041 | ret_val = igb_check_for_copper_link(hw); |
1033 | } | 1042 | } |
@@ -1345,7 +1354,7 @@ out: | |||
1345 | **/ | 1354 | **/ |
1346 | static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw) | 1355 | static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw) |
1347 | { | 1356 | { |
1348 | u32 ctrl_ext, ctrl_reg, reg; | 1357 | u32 ctrl_ext, ctrl_reg, reg, anadv_reg; |
1349 | bool pcs_autoneg; | 1358 | bool pcs_autoneg; |
1350 | s32 ret_val = E1000_SUCCESS; | 1359 | s32 ret_val = E1000_SUCCESS; |
1351 | u16 data; | 1360 | u16 data; |
@@ -1433,27 +1442,45 @@ static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw) | |||
1433 | reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | | 1442 | reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | |
1434 | E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); | 1443 | E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); |
1435 | 1444 | ||
1436 | /* | ||
1437 | * We force flow control to prevent the CTRL register values from being | ||
1438 | * overwritten by the autonegotiated flow control values | ||
1439 | */ | ||
1440 | reg |= E1000_PCS_LCTL_FORCE_FCTRL; | ||
1441 | |||
1442 | if (pcs_autoneg) { | 1445 | if (pcs_autoneg) { |
1443 | /* Set PCS register for autoneg */ | 1446 | /* Set PCS register for autoneg */ |
1444 | reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ | 1447 | reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ |
1445 | E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ | 1448 | E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ |
1449 | |||
1450 | /* Disable force flow control for autoneg */ | ||
1451 | reg &= ~E1000_PCS_LCTL_FORCE_FCTRL; | ||
1452 | |||
1453 | /* Configure flow control advertisement for autoneg */ | ||
1454 | anadv_reg = rd32(E1000_PCS_ANADV); | ||
1455 | anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE); | ||
1456 | switch (hw->fc.requested_mode) { | ||
1457 | case e1000_fc_full: | ||
1458 | case e1000_fc_rx_pause: | ||
1459 | anadv_reg |= E1000_TXCW_ASM_DIR; | ||
1460 | anadv_reg |= E1000_TXCW_PAUSE; | ||
1461 | break; | ||
1462 | case e1000_fc_tx_pause: | ||
1463 | anadv_reg |= E1000_TXCW_ASM_DIR; | ||
1464 | break; | ||
1465 | default: | ||
1466 | break; | ||
1467 | } | ||
1468 | wr32(E1000_PCS_ANADV, anadv_reg); | ||
1469 | |||
1446 | hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); | 1470 | hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); |
1447 | } else { | 1471 | } else { |
1448 | /* Set PCS register for forced link */ | 1472 | /* Set PCS register for forced link */ |
1449 | reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ | 1473 | reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ |
1450 | 1474 | ||
1475 | /* Force flow control for forced link */ | ||
1476 | reg |= E1000_PCS_LCTL_FORCE_FCTRL; | ||
1477 | |||
1451 | hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); | 1478 | hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); |
1452 | } | 1479 | } |
1453 | 1480 | ||
1454 | wr32(E1000_PCS_LCTL, reg); | 1481 | wr32(E1000_PCS_LCTL, reg); |
1455 | 1482 | ||
1456 | if (!igb_sgmii_active_82575(hw)) | 1483 | if (!pcs_autoneg && !igb_sgmii_active_82575(hw)) |
1457 | igb_force_mac_fc(hw); | 1484 | igb_force_mac_fc(hw); |
1458 | 1485 | ||
1459 | return ret_val; | 1486 | return ret_val; |
@@ -1927,6 +1954,12 @@ static s32 igb_reset_hw_82580(struct e1000_hw *hw) | |||
1927 | 1954 | ||
1928 | hw->dev_spec._82575.global_device_reset = false; | 1955 | hw->dev_spec._82575.global_device_reset = false; |
1929 | 1956 | ||
1957 | /* due to hw errata, global device reset doesn't always | ||
1958 | * work on 82580 | ||
1959 | */ | ||
1960 | if (hw->mac.type == e1000_82580) | ||
1961 | global_device_reset = false; | ||
1962 | |||
1930 | /* Get current control state. */ | 1963 | /* Get current control state. */ |
1931 | ctrl = rd32(E1000_CTRL); | 1964 | ctrl = rd32(E1000_CTRL); |
1932 | 1965 | ||