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authorSeungwon Jeon <tgih.jun@samsung.com>2013-08-30 11:13:31 -0400
committerChris Ball <cjb@laptop.org>2013-09-25 21:34:12 -0400
commit1f44a2a55787faa08a50266fa5dc99f0dcd36b7c (patch)
tree8f09f1a0e9d5967a20fc409bf3d244a8d3c0d8c1 /drivers/mmc
parent10b498419f41ffaca7510286c0db8ea34300576d (diff)
mmc: dw_mmc: set the supported max/min frequency
Both f_max and f_min will be informed for core layer to request valid clock rate. But current setting from 'host->bus_hz' may not represent the max/min frequency properly. Even if host can actually support high speed than bus_hz, core layer will not request clock rate over bus_hz. Basically, f_max/f_min can be set with the values according to spec. And then host will make its best effort to meet the rate. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Tested-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/dw_mmc.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index cca9aa6b11c5..50da6e330a15 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -50,6 +50,9 @@
50#define DW_MCI_RECV_STATUS 2 50#define DW_MCI_RECV_STATUS 2
51#define DW_MCI_DMA_THRESHOLD 16 51#define DW_MCI_DMA_THRESHOLD 16
52 52
53#define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
54#define DW_MCI_FREQ_MIN 400000 /* unit: HZ */
55
53#ifdef CONFIG_MMC_DW_IDMAC 56#ifdef CONFIG_MMC_DW_IDMAC
54#define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ 57#define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
55 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ 58 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
@@ -1936,6 +1939,7 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
1936 struct dw_mci_slot *slot; 1939 struct dw_mci_slot *slot;
1937 const struct dw_mci_drv_data *drv_data = host->drv_data; 1940 const struct dw_mci_drv_data *drv_data = host->drv_data;
1938 int ctrl_id, ret; 1941 int ctrl_id, ret;
1942 u32 freq[2];
1939 u8 bus_width; 1943 u8 bus_width;
1940 1944
1941 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); 1945 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
@@ -1951,8 +1955,14 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
1951 slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id); 1955 slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
1952 1956
1953 mmc->ops = &dw_mci_ops; 1957 mmc->ops = &dw_mci_ops;
1954 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510); 1958 if (of_property_read_u32_array(host->dev->of_node,
1955 mmc->f_max = host->bus_hz; 1959 "clock-freq-min-max", freq, 2)) {
1960 mmc->f_min = DW_MCI_FREQ_MIN;
1961 mmc->f_max = DW_MCI_FREQ_MAX;
1962 } else {
1963 mmc->f_min = freq[0];
1964 mmc->f_max = freq[1];
1965 }
1956 1966
1957 if (host->pdata->get_ocr) 1967 if (host->pdata->get_ocr)
1958 mmc->ocr_avail = host->pdata->get_ocr(id); 1968 mmc->ocr_avail = host->pdata->get_ocr(id);