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authorAlexander Stein <alexander.stein@systec-electronic.com>2013-01-28 04:44:12 -0500
committerWolfram Sang <wolfram@the-dreams.de>2013-02-11 09:53:49 -0500
commitb08369a174a183e88baa98ab5e3566a617a3a7f8 (patch)
tree63a3d942b41b6dca13e6d770fddb2937f34ebbca /drivers/i2c
parent4182b434bf760355a1516b1d3d9f73aa419eeeec (diff)
i2c: isch: Add module parameter for backbone clock rate if divider is unset
It was observed the Host Clock Divider was not written by the driver. It was still set to (default) 0, if not already set by BIOS, which caused garbage on SMBus. This driver adds a parameters which is used to calculate the divider appropriately for a default bitrate of 100 KHz. This new divider is only applied if the clock divider is still default 0. Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Reviewed-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
Diffstat (limited to 'drivers/i2c')
-rw-r--r--drivers/i2c/busses/i2c-isch.c17
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/i2c/busses/i2c-isch.c b/drivers/i2c/busses/i2c-isch.c
index 4099f79c2280..8c38aaa7417c 100644
--- a/drivers/i2c/busses/i2c-isch.c
+++ b/drivers/i2c/busses/i2c-isch.c
@@ -40,6 +40,7 @@
40/* SCH SMBus address offsets */ 40/* SCH SMBus address offsets */
41#define SMBHSTCNT (0 + sch_smba) 41#define SMBHSTCNT (0 + sch_smba)
42#define SMBHSTSTS (1 + sch_smba) 42#define SMBHSTSTS (1 + sch_smba)
43#define SMBHSTCLK (2 + sch_smba)
43#define SMBHSTADD (4 + sch_smba) /* TSA */ 44#define SMBHSTADD (4 + sch_smba) /* TSA */
44#define SMBHSTCMD (5 + sch_smba) 45#define SMBHSTCMD (5 + sch_smba)
45#define SMBHSTDAT0 (6 + sch_smba) 46#define SMBHSTDAT0 (6 + sch_smba)
@@ -58,6 +59,9 @@
58 59
59static unsigned short sch_smba; 60static unsigned short sch_smba;
60static struct i2c_adapter sch_adapter; 61static struct i2c_adapter sch_adapter;
62static int backbone_speed = 33000; /* backbone speed in kHz */
63module_param(backbone_speed, int, S_IRUSR | S_IWUSR);
64MODULE_PARM_DESC(backbone_speed, "Backbone speed in kHz, (default = 33000)");
61 65
62/* 66/*
63 * Start the i2c transaction -- the i2c_access will prepare the transaction 67 * Start the i2c transaction -- the i2c_access will prepare the transaction
@@ -156,6 +160,19 @@ static s32 sch_access(struct i2c_adapter *adap, u16 addr,
156 dev_dbg(&sch_adapter.dev, "SMBus busy (%02x)\n", temp); 160 dev_dbg(&sch_adapter.dev, "SMBus busy (%02x)\n", temp);
157 return -EAGAIN; 161 return -EAGAIN;
158 } 162 }
163 temp = inw(SMBHSTCLK);
164 if (!temp) {
165 /*
166 * We can't determine if we have 33 or 25 MHz clock for
167 * SMBus, so expect 33 MHz and calculate a bus clock of
168 * 100 kHz. If we actually run at 25 MHz the bus will be
169 * run ~75 kHz instead which should do no harm.
170 */
171 dev_notice(&sch_adapter.dev,
172 "Clock divider unitialized. Setting defaults\n");
173 outw(backbone_speed / (4 * 100), SMBHSTCLK);
174 }
175
159 dev_dbg(&sch_adapter.dev, "access size: %d %s\n", size, 176 dev_dbg(&sch_adapter.dev, "access size: %d %s\n", size,
160 (read_write)?"READ":"WRITE"); 177 (read_write)?"READ":"WRITE");
161 switch (size) { 178 switch (size) {