1 files changed, 17 insertions, 0 deletions

diff --git a/drivers/i2c/busses/i2c-isch.c b/drivers/i2c/busses/i2c-isch.c
index 4099f79c2280..8c38aaa7417c 100644
--- a/drivers/i2c/busses/i2c-isch.c
+++ b/drivers/i2c/busses/i2c-isch.c
@@ -40,6 +40,7 @@
 /* SCH SMBus address offsets */
 #define SMBHSTCNT       (0 + sch_smba)
 #define SMBHSTSTS       (1 + sch_smba)
+#define SMBHSTCLK       (2 + sch_smba)
 #define SMBHSTADD       (4 + sch_smba) /* TSA */
 #define SMBHSTCMD       (5 + sch_smba)
 #define SMBHSTDAT0      (6 + sch_smba)
@@ -58,6 +59,9 @@
 
 static unsigned short sch_smba;
 static struct i2c_adapter sch_adapter;
+static int backbone_speed = 33000; /* backbone speed in kHz */
+module_param(backbone_speed, int, S_IRUSR | S_IWUSR);
+MODULE_PARM_DESC(backbone_speed, "Backbone speed in kHz, (default = 33000)");
 
 /*
  * Start the i2c transaction -- the i2c_access will prepare the transaction
@@ -156,6 +160,19 @@ static s32 sch_access(struct i2c_adapter *adap, u16 addr,
                 dev_dbg(&sch_adapter.dev, "SMBus busy (%02x)\n", temp);
                 return -EAGAIN;
         }
+        temp = inw(SMBHSTCLK);
+        if (!temp) {
+                /*
+                 * We can't determine if we have 33 or 25 MHz clock for
+                 * SMBus, so expect 33 MHz and calculate a bus clock of
+                 * 100 kHz. If we actually run at 25 MHz the bus will be
+                 * run ~75 kHz instead which should do no harm.
+                 */
+                dev_notice(&sch_adapter.dev,
+                        "Clock divider unitialized. Setting defaults\n");
+                outw(backbone_speed / (4 * 100), SMBHSTCLK);
+        }
+
         dev_dbg(&sch_adapter.dev, "access size: %d %s\n", size,
                 (read_write)?"READ":"WRITE");
         switch (size) {