diff options
author | Glenn Elliott <gelliott@cs.unc.edu> | 2012-03-04 19:47:13 -0500 |
---|---|---|
committer | Glenn Elliott <gelliott@cs.unc.edu> | 2012-03-04 19:47:13 -0500 |
commit | c71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch) | |
tree | ecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /drivers/i2c/busses/i2c-i801.c | |
parent | ea53c912f8a86a8567697115b6a0d8152beee5c8 (diff) | |
parent | 6a00f206debf8a5c8899055726ad127dbeeed098 (diff) |
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts:
litmus/sched_cedf.c
Diffstat (limited to 'drivers/i2c/busses/i2c-i801.c')
-rw-r--r-- | drivers/i2c/busses/i2c-i801.c | 411 |
1 files changed, 240 insertions, 171 deletions
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c index c60081169cc3..ab26840d0c70 100644 --- a/drivers/i2c/busses/i2c-i801.c +++ b/drivers/i2c/busses/i2c-i801.c | |||
@@ -3,6 +3,8 @@ | |||
3 | Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker | 3 | Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker |
4 | <mdsxyz123@yahoo.com> | 4 | <mdsxyz123@yahoo.com> |
5 | Copyright (C) 2007, 2008 Jean Delvare <khali@linux-fr.org> | 5 | Copyright (C) 2007, 2008 Jean Delvare <khali@linux-fr.org> |
6 | Copyright (C) 2010 Intel Corporation, | ||
7 | David Woodhouse <dwmw2@infradead.org> | ||
6 | 8 | ||
7 | This program is free software; you can redistribute it and/or modify | 9 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | 10 | it under the terms of the GNU General Public License as published by |
@@ -38,11 +40,17 @@ | |||
38 | 82801G (ICH7) 0x27da 32 hard yes yes yes | 40 | 82801G (ICH7) 0x27da 32 hard yes yes yes |
39 | 82801H (ICH8) 0x283e 32 hard yes yes yes | 41 | 82801H (ICH8) 0x283e 32 hard yes yes yes |
40 | 82801I (ICH9) 0x2930 32 hard yes yes yes | 42 | 82801I (ICH9) 0x2930 32 hard yes yes yes |
41 | Tolapai 0x5032 32 hard yes yes yes | 43 | EP80579 (Tolapai) 0x5032 32 hard yes yes yes |
42 | ICH10 0x3a30 32 hard yes yes yes | 44 | ICH10 0x3a30 32 hard yes yes yes |
43 | ICH10 0x3a60 32 hard yes yes yes | 45 | ICH10 0x3a60 32 hard yes yes yes |
44 | 3400/5 Series (PCH) 0x3b30 32 hard yes yes yes | 46 | 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes |
45 | Cougar Point (PCH) 0x1c22 32 hard yes yes yes | 47 | 6 Series (PCH) 0x1c22 32 hard yes yes yes |
48 | Patsburg (PCH) 0x1d22 32 hard yes yes yes | ||
49 | Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes | ||
50 | Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes | ||
51 | Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes | ||
52 | DH89xxCC (PCH) 0x2330 32 hard yes yes yes | ||
53 | Panther Point (PCH) 0x1e22 32 hard yes yes yes | ||
46 | 54 | ||
47 | Features supported by this driver: | 55 | Features supported by this driver: |
48 | Software PEC no | 56 | Software PEC no |
@@ -50,12 +58,11 @@ | |||
50 | Block buffer yes | 58 | Block buffer yes |
51 | Block process call transaction no | 59 | Block process call transaction no |
52 | I2C block read transaction yes (doesn't use the block buffer) | 60 | I2C block read transaction yes (doesn't use the block buffer) |
61 | Slave mode no | ||
53 | 62 | ||
54 | See the file Documentation/i2c/busses/i2c-i801 for details. | 63 | See the file Documentation/i2c/busses/i2c-i801 for details. |
55 | */ | 64 | */ |
56 | 65 | ||
57 | /* Note: we assume there can only be one I801, with one SMBus interface */ | ||
58 | |||
59 | #include <linux/module.h> | 66 | #include <linux/module.h> |
60 | #include <linux/pci.h> | 67 | #include <linux/pci.h> |
61 | #include <linux/kernel.h> | 68 | #include <linux/kernel.h> |
@@ -67,18 +74,19 @@ | |||
67 | #include <linux/acpi.h> | 74 | #include <linux/acpi.h> |
68 | #include <linux/io.h> | 75 | #include <linux/io.h> |
69 | #include <linux/dmi.h> | 76 | #include <linux/dmi.h> |
77 | #include <linux/slab.h> | ||
70 | 78 | ||
71 | /* I801 SMBus address offsets */ | 79 | /* I801 SMBus address offsets */ |
72 | #define SMBHSTSTS (0 + i801_smba) | 80 | #define SMBHSTSTS(p) (0 + (p)->smba) |
73 | #define SMBHSTCNT (2 + i801_smba) | 81 | #define SMBHSTCNT(p) (2 + (p)->smba) |
74 | #define SMBHSTCMD (3 + i801_smba) | 82 | #define SMBHSTCMD(p) (3 + (p)->smba) |
75 | #define SMBHSTADD (4 + i801_smba) | 83 | #define SMBHSTADD(p) (4 + (p)->smba) |
76 | #define SMBHSTDAT0 (5 + i801_smba) | 84 | #define SMBHSTDAT0(p) (5 + (p)->smba) |
77 | #define SMBHSTDAT1 (6 + i801_smba) | 85 | #define SMBHSTDAT1(p) (6 + (p)->smba) |
78 | #define SMBBLKDAT (7 + i801_smba) | 86 | #define SMBBLKDAT(p) (7 + (p)->smba) |
79 | #define SMBPEC (8 + i801_smba) /* ICH3 and later */ | 87 | #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ |
80 | #define SMBAUXSTS (12 + i801_smba) /* ICH4 and later */ | 88 | #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ |
81 | #define SMBAUXCTL (13 + i801_smba) /* ICH4 and later */ | 89 | #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ |
82 | 90 | ||
83 | /* PCI Address Constants */ | 91 | /* PCI Address Constants */ |
84 | #define SMBBAR 4 | 92 | #define SMBBAR 4 |
@@ -89,7 +97,7 @@ | |||
89 | #define SMBHSTCFG_SMB_SMI_EN 2 | 97 | #define SMBHSTCFG_SMB_SMI_EN 2 |
90 | #define SMBHSTCFG_I2C_EN 4 | 98 | #define SMBHSTCFG_I2C_EN 4 |
91 | 99 | ||
92 | /* Auxillary control register bits, ICH4+ only */ | 100 | /* Auxiliary control register bits, ICH4+ only */ |
93 | #define SMBAUXCTL_CRC 1 | 101 | #define SMBAUXCTL_CRC 1 |
94 | #define SMBAUXCTL_E32B 2 | 102 | #define SMBAUXCTL_E32B 2 |
95 | 103 | ||
@@ -127,16 +135,33 @@ | |||
127 | SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \ | 135 | SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \ |
128 | SMBHSTSTS_INTR) | 136 | SMBHSTSTS_INTR) |
129 | 137 | ||
130 | static unsigned long i801_smba; | 138 | /* Older devices have their ID defined in <linux/pci_ids.h> */ |
131 | static unsigned char i801_original_hstcfg; | 139 | #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 |
140 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 | ||
141 | /* Patsburg also has three 'Integrated Device Function' SMBus controllers */ | ||
142 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 | ||
143 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 | ||
144 | #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 | ||
145 | #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 | ||
146 | #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 | ||
147 | #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 | ||
148 | |||
149 | struct i801_priv { | ||
150 | struct i2c_adapter adapter; | ||
151 | unsigned long smba; | ||
152 | unsigned char original_hstcfg; | ||
153 | struct pci_dev *pci_dev; | ||
154 | unsigned int features; | ||
155 | }; | ||
156 | |||
132 | static struct pci_driver i801_driver; | 157 | static struct pci_driver i801_driver; |
133 | static struct pci_dev *I801_dev; | ||
134 | 158 | ||
135 | #define FEATURE_SMBUS_PEC (1 << 0) | 159 | #define FEATURE_SMBUS_PEC (1 << 0) |
136 | #define FEATURE_BLOCK_BUFFER (1 << 1) | 160 | #define FEATURE_BLOCK_BUFFER (1 << 1) |
137 | #define FEATURE_BLOCK_PROC (1 << 2) | 161 | #define FEATURE_BLOCK_PROC (1 << 2) |
138 | #define FEATURE_I2C_BLOCK_READ (1 << 3) | 162 | #define FEATURE_I2C_BLOCK_READ (1 << 3) |
139 | static unsigned int i801_features; | 163 | /* Not really a feature, but it's convenient to handle it as such */ |
164 | #define FEATURE_IDF (1 << 15) | ||
140 | 165 | ||
141 | static const char *i801_feature_names[] = { | 166 | static const char *i801_feature_names[] = { |
142 | "SMBus PEC", | 167 | "SMBus PEC", |
@@ -151,24 +176,24 @@ MODULE_PARM_DESC(disable_features, "Disable selected driver features"); | |||
151 | 176 | ||
152 | /* Make sure the SMBus host is ready to start transmitting. | 177 | /* Make sure the SMBus host is ready to start transmitting. |
153 | Return 0 if it is, -EBUSY if it is not. */ | 178 | Return 0 if it is, -EBUSY if it is not. */ |
154 | static int i801_check_pre(void) | 179 | static int i801_check_pre(struct i801_priv *priv) |
155 | { | 180 | { |
156 | int status; | 181 | int status; |
157 | 182 | ||
158 | status = inb_p(SMBHSTSTS); | 183 | status = inb_p(SMBHSTSTS(priv)); |
159 | if (status & SMBHSTSTS_HOST_BUSY) { | 184 | if (status & SMBHSTSTS_HOST_BUSY) { |
160 | dev_err(&I801_dev->dev, "SMBus is busy, can't use it!\n"); | 185 | dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); |
161 | return -EBUSY; | 186 | return -EBUSY; |
162 | } | 187 | } |
163 | 188 | ||
164 | status &= STATUS_FLAGS; | 189 | status &= STATUS_FLAGS; |
165 | if (status) { | 190 | if (status) { |
166 | dev_dbg(&I801_dev->dev, "Clearing status flags (%02x)\n", | 191 | dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", |
167 | status); | 192 | status); |
168 | outb_p(status, SMBHSTSTS); | 193 | outb_p(status, SMBHSTSTS(priv)); |
169 | status = inb_p(SMBHSTSTS) & STATUS_FLAGS; | 194 | status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; |
170 | if (status) { | 195 | if (status) { |
171 | dev_err(&I801_dev->dev, | 196 | dev_err(&priv->pci_dev->dev, |
172 | "Failed clearing status flags (%02x)\n", | 197 | "Failed clearing status flags (%02x)\n", |
173 | status); | 198 | status); |
174 | return -EBUSY; | 199 | return -EBUSY; |
@@ -179,48 +204,50 @@ static int i801_check_pre(void) | |||
179 | } | 204 | } |
180 | 205 | ||
181 | /* Convert the status register to an error code, and clear it. */ | 206 | /* Convert the status register to an error code, and clear it. */ |
182 | static int i801_check_post(int status, int timeout) | 207 | static int i801_check_post(struct i801_priv *priv, int status, int timeout) |
183 | { | 208 | { |
184 | int result = 0; | 209 | int result = 0; |
185 | 210 | ||
186 | /* If the SMBus is still busy, we give up */ | 211 | /* If the SMBus is still busy, we give up */ |
187 | if (timeout) { | 212 | if (timeout) { |
188 | dev_err(&I801_dev->dev, "Transaction timeout\n"); | 213 | dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); |
189 | /* try to stop the current command */ | 214 | /* try to stop the current command */ |
190 | dev_dbg(&I801_dev->dev, "Terminating the current operation\n"); | 215 | dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); |
191 | outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT); | 216 | outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL, |
217 | SMBHSTCNT(priv)); | ||
192 | msleep(1); | 218 | msleep(1); |
193 | outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT); | 219 | outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL), |
220 | SMBHSTCNT(priv)); | ||
194 | 221 | ||
195 | /* Check if it worked */ | 222 | /* Check if it worked */ |
196 | status = inb_p(SMBHSTSTS); | 223 | status = inb_p(SMBHSTSTS(priv)); |
197 | if ((status & SMBHSTSTS_HOST_BUSY) || | 224 | if ((status & SMBHSTSTS_HOST_BUSY) || |
198 | !(status & SMBHSTSTS_FAILED)) | 225 | !(status & SMBHSTSTS_FAILED)) |
199 | dev_err(&I801_dev->dev, | 226 | dev_err(&priv->pci_dev->dev, |
200 | "Failed terminating the transaction\n"); | 227 | "Failed terminating the transaction\n"); |
201 | outb_p(STATUS_FLAGS, SMBHSTSTS); | 228 | outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); |
202 | return -ETIMEDOUT; | 229 | return -ETIMEDOUT; |
203 | } | 230 | } |
204 | 231 | ||
205 | if (status & SMBHSTSTS_FAILED) { | 232 | if (status & SMBHSTSTS_FAILED) { |
206 | result = -EIO; | 233 | result = -EIO; |
207 | dev_err(&I801_dev->dev, "Transaction failed\n"); | 234 | dev_err(&priv->pci_dev->dev, "Transaction failed\n"); |
208 | } | 235 | } |
209 | if (status & SMBHSTSTS_DEV_ERR) { | 236 | if (status & SMBHSTSTS_DEV_ERR) { |
210 | result = -ENXIO; | 237 | result = -ENXIO; |
211 | dev_dbg(&I801_dev->dev, "No response\n"); | 238 | dev_dbg(&priv->pci_dev->dev, "No response\n"); |
212 | } | 239 | } |
213 | if (status & SMBHSTSTS_BUS_ERR) { | 240 | if (status & SMBHSTSTS_BUS_ERR) { |
214 | result = -EAGAIN; | 241 | result = -EAGAIN; |
215 | dev_dbg(&I801_dev->dev, "Lost arbitration\n"); | 242 | dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); |
216 | } | 243 | } |
217 | 244 | ||
218 | if (result) { | 245 | if (result) { |
219 | /* Clear error flags */ | 246 | /* Clear error flags */ |
220 | outb_p(status & STATUS_FLAGS, SMBHSTSTS); | 247 | outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv)); |
221 | status = inb_p(SMBHSTSTS) & STATUS_FLAGS; | 248 | status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; |
222 | if (status) { | 249 | if (status) { |
223 | dev_warn(&I801_dev->dev, "Failed clearing status " | 250 | dev_warn(&priv->pci_dev->dev, "Failed clearing status " |
224 | "flags at end of transaction (%02x)\n", | 251 | "flags at end of transaction (%02x)\n", |
225 | status); | 252 | status); |
226 | } | 253 | } |
@@ -229,86 +256,88 @@ static int i801_check_post(int status, int timeout) | |||
229 | return result; | 256 | return result; |
230 | } | 257 | } |
231 | 258 | ||
232 | static int i801_transaction(int xact) | 259 | static int i801_transaction(struct i801_priv *priv, int xact) |
233 | { | 260 | { |
234 | int status; | 261 | int status; |
235 | int result; | 262 | int result; |
236 | int timeout = 0; | 263 | int timeout = 0; |
237 | 264 | ||
238 | result = i801_check_pre(); | 265 | result = i801_check_pre(priv); |
239 | if (result < 0) | 266 | if (result < 0) |
240 | return result; | 267 | return result; |
241 | 268 | ||
242 | /* the current contents of SMBHSTCNT can be overwritten, since PEC, | 269 | /* the current contents of SMBHSTCNT can be overwritten, since PEC, |
243 | * INTREN, SMBSCMD are passed in xact */ | 270 | * INTREN, SMBSCMD are passed in xact */ |
244 | outb_p(xact | I801_START, SMBHSTCNT); | 271 | outb_p(xact | I801_START, SMBHSTCNT(priv)); |
245 | 272 | ||
246 | /* We will always wait for a fraction of a second! */ | 273 | /* We will always wait for a fraction of a second! */ |
247 | do { | 274 | do { |
248 | msleep(1); | 275 | msleep(1); |
249 | status = inb_p(SMBHSTSTS); | 276 | status = inb_p(SMBHSTSTS(priv)); |
250 | } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT)); | 277 | } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT)); |
251 | 278 | ||
252 | result = i801_check_post(status, timeout > MAX_TIMEOUT); | 279 | result = i801_check_post(priv, status, timeout > MAX_TIMEOUT); |
253 | if (result < 0) | 280 | if (result < 0) |
254 | return result; | 281 | return result; |
255 | 282 | ||
256 | outb_p(SMBHSTSTS_INTR, SMBHSTSTS); | 283 | outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); |
257 | return 0; | 284 | return 0; |
258 | } | 285 | } |
259 | 286 | ||
260 | /* wait for INTR bit as advised by Intel */ | 287 | /* wait for INTR bit as advised by Intel */ |
261 | static void i801_wait_hwpec(void) | 288 | static void i801_wait_hwpec(struct i801_priv *priv) |
262 | { | 289 | { |
263 | int timeout = 0; | 290 | int timeout = 0; |
264 | int status; | 291 | int status; |
265 | 292 | ||
266 | do { | 293 | do { |
267 | msleep(1); | 294 | msleep(1); |
268 | status = inb_p(SMBHSTSTS); | 295 | status = inb_p(SMBHSTSTS(priv)); |
269 | } while ((!(status & SMBHSTSTS_INTR)) | 296 | } while ((!(status & SMBHSTSTS_INTR)) |
270 | && (timeout++ < MAX_TIMEOUT)); | 297 | && (timeout++ < MAX_TIMEOUT)); |
271 | 298 | ||
272 | if (timeout > MAX_TIMEOUT) | 299 | if (timeout > MAX_TIMEOUT) |
273 | dev_dbg(&I801_dev->dev, "PEC Timeout!\n"); | 300 | dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n"); |
274 | 301 | ||
275 | outb_p(status, SMBHSTSTS); | 302 | outb_p(status, SMBHSTSTS(priv)); |
276 | } | 303 | } |
277 | 304 | ||
278 | static int i801_block_transaction_by_block(union i2c_smbus_data *data, | 305 | static int i801_block_transaction_by_block(struct i801_priv *priv, |
306 | union i2c_smbus_data *data, | ||
279 | char read_write, int hwpec) | 307 | char read_write, int hwpec) |
280 | { | 308 | { |
281 | int i, len; | 309 | int i, len; |
282 | int status; | 310 | int status; |
283 | 311 | ||
284 | inb_p(SMBHSTCNT); /* reset the data buffer index */ | 312 | inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ |
285 | 313 | ||
286 | /* Use 32-byte buffer to process this transaction */ | 314 | /* Use 32-byte buffer to process this transaction */ |
287 | if (read_write == I2C_SMBUS_WRITE) { | 315 | if (read_write == I2C_SMBUS_WRITE) { |
288 | len = data->block[0]; | 316 | len = data->block[0]; |
289 | outb_p(len, SMBHSTDAT0); | 317 | outb_p(len, SMBHSTDAT0(priv)); |
290 | for (i = 0; i < len; i++) | 318 | for (i = 0; i < len; i++) |
291 | outb_p(data->block[i+1], SMBBLKDAT); | 319 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
292 | } | 320 | } |
293 | 321 | ||
294 | status = i801_transaction(I801_BLOCK_DATA | ENABLE_INT9 | | 322 | status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 | |
295 | I801_PEC_EN * hwpec); | 323 | I801_PEC_EN * hwpec); |
296 | if (status) | 324 | if (status) |
297 | return status; | 325 | return status; |
298 | 326 | ||
299 | if (read_write == I2C_SMBUS_READ) { | 327 | if (read_write == I2C_SMBUS_READ) { |
300 | len = inb_p(SMBHSTDAT0); | 328 | len = inb_p(SMBHSTDAT0(priv)); |
301 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) | 329 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) |
302 | return -EPROTO; | 330 | return -EPROTO; |
303 | 331 | ||
304 | data->block[0] = len; | 332 | data->block[0] = len; |
305 | for (i = 0; i < len; i++) | 333 | for (i = 0; i < len; i++) |
306 | data->block[i + 1] = inb_p(SMBBLKDAT); | 334 | data->block[i + 1] = inb_p(SMBBLKDAT(priv)); |
307 | } | 335 | } |
308 | return 0; | 336 | return 0; |
309 | } | 337 | } |
310 | 338 | ||
311 | static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data, | 339 | static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, |
340 | union i2c_smbus_data *data, | ||
312 | char read_write, int command, | 341 | char read_write, int command, |
313 | int hwpec) | 342 | int hwpec) |
314 | { | 343 | { |
@@ -318,15 +347,15 @@ static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data, | |||
318 | int result; | 347 | int result; |
319 | int timeout; | 348 | int timeout; |
320 | 349 | ||
321 | result = i801_check_pre(); | 350 | result = i801_check_pre(priv); |
322 | if (result < 0) | 351 | if (result < 0) |
323 | return result; | 352 | return result; |
324 | 353 | ||
325 | len = data->block[0]; | 354 | len = data->block[0]; |
326 | 355 | ||
327 | if (read_write == I2C_SMBUS_WRITE) { | 356 | if (read_write == I2C_SMBUS_WRITE) { |
328 | outb_p(len, SMBHSTDAT0); | 357 | outb_p(len, SMBHSTDAT0(priv)); |
329 | outb_p(data->block[1], SMBBLKDAT); | 358 | outb_p(data->block[1], SMBBLKDAT(priv)); |
330 | } | 359 | } |
331 | 360 | ||
332 | for (i = 1; i <= len; i++) { | 361 | for (i = 1; i <= len; i++) { |
@@ -342,34 +371,37 @@ static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data, | |||
342 | else | 371 | else |
343 | smbcmd = I801_BLOCK_DATA; | 372 | smbcmd = I801_BLOCK_DATA; |
344 | } | 373 | } |
345 | outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT); | 374 | outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv)); |
346 | 375 | ||
347 | if (i == 1) | 376 | if (i == 1) |
348 | outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT); | 377 | outb_p(inb(SMBHSTCNT(priv)) | I801_START, |
378 | SMBHSTCNT(priv)); | ||
349 | 379 | ||
350 | /* We will always wait for a fraction of a second! */ | 380 | /* We will always wait for a fraction of a second! */ |
351 | timeout = 0; | 381 | timeout = 0; |
352 | do { | 382 | do { |
353 | msleep(1); | 383 | msleep(1); |
354 | status = inb_p(SMBHSTSTS); | 384 | status = inb_p(SMBHSTSTS(priv)); |
355 | } while ((!(status & SMBHSTSTS_BYTE_DONE)) | 385 | } while ((!(status & SMBHSTSTS_BYTE_DONE)) |
356 | && (timeout++ < MAX_TIMEOUT)); | 386 | && (timeout++ < MAX_TIMEOUT)); |
357 | 387 | ||
358 | result = i801_check_post(status, timeout > MAX_TIMEOUT); | 388 | result = i801_check_post(priv, status, timeout > MAX_TIMEOUT); |
359 | if (result < 0) | 389 | if (result < 0) |
360 | return result; | 390 | return result; |
361 | 391 | ||
362 | if (i == 1 && read_write == I2C_SMBUS_READ | 392 | if (i == 1 && read_write == I2C_SMBUS_READ |
363 | && command != I2C_SMBUS_I2C_BLOCK_DATA) { | 393 | && command != I2C_SMBUS_I2C_BLOCK_DATA) { |
364 | len = inb_p(SMBHSTDAT0); | 394 | len = inb_p(SMBHSTDAT0(priv)); |
365 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { | 395 | if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { |
366 | dev_err(&I801_dev->dev, | 396 | dev_err(&priv->pci_dev->dev, |
367 | "Illegal SMBus block read size %d\n", | 397 | "Illegal SMBus block read size %d\n", |
368 | len); | 398 | len); |
369 | /* Recover */ | 399 | /* Recover */ |
370 | while (inb_p(SMBHSTSTS) & SMBHSTSTS_HOST_BUSY) | 400 | while (inb_p(SMBHSTSTS(priv)) & |
371 | outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS); | 401 | SMBHSTSTS_HOST_BUSY) |
372 | outb_p(SMBHSTSTS_INTR, SMBHSTSTS); | 402 | outb_p(SMBHSTSTS_BYTE_DONE, |
403 | SMBHSTSTS(priv)); | ||
404 | outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); | ||
373 | return -EPROTO; | 405 | return -EPROTO; |
374 | } | 406 | } |
375 | data->block[0] = len; | 407 | data->block[0] = len; |
@@ -377,27 +409,28 @@ static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data, | |||
377 | 409 | ||
378 | /* Retrieve/store value in SMBBLKDAT */ | 410 | /* Retrieve/store value in SMBBLKDAT */ |
379 | if (read_write == I2C_SMBUS_READ) | 411 | if (read_write == I2C_SMBUS_READ) |
380 | data->block[i] = inb_p(SMBBLKDAT); | 412 | data->block[i] = inb_p(SMBBLKDAT(priv)); |
381 | if (read_write == I2C_SMBUS_WRITE && i+1 <= len) | 413 | if (read_write == I2C_SMBUS_WRITE && i+1 <= len) |
382 | outb_p(data->block[i+1], SMBBLKDAT); | 414 | outb_p(data->block[i+1], SMBBLKDAT(priv)); |
383 | 415 | ||
384 | /* signals SMBBLKDAT ready */ | 416 | /* signals SMBBLKDAT ready */ |
385 | outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS); | 417 | outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv)); |
386 | } | 418 | } |
387 | 419 | ||
388 | return 0; | 420 | return 0; |
389 | } | 421 | } |
390 | 422 | ||
391 | static int i801_set_block_buffer_mode(void) | 423 | static int i801_set_block_buffer_mode(struct i801_priv *priv) |
392 | { | 424 | { |
393 | outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_E32B, SMBAUXCTL); | 425 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); |
394 | if ((inb_p(SMBAUXCTL) & SMBAUXCTL_E32B) == 0) | 426 | if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) |
395 | return -EIO; | 427 | return -EIO; |
396 | return 0; | 428 | return 0; |
397 | } | 429 | } |
398 | 430 | ||
399 | /* Block transaction function */ | 431 | /* Block transaction function */ |
400 | static int i801_block_transaction(union i2c_smbus_data *data, char read_write, | 432 | static int i801_block_transaction(struct i801_priv *priv, |
433 | union i2c_smbus_data *data, char read_write, | ||
401 | int command, int hwpec) | 434 | int command, int hwpec) |
402 | { | 435 | { |
403 | int result = 0; | 436 | int result = 0; |
@@ -406,11 +439,11 @@ static int i801_block_transaction(union i2c_smbus_data *data, char read_write, | |||
406 | if (command == I2C_SMBUS_I2C_BLOCK_DATA) { | 439 | if (command == I2C_SMBUS_I2C_BLOCK_DATA) { |
407 | if (read_write == I2C_SMBUS_WRITE) { | 440 | if (read_write == I2C_SMBUS_WRITE) { |
408 | /* set I2C_EN bit in configuration register */ | 441 | /* set I2C_EN bit in configuration register */ |
409 | pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc); | 442 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); |
410 | pci_write_config_byte(I801_dev, SMBHSTCFG, | 443 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, |
411 | hostc | SMBHSTCFG_I2C_EN); | 444 | hostc | SMBHSTCFG_I2C_EN); |
412 | } else if (!(i801_features & FEATURE_I2C_BLOCK_READ)) { | 445 | } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { |
413 | dev_err(&I801_dev->dev, | 446 | dev_err(&priv->pci_dev->dev, |
414 | "I2C block read is unsupported!\n"); | 447 | "I2C block read is unsupported!\n"); |
415 | return -EOPNOTSUPP; | 448 | return -EOPNOTSUPP; |
416 | } | 449 | } |
@@ -429,22 +462,23 @@ static int i801_block_transaction(union i2c_smbus_data *data, char read_write, | |||
429 | /* Experience has shown that the block buffer can only be used for | 462 | /* Experience has shown that the block buffer can only be used for |
430 | SMBus (not I2C) block transactions, even though the datasheet | 463 | SMBus (not I2C) block transactions, even though the datasheet |
431 | doesn't mention this limitation. */ | 464 | doesn't mention this limitation. */ |
432 | if ((i801_features & FEATURE_BLOCK_BUFFER) | 465 | if ((priv->features & FEATURE_BLOCK_BUFFER) |
433 | && command != I2C_SMBUS_I2C_BLOCK_DATA | 466 | && command != I2C_SMBUS_I2C_BLOCK_DATA |
434 | && i801_set_block_buffer_mode() == 0) | 467 | && i801_set_block_buffer_mode(priv) == 0) |
435 | result = i801_block_transaction_by_block(data, read_write, | 468 | result = i801_block_transaction_by_block(priv, data, |
436 | hwpec); | 469 | read_write, hwpec); |
437 | else | 470 | else |
438 | result = i801_block_transaction_byte_by_byte(data, read_write, | 471 | result = i801_block_transaction_byte_by_byte(priv, data, |
472 | read_write, | ||
439 | command, hwpec); | 473 | command, hwpec); |
440 | 474 | ||
441 | if (result == 0 && hwpec) | 475 | if (result == 0 && hwpec) |
442 | i801_wait_hwpec(); | 476 | i801_wait_hwpec(priv); |
443 | 477 | ||
444 | if (command == I2C_SMBUS_I2C_BLOCK_DATA | 478 | if (command == I2C_SMBUS_I2C_BLOCK_DATA |
445 | && read_write == I2C_SMBUS_WRITE) { | 479 | && read_write == I2C_SMBUS_WRITE) { |
446 | /* restore saved configuration register value */ | 480 | /* restore saved configuration register value */ |
447 | pci_write_config_byte(I801_dev, SMBHSTCFG, hostc); | 481 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); |
448 | } | 482 | } |
449 | return result; | 483 | return result; |
450 | } | 484 | } |
@@ -457,81 +491,85 @@ static s32 i801_access(struct i2c_adapter *adap, u16 addr, | |||
457 | int hwpec; | 491 | int hwpec; |
458 | int block = 0; | 492 | int block = 0; |
459 | int ret, xact = 0; | 493 | int ret, xact = 0; |
494 | struct i801_priv *priv = i2c_get_adapdata(adap); | ||
460 | 495 | ||
461 | hwpec = (i801_features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) | 496 | hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) |
462 | && size != I2C_SMBUS_QUICK | 497 | && size != I2C_SMBUS_QUICK |
463 | && size != I2C_SMBUS_I2C_BLOCK_DATA; | 498 | && size != I2C_SMBUS_I2C_BLOCK_DATA; |
464 | 499 | ||
465 | switch (size) { | 500 | switch (size) { |
466 | case I2C_SMBUS_QUICK: | 501 | case I2C_SMBUS_QUICK: |
467 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | 502 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), |
468 | SMBHSTADD); | 503 | SMBHSTADD(priv)); |
469 | xact = I801_QUICK; | 504 | xact = I801_QUICK; |
470 | break; | 505 | break; |
471 | case I2C_SMBUS_BYTE: | 506 | case I2C_SMBUS_BYTE: |
472 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | 507 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), |
473 | SMBHSTADD); | 508 | SMBHSTADD(priv)); |
474 | if (read_write == I2C_SMBUS_WRITE) | 509 | if (read_write == I2C_SMBUS_WRITE) |
475 | outb_p(command, SMBHSTCMD); | 510 | outb_p(command, SMBHSTCMD(priv)); |
476 | xact = I801_BYTE; | 511 | xact = I801_BYTE; |
477 | break; | 512 | break; |
478 | case I2C_SMBUS_BYTE_DATA: | 513 | case I2C_SMBUS_BYTE_DATA: |
479 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | 514 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), |
480 | SMBHSTADD); | 515 | SMBHSTADD(priv)); |
481 | outb_p(command, SMBHSTCMD); | 516 | outb_p(command, SMBHSTCMD(priv)); |
482 | if (read_write == I2C_SMBUS_WRITE) | 517 | if (read_write == I2C_SMBUS_WRITE) |
483 | outb_p(data->byte, SMBHSTDAT0); | 518 | outb_p(data->byte, SMBHSTDAT0(priv)); |
484 | xact = I801_BYTE_DATA; | 519 | xact = I801_BYTE_DATA; |
485 | break; | 520 | break; |
486 | case I2C_SMBUS_WORD_DATA: | 521 | case I2C_SMBUS_WORD_DATA: |
487 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | 522 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), |
488 | SMBHSTADD); | 523 | SMBHSTADD(priv)); |
489 | outb_p(command, SMBHSTCMD); | 524 | outb_p(command, SMBHSTCMD(priv)); |
490 | if (read_write == I2C_SMBUS_WRITE) { | 525 | if (read_write == I2C_SMBUS_WRITE) { |
491 | outb_p(data->word & 0xff, SMBHSTDAT0); | 526 | outb_p(data->word & 0xff, SMBHSTDAT0(priv)); |
492 | outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1); | 527 | outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); |
493 | } | 528 | } |
494 | xact = I801_WORD_DATA; | 529 | xact = I801_WORD_DATA; |
495 | break; | 530 | break; |
496 | case I2C_SMBUS_BLOCK_DATA: | 531 | case I2C_SMBUS_BLOCK_DATA: |
497 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), | 532 | outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), |
498 | SMBHSTADD); | 533 | SMBHSTADD(priv)); |
499 | outb_p(command, SMBHSTCMD); | 534 | outb_p(command, SMBHSTCMD(priv)); |
500 | block = 1; | 535 | block = 1; |
501 | break; | 536 | break; |
502 | case I2C_SMBUS_I2C_BLOCK_DATA: | 537 | case I2C_SMBUS_I2C_BLOCK_DATA: |
503 | /* NB: page 240 of ICH5 datasheet shows that the R/#W | 538 | /* NB: page 240 of ICH5 datasheet shows that the R/#W |
504 | * bit should be cleared here, even when reading */ | 539 | * bit should be cleared here, even when reading */ |
505 | outb_p((addr & 0x7f) << 1, SMBHSTADD); | 540 | outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); |
506 | if (read_write == I2C_SMBUS_READ) { | 541 | if (read_write == I2C_SMBUS_READ) { |
507 | /* NB: page 240 of ICH5 datasheet also shows | 542 | /* NB: page 240 of ICH5 datasheet also shows |
508 | * that DATA1 is the cmd field when reading */ | 543 | * that DATA1 is the cmd field when reading */ |
509 | outb_p(command, SMBHSTDAT1); | 544 | outb_p(command, SMBHSTDAT1(priv)); |
510 | } else | 545 | } else |
511 | outb_p(command, SMBHSTCMD); | 546 | outb_p(command, SMBHSTCMD(priv)); |
512 | block = 1; | 547 | block = 1; |
513 | break; | 548 | break; |
514 | default: | 549 | default: |
515 | dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size); | 550 | dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", |
551 | size); | ||
516 | return -EOPNOTSUPP; | 552 | return -EOPNOTSUPP; |
517 | } | 553 | } |
518 | 554 | ||
519 | if (hwpec) /* enable/disable hardware PEC */ | 555 | if (hwpec) /* enable/disable hardware PEC */ |
520 | outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL); | 556 | outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); |
521 | else | 557 | else |
522 | outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL); | 558 | outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), |
559 | SMBAUXCTL(priv)); | ||
523 | 560 | ||
524 | if (block) | 561 | if (block) |
525 | ret = i801_block_transaction(data, read_write, size, hwpec); | 562 | ret = i801_block_transaction(priv, data, read_write, size, |
563 | hwpec); | ||
526 | else | 564 | else |
527 | ret = i801_transaction(xact | ENABLE_INT9); | 565 | ret = i801_transaction(priv, xact | ENABLE_INT9); |
528 | 566 | ||
529 | /* Some BIOSes don't like it when PEC is enabled at reboot or resume | 567 | /* Some BIOSes don't like it when PEC is enabled at reboot or resume |
530 | time, so we forcibly disable it after every transaction. Turn off | 568 | time, so we forcibly disable it after every transaction. Turn off |
531 | E32B for the same reason. */ | 569 | E32B for the same reason. */ |
532 | if (hwpec || block) | 570 | if (hwpec || block) |
533 | outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), | 571 | outb_p(inb_p(SMBAUXCTL(priv)) & |
534 | SMBAUXCTL); | 572 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); |
535 | 573 | ||
536 | if (block) | 574 | if (block) |
537 | return ret; | 575 | return ret; |
@@ -543,10 +581,11 @@ static s32 i801_access(struct i2c_adapter *adap, u16 addr, | |||
543 | switch (xact & 0x7f) { | 581 | switch (xact & 0x7f) { |
544 | case I801_BYTE: /* Result put in SMBHSTDAT0 */ | 582 | case I801_BYTE: /* Result put in SMBHSTDAT0 */ |
545 | case I801_BYTE_DATA: | 583 | case I801_BYTE_DATA: |
546 | data->byte = inb_p(SMBHSTDAT0); | 584 | data->byte = inb_p(SMBHSTDAT0(priv)); |
547 | break; | 585 | break; |
548 | case I801_WORD_DATA: | 586 | case I801_WORD_DATA: |
549 | data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8); | 587 | data->word = inb_p(SMBHSTDAT0(priv)) + |
588 | (inb_p(SMBHSTDAT1(priv)) << 8); | ||
550 | break; | 589 | break; |
551 | } | 590 | } |
552 | return 0; | 591 | return 0; |
@@ -555,11 +594,13 @@ static s32 i801_access(struct i2c_adapter *adap, u16 addr, | |||
555 | 594 | ||
556 | static u32 i801_func(struct i2c_adapter *adapter) | 595 | static u32 i801_func(struct i2c_adapter *adapter) |
557 | { | 596 | { |
597 | struct i801_priv *priv = i2c_get_adapdata(adapter); | ||
598 | |||
558 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | | 599 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | |
559 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | | 600 | I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | |
560 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | | 601 | I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | |
561 | ((i801_features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | | 602 | ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | |
562 | ((i801_features & FEATURE_I2C_BLOCK_READ) ? | 603 | ((priv->features & FEATURE_I2C_BLOCK_READ) ? |
563 | I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0); | 604 | I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0); |
564 | } | 605 | } |
565 | 606 | ||
@@ -568,12 +609,6 @@ static const struct i2c_algorithm smbus_algorithm = { | |||
568 | .functionality = i801_func, | 609 | .functionality = i801_func, |
569 | }; | 610 | }; |
570 | 611 | ||
571 | static struct i2c_adapter i801_adapter = { | ||
572 | .owner = THIS_MODULE, | ||
573 | .class = I2C_CLASS_HWMON | I2C_CLASS_SPD, | ||
574 | .algo = &smbus_algorithm, | ||
575 | }; | ||
576 | |||
577 | static const struct pci_device_id i801_ids[] = { | 612 | static const struct pci_device_id i801_ids[] = { |
578 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, | 613 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, |
579 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, | 614 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, |
@@ -587,17 +622,23 @@ static const struct pci_device_id i801_ids[] = { | |||
587 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, | 622 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, |
588 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, | 623 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, |
589 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, | 624 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, |
590 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TOLAPAI_1) }, | 625 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, |
591 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, | 626 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, |
592 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, | 627 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, |
593 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PCH_SMBUS) }, | 628 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, |
594 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CPT_SMBUS) }, | 629 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, |
630 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, | ||
631 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, | ||
632 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, | ||
633 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, | ||
634 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, | ||
635 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, | ||
595 | { 0, } | 636 | { 0, } |
596 | }; | 637 | }; |
597 | 638 | ||
598 | MODULE_DEVICE_TABLE(pci, i801_ids); | 639 | MODULE_DEVICE_TABLE(pci, i801_ids); |
599 | 640 | ||
600 | #if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE | 641 | #if defined CONFIG_X86 && defined CONFIG_DMI |
601 | static unsigned char apanel_addr; | 642 | static unsigned char apanel_addr; |
602 | 643 | ||
603 | /* Scan the system ROM for the signature "FJKEYINF" */ | 644 | /* Scan the system ROM for the signature "FJKEYINF" */ |
@@ -627,11 +668,7 @@ static void __init input_apanel_init(void) | |||
627 | } | 668 | } |
628 | iounmap(bios); | 669 | iounmap(bios); |
629 | } | 670 | } |
630 | #else | ||
631 | static void __init input_apanel_init(void) {} | ||
632 | #endif | ||
633 | 671 | ||
634 | #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE | ||
635 | struct dmi_onboard_device_info { | 672 | struct dmi_onboard_device_info { |
636 | const char *name; | 673 | const char *name; |
637 | u8 type; | 674 | u8 type; |
@@ -697,23 +734,60 @@ static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm, | |||
697 | dmi_check_onboard_device(type, name, adap); | 734 | dmi_check_onboard_device(type, name, adap); |
698 | } | 735 | } |
699 | } | 736 | } |
700 | #endif | 737 | |
738 | /* Register optional slaves */ | ||
739 | static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) | ||
740 | { | ||
741 | /* Only register slaves on main SMBus channel */ | ||
742 | if (priv->features & FEATURE_IDF) | ||
743 | return; | ||
744 | |||
745 | if (apanel_addr) { | ||
746 | struct i2c_board_info info; | ||
747 | |||
748 | memset(&info, 0, sizeof(struct i2c_board_info)); | ||
749 | info.addr = apanel_addr; | ||
750 | strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); | ||
751 | i2c_new_device(&priv->adapter, &info); | ||
752 | } | ||
753 | |||
754 | if (dmi_name_in_vendors("FUJITSU")) | ||
755 | dmi_walk(dmi_check_onboard_devices, &priv->adapter); | ||
756 | } | ||
757 | #else | ||
758 | static void __init input_apanel_init(void) {} | ||
759 | static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {} | ||
760 | #endif /* CONFIG_X86 && CONFIG_DMI */ | ||
701 | 761 | ||
702 | static int __devinit i801_probe(struct pci_dev *dev, | 762 | static int __devinit i801_probe(struct pci_dev *dev, |
703 | const struct pci_device_id *id) | 763 | const struct pci_device_id *id) |
704 | { | 764 | { |
705 | unsigned char temp; | 765 | unsigned char temp; |
706 | int err, i; | 766 | int err, i; |
767 | struct i801_priv *priv; | ||
768 | |||
769 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | ||
770 | if (!priv) | ||
771 | return -ENOMEM; | ||
707 | 772 | ||
708 | I801_dev = dev; | 773 | i2c_set_adapdata(&priv->adapter, priv); |
709 | i801_features = 0; | 774 | priv->adapter.owner = THIS_MODULE; |
775 | priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; | ||
776 | priv->adapter.algo = &smbus_algorithm; | ||
777 | |||
778 | priv->pci_dev = dev; | ||
710 | switch (dev->device) { | 779 | switch (dev->device) { |
780 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: | ||
781 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: | ||
782 | case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: | ||
783 | priv->features |= FEATURE_IDF; | ||
784 | /* fall through */ | ||
711 | default: | 785 | default: |
712 | i801_features |= FEATURE_I2C_BLOCK_READ; | 786 | priv->features |= FEATURE_I2C_BLOCK_READ; |
713 | /* fall through */ | 787 | /* fall through */ |
714 | case PCI_DEVICE_ID_INTEL_82801DB_3: | 788 | case PCI_DEVICE_ID_INTEL_82801DB_3: |
715 | i801_features |= FEATURE_SMBUS_PEC; | 789 | priv->features |= FEATURE_SMBUS_PEC; |
716 | i801_features |= FEATURE_BLOCK_BUFFER; | 790 | priv->features |= FEATURE_BLOCK_BUFFER; |
717 | /* fall through */ | 791 | /* fall through */ |
718 | case PCI_DEVICE_ID_INTEL_82801CA_3: | 792 | case PCI_DEVICE_ID_INTEL_82801CA_3: |
719 | case PCI_DEVICE_ID_INTEL_82801BA_2: | 793 | case PCI_DEVICE_ID_INTEL_82801BA_2: |
@@ -724,11 +798,11 @@ static int __devinit i801_probe(struct pci_dev *dev, | |||
724 | 798 | ||
725 | /* Disable features on user request */ | 799 | /* Disable features on user request */ |
726 | for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { | 800 | for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { |
727 | if (i801_features & disable_features & (1 << i)) | 801 | if (priv->features & disable_features & (1 << i)) |
728 | dev_notice(&dev->dev, "%s disabled by user\n", | 802 | dev_notice(&dev->dev, "%s disabled by user\n", |
729 | i801_feature_names[i]); | 803 | i801_feature_names[i]); |
730 | } | 804 | } |
731 | i801_features &= ~disable_features; | 805 | priv->features &= ~disable_features; |
732 | 806 | ||
733 | err = pci_enable_device(dev); | 807 | err = pci_enable_device(dev); |
734 | if (err) { | 808 | if (err) { |
@@ -738,8 +812,8 @@ static int __devinit i801_probe(struct pci_dev *dev, | |||
738 | } | 812 | } |
739 | 813 | ||
740 | /* Determine the address of the SMBus area */ | 814 | /* Determine the address of the SMBus area */ |
741 | i801_smba = pci_resource_start(dev, SMBBAR); | 815 | priv->smba = pci_resource_start(dev, SMBBAR); |
742 | if (!i801_smba) { | 816 | if (!priv->smba) { |
743 | dev_err(&dev->dev, "SMBus base address uninitialized, " | 817 | dev_err(&dev->dev, "SMBus base address uninitialized, " |
744 | "upgrade BIOS\n"); | 818 | "upgrade BIOS\n"); |
745 | err = -ENODEV; | 819 | err = -ENODEV; |
@@ -755,19 +829,19 @@ static int __devinit i801_probe(struct pci_dev *dev, | |||
755 | err = pci_request_region(dev, SMBBAR, i801_driver.name); | 829 | err = pci_request_region(dev, SMBBAR, i801_driver.name); |
756 | if (err) { | 830 | if (err) { |
757 | dev_err(&dev->dev, "Failed to request SMBus region " | 831 | dev_err(&dev->dev, "Failed to request SMBus region " |
758 | "0x%lx-0x%Lx\n", i801_smba, | 832 | "0x%lx-0x%Lx\n", priv->smba, |
759 | (unsigned long long)pci_resource_end(dev, SMBBAR)); | 833 | (unsigned long long)pci_resource_end(dev, SMBBAR)); |
760 | goto exit; | 834 | goto exit; |
761 | } | 835 | } |
762 | 836 | ||
763 | pci_read_config_byte(I801_dev, SMBHSTCFG, &temp); | 837 | pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp); |
764 | i801_original_hstcfg = temp; | 838 | priv->original_hstcfg = temp; |
765 | temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ | 839 | temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ |
766 | if (!(temp & SMBHSTCFG_HST_EN)) { | 840 | if (!(temp & SMBHSTCFG_HST_EN)) { |
767 | dev_info(&dev->dev, "Enabling SMBus device\n"); | 841 | dev_info(&dev->dev, "Enabling SMBus device\n"); |
768 | temp |= SMBHSTCFG_HST_EN; | 842 | temp |= SMBHSTCFG_HST_EN; |
769 | } | 843 | } |
770 | pci_write_config_byte(I801_dev, SMBHSTCFG, temp); | 844 | pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp); |
771 | 845 | ||
772 | if (temp & SMBHSTCFG_SMB_SMI_EN) | 846 | if (temp & SMBHSTCFG_SMB_SMI_EN) |
773 | dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); | 847 | dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); |
@@ -775,53 +849,45 @@ static int __devinit i801_probe(struct pci_dev *dev, | |||
775 | dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n"); | 849 | dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n"); |
776 | 850 | ||
777 | /* Clear special mode bits */ | 851 | /* Clear special mode bits */ |
778 | if (i801_features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) | 852 | if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) |
779 | outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), | 853 | outb_p(inb_p(SMBAUXCTL(priv)) & |
780 | SMBAUXCTL); | 854 | ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); |
781 | 855 | ||
782 | /* set up the sysfs linkage to our parent device */ | 856 | /* set up the sysfs linkage to our parent device */ |
783 | i801_adapter.dev.parent = &dev->dev; | 857 | priv->adapter.dev.parent = &dev->dev; |
784 | 858 | ||
785 | /* Retry up to 3 times on lost arbitration */ | 859 | /* Retry up to 3 times on lost arbitration */ |
786 | i801_adapter.retries = 3; | 860 | priv->adapter.retries = 3; |
787 | 861 | ||
788 | snprintf(i801_adapter.name, sizeof(i801_adapter.name), | 862 | snprintf(priv->adapter.name, sizeof(priv->adapter.name), |
789 | "SMBus I801 adapter at %04lx", i801_smba); | 863 | "SMBus I801 adapter at %04lx", priv->smba); |
790 | err = i2c_add_adapter(&i801_adapter); | 864 | err = i2c_add_adapter(&priv->adapter); |
791 | if (err) { | 865 | if (err) { |
792 | dev_err(&dev->dev, "Failed to add SMBus adapter\n"); | 866 | dev_err(&dev->dev, "Failed to add SMBus adapter\n"); |
793 | goto exit_release; | 867 | goto exit_release; |
794 | } | 868 | } |
795 | 869 | ||
796 | /* Register optional slaves */ | 870 | i801_probe_optional_slaves(priv); |
797 | #if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE | ||
798 | if (apanel_addr) { | ||
799 | struct i2c_board_info info; | ||
800 | |||
801 | memset(&info, 0, sizeof(struct i2c_board_info)); | ||
802 | info.addr = apanel_addr; | ||
803 | strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); | ||
804 | i2c_new_device(&i801_adapter, &info); | ||
805 | } | ||
806 | #endif | ||
807 | #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE | ||
808 | if (dmi_name_in_vendors("FUJITSU")) | ||
809 | dmi_walk(dmi_check_onboard_devices, &i801_adapter); | ||
810 | #endif | ||
811 | 871 | ||
872 | pci_set_drvdata(dev, priv); | ||
812 | return 0; | 873 | return 0; |
813 | 874 | ||
814 | exit_release: | 875 | exit_release: |
815 | pci_release_region(dev, SMBBAR); | 876 | pci_release_region(dev, SMBBAR); |
816 | exit: | 877 | exit: |
878 | kfree(priv); | ||
817 | return err; | 879 | return err; |
818 | } | 880 | } |
819 | 881 | ||
820 | static void __devexit i801_remove(struct pci_dev *dev) | 882 | static void __devexit i801_remove(struct pci_dev *dev) |
821 | { | 883 | { |
822 | i2c_del_adapter(&i801_adapter); | 884 | struct i801_priv *priv = pci_get_drvdata(dev); |
823 | pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg); | 885 | |
886 | i2c_del_adapter(&priv->adapter); | ||
887 | pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); | ||
824 | pci_release_region(dev, SMBBAR); | 888 | pci_release_region(dev, SMBBAR); |
889 | pci_set_drvdata(dev, NULL); | ||
890 | kfree(priv); | ||
825 | /* | 891 | /* |
826 | * do not call pci_disable_device(dev) since it can cause hard hangs on | 892 | * do not call pci_disable_device(dev) since it can cause hard hangs on |
827 | * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) | 893 | * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) |
@@ -831,8 +897,10 @@ static void __devexit i801_remove(struct pci_dev *dev) | |||
831 | #ifdef CONFIG_PM | 897 | #ifdef CONFIG_PM |
832 | static int i801_suspend(struct pci_dev *dev, pm_message_t mesg) | 898 | static int i801_suspend(struct pci_dev *dev, pm_message_t mesg) |
833 | { | 899 | { |
900 | struct i801_priv *priv = pci_get_drvdata(dev); | ||
901 | |||
834 | pci_save_state(dev); | 902 | pci_save_state(dev); |
835 | pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg); | 903 | pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); |
836 | pci_set_power_state(dev, pci_choose_state(dev, mesg)); | 904 | pci_set_power_state(dev, pci_choose_state(dev, mesg)); |
837 | return 0; | 905 | return 0; |
838 | } | 906 | } |
@@ -859,7 +927,8 @@ static struct pci_driver i801_driver = { | |||
859 | 927 | ||
860 | static int __init i2c_i801_init(void) | 928 | static int __init i2c_i801_init(void) |
861 | { | 929 | { |
862 | input_apanel_init(); | 930 | if (dmi_name_in_vendors("FUJITSU")) |
931 | input_apanel_init(); | ||
863 | return pci_register_driver(&i801_driver); | 932 | return pci_register_driver(&i801_driver); |
864 | } | 933 | } |
865 | 934 | ||