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authorDave Airlie <airlied@redhat.com>2015-02-04 19:32:44 -0500
committerDave Airlie <airlied@redhat.com>2015-02-04 19:32:44 -0500
commit225963dd3eb71357b086bc091a5594d0fa2ac783 (patch)
tree89ae69cbeaa77d1e640628b68b93f42cfdbdadef /drivers/gpu
parente4bf44b3b558742fb7c58b4d34e206c8942f07e6 (diff)
parentb838cbee0d6f0234406e435032b2304f3d05515d (diff)
Merge branch 'drm-intel-next' of git://anongit.freedesktop.org/drm-intel into drm-next
drm-intel-next-2015-01-30: - chv rps improvements from Ville - atomic state handling prep work from Ander - execlist request tracking refactoring from Nick Hoath - forcewake code consolidation from Chris&Mika - fastboot plane config refactoring and skl support from Damien - some more skl pm patches all over (Damien) - refactor dsi code to use drm dsi helpers and drm_panel infrastructure (Jani) - first cut at experimental atomic plane updates (Matt Roper) - piles of smaller things all over, as usual * 'drm-intel-next' of git://anongit.freedesktop.org/drm-intel: (102 commits) drm/i915: Remove bogus locking check in the hangcheck code drm/i915: Update DRIVER_DATE to 20150130 drm/i915: Use pipe_config's cpu_transcoder for reading encoder hw state drm/i915: Fix a use-after-free in intel_execlists_retire_requests drm/i915: Split shared dpll setup out of __intel_set_mode() drm/i915: Don't do posting reads on getting forcewake drm/i915: Do uncore early sanitize after domain init drm/i915: Handle CHV in vlv_set_rps_idle() drm/i915: Remove nested work in gpu error handling drm/i915/documentation: Add intel_uncore.c to drm.tmpl drm/i915/dsi: remove intel_dsi_cmd.c and the unused functions therein drm/i915/dsi: move dpi_send_cmd() to intel_dsi.c and make it static drm/i915/dsi: remove old read/write functions in favor of new stuff drm/i915/dsi: make the vbt panel driver use mipi_dsi_device for transfers drm/i915/dsi: add drm mipi dsi host support drm/i915/dsi: switch to drm_panel interface drm/i915/skl: Enabling PSR on Skylake Revert "drm/i915: Fix mutex->owner inspection race under DEBUG_MUTEXES" drm/i915: Be consistent on printing seqnos drm/i915: Display current hangcheck status in debugfs ...
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/Kconfig2
-rw-r--r--drivers/gpu/drm/i915/Makefile2
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c195
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c28
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c15
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h176
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c72
-rw-r--r--drivers/gpu/drm/i915/i915_gem_execbuffer.c26
-rw-r--r--drivers/gpu/drm/i915/i915_gpu_error.c2
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c77
-rw-r--r--drivers/gpu/drm/i915/i915_params.c5
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h28
-rw-r--r--drivers/gpu/drm/i915/i915_sysfs.c133
-rw-r--r--drivers/gpu/drm/i915/intel_atomic.c237
-rw-r--r--drivers/gpu/drm/i915/intel_atomic_plane.c116
-rw-r--r--drivers/gpu/drm/i915/intel_audio.c2
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c19
-rw-r--r--drivers/gpu/drm/i915/intel_ddi.c105
-rw-r--r--drivers/gpu/drm/i915/intel_display.c1071
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c232
-rw-r--r--drivers/gpu/drm/i915/intel_dp_mst.c19
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h115
-rw-r--r--drivers/gpu/drm/i915/intel_dsi.c359
-rw-r--r--drivers/gpu/drm/i915/intel_dsi.h69
-rw-r--r--drivers/gpu/drm/i915/intel_dsi_cmd.c432
-rw-r--r--drivers/gpu/drm/i915/intel_dsi_cmd.h78
-rw-r--r--drivers/gpu/drm/i915/intel_dsi_panel_vbt.c290
-rw-r--r--drivers/gpu/drm/i915/intel_dvo.c23
-rw-r--r--drivers/gpu/drm/i915/intel_fbc.c12
-rw-r--r--drivers/gpu/drm/i915/intel_fbdev.c15
-rw-r--r--drivers/gpu/drm/i915/intel_fifo_underrun.c2
-rw-r--r--drivers/gpu/drm/i915/intel_frontbuffer.c2
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c51
-rw-r--r--drivers/gpu/drm/i915/intel_lrc.c187
-rw-r--r--drivers/gpu/drm/i915/intel_lrc.h41
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c19
-rw-r--r--drivers/gpu/drm/i915/intel_overlay.c2
-rw-r--r--drivers/gpu/drm/i915/intel_panel.c16
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c262
-rw-r--r--drivers/gpu/drm/i915/intel_psr.c34
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c22
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.h14
-rw-r--r--drivers/gpu/drm/i915/intel_runtime_pm.c15
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c31
-rw-r--r--drivers/gpu/drm/i915/intel_sideband.c4
-rw-r--r--drivers/gpu/drm/i915/intel_sprite.c62
-rw-r--r--drivers/gpu/drm/i915/intel_tv.c13
-rw-r--r--drivers/gpu/drm/i915/intel_uncore.c1126
48 files changed, 3177 insertions, 2681 deletions
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 4e39ab34eb1c..74acca9bcd9d 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -11,6 +11,8 @@ config DRM_I915
11 select SHMEM 11 select SHMEM
12 select TMPFS 12 select TMPFS
13 select DRM_KMS_HELPER 13 select DRM_KMS_HELPER
14 select DRM_PANEL
15 select DRM_MIPI_DSI
14 # i915 depends on ACPI_VIDEO when ACPI is enabled 16 # i915 depends on ACPI_VIDEO when ACPI is enabled
15 # but for select to work, need to select ACPI_VIDEO's dependencies, ick 17 # but for select to work, need to select ACPI_VIDEO's dependencies, ick
16 select BACKLIGHT_LCD_SUPPORT if ACPI 18 select BACKLIGHT_LCD_SUPPORT if ACPI
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 16e3dc350274..f01922591679 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -66,12 +66,12 @@ i915-y += dvo_ch7017.o \
66 dvo_ns2501.o \ 66 dvo_ns2501.o \
67 dvo_sil164.o \ 67 dvo_sil164.o \
68 dvo_tfp410.o \ 68 dvo_tfp410.o \
69 intel_atomic.o \
69 intel_atomic_plane.o \ 70 intel_atomic_plane.o \
70 intel_crt.o \ 71 intel_crt.o \
71 intel_ddi.o \ 72 intel_ddi.o \
72 intel_dp.o \ 73 intel_dp.o \
73 intel_dp_mst.o \ 74 intel_dp_mst.o \
74 intel_dsi_cmd.o \
75 intel_dsi.o \ 75 intel_dsi.o \
76 intel_dsi_pll.o \ 76 intel_dsi_pll.o \
77 intel_dsi_panel_vbt.o \ 77 intel_dsi_panel_vbt.o \
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 0d11cbe9f80c..211d4949a675 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -123,7 +123,7 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
123 struct i915_vma *vma; 123 struct i915_vma *vma;
124 int pin_count = 0; 124 int pin_count = 0;
125 125
126 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s", 126 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s",
127 &obj->base, 127 &obj->base,
128 get_pin_flag(obj), 128 get_pin_flag(obj),
129 get_tiling_flag(obj), 129 get_tiling_flag(obj),
@@ -569,7 +569,7 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data)
569 struct intel_engine_cs *ring = 569 struct intel_engine_cs *ring =
570 i915_gem_request_get_ring(work->flip_queued_req); 570 i915_gem_request_get_ring(work->flip_queued_req);
571 571
572 seq_printf(m, "Flip queued on %s at seqno %u, next seqno %u [current breadcrumb %u], completed? %d\n", 572 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
573 ring->name, 573 ring->name,
574 i915_gem_request_get_seqno(work->flip_queued_req), 574 i915_gem_request_get_seqno(work->flip_queued_req),
575 dev_priv->next_seqno, 575 dev_priv->next_seqno,
@@ -658,7 +658,7 @@ static int i915_gem_request_info(struct seq_file *m, void *data)
658 list_for_each_entry(gem_request, 658 list_for_each_entry(gem_request,
659 &ring->request_list, 659 &ring->request_list,
660 list) { 660 list) {
661 seq_printf(m, " %d @ %d\n", 661 seq_printf(m, " %x @ %d\n",
662 gem_request->seqno, 662 gem_request->seqno,
663 (int) (jiffies - gem_request->emitted_jiffies)); 663 (int) (jiffies - gem_request->emitted_jiffies));
664 } 664 }
@@ -676,7 +676,7 @@ static void i915_ring_seqno_info(struct seq_file *m,
676 struct intel_engine_cs *ring) 676 struct intel_engine_cs *ring)
677{ 677{
678 if (ring->get_seqno) { 678 if (ring->get_seqno) {
679 seq_printf(m, "Current sequence (%s): %u\n", 679 seq_printf(m, "Current sequence (%s): %x\n",
680 ring->name, ring->get_seqno(ring, false)); 680 ring->name, ring->get_seqno(ring, false));
681 } 681 }
682} 682}
@@ -1105,7 +1105,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
1105 if (ret) 1105 if (ret)
1106 goto out; 1106 goto out;
1107 1107
1108 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); 1108 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1109 1109
1110 reqf = I915_READ(GEN6_RPNSWREQ); 1110 reqf = I915_READ(GEN6_RPNSWREQ);
1111 reqf &= ~GEN6_TURBO_DISABLE; 1111 reqf &= ~GEN6_TURBO_DISABLE;
@@ -1113,7 +1113,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
1113 reqf >>= 24; 1113 reqf >>= 24;
1114 else 1114 else
1115 reqf >>= 25; 1115 reqf >>= 25;
1116 reqf *= GT_FREQUENCY_MULTIPLIER; 1116 reqf = intel_gpu_freq(dev_priv, reqf);
1117 1117
1118 rpmodectl = I915_READ(GEN6_RP_CONTROL); 1118 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1119 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD); 1119 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
@@ -1130,9 +1130,9 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
1130 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; 1130 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1131 else 1131 else
1132 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; 1132 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1133 cagf *= GT_FREQUENCY_MULTIPLIER; 1133 cagf = intel_gpu_freq(dev_priv, cagf);
1134 1134
1135 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); 1135 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1136 mutex_unlock(&dev->struct_mutex); 1136 mutex_unlock(&dev->struct_mutex);
1137 1137
1138 if (IS_GEN6(dev) || IS_GEN7(dev)) { 1138 if (IS_GEN6(dev) || IS_GEN7(dev)) {
@@ -1178,18 +1178,18 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
1178 1178
1179 max_freq = (rp_state_cap & 0xff0000) >> 16; 1179 max_freq = (rp_state_cap & 0xff0000) >> 16;
1180 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", 1180 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1181 max_freq * GT_FREQUENCY_MULTIPLIER); 1181 intel_gpu_freq(dev_priv, max_freq));
1182 1182
1183 max_freq = (rp_state_cap & 0xff00) >> 8; 1183 max_freq = (rp_state_cap & 0xff00) >> 8;
1184 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", 1184 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1185 max_freq * GT_FREQUENCY_MULTIPLIER); 1185 intel_gpu_freq(dev_priv, max_freq));
1186 1186
1187 max_freq = rp_state_cap & 0xff; 1187 max_freq = rp_state_cap & 0xff;
1188 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", 1188 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1189 max_freq * GT_FREQUENCY_MULTIPLIER); 1189 intel_gpu_freq(dev_priv, max_freq));
1190 1190
1191 seq_printf(m, "Max overclocked frequency: %dMHz\n", 1191 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1192 dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER); 1192 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1193 } else if (IS_VALLEYVIEW(dev)) { 1193 } else if (IS_VALLEYVIEW(dev)) {
1194 u32 freq_sts; 1194 u32 freq_sts;
1195 1195
@@ -1199,16 +1199,17 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
1199 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); 1199 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1200 1200
1201 seq_printf(m, "max GPU freq: %d MHz\n", 1201 seq_printf(m, "max GPU freq: %d MHz\n",
1202 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq)); 1202 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1203 1203
1204 seq_printf(m, "min GPU freq: %d MHz\n", 1204 seq_printf(m, "min GPU freq: %d MHz\n",
1205 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq)); 1205 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1206 1206
1207 seq_printf(m, "efficient (RPe) frequency: %d MHz\n", 1207 seq_printf(m,
1208 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); 1208 "efficient (RPe) frequency: %d MHz\n",
1209 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1209 1210
1210 seq_printf(m, "current GPU freq: %d MHz\n", 1211 seq_printf(m, "current GPU freq: %d MHz\n",
1211 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff)); 1212 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1212 mutex_unlock(&dev_priv->rps.hw_lock); 1213 mutex_unlock(&dev_priv->rps.hw_lock);
1213 } else { 1214 } else {
1214 seq_puts(m, "no P-state info available\n"); 1215 seq_puts(m, "no P-state info available\n");
@@ -1219,6 +1220,41 @@ out:
1219 return ret; 1220 return ret;
1220} 1221}
1221 1222
1223static int i915_hangcheck_info(struct seq_file *m, void *unused)
1224{
1225 struct drm_info_node *node = m->private;
1226 struct drm_i915_private *dev_priv = to_i915(node->minor->dev);
1227 struct intel_engine_cs *ring;
1228 int i;
1229
1230 if (!i915.enable_hangcheck) {
1231 seq_printf(m, "Hangcheck disabled\n");
1232 return 0;
1233 }
1234
1235 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1236 seq_printf(m, "Hangcheck active, fires in %dms\n",
1237 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1238 jiffies));
1239 } else
1240 seq_printf(m, "Hangcheck inactive\n");
1241
1242 for_each_ring(ring, dev_priv, i) {
1243 seq_printf(m, "%s:\n", ring->name);
1244 seq_printf(m, "\tseqno = %x [current %x]\n",
1245 ring->hangcheck.seqno, ring->get_seqno(ring, false));
1246 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1247 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1248 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1249 (long long)ring->hangcheck.acthd,
1250 (long long)intel_ring_get_active_head(ring));
1251 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1252 (long long)ring->hangcheck.max_acthd);
1253 }
1254
1255 return 0;
1256}
1257
1222static int ironlake_drpc_info(struct seq_file *m) 1258static int ironlake_drpc_info(struct seq_file *m)
1223{ 1259{
1224 struct drm_info_node *node = m->private; 1260 struct drm_info_node *node = m->private;
@@ -1288,14 +1324,31 @@ static int ironlake_drpc_info(struct seq_file *m)
1288 return 0; 1324 return 0;
1289} 1325}
1290 1326
1291static int vlv_drpc_info(struct seq_file *m) 1327static int i915_forcewake_domains(struct seq_file *m, void *data)
1292{ 1328{
1329 struct drm_info_node *node = m->private;
1330 struct drm_device *dev = node->minor->dev;
1331 struct drm_i915_private *dev_priv = dev->dev_private;
1332 struct intel_uncore_forcewake_domain *fw_domain;
1333 int i;
1334
1335 spin_lock_irq(&dev_priv->uncore.lock);
1336 for_each_fw_domain(fw_domain, dev_priv, i) {
1337 seq_printf(m, "%s.wake_count = %u\n",
1338 intel_uncore_forcewake_domain_to_str(i),
1339 fw_domain->wake_count);
1340 }
1341 spin_unlock_irq(&dev_priv->uncore.lock);
1342
1343 return 0;
1344}
1293 1345
1346static int vlv_drpc_info(struct seq_file *m)
1347{
1294 struct drm_info_node *node = m->private; 1348 struct drm_info_node *node = m->private;
1295 struct drm_device *dev = node->minor->dev; 1349 struct drm_device *dev = node->minor->dev;
1296 struct drm_i915_private *dev_priv = dev->dev_private; 1350 struct drm_i915_private *dev_priv = dev->dev_private;
1297 u32 rpmodectl1, rcctl1, pw_status; 1351 u32 rpmodectl1, rcctl1, pw_status;
1298 unsigned fw_rendercount = 0, fw_mediacount = 0;
1299 1352
1300 intel_runtime_pm_get(dev_priv); 1353 intel_runtime_pm_get(dev_priv);
1301 1354
@@ -1327,22 +1380,11 @@ static int vlv_drpc_info(struct seq_file *m)
1327 seq_printf(m, "Media RC6 residency since boot: %u\n", 1380 seq_printf(m, "Media RC6 residency since boot: %u\n",
1328 I915_READ(VLV_GT_MEDIA_RC6)); 1381 I915_READ(VLV_GT_MEDIA_RC6));
1329 1382
1330 spin_lock_irq(&dev_priv->uncore.lock); 1383 return i915_forcewake_domains(m, NULL);
1331 fw_rendercount = dev_priv->uncore.fw_rendercount;
1332 fw_mediacount = dev_priv->uncore.fw_mediacount;
1333 spin_unlock_irq(&dev_priv->uncore.lock);
1334
1335 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1336 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1337
1338
1339 return 0;
1340} 1384}
1341 1385
1342
1343static int gen6_drpc_info(struct seq_file *m) 1386static int gen6_drpc_info(struct seq_file *m)
1344{ 1387{
1345
1346 struct drm_info_node *node = m->private; 1388 struct drm_info_node *node = m->private;
1347 struct drm_device *dev = node->minor->dev; 1389 struct drm_device *dev = node->minor->dev;
1348 struct drm_i915_private *dev_priv = dev->dev_private; 1390 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1356,7 +1398,7 @@ static int gen6_drpc_info(struct seq_file *m)
1356 intel_runtime_pm_get(dev_priv); 1398 intel_runtime_pm_get(dev_priv);
1357 1399
1358 spin_lock_irq(&dev_priv->uncore.lock); 1400 spin_lock_irq(&dev_priv->uncore.lock);
1359 forcewake_count = dev_priv->uncore.forcewake_count; 1401 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1360 spin_unlock_irq(&dev_priv->uncore.lock); 1402 spin_unlock_irq(&dev_priv->uncore.lock);
1361 1403
1362 if (forcewake_count) { 1404 if (forcewake_count) {
@@ -1671,7 +1713,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
1671 GEN6_PCODE_READ_MIN_FREQ_TABLE, 1713 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1672 &ia_freq); 1714 &ia_freq);
1673 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", 1715 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1674 gpu_freq * GT_FREQUENCY_MULTIPLIER, 1716 intel_gpu_freq(dev_priv, gpu_freq),
1675 ((ia_freq >> 0) & 0xff) * 100, 1717 ((ia_freq >> 0) & 0xff) * 100,
1676 ((ia_freq >> 8) & 0xff) * 100); 1718 ((ia_freq >> 8) & 0xff) * 100);
1677 } 1719 }
@@ -1928,7 +1970,7 @@ static int i915_execlists(struct seq_file *m, void *data)
1928 intel_runtime_pm_get(dev_priv); 1970 intel_runtime_pm_get(dev_priv);
1929 1971
1930 for_each_ring(ring, dev_priv, ring_id) { 1972 for_each_ring(ring, dev_priv, ring_id) {
1931 struct intel_ctx_submit_request *head_req = NULL; 1973 struct drm_i915_gem_request *head_req = NULL;
1932 int count = 0; 1974 int count = 0;
1933 unsigned long flags; 1975 unsigned long flags;
1934 1976
@@ -1961,7 +2003,7 @@ static int i915_execlists(struct seq_file *m, void *data)
1961 list_for_each(cursor, &ring->execlist_queue) 2003 list_for_each(cursor, &ring->execlist_queue)
1962 count++; 2004 count++;
1963 head_req = list_first_entry_or_null(&ring->execlist_queue, 2005 head_req = list_first_entry_or_null(&ring->execlist_queue,
1964 struct intel_ctx_submit_request, execlist_link); 2006 struct drm_i915_gem_request, execlist_link);
1965 spin_unlock_irqrestore(&ring->execlist_lock, flags); 2007 spin_unlock_irqrestore(&ring->execlist_lock, flags);
1966 2008
1967 seq_printf(m, "\t%d requests in queue\n", count); 2009 seq_printf(m, "\t%d requests in queue\n", count);
@@ -1984,30 +2026,6 @@ static int i915_execlists(struct seq_file *m, void *data)
1984 return 0; 2026 return 0;
1985} 2027}
1986 2028
1987static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1988{
1989 struct drm_info_node *node = m->private;
1990 struct drm_device *dev = node->minor->dev;
1991 struct drm_i915_private *dev_priv = dev->dev_private;
1992 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
1993
1994 spin_lock_irq(&dev_priv->uncore.lock);
1995 if (IS_VALLEYVIEW(dev)) {
1996 fw_rendercount = dev_priv->uncore.fw_rendercount;
1997 fw_mediacount = dev_priv->uncore.fw_mediacount;
1998 } else
1999 forcewake_count = dev_priv->uncore.forcewake_count;
2000 spin_unlock_irq(&dev_priv->uncore.lock);
2001
2002 if (IS_VALLEYVIEW(dev)) {
2003 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
2004 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
2005 } else
2006 seq_printf(m, "forcewake count = %u\n", forcewake_count);
2007
2008 return 0;
2009}
2010
2011static const char *swizzle_string(unsigned swizzle) 2029static const char *swizzle_string(unsigned swizzle)
2012{ 2030{
2013 switch (swizzle) { 2031 switch (swizzle) {
@@ -2400,6 +2418,14 @@ static const char *power_domain_str(enum intel_display_power_domain domain)
2400 return "AUDIO"; 2418 return "AUDIO";
2401 case POWER_DOMAIN_PLLS: 2419 case POWER_DOMAIN_PLLS:
2402 return "PLLS"; 2420 return "PLLS";
2421 case POWER_DOMAIN_AUX_A:
2422 return "AUX_A";
2423 case POWER_DOMAIN_AUX_B:
2424 return "AUX_B";
2425 case POWER_DOMAIN_AUX_C:
2426 return "AUX_C";
2427 case POWER_DOMAIN_AUX_D:
2428 return "AUX_D";
2403 case POWER_DOMAIN_INIT: 2429 case POWER_DOMAIN_INIT:
2404 return "INIT"; 2430 return "INIT";
2405 default: 2431 default:
@@ -2628,7 +2654,8 @@ static int i915_display_info(struct seq_file *m, void *unused)
2628 2654
2629 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n", 2655 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2630 crtc->base.base.id, pipe_name(crtc->pipe), 2656 crtc->base.base.id, pipe_name(crtc->pipe),
2631 yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h); 2657 yesno(crtc->active), crtc->config->pipe_src_w,
2658 crtc->config->pipe_src_h);
2632 if (crtc->active) { 2659 if (crtc->active) {
2633 intel_crtc_info(m, crtc); 2660 intel_crtc_info(m, crtc);
2634 2661
@@ -3362,9 +3389,9 @@ static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3362 * relevant on hsw with pipe A when using the always-on power well 3389 * relevant on hsw with pipe A when using the always-on power well
3363 * routing. 3390 * routing.
3364 */ 3391 */
3365 if (crtc->config.cpu_transcoder == TRANSCODER_EDP && 3392 if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
3366 !crtc->config.pch_pfit.enabled) { 3393 !crtc->config->pch_pfit.enabled) {
3367 crtc->config.pch_pfit.force_thru = true; 3394 crtc->config->pch_pfit.force_thru = true;
3368 3395
3369 intel_display_power_get(dev_priv, 3396 intel_display_power_get(dev_priv,
3370 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A)); 3397 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
@@ -3388,8 +3415,8 @@ static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3388 * relevant on hsw with pipe A when using the always-on power well 3415 * relevant on hsw with pipe A when using the always-on power well
3389 * routing. 3416 * routing.
3390 */ 3417 */
3391 if (crtc->config.pch_pfit.force_thru) { 3418 if (crtc->config->pch_pfit.force_thru) {
3392 crtc->config.pch_pfit.force_thru = false; 3419 crtc->config->pch_pfit.force_thru = false;
3393 3420
3394 dev_priv->display.crtc_disable(&crtc->base); 3421 dev_priv->display.crtc_disable(&crtc->base);
3395 dev_priv->display.crtc_enable(&crtc->base); 3422 dev_priv->display.crtc_enable(&crtc->base);
@@ -3942,6 +3969,17 @@ i915_wedged_set(void *data, u64 val)
3942 struct drm_device *dev = data; 3969 struct drm_device *dev = data;
3943 struct drm_i915_private *dev_priv = dev->dev_private; 3970 struct drm_i915_private *dev_priv = dev->dev_private;
3944 3971
3972 /*
3973 * There is no safeguard against this debugfs entry colliding
3974 * with the hangcheck calling same i915_handle_error() in
3975 * parallel, causing an explosion. For now we assume that the
3976 * test harness is responsible enough not to inject gpu hangs
3977 * while it is writing to 'i915_wedged'
3978 */
3979
3980 if (i915_reset_in_progress(&dev_priv->gpu_error))
3981 return -EAGAIN;
3982
3945 intel_runtime_pm_get(dev_priv); 3983 intel_runtime_pm_get(dev_priv);
3946 3984
3947 i915_handle_error(dev, val, 3985 i915_handle_error(dev, val,
@@ -4128,10 +4166,7 @@ i915_max_freq_get(void *data, u64 *val)
4128 if (ret) 4166 if (ret)
4129 return ret; 4167 return ret;
4130 4168
4131 if (IS_VALLEYVIEW(dev)) 4169 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4132 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4133 else
4134 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4135 mutex_unlock(&dev_priv->rps.hw_lock); 4170 mutex_unlock(&dev_priv->rps.hw_lock);
4136 4171
4137 return 0; 4172 return 0;
@@ -4160,12 +4195,12 @@ i915_max_freq_set(void *data, u64 val)
4160 * Turbo will still be enabled, but won't go above the set value. 4195 * Turbo will still be enabled, but won't go above the set value.
4161 */ 4196 */
4162 if (IS_VALLEYVIEW(dev)) { 4197 if (IS_VALLEYVIEW(dev)) {
4163 val = vlv_freq_opcode(dev_priv, val); 4198 val = intel_freq_opcode(dev_priv, val);
4164 4199
4165 hw_max = dev_priv->rps.max_freq; 4200 hw_max = dev_priv->rps.max_freq;
4166 hw_min = dev_priv->rps.min_freq; 4201 hw_min = dev_priv->rps.min_freq;
4167 } else { 4202 } else {
4168 do_div(val, GT_FREQUENCY_MULTIPLIER); 4203 val = intel_freq_opcode(dev_priv, val);
4169 4204
4170 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 4205 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4171 hw_max = dev_priv->rps.max_freq; 4206 hw_max = dev_priv->rps.max_freq;
@@ -4209,10 +4244,7 @@ i915_min_freq_get(void *data, u64 *val)
4209 if (ret) 4244 if (ret)
4210 return ret; 4245 return ret;
4211 4246
4212 if (IS_VALLEYVIEW(dev)) 4247 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4213 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4214 else
4215 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4216 mutex_unlock(&dev_priv->rps.hw_lock); 4248 mutex_unlock(&dev_priv->rps.hw_lock);
4217 4249
4218 return 0; 4250 return 0;
@@ -4241,12 +4273,12 @@ i915_min_freq_set(void *data, u64 val)
4241 * Turbo will still be enabled, but won't go below the set value. 4273 * Turbo will still be enabled, but won't go below the set value.
4242 */ 4274 */
4243 if (IS_VALLEYVIEW(dev)) { 4275 if (IS_VALLEYVIEW(dev)) {
4244 val = vlv_freq_opcode(dev_priv, val); 4276 val = intel_freq_opcode(dev_priv, val);
4245 4277
4246 hw_max = dev_priv->rps.max_freq; 4278 hw_max = dev_priv->rps.max_freq;
4247 hw_min = dev_priv->rps.min_freq; 4279 hw_min = dev_priv->rps.min_freq;
4248 } else { 4280 } else {
4249 do_div(val, GT_FREQUENCY_MULTIPLIER); 4281 val = intel_freq_opcode(dev_priv, val);
4250 4282
4251 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 4283 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4252 hw_max = dev_priv->rps.max_freq; 4284 hw_max = dev_priv->rps.max_freq;
@@ -4338,7 +4370,8 @@ static int i915_forcewake_open(struct inode *inode, struct file *file)
4338 if (INTEL_INFO(dev)->gen < 6) 4370 if (INTEL_INFO(dev)->gen < 6)
4339 return 0; 4371 return 0;
4340 4372
4341 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); 4373 intel_runtime_pm_get(dev_priv);
4374 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4342 4375
4343 return 0; 4376 return 0;
4344} 4377}
@@ -4351,7 +4384,8 @@ static int i915_forcewake_release(struct inode *inode, struct file *file)
4351 if (INTEL_INFO(dev)->gen < 6) 4384 if (INTEL_INFO(dev)->gen < 6)
4352 return 0; 4385 return 0;
4353 4386
4354 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); 4387 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4388 intel_runtime_pm_put(dev_priv);
4355 4389
4356 return 0; 4390 return 0;
4357} 4391}
@@ -4414,6 +4448,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
4414 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS}, 4448 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
4415 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0}, 4449 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4416 {"i915_frequency_info", i915_frequency_info, 0}, 4450 {"i915_frequency_info", i915_frequency_info, 0},
4451 {"i915_hangcheck_info", i915_hangcheck_info, 0},
4417 {"i915_drpc_info", i915_drpc_info, 0}, 4452 {"i915_drpc_info", i915_drpc_info, 0},
4418 {"i915_emon_status", i915_emon_status, 0}, 4453 {"i915_emon_status", i915_emon_status, 0},
4419 {"i915_ring_freq_table", i915_ring_freq_table, 0}, 4454 {"i915_ring_freq_table", i915_ring_freq_table, 0},
@@ -4425,7 +4460,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
4425 {"i915_context_status", i915_context_status, 0}, 4460 {"i915_context_status", i915_context_status, 0},
4426 {"i915_dump_lrc", i915_dump_lrc, 0}, 4461 {"i915_dump_lrc", i915_dump_lrc, 0},
4427 {"i915_execlists", i915_execlists, 0}, 4462 {"i915_execlists", i915_execlists, 0},
4428 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, 4463 {"i915_forcewake_domains", i915_forcewake_domains, 0},
4429 {"i915_swizzle_info", i915_swizzle_info, 0}, 4464 {"i915_swizzle_info", i915_swizzle_info, 0},
4430 {"i915_ppgtt_info", i915_ppgtt_info, 0}, 4465 {"i915_ppgtt_info", i915_ppgtt_info, 0},
4431 {"i915_llc", i915_llc, 0}, 4466 {"i915_llc", i915_llc, 0},
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 2447de36de44..1a46787129e7 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -92,6 +92,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
92 case I915_PARAM_HAS_VEBOX: 92 case I915_PARAM_HAS_VEBOX:
93 value = intel_ring_initialized(&dev_priv->ring[VECS]); 93 value = intel_ring_initialized(&dev_priv->ring[VECS]);
94 break; 94 break;
95 case I915_PARAM_HAS_BSD2:
96 value = intel_ring_initialized(&dev_priv->ring[VCS2]);
97 break;
95 case I915_PARAM_HAS_RELAXED_FENCING: 98 case I915_PARAM_HAS_RELAXED_FENCING:
96 value = 1; 99 value = 1;
97 break; 100 break;
@@ -601,6 +604,17 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
601 info->num_pipes = 0; 604 info->num_pipes = 0;
602 } 605 }
603 } 606 }
607
608 if (IS_CHERRYVIEW(dev)) {
609 u32 fuse, mask_eu;
610
611 fuse = I915_READ(CHV_FUSE_GT);
612 mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
613 CHV_FGT_EU_DIS_SS0_R1_MASK |
614 CHV_FGT_EU_DIS_SS1_R0_MASK |
615 CHV_FGT_EU_DIS_SS1_R1_MASK);
616 info->eu_total = 16 - hweight32(mask_eu);
617 }
604} 618}
605 619
606/** 620/**
@@ -776,6 +790,14 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
776 goto out_freewq; 790 goto out_freewq;
777 } 791 }
778 792
793 dev_priv->gpu_error.hangcheck_wq =
794 alloc_ordered_workqueue("i915-hangcheck", 0);
795 if (dev_priv->gpu_error.hangcheck_wq == NULL) {
796 DRM_ERROR("Failed to create our hangcheck workqueue.\n");
797 ret = -ENOMEM;
798 goto out_freedpwq;
799 }
800
779 intel_irq_init(dev_priv); 801 intel_irq_init(dev_priv);
780 intel_uncore_sanitize(dev); 802 intel_uncore_sanitize(dev);
781 803
@@ -850,6 +872,8 @@ out_gem_unload:
850 intel_teardown_gmbus(dev); 872 intel_teardown_gmbus(dev);
851 intel_teardown_mchbar(dev); 873 intel_teardown_mchbar(dev);
852 pm_qos_remove_request(&dev_priv->pm_qos); 874 pm_qos_remove_request(&dev_priv->pm_qos);
875 destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
876out_freedpwq:
853 destroy_workqueue(dev_priv->dp_wq); 877 destroy_workqueue(dev_priv->dp_wq);
854out_freewq: 878out_freewq:
855 destroy_workqueue(dev_priv->wq); 879 destroy_workqueue(dev_priv->wq);
@@ -920,8 +944,7 @@ int i915_driver_unload(struct drm_device *dev)
920 } 944 }
921 945
922 /* Free error state after interrupts are fully disabled. */ 946 /* Free error state after interrupts are fully disabled. */
923 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); 947 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
924 cancel_work_sync(&dev_priv->gpu_error.work);
925 i915_destroy_error_state(dev); 948 i915_destroy_error_state(dev);
926 949
927 if (dev->pdev->msi_enabled) 950 if (dev->pdev->msi_enabled)
@@ -946,6 +969,7 @@ int i915_driver_unload(struct drm_device *dev)
946 969
947 destroy_workqueue(dev_priv->dp_wq); 970 destroy_workqueue(dev_priv->dp_wq);
948 destroy_workqueue(dev_priv->wq); 971 destroy_workqueue(dev_priv->wq);
972 destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
949 pm_qos_remove_request(&dev_priv->pm_qos); 973 pm_qos_remove_request(&dev_priv->pm_qos);
950 974
951 i915_global_gtt_cleanup(dev); 975 i915_global_gtt_cleanup(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 308774f42079..5f50e7033ef7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1365,8 +1365,6 @@ static int intel_runtime_suspend(struct device *device)
1365 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) 1365 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1366 return -ENODEV; 1366 return -ENODEV;
1367 1367
1368 assert_force_wake_inactive(dev_priv);
1369
1370 DRM_DEBUG_KMS("Suspending device\n"); 1368 DRM_DEBUG_KMS("Suspending device\n");
1371 1369
1372 /* 1370 /*
@@ -1404,7 +1402,8 @@ static int intel_runtime_suspend(struct device *device)
1404 return ret; 1402 return ret;
1405 } 1403 }
1406 1404
1407 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); 1405 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1406 intel_uncore_forcewake_reset(dev, false);
1408 dev_priv->pm.suspended = true; 1407 dev_priv->pm.suspended = true;
1409 1408
1410 /* 1409 /*
@@ -1432,6 +1431,8 @@ static int intel_runtime_suspend(struct device *device)
1432 intel_opregion_notify_adapter(dev, PCI_D3hot); 1431 intel_opregion_notify_adapter(dev, PCI_D3hot);
1433 } 1432 }
1434 1433
1434 assert_forcewakes_inactive(dev_priv);
1435
1435 DRM_DEBUG_KMS("Device suspended\n"); 1436 DRM_DEBUG_KMS("Device suspended\n");
1436 return 0; 1437 return 0;
1437} 1438}
@@ -1642,6 +1643,14 @@ static int __init i915_init(void)
1642#endif 1643#endif
1643 } 1644 }
1644 1645
1646 /*
1647 * FIXME: Note that we're lying to the DRM core here so that we can get access
1648 * to the atomic ioctl and the atomic properties. Only plane operations on
1649 * a single CRTC will actually work.
1650 */
1651 if (i915.nuclear_pageflip)
1652 driver.driver_features |= DRIVER_ATOMIC;
1653
1645 return drm_pci_init(&driver, &i915_pci_driver); 1654 return drm_pci_init(&driver, &i915_pci_driver);
1646} 1655}
1647 1656
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ede48628bf85..d8b4d0a887f8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -55,7 +55,7 @@
55 55
56#define DRIVER_NAME "i915" 56#define DRIVER_NAME "i915"
57#define DRIVER_DESC "Intel Graphics" 57#define DRIVER_DESC "Intel Graphics"
58#define DRIVER_DATE "20150117" 58#define DRIVER_DATE "20150130"
59 59
60#undef WARN_ON 60#undef WARN_ON
61/* Many gcc seem to no see through this and fall over :( */ 61/* Many gcc seem to no see through this and fall over :( */
@@ -184,6 +184,10 @@ enum intel_display_power_domain {
184 POWER_DOMAIN_VGA, 184 POWER_DOMAIN_VGA,
185 POWER_DOMAIN_AUDIO, 185 POWER_DOMAIN_AUDIO,
186 POWER_DOMAIN_PLLS, 186 POWER_DOMAIN_PLLS,
187 POWER_DOMAIN_AUX_A,
188 POWER_DOMAIN_AUX_B,
189 POWER_DOMAIN_AUX_C,
190 POWER_DOMAIN_AUX_D,
187 POWER_DOMAIN_INIT, 191 POWER_DOMAIN_INIT,
188 192
189 POWER_DOMAIN_NUM, 193 POWER_DOMAIN_NUM,
@@ -499,8 +503,8 @@ struct drm_i915_error_state {
499 503
500struct intel_connector; 504struct intel_connector;
501struct intel_encoder; 505struct intel_encoder;
502struct intel_crtc_config; 506struct intel_crtc_state;
503struct intel_plane_config; 507struct intel_initial_plane_config;
504struct intel_crtc; 508struct intel_crtc;
505struct intel_limit; 509struct intel_limit;
506struct dpll; 510struct dpll;
@@ -538,10 +542,11 @@ struct drm_i915_display_funcs {
538 /* Returns the active state of the crtc, and if the crtc is active, 542 /* Returns the active state of the crtc, and if the crtc is active,
539 * fills out the pipe-config with the hw state. */ 543 * fills out the pipe-config with the hw state. */
540 bool (*get_pipe_config)(struct intel_crtc *, 544 bool (*get_pipe_config)(struct intel_crtc *,
541 struct intel_crtc_config *); 545 struct intel_crtc_state *);
542 void (*get_plane_config)(struct intel_crtc *, 546 void (*get_initial_plane_config)(struct intel_crtc *,
543 struct intel_plane_config *); 547 struct intel_initial_plane_config *);
544 int (*crtc_compute_clock)(struct intel_crtc *crtc); 548 int (*crtc_compute_clock)(struct intel_crtc *crtc,
549 struct intel_crtc_state *crtc_state);
545 void (*crtc_enable)(struct drm_crtc *crtc); 550 void (*crtc_enable)(struct drm_crtc *crtc);
546 void (*crtc_disable)(struct drm_crtc *crtc); 551 void (*crtc_disable)(struct drm_crtc *crtc);
547 void (*off)(struct drm_crtc *crtc); 552 void (*off)(struct drm_crtc *crtc);
@@ -574,11 +579,28 @@ struct drm_i915_display_funcs {
574 void (*enable_backlight)(struct intel_connector *connector); 579 void (*enable_backlight)(struct intel_connector *connector);
575}; 580};
576 581
582enum forcewake_domain_id {
583 FW_DOMAIN_ID_RENDER = 0,
584 FW_DOMAIN_ID_BLITTER,
585 FW_DOMAIN_ID_MEDIA,
586
587 FW_DOMAIN_ID_COUNT
588};
589
590enum forcewake_domains {
591 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
592 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
593 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
594 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
595 FORCEWAKE_BLITTER |
596 FORCEWAKE_MEDIA)
597};
598
577struct intel_uncore_funcs { 599struct intel_uncore_funcs {
578 void (*force_wake_get)(struct drm_i915_private *dev_priv, 600 void (*force_wake_get)(struct drm_i915_private *dev_priv,
579 int fw_engine); 601 enum forcewake_domains domains);
580 void (*force_wake_put)(struct drm_i915_private *dev_priv, 602 void (*force_wake_put)(struct drm_i915_private *dev_priv,
581 int fw_engine); 603 enum forcewake_domains domains);
582 604
583 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 605 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
584 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 606 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
@@ -601,14 +623,31 @@ struct intel_uncore {
601 struct intel_uncore_funcs funcs; 623 struct intel_uncore_funcs funcs;
602 624
603 unsigned fifo_count; 625 unsigned fifo_count;
604 unsigned forcewake_count; 626 enum forcewake_domains fw_domains;
605 627
606 unsigned fw_rendercount; 628 struct intel_uncore_forcewake_domain {
607 unsigned fw_mediacount; 629 struct drm_i915_private *i915;
608 unsigned fw_blittercount; 630 enum forcewake_domain_id id;
609 631 unsigned wake_count;
610 struct timer_list force_wake_timer; 632 struct timer_list timer;
611}; 633 u32 reg_set;
634 u32 val_set;
635 u32 val_clear;
636 u32 reg_ack;
637 u32 reg_post;
638 u32 val_reset;
639 } fw_domain[FW_DOMAIN_ID_COUNT];
640};
641
642/* Iterate over initialised fw domains */
643#define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
644 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
645 (i__) < FW_DOMAIN_ID_COUNT; \
646 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
647 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
648
649#define for_each_fw_domain(domain__, dev_priv__, i__) \
650 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
612 651
613#define DEV_INFO_FOR_EACH_FLAG(func, sep) \ 652#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
614 func(is_mobile) sep \ 653 func(is_mobile) sep \
@@ -653,6 +692,7 @@ struct intel_device_info {
653 int trans_offsets[I915_MAX_TRANSCODERS]; 692 int trans_offsets[I915_MAX_TRANSCODERS];
654 int palette_offsets[I915_MAX_PIPES]; 693 int palette_offsets[I915_MAX_PIPES];
655 int cursor_offsets[I915_MAX_PIPES]; 694 int cursor_offsets[I915_MAX_PIPES];
695 unsigned int eu_total;
656}; 696};
657 697
658#undef DEFINE_FLAG 698#undef DEFINE_FLAG
@@ -725,7 +765,7 @@ struct intel_context {
725 struct { 765 struct {
726 struct drm_i915_gem_object *state; 766 struct drm_i915_gem_object *state;
727 struct intel_ringbuffer *ringbuf; 767 struct intel_ringbuffer *ringbuf;
728 int unpin_count; 768 int pin_count;
729 } engine[I915_NUM_RINGS]; 769 } engine[I915_NUM_RINGS];
730 770
731 struct list_head link; 771 struct list_head link;
@@ -776,11 +816,33 @@ struct i915_fbc {
776 } no_fbc_reason; 816 } no_fbc_reason;
777}; 817};
778 818
779struct i915_drrs { 819/**
780 struct intel_connector *connector; 820 * HIGH_RR is the highest eDP panel refresh rate read from EDID
821 * LOW_RR is the lowest eDP panel refresh rate found from EDID
822 * parsing for same resolution.
823 */
824enum drrs_refresh_rate_type {
825 DRRS_HIGH_RR,
826 DRRS_LOW_RR,
827 DRRS_MAX_RR, /* RR count */
828};
829
830enum drrs_support_type {
831 DRRS_NOT_SUPPORTED = 0,
832 STATIC_DRRS_SUPPORT = 1,
833 SEAMLESS_DRRS_SUPPORT = 2
781}; 834};
782 835
783struct intel_dp; 836struct intel_dp;
837struct i915_drrs {
838 struct mutex mutex;
839 struct delayed_work work;
840 struct intel_dp *dp;
841 unsigned busy_frontbuffer_bits;
842 enum drrs_refresh_rate_type refresh_rate_type;
843 enum drrs_support_type type;
844};
845
784struct i915_psr { 846struct i915_psr {
785 struct mutex lock; 847 struct mutex lock;
786 bool sink_support; 848 bool sink_support;
@@ -1283,14 +1345,13 @@ struct i915_gpu_error {
1283 /* Hang gpu twice in this window and your context gets banned */ 1345 /* Hang gpu twice in this window and your context gets banned */
1284#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) 1346#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1285 1347
1286 struct timer_list hangcheck_timer; 1348 struct workqueue_struct *hangcheck_wq;
1349 struct delayed_work hangcheck_work;
1287 1350
1288 /* For reset and error_state handling. */ 1351 /* For reset and error_state handling. */
1289 spinlock_t lock; 1352 spinlock_t lock;
1290 /* Protected by the above dev->gpu_error.lock. */ 1353 /* Protected by the above dev->gpu_error.lock. */
1291 struct drm_i915_error_state *first_error; 1354 struct drm_i915_error_state *first_error;
1292 struct work_struct work;
1293
1294 1355
1295 unsigned long missed_irq_rings; 1356 unsigned long missed_irq_rings;
1296 1357
@@ -1360,12 +1421,6 @@ struct ddi_vbt_port_info {
1360 uint8_t supports_dp:1; 1421 uint8_t supports_dp:1;
1361}; 1422};
1362 1423
1363enum drrs_support_type {
1364 DRRS_NOT_SUPPORTED = 0,
1365 STATIC_DRRS_SUPPORT = 1,
1366 SEAMLESS_DRRS_SUPPORT = 2
1367};
1368
1369enum psr_lines_to_wait { 1424enum psr_lines_to_wait {
1370 PSR_0_LINES_TO_WAIT = 0, 1425 PSR_0_LINES_TO_WAIT = 0,
1371 PSR_1_LINE_TO_WAIT, 1426 PSR_1_LINE_TO_WAIT,
@@ -1999,6 +2054,7 @@ struct drm_i915_gem_object {
1999 */ 2054 */
2000 unsigned long gt_ro:1; 2055 unsigned long gt_ro:1;
2001 unsigned int cache_level:3; 2056 unsigned int cache_level:3;
2057 unsigned int cache_dirty:1;
2002 2058
2003 unsigned int has_dma_mapping:1; 2059 unsigned int has_dma_mapping:1;
2004 2060
@@ -2071,7 +2127,14 @@ struct drm_i915_gem_request {
2071 /** Position in the ringbuffer of the start of the request */ 2127 /** Position in the ringbuffer of the start of the request */
2072 u32 head; 2128 u32 head;
2073 2129
2074 /** Position in the ringbuffer of the end of the request */ 2130 /**
2131 * Position in the ringbuffer of the start of the postfix.
2132 * This is required to calculate the maximum available ringbuffer
2133 * space without overwriting the postfix.
2134 */
2135 u32 postfix;
2136
2137 /** Position in the ringbuffer of the end of the whole request */
2075 u32 tail; 2138 u32 tail;
2076 2139
2077 /** Context related to this request */ 2140 /** Context related to this request */
@@ -2091,6 +2154,26 @@ struct drm_i915_gem_request {
2091 struct list_head client_list; 2154 struct list_head client_list;
2092 2155
2093 uint32_t uniq; 2156 uint32_t uniq;
2157
2158 /**
2159 * The ELSP only accepts two elements at a time, so we queue
2160 * context/tail pairs on a given queue (ring->execlist_queue) until the
2161 * hardware is available. The queue serves a double purpose: we also use
2162 * it to keep track of the up to 2 contexts currently in the hardware
2163 * (usually one in execution and the other queued up by the GPU): We
2164 * only remove elements from the head of the queue when the hardware
2165 * informs us that an element has been completed.
2166 *
2167 * All accesses to the queue are mediated by a spinlock
2168 * (ring->execlist_lock).
2169 */
2170
2171 /** Execlist link in the submission queue.*/
2172 struct list_head execlist_link;
2173
2174 /** Execlists no. of times this request has been sent to the ELSP */
2175 int elsp_submitted;
2176
2094}; 2177};
2095 2178
2096void i915_gem_request_free(struct kref *req_ref); 2179void i915_gem_request_free(struct kref *req_ref);
@@ -2372,7 +2455,8 @@ struct drm_i915_cmd_table {
2372#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) 2455#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2373#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) 2456#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2374#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ 2457#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2375 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 2458 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2459 IS_SKYLAKE(dev))
2376#define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ 2460#define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2377 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev)) 2461 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2378#define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) 2462#define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
@@ -2443,6 +2527,7 @@ struct i915_params {
2443 int use_mmio_flip; 2527 int use_mmio_flip;
2444 bool mmio_debug; 2528 bool mmio_debug;
2445 bool verbose_state_checks; 2529 bool verbose_state_checks;
2530 bool nuclear_pageflip;
2446}; 2531};
2447extern struct i915_params i915 __read_mostly; 2532extern struct i915_params i915 __read_mostly;
2448 2533
@@ -2487,6 +2572,12 @@ extern void intel_uncore_init(struct drm_device *dev);
2487extern void intel_uncore_check_errors(struct drm_device *dev); 2572extern void intel_uncore_check_errors(struct drm_device *dev);
2488extern void intel_uncore_fini(struct drm_device *dev); 2573extern void intel_uncore_fini(struct drm_device *dev);
2489extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); 2574extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2575const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2576void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2577 enum forcewake_domains domains);
2578void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2579 enum forcewake_domains domains);
2580void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2490 2581
2491void 2582void
2492i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, 2583i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
@@ -3118,20 +3209,12 @@ extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3118 struct drm_device *dev, 3209 struct drm_device *dev,
3119 struct intel_display_error_state *error); 3210 struct intel_display_error_state *error);
3120 3211
3121/* On SNB platform, before reading ring registers forcewake bit
3122 * must be set to prevent GT core from power down and stale values being
3123 * returned.
3124 */
3125void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
3126void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
3127void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
3128
3129int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); 3212int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3130int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); 3213int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3131 3214
3132/* intel_sideband.c */ 3215/* intel_sideband.c */
3133u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); 3216u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3134void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); 3217void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3135u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); 3218u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3136u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); 3219u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3137void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3220void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
@@ -3152,15 +3235,8 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3152u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); 3235u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3153void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 3236void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3154 3237
3155int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val); 3238int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3156int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val); 3239int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3157
3158#define FORCEWAKE_RENDER (1 << 0)
3159#define FORCEWAKE_MEDIA (1 << 1)
3160#define FORCEWAKE_BLITTER (1 << 2)
3161#define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA | \
3162 FORCEWAKE_BLITTER)
3163
3164 3240
3165#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) 3241#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3166#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) 3242#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6c403654e33a..36f1093e3c63 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -39,8 +39,7 @@
39#include <linux/dma-buf.h> 39#include <linux/dma-buf.h>
40 40
41static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); 41static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
42static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, 42static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
43 bool force);
44static __must_check int 43static __must_check int
45i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, 44i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
46 bool readonly); 45 bool readonly);
@@ -1516,7 +1515,7 @@ i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1516 1515
1517 /* Pinned buffers may be scanout, so flush the cache */ 1516 /* Pinned buffers may be scanout, so flush the cache */
1518 if (obj->pin_display) 1517 if (obj->pin_display)
1519 i915_gem_object_flush_cpu_write_domain(obj, true); 1518 i915_gem_object_flush_cpu_write_domain(obj);
1520 1519
1521 drm_gem_object_unreference(&obj->base); 1520 drm_gem_object_unreference(&obj->base);
1522unlock: 1521unlock:
@@ -2414,7 +2413,7 @@ int __i915_add_request(struct intel_engine_cs *ring,
2414 struct drm_i915_private *dev_priv = ring->dev->dev_private; 2413 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2415 struct drm_i915_gem_request *request; 2414 struct drm_i915_gem_request *request;
2416 struct intel_ringbuffer *ringbuf; 2415 struct intel_ringbuffer *ringbuf;
2417 u32 request_ring_position, request_start; 2416 u32 request_start;
2418 int ret; 2417 int ret;
2419 2418
2420 request = ring->outstanding_lazy_request; 2419 request = ring->outstanding_lazy_request;
@@ -2422,8 +2421,7 @@ int __i915_add_request(struct intel_engine_cs *ring,
2422 return -ENOMEM; 2421 return -ENOMEM;
2423 2422
2424 if (i915.enable_execlists) { 2423 if (i915.enable_execlists) {
2425 struct intel_context *ctx = request->ctx; 2424 ringbuf = request->ctx->engine[ring->id].ringbuf;
2426 ringbuf = ctx->engine[ring->id].ringbuf;
2427 } else 2425 } else
2428 ringbuf = ring->buffer; 2426 ringbuf = ring->buffer;
2429 2427
@@ -2436,7 +2434,7 @@ int __i915_add_request(struct intel_engine_cs *ring,
2436 * what. 2434 * what.
2437 */ 2435 */
2438 if (i915.enable_execlists) { 2436 if (i915.enable_execlists) {
2439 ret = logical_ring_flush_all_caches(ringbuf); 2437 ret = logical_ring_flush_all_caches(ringbuf, request->ctx);
2440 if (ret) 2438 if (ret)
2441 return ret; 2439 return ret;
2442 } else { 2440 } else {
@@ -2450,10 +2448,10 @@ int __i915_add_request(struct intel_engine_cs *ring,
2450 * GPU processing the request, we never over-estimate the 2448 * GPU processing the request, we never over-estimate the
2451 * position of the head. 2449 * position of the head.
2452 */ 2450 */
2453 request_ring_position = intel_ring_get_tail(ringbuf); 2451 request->postfix = intel_ring_get_tail(ringbuf);
2454 2452
2455 if (i915.enable_execlists) { 2453 if (i915.enable_execlists) {
2456 ret = ring->emit_request(ringbuf); 2454 ret = ring->emit_request(ringbuf, request);
2457 if (ret) 2455 if (ret)
2458 return ret; 2456 return ret;
2459 } else { 2457 } else {
@@ -2463,7 +2461,7 @@ int __i915_add_request(struct intel_engine_cs *ring,
2463 } 2461 }
2464 2462
2465 request->head = request_start; 2463 request->head = request_start;
2466 request->tail = request_ring_position; 2464 request->tail = intel_ring_get_tail(ringbuf);
2467 2465
2468 /* Whilst this request exists, batch_obj will be on the 2466 /* Whilst this request exists, batch_obj will be on the
2469 * active_list, and so will hold the active reference. Only when this 2467 * active_list, and so will hold the active reference. Only when this
@@ -2650,13 +2648,17 @@ static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2650 * pinned in place. 2648 * pinned in place.
2651 */ 2649 */
2652 while (!list_empty(&ring->execlist_queue)) { 2650 while (!list_empty(&ring->execlist_queue)) {
2653 struct intel_ctx_submit_request *submit_req; 2651 struct drm_i915_gem_request *submit_req;
2654 2652
2655 submit_req = list_first_entry(&ring->execlist_queue, 2653 submit_req = list_first_entry(&ring->execlist_queue,
2656 struct intel_ctx_submit_request, 2654 struct drm_i915_gem_request,
2657 execlist_link); 2655 execlist_link);
2658 list_del(&submit_req->execlist_link); 2656 list_del(&submit_req->execlist_link);
2659 intel_runtime_pm_put(dev_priv); 2657 intel_runtime_pm_put(dev_priv);
2658
2659 if (submit_req->ctx != ring->default_context)
2660 intel_lr_context_unpin(ring, submit_req->ctx);
2661
2660 i915_gem_context_unreference(submit_req->ctx); 2662 i915_gem_context_unreference(submit_req->ctx);
2661 kfree(submit_req); 2663 kfree(submit_req);
2662 } 2664 }
@@ -2783,7 +2785,7 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2783 * of tail of the request to update the last known position 2785 * of tail of the request to update the last known position
2784 * of the GPU head. 2786 * of the GPU head.
2785 */ 2787 */
2786 ringbuf->last_retired_head = request->tail; 2788 ringbuf->last_retired_head = request->postfix;
2787 2789
2788 i915_gem_free_request(request); 2790 i915_gem_free_request(request);
2789 } 2791 }
@@ -3634,11 +3636,14 @@ i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3634 * snooping behaviour occurs naturally as the result of our domain 3636 * snooping behaviour occurs naturally as the result of our domain
3635 * tracking. 3637 * tracking.
3636 */ 3638 */
3637 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) 3639 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3640 obj->cache_dirty = true;
3638 return false; 3641 return false;
3642 }
3639 3643
3640 trace_i915_gem_object_clflush(obj); 3644 trace_i915_gem_object_clflush(obj);
3641 drm_clflush_sg(obj->pages); 3645 drm_clflush_sg(obj->pages);
3646 obj->cache_dirty = false;
3642 3647
3643 return true; 3648 return true;
3644} 3649}
@@ -3674,15 +3679,14 @@ i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3674 3679
3675/** Flushes the CPU write domain for the object if it's dirty. */ 3680/** Flushes the CPU write domain for the object if it's dirty. */
3676static void 3681static void
3677i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, 3682i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3678 bool force)
3679{ 3683{
3680 uint32_t old_write_domain; 3684 uint32_t old_write_domain;
3681 3685
3682 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) 3686 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3683 return; 3687 return;
3684 3688
3685 if (i915_gem_clflush_object(obj, force)) 3689 if (i915_gem_clflush_object(obj, obj->pin_display))
3686 i915_gem_chipset_flush(obj->base.dev); 3690 i915_gem_chipset_flush(obj->base.dev);
3687 3691
3688 old_write_domain = obj->base.write_domain; 3692 old_write_domain = obj->base.write_domain;
@@ -3729,7 +3733,7 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3729 if (ret) 3733 if (ret)
3730 return ret; 3734 return ret;
3731 3735
3732 i915_gem_object_flush_cpu_write_domain(obj, false); 3736 i915_gem_object_flush_cpu_write_domain(obj);
3733 3737
3734 /* Serialise direct access to this object with the barriers for 3738 /* Serialise direct access to this object with the barriers for
3735 * coherent writes from the GPU, by effectively invalidating the 3739 * coherent writes from the GPU, by effectively invalidating the
@@ -3821,27 +3825,11 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3821 vma->node.color = cache_level; 3825 vma->node.color = cache_level;
3822 obj->cache_level = cache_level; 3826 obj->cache_level = cache_level;
3823 3827
3824 if (cpu_write_needs_clflush(obj)) { 3828 if (obj->cache_dirty &&
3825 u32 old_read_domains, old_write_domain; 3829 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
3826 3830 cpu_write_needs_clflush(obj)) {
3827 /* If we're coming from LLC cached, then we haven't 3831 if (i915_gem_clflush_object(obj, true))
3828 * actually been tracking whether the data is in the 3832 i915_gem_chipset_flush(obj->base.dev);
3829 * CPU cache or not, since we only allow one bit set
3830 * in obj->write_domain and have been skipping the clflushes.
3831 * Just set it to the CPU cache for now.
3832 */
3833 i915_gem_object_retire(obj);
3834 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3835
3836 old_read_domains = obj->base.read_domains;
3837 old_write_domain = obj->base.write_domain;
3838
3839 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3840 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3841
3842 trace_i915_gem_object_change_domain(obj,
3843 old_read_domains,
3844 old_write_domain);
3845 } 3833 }
3846 3834
3847 return 0; 3835 return 0;
@@ -3991,7 +3979,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3991 if (ret) 3979 if (ret)
3992 goto err_unpin_display; 3980 goto err_unpin_display;
3993 3981
3994 i915_gem_object_flush_cpu_write_domain(obj, true); 3982 i915_gem_object_flush_cpu_write_domain(obj);
3995 3983
3996 old_write_domain = obj->base.write_domain; 3984 old_write_domain = obj->base.write_domain;
3997 old_read_domains = obj->base.read_domains; 3985 old_read_domains = obj->base.read_domains;
@@ -4620,7 +4608,7 @@ i915_gem_suspend(struct drm_device *dev)
4620 i915_gem_stop_ringbuffers(dev); 4608 i915_gem_stop_ringbuffers(dev);
4621 mutex_unlock(&dev->struct_mutex); 4609 mutex_unlock(&dev->struct_mutex);
4622 4610
4623 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); 4611 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4624 cancel_delayed_work_sync(&dev_priv->mm.retire_work); 4612 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4625 flush_delayed_work(&dev_priv->mm.idle_work); 4613 flush_delayed_work(&dev_priv->mm.idle_work);
4626 4614
@@ -5111,7 +5099,7 @@ static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5111 if (!mutex_is_locked(mutex)) 5099 if (!mutex_is_locked(mutex))
5112 return false; 5100 return false;
5113 5101
5114#if defined(CONFIG_SMP) && !defined(CONFIG_DEBUG_MUTEXES) 5102#if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5115 return mutex->owner == task; 5103 return mutex->owner == task;
5116#else 5104#else
5117 /* Since UP may be pre-empted, we cannot assume that we own the lock */ 5105 /* Since UP may be pre-empted, we cannot assume that we own the lock */
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index e3ef17783765..b773368fc62c 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1380,13 +1380,35 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1380 return -EINVAL; 1380 return -EINVAL;
1381 } 1381 }
1382 1382
1383 if (((args->flags & I915_EXEC_RING_MASK) != I915_EXEC_BSD) &&
1384 ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
1385 DRM_DEBUG("execbuf with non bsd ring but with invalid "
1386 "bsd dispatch flags: %d\n", (int)(args->flags));
1387 return -EINVAL;
1388 }
1389
1383 if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT) 1390 if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT)
1384 ring = &dev_priv->ring[RCS]; 1391 ring = &dev_priv->ring[RCS];
1385 else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) { 1392 else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) {
1386 if (HAS_BSD2(dev)) { 1393 if (HAS_BSD2(dev)) {
1387 int ring_id; 1394 int ring_id;
1388 ring_id = gen8_dispatch_bsd_ring(dev, file); 1395
1389 ring = &dev_priv->ring[ring_id]; 1396 switch (args->flags & I915_EXEC_BSD_MASK) {
1397 case I915_EXEC_BSD_DEFAULT:
1398 ring_id = gen8_dispatch_bsd_ring(dev, file);
1399 ring = &dev_priv->ring[ring_id];
1400 break;
1401 case I915_EXEC_BSD_RING1:
1402 ring = &dev_priv->ring[VCS];
1403 break;
1404 case I915_EXEC_BSD_RING2:
1405 ring = &dev_priv->ring[VCS2];
1406 break;
1407 default:
1408 DRM_DEBUG("execbuf with unknown bsd ring: %d\n",
1409 (int)(args->flags & I915_EXEC_BSD_MASK));
1410 return -EINVAL;
1411 }
1390 } else 1412 } else
1391 ring = &dev_priv->ring[VCS]; 1413 ring = &dev_priv->ring[VCS];
1392 } else 1414 } else
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index be5c9908659b..48ddbf44c862 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1052,7 +1052,7 @@ static void i915_gem_record_rings(struct drm_device *dev,
1052 erq = &error->ring[i].requests[count++]; 1052 erq = &error->ring[i].requests[count++];
1053 erq->seqno = request->seqno; 1053 erq->seqno = request->seqno;
1054 erq->jiffies = request->emitted_jiffies; 1054 erq->jiffies = request->emitted_jiffies;
1055 erq->tail = request->tail; 1055 erq->tail = request->postfix;
1056 } 1056 }
1057 } 1057 }
1058} 1058}
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8fe5a87705f7..4145d95902f5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -593,7 +593,7 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
593 struct intel_crtc *intel_crtc = 593 struct intel_crtc *intel_crtc =
594 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 594 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
595 const struct drm_display_mode *mode = 595 const struct drm_display_mode *mode =
596 &intel_crtc->config.adjusted_mode; 596 &intel_crtc->config->base.adjusted_mode;
597 597
598 htotal = mode->crtc_htotal; 598 htotal = mode->crtc_htotal;
599 hsync_start = mode->crtc_hsync_start; 599 hsync_start = mode->crtc_hsync_start;
@@ -664,7 +664,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
664{ 664{
665 struct drm_device *dev = crtc->base.dev; 665 struct drm_device *dev = crtc->base.dev;
666 struct drm_i915_private *dev_priv = dev->dev_private; 666 struct drm_i915_private *dev_priv = dev->dev_private;
667 const struct drm_display_mode *mode = &crtc->config.adjusted_mode; 667 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
668 enum pipe pipe = crtc->pipe; 668 enum pipe pipe = crtc->pipe;
669 int position, vtotal; 669 int position, vtotal;
670 670
@@ -691,7 +691,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
691 struct drm_i915_private *dev_priv = dev->dev_private; 691 struct drm_i915_private *dev_priv = dev->dev_private;
692 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 692 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
694 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; 694 const struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
695 int position; 695 int position;
696 int vbl_start, vbl_end, hsync_start, htotal, vtotal; 696 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
697 bool in_vbl = true; 697 bool in_vbl = true;
@@ -849,7 +849,7 @@ static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
849 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, 849 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
850 vblank_time, flags, 850 vblank_time, flags,
851 crtc, 851 crtc,
852 &to_intel_crtc(crtc)->config.adjusted_mode); 852 &to_intel_crtc(crtc)->config->base.adjusted_mode);
853} 853}
854 854
855static bool intel_hpd_irq_event(struct drm_device *dev, 855static bool intel_hpd_irq_event(struct drm_device *dev,
@@ -879,7 +879,7 @@ static void i915_digport_work_func(struct work_struct *work)
879 container_of(work, struct drm_i915_private, dig_port_work); 879 container_of(work, struct drm_i915_private, dig_port_work);
880 u32 long_port_mask, short_port_mask; 880 u32 long_port_mask, short_port_mask;
881 struct intel_digital_port *intel_dig_port; 881 struct intel_digital_port *intel_dig_port;
882 int i, ret; 882 int i;
883 u32 old_bits = 0; 883 u32 old_bits = 0;
884 884
885 spin_lock_irq(&dev_priv->irq_lock); 885 spin_lock_irq(&dev_priv->irq_lock);
@@ -903,9 +903,11 @@ static void i915_digport_work_func(struct work_struct *work)
903 valid = true; 903 valid = true;
904 904
905 if (valid) { 905 if (valid) {
906 enum irqreturn ret;
907
906 ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd); 908 ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
907 if (ret == true) { 909 if (ret == IRQ_NONE) {
908 /* if we get true fallback to old school hpd */ 910 /* fall back to old school hpd */
909 old_bits |= (1 << intel_dig_port->base.hpd_pin); 911 old_bits |= (1 << intel_dig_port->base.hpd_pin);
910 } 912 }
911 } 913 }
@@ -2419,19 +2421,15 @@ static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2419} 2421}
2420 2422
2421/** 2423/**
2422 * i915_error_work_func - do process context error handling work 2424 * i915_reset_and_wakeup - do process context error handling work
2423 * @work: work struct
2424 * 2425 *
2425 * Fire an error uevent so userspace can see that a hang or error 2426 * Fire an error uevent so userspace can see that a hang or error
2426 * was detected. 2427 * was detected.
2427 */ 2428 */
2428static void i915_error_work_func(struct work_struct *work) 2429static void i915_reset_and_wakeup(struct drm_device *dev)
2429{ 2430{
2430 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, 2431 struct drm_i915_private *dev_priv = to_i915(dev);
2431 work); 2432 struct i915_gpu_error *error = &dev_priv->gpu_error;
2432 struct drm_i915_private *dev_priv =
2433 container_of(error, struct drm_i915_private, gpu_error);
2434 struct drm_device *dev = dev_priv->dev;
2435 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; 2433 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2436 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; 2434 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2437 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; 2435 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
@@ -2598,10 +2596,10 @@ static void i915_report_and_clear_eir(struct drm_device *dev)
2598} 2596}
2599 2597
2600/** 2598/**
2601 * i915_handle_error - handle an error interrupt 2599 * i915_handle_error - handle a gpu error
2602 * @dev: drm device 2600 * @dev: drm device
2603 * 2601 *
2604 * Do some basic checking of regsiter state at error interrupt time and 2602 * Do some basic checking of regsiter state at error time and
2605 * dump it to the syslog. Also call i915_capture_error_state() to make 2603 * dump it to the syslog. Also call i915_capture_error_state() to make
2606 * sure we get a record and make it available in debugfs. Fire a uevent 2604 * sure we get a record and make it available in debugfs. Fire a uevent
2607 * so userspace knows something bad happened (should trigger collection 2605 * so userspace knows something bad happened (should trigger collection
@@ -2626,9 +2624,9 @@ void i915_handle_error(struct drm_device *dev, bool wedged,
2626 &dev_priv->gpu_error.reset_counter); 2624 &dev_priv->gpu_error.reset_counter);
2627 2625
2628 /* 2626 /*
2629 * Wakeup waiting processes so that the reset work function 2627 * Wakeup waiting processes so that the reset function
2630 * i915_error_work_func doesn't deadlock trying to grab various 2628 * i915_reset_and_wakeup doesn't deadlock trying to grab
2631 * locks. By bumping the reset counter first, the woken 2629 * various locks. By bumping the reset counter first, the woken
2632 * processes will see a reset in progress and back off, 2630 * processes will see a reset in progress and back off,
2633 * releasing their locks and then wait for the reset completion. 2631 * releasing their locks and then wait for the reset completion.
2634 * We must do this for _all_ gpu waiters that might hold locks 2632 * We must do this for _all_ gpu waiters that might hold locks
@@ -2641,13 +2639,7 @@ void i915_handle_error(struct drm_device *dev, bool wedged,
2641 i915_error_wake_up(dev_priv, false); 2639 i915_error_wake_up(dev_priv, false);
2642 } 2640 }
2643 2641
2644 /* 2642 i915_reset_and_wakeup(dev);
2645 * Our reset work can grab modeset locks (since it needs to reset the
2646 * state of outstanding pagelips). Hence it must not be run on our own
2647 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2648 * code will deadlock.
2649 */
2650 schedule_work(&dev_priv->gpu_error.work);
2651} 2643}
2652 2644
2653/* Called from drm generic code, passed 'crtc' which 2645/* Called from drm generic code, passed 'crtc' which
@@ -2972,7 +2964,7 @@ ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2972 return HANGCHECK_HUNG; 2964 return HANGCHECK_HUNG;
2973} 2965}
2974 2966
2975/** 2967/*
2976 * This is called when the chip hasn't reported back with completed 2968 * This is called when the chip hasn't reported back with completed
2977 * batchbuffers in a long time. We keep track per ring seqno progress and 2969 * batchbuffers in a long time. We keep track per ring seqno progress and
2978 * if there are no progress, hangcheck score for that ring is increased. 2970 * if there are no progress, hangcheck score for that ring is increased.
@@ -2980,10 +2972,12 @@ ring_stuck(struct intel_engine_cs *ring, u64 acthd)
2980 * we kick the ring. If we see no progress on three subsequent calls 2972 * we kick the ring. If we see no progress on three subsequent calls
2981 * we assume chip is wedged and try to fix it by resetting the chip. 2973 * we assume chip is wedged and try to fix it by resetting the chip.
2982 */ 2974 */
2983static void i915_hangcheck_elapsed(unsigned long data) 2975static void i915_hangcheck_elapsed(struct work_struct *work)
2984{ 2976{
2985 struct drm_device *dev = (struct drm_device *)data; 2977 struct drm_i915_private *dev_priv =
2986 struct drm_i915_private *dev_priv = dev->dev_private; 2978 container_of(work, typeof(*dev_priv),
2979 gpu_error.hangcheck_work.work);
2980 struct drm_device *dev = dev_priv->dev;
2987 struct intel_engine_cs *ring; 2981 struct intel_engine_cs *ring;
2988 int i; 2982 int i;
2989 int busy_count = 0, rings_hung = 0; 2983 int busy_count = 0, rings_hung = 0;
@@ -3097,17 +3091,18 @@ static void i915_hangcheck_elapsed(unsigned long data)
3097 3091
3098void i915_queue_hangcheck(struct drm_device *dev) 3092void i915_queue_hangcheck(struct drm_device *dev)
3099{ 3093{
3100 struct drm_i915_private *dev_priv = dev->dev_private; 3094 struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
3101 struct timer_list *timer = &dev_priv->gpu_error.hangcheck_timer;
3102 3095
3103 if (!i915.enable_hangcheck) 3096 if (!i915.enable_hangcheck)
3104 return; 3097 return;
3105 3098
3106 /* Don't continually defer the hangcheck, but make sure it is active */ 3099 /* Don't continually defer the hangcheck so that it is always run at
3107 if (timer_pending(timer)) 3100 * least once after work has been scheduled on any ring. Otherwise,
3108 return; 3101 * we will ignore a hung ring if a second ring is kept busy.
3109 mod_timer(timer, 3102 */
3110 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); 3103
3104 queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
3105 round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
3111} 3106}
3112 3107
3113static void ibx_irq_reset(struct drm_device *dev) 3108static void ibx_irq_reset(struct drm_device *dev)
@@ -4340,7 +4335,6 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
4340 4335
4341 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); 4336 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4342 INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func); 4337 INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func);
4343 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4344 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); 4338 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4345 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); 4339 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4346 4340
@@ -4351,9 +4345,8 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
4351 else 4345 else
4352 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; 4346 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4353 4347
4354 setup_timer(&dev_priv->gpu_error.hangcheck_timer, 4348 INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4355 i915_hangcheck_elapsed, 4349 i915_hangcheck_elapsed);
4356 (unsigned long) dev);
4357 INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work, 4350 INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work,
4358 intel_hpd_irq_reenable_work); 4351 intel_hpd_irq_reenable_work);
4359 4352
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 07252d8dc726..44f2262a5553 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -52,6 +52,7 @@ struct i915_params i915 __read_mostly = {
52 .use_mmio_flip = 0, 52 .use_mmio_flip = 0,
53 .mmio_debug = 0, 53 .mmio_debug = 0,
54 .verbose_state_checks = 1, 54 .verbose_state_checks = 1,
55 .nuclear_pageflip = 0,
55}; 56};
56 57
57module_param_named(modeset, i915.modeset, int, 0400); 58module_param_named(modeset, i915.modeset, int, 0400);
@@ -178,3 +179,7 @@ MODULE_PARM_DESC(mmio_debug,
178module_param_named(verbose_state_checks, i915.verbose_state_checks, bool, 0600); 179module_param_named(verbose_state_checks, i915.verbose_state_checks, bool, 0600);
179MODULE_PARM_DESC(verbose_state_checks, 180MODULE_PARM_DESC(verbose_state_checks,
180 "Enable verbose logs (ie. WARN_ON()) in case of unexpected hw state conditions."); 181 "Enable verbose logs (ie. WARN_ON()) in case of unexpected hw state conditions.");
182
183module_param_named_unsafe(nuclear_pageflip, i915.nuclear_pageflip, bool, 0600);
184MODULE_PARM_DESC(nuclear_pageflip,
185 "Force atomic modeset functionality; only planes work for now (default: false).");
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a39bb0385bcb..33b3d0a24071 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -605,6 +605,15 @@ enum punit_power_well {
605#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */ 605#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
606#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */ 606#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
607 607
608#define FB_GFX_FMAX_AT_VMAX_FUSE 0x136
609#define FB_GFX_FREQ_FUSE_MASK 0xff
610#define FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT 24
611#define FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT 16
612#define FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT 8
613
614#define FB_GFX_FMIN_AT_VMIN_FUSE 0x137
615#define FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT 8
616
608#define PUNIT_GPU_STATUS_REG 0xdb 617#define PUNIT_GPU_STATUS_REG 0xdb
609#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16 618#define PUNIT_GPU_STATUS_MAX_FREQ_SHIFT 16
610#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff 619#define PUNIT_GPU_STATUS_MAX_FREQ_MASK 0xff
@@ -1471,6 +1480,17 @@ enum punit_power_well {
1471#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) 1480#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
1472#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) 1481#define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10)
1473 1482
1483/* Fuse readout registers for GT */
1484#define CHV_FUSE_GT (VLV_DISPLAY_BASE + 0x2168)
1485#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
1486#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
1487#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
1488#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
1489#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
1490#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
1491#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
1492#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
1493
1474#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050 1494#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
1475#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0) 1495#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
1476#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2) 1496#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
@@ -3748,6 +3768,11 @@ enum punit_power_well {
3748#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) 3768#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
3749#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) 3769#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
3750#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 3770#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
3771#define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL (1 << 14)
3772#define DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL (1 << 13)
3773#define DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL (1 << 12)
3774#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL_MASK (1f << 5)
3775#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5)
3751#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) 3776#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1)
3752 3777
3753/* 3778/*
@@ -6052,6 +6077,9 @@ enum punit_power_well {
6052#define GEN6_PMINTRMSK 0xA168 6077#define GEN6_PMINTRMSK 0xA168
6053#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31) 6078#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31)
6054#define VLV_PWRDWNUPCTL 0xA294 6079#define VLV_PWRDWNUPCTL 0xA294
6080#define GEN9_MEDIA_PG_IDLE_HYSTERESIS 0xA0C4
6081#define GEN9_RENDER_PG_IDLE_HYSTERESIS 0xA0C8
6082#define GEN9_PG_ENABLE 0xA210
6055 6083
6056#define VLV_CHICKEN_3 (VLV_DISPLAY_BASE + 0x7040C) 6084#define VLV_CHICKEN_3 (VLV_DISPLAY_BASE + 0x7040C)
6057#define PIXEL_OVERLAP_CNT_MASK (3 << 30) 6085#define PIXEL_OVERLAP_CNT_MASK (3 << 30)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 4a5af695307e..49f5ade0edb7 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -49,14 +49,14 @@ static u32 calc_residency(struct drm_device *dev, const u32 reg)
49 49
50 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */ 50 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
51 if (IS_VALLEYVIEW(dev)) { 51 if (IS_VALLEYVIEW(dev)) {
52 u32 reg, czcount_30ns; 52 u32 clk_reg, czcount_30ns;
53 53
54 if (IS_CHERRYVIEW(dev)) 54 if (IS_CHERRYVIEW(dev))
55 reg = CHV_CLK_CTL1; 55 clk_reg = CHV_CLK_CTL1;
56 else 56 else
57 reg = VLV_CLK_CTL2; 57 clk_reg = VLV_CLK_CTL2;
58 58
59 czcount_30ns = I915_READ(reg) >> CLK_CTL2_CZCOUNT_30NS_SHIFT; 59 czcount_30ns = I915_READ(clk_reg) >> CLK_CTL2_CZCOUNT_30NS_SHIFT;
60 60
61 if (!czcount_30ns) { 61 if (!czcount_30ns) {
62 WARN(!czcount_30ns, "bogus CZ count value"); 62 WARN(!czcount_30ns, "bogus CZ count value");
@@ -116,8 +116,6 @@ show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
116{ 116{
117 struct drm_minor *dminor = dev_to_drm_minor(kdev); 117 struct drm_minor *dminor = dev_to_drm_minor(kdev);
118 u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p); 118 u32 rc6p_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6p);
119 if (IS_VALLEYVIEW(dminor->dev))
120 rc6p_residency = 0;
121 return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency); 119 return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
122} 120}
123 121
@@ -126,8 +124,6 @@ show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
126{ 124{
127 struct drm_minor *dminor = dev_to_drm_minor(kdev); 125 struct drm_minor *dminor = dev_to_drm_minor(kdev);
128 u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp); 126 u32 rc6pp_residency = calc_residency(dminor->dev, GEN6_GT_GFX_RC6pp);
129 if (IS_VALLEYVIEW(dminor->dev))
130 rc6pp_residency = 0;
131 return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency); 127 return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
132} 128}
133 129
@@ -285,7 +281,7 @@ static struct bin_attribute dpf_attrs_1 = {
285 .private = (void *)1 281 .private = (void *)1
286}; 282};
287 283
288static ssize_t gt_cur_freq_mhz_show(struct device *kdev, 284static ssize_t gt_act_freq_mhz_show(struct device *kdev,
289 struct device_attribute *attr, char *buf) 285 struct device_attribute *attr, char *buf)
290{ 286{
291 struct drm_minor *minor = dev_to_drm_minor(kdev); 287 struct drm_minor *minor = dev_to_drm_minor(kdev);
@@ -301,9 +297,14 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
301 if (IS_VALLEYVIEW(dev_priv->dev)) { 297 if (IS_VALLEYVIEW(dev_priv->dev)) {
302 u32 freq; 298 u32 freq;
303 freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 299 freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
304 ret = vlv_gpu_freq(dev_priv, (freq >> 8) & 0xff); 300 ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
305 } else { 301 } else {
306 ret = dev_priv->rps.cur_freq * GT_FREQUENCY_MULTIPLIER; 302 u32 rpstat = I915_READ(GEN6_RPSTAT1);
303 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
304 ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
305 else
306 ret = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
307 ret = intel_gpu_freq(dev_priv, ret);
307 } 308 }
308 mutex_unlock(&dev_priv->rps.hw_lock); 309 mutex_unlock(&dev_priv->rps.hw_lock);
309 310
@@ -312,6 +313,27 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
312 return snprintf(buf, PAGE_SIZE, "%d\n", ret); 313 return snprintf(buf, PAGE_SIZE, "%d\n", ret);
313} 314}
314 315
316static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
317 struct device_attribute *attr, char *buf)
318{
319 struct drm_minor *minor = dev_to_drm_minor(kdev);
320 struct drm_device *dev = minor->dev;
321 struct drm_i915_private *dev_priv = dev->dev_private;
322 int ret;
323
324 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
325
326 intel_runtime_pm_get(dev_priv);
327
328 mutex_lock(&dev_priv->rps.hw_lock);
329 ret = intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq);
330 mutex_unlock(&dev_priv->rps.hw_lock);
331
332 intel_runtime_pm_put(dev_priv);
333
334 return snprintf(buf, PAGE_SIZE, "%d\n", ret);
335}
336
315static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev, 337static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
316 struct device_attribute *attr, char *buf) 338 struct device_attribute *attr, char *buf)
317{ 339{
@@ -319,8 +341,9 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
319 struct drm_device *dev = minor->dev; 341 struct drm_device *dev = minor->dev;
320 struct drm_i915_private *dev_priv = dev->dev_private; 342 struct drm_i915_private *dev_priv = dev->dev_private;
321 343
322 return snprintf(buf, PAGE_SIZE, "%d\n", 344 return snprintf(buf, PAGE_SIZE,
323 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); 345 "%d\n",
346 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
324} 347}
325 348
326static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 349static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
@@ -333,10 +356,7 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute
333 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 356 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
334 357
335 mutex_lock(&dev_priv->rps.hw_lock); 358 mutex_lock(&dev_priv->rps.hw_lock);
336 if (IS_VALLEYVIEW(dev_priv->dev)) 359 ret = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
337 ret = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
338 else
339 ret = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
340 mutex_unlock(&dev_priv->rps.hw_lock); 360 mutex_unlock(&dev_priv->rps.hw_lock);
341 361
342 return snprintf(buf, PAGE_SIZE, "%d\n", ret); 362 return snprintf(buf, PAGE_SIZE, "%d\n", ret);
@@ -360,10 +380,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
360 380
361 mutex_lock(&dev_priv->rps.hw_lock); 381 mutex_lock(&dev_priv->rps.hw_lock);
362 382
363 if (IS_VALLEYVIEW(dev_priv->dev)) 383 val = intel_freq_opcode(dev_priv, val);
364 val = vlv_freq_opcode(dev_priv, val);
365 else
366 val /= GT_FREQUENCY_MULTIPLIER;
367 384
368 if (val < dev_priv->rps.min_freq || 385 if (val < dev_priv->rps.min_freq ||
369 val > dev_priv->rps.max_freq || 386 val > dev_priv->rps.max_freq ||
@@ -374,21 +391,21 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
374 391
375 if (val > dev_priv->rps.rp0_freq) 392 if (val > dev_priv->rps.rp0_freq)
376 DRM_DEBUG("User requested overclocking to %d\n", 393 DRM_DEBUG("User requested overclocking to %d\n",
377 val * GT_FREQUENCY_MULTIPLIER); 394 intel_gpu_freq(dev_priv, val));
378 395
379 dev_priv->rps.max_freq_softlimit = val; 396 dev_priv->rps.max_freq_softlimit = val;
380 397
381 if (dev_priv->rps.cur_freq > val) { 398 val = clamp_t(int, dev_priv->rps.cur_freq,
382 if (IS_VALLEYVIEW(dev)) 399 dev_priv->rps.min_freq_softlimit,
383 valleyview_set_rps(dev, val); 400 dev_priv->rps.max_freq_softlimit);
384 else 401
385 gen6_set_rps(dev, val); 402 /* We still need *_set_rps to process the new max_delay and
386 } else if (!IS_VALLEYVIEW(dev)) { 403 * update the interrupt limits and PMINTRMSK even though
387 /* We still need gen6_set_rps to process the new max_delay and 404 * frequency request may be unchanged. */
388 * update the interrupt limits even though frequency request is 405 if (IS_VALLEYVIEW(dev))
389 * unchanged. */ 406 valleyview_set_rps(dev, val);
390 gen6_set_rps(dev, dev_priv->rps.cur_freq); 407 else
391 } 408 gen6_set_rps(dev, val);
392 409
393 mutex_unlock(&dev_priv->rps.hw_lock); 410 mutex_unlock(&dev_priv->rps.hw_lock);
394 411
@@ -405,10 +422,7 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute
405 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 422 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
406 423
407 mutex_lock(&dev_priv->rps.hw_lock); 424 mutex_lock(&dev_priv->rps.hw_lock);
408 if (IS_VALLEYVIEW(dev_priv->dev)) 425 ret = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
409 ret = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
410 else
411 ret = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
412 mutex_unlock(&dev_priv->rps.hw_lock); 426 mutex_unlock(&dev_priv->rps.hw_lock);
413 427
414 return snprintf(buf, PAGE_SIZE, "%d\n", ret); 428 return snprintf(buf, PAGE_SIZE, "%d\n", ret);
@@ -432,10 +446,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
432 446
433 mutex_lock(&dev_priv->rps.hw_lock); 447 mutex_lock(&dev_priv->rps.hw_lock);
434 448
435 if (IS_VALLEYVIEW(dev)) 449 val = intel_freq_opcode(dev_priv, val);
436 val = vlv_freq_opcode(dev_priv, val);
437 else
438 val /= GT_FREQUENCY_MULTIPLIER;
439 450
440 if (val < dev_priv->rps.min_freq || 451 if (val < dev_priv->rps.min_freq ||
441 val > dev_priv->rps.max_freq || 452 val > dev_priv->rps.max_freq ||
@@ -446,17 +457,17 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
446 457
447 dev_priv->rps.min_freq_softlimit = val; 458 dev_priv->rps.min_freq_softlimit = val;
448 459
449 if (dev_priv->rps.cur_freq < val) { 460 val = clamp_t(int, dev_priv->rps.cur_freq,
450 if (IS_VALLEYVIEW(dev)) 461 dev_priv->rps.min_freq_softlimit,
451 valleyview_set_rps(dev, val); 462 dev_priv->rps.max_freq_softlimit);
452 else 463
453 gen6_set_rps(dev, val); 464 /* We still need *_set_rps to process the new min_delay and
454 } else if (!IS_VALLEYVIEW(dev)) { 465 * update the interrupt limits and PMINTRMSK even though
455 /* We still need gen6_set_rps to process the new min_delay and 466 * frequency request may be unchanged. */
456 * update the interrupt limits even though frequency request is 467 if (IS_VALLEYVIEW(dev))
457 * unchanged. */ 468 valleyview_set_rps(dev, val);
458 gen6_set_rps(dev, dev_priv->rps.cur_freq); 469 else
459 } 470 gen6_set_rps(dev, val);
460 471
461 mutex_unlock(&dev_priv->rps.hw_lock); 472 mutex_unlock(&dev_priv->rps.hw_lock);
462 473
@@ -464,6 +475,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
464 475
465} 476}
466 477
478static DEVICE_ATTR(gt_act_freq_mhz, S_IRUGO, gt_act_freq_mhz_show, NULL);
467static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL); 479static DEVICE_ATTR(gt_cur_freq_mhz, S_IRUGO, gt_cur_freq_mhz_show, NULL);
468static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store); 480static DEVICE_ATTR(gt_max_freq_mhz, S_IRUGO | S_IWUSR, gt_max_freq_mhz_show, gt_max_freq_mhz_store);
469static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store); 481static DEVICE_ATTR(gt_min_freq_mhz, S_IRUGO | S_IWUSR, gt_min_freq_mhz_show, gt_min_freq_mhz_store);
@@ -494,19 +506,22 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr
494 506
495 if (attr == &dev_attr_gt_RP0_freq_mhz) { 507 if (attr == &dev_attr_gt_RP0_freq_mhz) {
496 if (IS_VALLEYVIEW(dev)) 508 if (IS_VALLEYVIEW(dev))
497 val = vlv_gpu_freq(dev_priv, dev_priv->rps.rp0_freq); 509 val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
498 else 510 else
499 val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER; 511 val = intel_gpu_freq(dev_priv,
512 ((rp_state_cap & 0x0000ff) >> 0));
500 } else if (attr == &dev_attr_gt_RP1_freq_mhz) { 513 } else if (attr == &dev_attr_gt_RP1_freq_mhz) {
501 if (IS_VALLEYVIEW(dev)) 514 if (IS_VALLEYVIEW(dev))
502 val = vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq); 515 val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
503 else 516 else
504 val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER; 517 val = intel_gpu_freq(dev_priv,
518 ((rp_state_cap & 0x00ff00) >> 8));
505 } else if (attr == &dev_attr_gt_RPn_freq_mhz) { 519 } else if (attr == &dev_attr_gt_RPn_freq_mhz) {
506 if (IS_VALLEYVIEW(dev)) 520 if (IS_VALLEYVIEW(dev))
507 val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq); 521 val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq);
508 else 522 else
509 val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER; 523 val = intel_gpu_freq(dev_priv,
524 ((rp_state_cap & 0xff0000) >> 16));
510 } else { 525 } else {
511 BUG(); 526 BUG();
512 } 527 }
@@ -514,6 +529,7 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr
514} 529}
515 530
516static const struct attribute *gen6_attrs[] = { 531static const struct attribute *gen6_attrs[] = {
532 &dev_attr_gt_act_freq_mhz.attr,
517 &dev_attr_gt_cur_freq_mhz.attr, 533 &dev_attr_gt_cur_freq_mhz.attr,
518 &dev_attr_gt_max_freq_mhz.attr, 534 &dev_attr_gt_max_freq_mhz.attr,
519 &dev_attr_gt_min_freq_mhz.attr, 535 &dev_attr_gt_min_freq_mhz.attr,
@@ -524,6 +540,7 @@ static const struct attribute *gen6_attrs[] = {
524}; 540};
525 541
526static const struct attribute *vlv_attrs[] = { 542static const struct attribute *vlv_attrs[] = {
543 &dev_attr_gt_act_freq_mhz.attr,
527 &dev_attr_gt_cur_freq_mhz.attr, 544 &dev_attr_gt_cur_freq_mhz.attr,
528 &dev_attr_gt_max_freq_mhz.attr, 545 &dev_attr_gt_max_freq_mhz.attr,
529 &dev_attr_gt_min_freq_mhz.attr, 546 &dev_attr_gt_min_freq_mhz.attr,
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
new file mode 100644
index 000000000000..19a9dd5408f3
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -0,0 +1,237 @@
1/*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24/**
25 * DOC: atomic modeset support
26 *
27 * The functions here implement the state management and hardware programming
28 * dispatch required by the atomic modeset infrastructure.
29 * See intel_atomic_plane.c for the plane-specific atomic functionality.
30 */
31
32#include <drm/drmP.h>
33#include <drm/drm_atomic.h>
34#include <drm/drm_atomic_helper.h>
35#include <drm/drm_plane_helper.h>
36#include "intel_drv.h"
37
38
39/**
40 * intel_atomic_check - validate state object
41 * @dev: drm device
42 * @state: state to validate
43 */
44int intel_atomic_check(struct drm_device *dev,
45 struct drm_atomic_state *state)
46{
47 int nplanes = dev->mode_config.num_total_plane;
48 int ncrtcs = dev->mode_config.num_crtc;
49 int nconnectors = dev->mode_config.num_connector;
50 enum pipe nuclear_pipe = INVALID_PIPE;
51 int ret;
52 int i;
53 bool not_nuclear = false;
54
55 /*
56 * FIXME: At the moment, we only support "nuclear pageflip" on a
57 * single CRTC. Cross-crtc updates will be added later.
58 */
59 for (i = 0; i < nplanes; i++) {
60 struct intel_plane *plane = to_intel_plane(state->planes[i]);
61 if (!plane)
62 continue;
63
64 if (nuclear_pipe == INVALID_PIPE) {
65 nuclear_pipe = plane->pipe;
66 } else if (nuclear_pipe != plane->pipe) {
67 DRM_DEBUG_KMS("i915 only support atomic plane operations on a single CRTC at the moment\n");
68 return -EINVAL;
69 }
70 }
71
72 /*
73 * FIXME: We only handle planes for now; make sure there are no CRTC's
74 * or connectors involved.
75 */
76 state->allow_modeset = false;
77 for (i = 0; i < ncrtcs; i++) {
78 struct intel_crtc *crtc = to_intel_crtc(state->crtcs[i]);
79 if (crtc && crtc->pipe != nuclear_pipe)
80 not_nuclear = true;
81 }
82 for (i = 0; i < nconnectors; i++)
83 if (state->connectors[i] != NULL)
84 not_nuclear = true;
85
86 if (not_nuclear) {
87 DRM_DEBUG_KMS("i915 only supports atomic plane operations at the moment\n");
88 return -EINVAL;
89 }
90
91 ret = drm_atomic_helper_check_planes(dev, state);
92 if (ret)
93 return ret;
94
95 return ret;
96}
97
98
99/**
100 * intel_atomic_commit - commit validated state object
101 * @dev: DRM device
102 * @state: the top-level driver state object
103 * @async: asynchronous commit
104 *
105 * This function commits a top-level state object that has been validated
106 * with drm_atomic_helper_check().
107 *
108 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
109 * we can only handle plane-related operations and do not yet support
110 * asynchronous commit.
111 *
112 * RETURNS
113 * Zero for success or -errno.
114 */
115int intel_atomic_commit(struct drm_device *dev,
116 struct drm_atomic_state *state,
117 bool async)
118{
119 int ret;
120 int i;
121
122 if (async) {
123 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
124 return -EINVAL;
125 }
126
127 ret = drm_atomic_helper_prepare_planes(dev, state);
128 if (ret)
129 return ret;
130
131 /* Point of no return */
132
133 /*
134 * FIXME: The proper sequence here will eventually be:
135 *
136 * drm_atomic_helper_swap_state(dev, state)
137 * drm_atomic_helper_commit_pre_planes(dev, state);
138 * drm_atomic_helper_commit_planes(dev, state);
139 * drm_atomic_helper_commit_post_planes(dev, state);
140 * drm_atomic_helper_wait_for_vblanks(dev, state);
141 * drm_atomic_helper_cleanup_planes(dev, state);
142 * drm_atomic_state_free(state);
143 *
144 * once we have full atomic modeset. For now, just manually update
145 * plane states to avoid clobbering good states with dummy states
146 * while nuclear pageflipping.
147 */
148 for (i = 0; i < dev->mode_config.num_total_plane; i++) {
149 struct drm_plane *plane = state->planes[i];
150
151 if (!plane)
152 continue;
153
154 plane->state->state = state;
155 swap(state->plane_states[i], plane->state);
156 plane->state->state = NULL;
157 }
158 drm_atomic_helper_commit_planes(dev, state);
159 drm_atomic_helper_wait_for_vblanks(dev, state);
160 drm_atomic_helper_cleanup_planes(dev, state);
161 drm_atomic_state_free(state);
162
163 return 0;
164}
165
166/**
167 * intel_connector_atomic_get_property - fetch connector property value
168 * @connector: connector to fetch property for
169 * @state: state containing the property value
170 * @property: property to look up
171 * @val: pointer to write property value into
172 *
173 * The DRM core does not store shadow copies of properties for
174 * atomic-capable drivers. This entrypoint is used to fetch
175 * the current value of a driver-specific connector property.
176 */
177int
178intel_connector_atomic_get_property(struct drm_connector *connector,
179 const struct drm_connector_state *state,
180 struct drm_property *property,
181 uint64_t *val)
182{
183 int i;
184
185 /*
186 * TODO: We only have atomic modeset for planes at the moment, so the
187 * crtc/connector code isn't quite ready yet. Until it's ready,
188 * continue to look up all property values in the DRM's shadow copy
189 * in obj->properties->values[].
190 *
191 * When the crtc/connector state work matures, this function should
192 * be updated to read the values out of the state structure instead.
193 */
194 for (i = 0; i < connector->base.properties->count; i++) {
195 if (connector->base.properties->properties[i] == property) {
196 *val = connector->base.properties->values[i];
197 return 0;
198 }
199 }
200
201 return -EINVAL;
202}
203
204/*
205 * intel_crtc_duplicate_state - duplicate crtc state
206 * @crtc: drm crtc
207 *
208 * Allocates and returns a copy of the crtc state (both common and
209 * Intel-specific) for the specified crtc.
210 *
211 * Returns: The newly allocated crtc state, or NULL on failure.
212 */
213struct drm_crtc_state *
214intel_crtc_duplicate_state(struct drm_crtc *crtc)
215{
216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
217
218 if (WARN_ON(!intel_crtc->config))
219 return kzalloc(sizeof(*intel_crtc->config), GFP_KERNEL);
220
221 return kmemdup(intel_crtc->config, sizeof(*intel_crtc->config),
222 GFP_KERNEL);
223}
224
225/**
226 * intel_crtc_destroy_state - destroy crtc state
227 * @crtc: drm crtc
228 *
229 * Destroys the crtc state (both common and Intel-specific) for the
230 * specified crtc.
231 */
232void
233intel_crtc_destroy_state(struct drm_crtc *crtc,
234 struct drm_crtc_state *state)
235{
236 drm_atomic_helper_crtc_destroy_state(crtc, state);
237}
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 5488efef1837..9e6f727dfd19 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -37,31 +37,58 @@
37#include "intel_drv.h" 37#include "intel_drv.h"
38 38
39/** 39/**
40 * intel_create_plane_state - create plane state object
41 * @plane: drm plane
42 *
43 * Allocates a fresh plane state for the given plane and sets some of
44 * the state values to sensible initial values.
45 *
46 * Returns: A newly allocated plane state, or NULL on failure
47 */
48struct intel_plane_state *
49intel_create_plane_state(struct drm_plane *plane)
50{
51 struct intel_plane_state *state;
52
53 state = kzalloc(sizeof(*state), GFP_KERNEL);
54 if (!state)
55 return NULL;
56
57 state->base.plane = plane;
58 state->base.rotation = BIT(DRM_ROTATE_0);
59
60 return state;
61}
62
63/**
40 * intel_plane_duplicate_state - duplicate plane state 64 * intel_plane_duplicate_state - duplicate plane state
41 * @plane: drm plane 65 * @plane: drm plane
42 * 66 *
43 * Allocates and returns a copy of the plane state (both common and 67 * Allocates and returns a copy of the plane state (both common and
44 * Intel-specific) for the specified plane. 68 * Intel-specific) for the specified plane.
45 * 69 *
46 * Returns: The newly allocated plane state, or NULL or failure. 70 * Returns: The newly allocated plane state, or NULL on failure.
47 */ 71 */
48struct drm_plane_state * 72struct drm_plane_state *
49intel_plane_duplicate_state(struct drm_plane *plane) 73intel_plane_duplicate_state(struct drm_plane *plane)
50{ 74{
51 struct intel_plane_state *state; 75 struct drm_plane_state *state;
76 struct intel_plane_state *intel_state;
52 77
53 if (plane->state) 78 if (WARN_ON(!plane->state))
54 state = kmemdup(plane->state, sizeof(*state), GFP_KERNEL); 79 intel_state = intel_create_plane_state(plane);
55 else 80 else
56 state = kzalloc(sizeof(*state), GFP_KERNEL); 81 intel_state = kmemdup(plane->state, sizeof(*intel_state),
82 GFP_KERNEL);
57 83
58 if (!state) 84 if (!intel_state)
59 return NULL; 85 return NULL;
60 86
61 if (state->base.fb) 87 state = &intel_state->base;
62 drm_framebuffer_reference(state->base.fb); 88 if (state->fb)
89 drm_framebuffer_reference(state->fb);
63 90
64 return &state->base; 91 return state;
65} 92}
66 93
67/** 94/**
@@ -91,6 +118,15 @@ static int intel_plane_atomic_check(struct drm_plane *plane,
91 intel_crtc = to_intel_crtc(crtc); 118 intel_crtc = to_intel_crtc(crtc);
92 119
93 /* 120 /*
121 * Both crtc and plane->crtc could be NULL if we're updating a
122 * property while the plane is disabled. We don't actually have
123 * anything driver-specific we need to test in that case, so
124 * just return success.
125 */
126 if (!crtc)
127 return 0;
128
129 /*
94 * The original src/dest coordinates are stored in state->base, but 130 * The original src/dest coordinates are stored in state->base, but
95 * we want to keep another copy internal to our driver that we can 131 * we want to keep another copy internal to our driver that we can
96 * clip/modify ourselves. 132 * clip/modify ourselves.
@@ -108,9 +144,9 @@ static int intel_plane_atomic_check(struct drm_plane *plane,
108 intel_state->clip.x1 = 0; 144 intel_state->clip.x1 = 0;
109 intel_state->clip.y1 = 0; 145 intel_state->clip.y1 = 0;
110 intel_state->clip.x2 = 146 intel_state->clip.x2 =
111 intel_crtc->active ? intel_crtc->config.pipe_src_w : 0; 147 intel_crtc->active ? intel_crtc->config->pipe_src_w : 0;
112 intel_state->clip.y2 = 148 intel_state->clip.y2 =
113 intel_crtc->active ? intel_crtc->config.pipe_src_h : 0; 149 intel_crtc->active ? intel_crtc->config->pipe_src_h : 0;
114 150
115 /* 151 /*
116 * Disabling a plane is always okay; we just need to update 152 * Disabling a plane is always okay; we just need to update
@@ -150,3 +186,61 @@ const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
150 .atomic_update = intel_plane_atomic_update, 186 .atomic_update = intel_plane_atomic_update,
151}; 187};
152 188
189/**
190 * intel_plane_atomic_get_property - fetch plane property value
191 * @plane: plane to fetch property for
192 * @state: state containing the property value
193 * @property: property to look up
194 * @val: pointer to write property value into
195 *
196 * The DRM core does not store shadow copies of properties for
197 * atomic-capable drivers. This entrypoint is used to fetch
198 * the current value of a driver-specific plane property.
199 */
200int
201intel_plane_atomic_get_property(struct drm_plane *plane,
202 const struct drm_plane_state *state,
203 struct drm_property *property,
204 uint64_t *val)
205{
206 struct drm_mode_config *config = &plane->dev->mode_config;
207
208 if (property == config->rotation_property) {
209 *val = state->rotation;
210 } else {
211 DRM_DEBUG_KMS("Unknown plane property '%s'\n", property->name);
212 return -EINVAL;
213 }
214
215 return 0;
216}
217
218/**
219 * intel_plane_atomic_set_property - set plane property value
220 * @plane: plane to set property for
221 * @state: state to update property value in
222 * @property: property to set
223 * @val: value to set property to
224 *
225 * Writes the specified property value for a plane into the provided atomic
226 * state object.
227 *
228 * Returns 0 on success, -EINVAL on unrecognized properties
229 */
230int
231intel_plane_atomic_set_property(struct drm_plane *plane,
232 struct drm_plane_state *state,
233 struct drm_property *property,
234 uint64_t val)
235{
236 struct drm_mode_config *config = &plane->dev->mode_config;
237
238 if (property == config->rotation_property) {
239 state->rotation = val;
240 } else {
241 DRM_DEBUG_KMS("Unknown plane property '%s'\n", property->name);
242 return -EINVAL;
243 }
244
245 return 0;
246}
diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index ee41b882e71a..2396cc702d18 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -400,7 +400,7 @@ void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
400{ 400{
401 struct drm_encoder *encoder = &intel_encoder->base; 401 struct drm_encoder *encoder = &intel_encoder->base;
402 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); 402 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
403 struct drm_display_mode *mode = &crtc->config.adjusted_mode; 403 struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
404 struct drm_connector *connector; 404 struct drm_connector *connector;
405 struct drm_device *dev = encoder->dev; 405 struct drm_device *dev = encoder->dev;
406 struct drm_i915_private *dev_priv = dev->dev_private; 406 struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index a9af9a4866db..e66e17af0a56 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -28,6 +28,7 @@
28#include <linux/i2c.h> 28#include <linux/i2c.h>
29#include <linux/slab.h> 29#include <linux/slab.h>
30#include <drm/drmP.h> 30#include <drm/drmP.h>
31#include <drm/drm_atomic_helper.h>
31#include <drm/drm_crtc.h> 32#include <drm/drm_crtc.h>
32#include <drm/drm_crtc_helper.h> 33#include <drm/drm_crtc_helper.h>
33#include <drm/drm_edid.h> 34#include <drm/drm_edid.h>
@@ -110,31 +111,31 @@ static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
110} 111}
111 112
112static void intel_crt_get_config(struct intel_encoder *encoder, 113static void intel_crt_get_config(struct intel_encoder *encoder,
113 struct intel_crtc_config *pipe_config) 114 struct intel_crtc_state *pipe_config)
114{ 115{
115 struct drm_device *dev = encoder->base.dev; 116 struct drm_device *dev = encoder->base.dev;
116 int dotclock; 117 int dotclock;
117 118
118 pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); 119 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
119 120
120 dotclock = pipe_config->port_clock; 121 dotclock = pipe_config->port_clock;
121 122
122 if (HAS_PCH_SPLIT(dev)) 123 if (HAS_PCH_SPLIT(dev))
123 ironlake_check_encoder_dotclock(pipe_config, dotclock); 124 ironlake_check_encoder_dotclock(pipe_config, dotclock);
124 125
125 pipe_config->adjusted_mode.crtc_clock = dotclock; 126 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
126} 127}
127 128
128static void hsw_crt_get_config(struct intel_encoder *encoder, 129static void hsw_crt_get_config(struct intel_encoder *encoder,
129 struct intel_crtc_config *pipe_config) 130 struct intel_crtc_state *pipe_config)
130{ 131{
131 intel_ddi_get_config(encoder, pipe_config); 132 intel_ddi_get_config(encoder, pipe_config);
132 133
133 pipe_config->adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 134 pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
134 DRM_MODE_FLAG_NHSYNC | 135 DRM_MODE_FLAG_NHSYNC |
135 DRM_MODE_FLAG_PVSYNC | 136 DRM_MODE_FLAG_PVSYNC |
136 DRM_MODE_FLAG_NVSYNC); 137 DRM_MODE_FLAG_NVSYNC);
137 pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder); 138 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder);
138} 139}
139 140
140static void hsw_crt_pre_enable(struct intel_encoder *encoder) 141static void hsw_crt_pre_enable(struct intel_encoder *encoder)
@@ -157,7 +158,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
157 struct drm_i915_private *dev_priv = dev->dev_private; 158 struct drm_i915_private *dev_priv = dev->dev_private;
158 struct intel_crt *crt = intel_encoder_to_crt(encoder); 159 struct intel_crt *crt = intel_encoder_to_crt(encoder);
159 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 160 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
160 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; 161 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
161 u32 adpa; 162 u32 adpa;
162 163
163 if (INTEL_INFO(dev)->gen >= 5) 164 if (INTEL_INFO(dev)->gen >= 5)
@@ -303,7 +304,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
303} 304}
304 305
305static bool intel_crt_compute_config(struct intel_encoder *encoder, 306static bool intel_crt_compute_config(struct intel_encoder *encoder,
306 struct intel_crtc_config *pipe_config) 307 struct intel_crtc_state *pipe_config)
307{ 308{
308 struct drm_device *dev = encoder->base.dev; 309 struct drm_device *dev = encoder->base.dev;
309 310
@@ -792,6 +793,8 @@ static const struct drm_connector_funcs intel_crt_connector_funcs = {
792 .fill_modes = drm_helper_probe_single_connector_modes, 793 .fill_modes = drm_helper_probe_single_connector_modes,
793 .destroy = intel_crt_destroy, 794 .destroy = intel_crt_destroy,
794 .set_property = intel_crt_set_property, 795 .set_property = intel_crt_set_property,
796 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
797 .atomic_get_property = intel_connector_atomic_get_property,
795}; 798};
796 799
797static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { 800static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 1c92ad47502b..f14e8a2a022d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -328,7 +328,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
328 /* Enable the PCH Receiver FDI PLL */ 328 /* Enable the PCH Receiver FDI PLL */
329 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 329 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
330 FDI_RX_PLL_ENABLE | 330 FDI_RX_PLL_ENABLE |
331 FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); 331 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
332 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 332 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
333 POSTING_READ(_FDI_RXA_CTL); 333 POSTING_READ(_FDI_RXA_CTL);
334 udelay(220); 334 udelay(220);
@@ -338,8 +338,8 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
338 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 338 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
339 339
340 /* Configure Port Clock Select */ 340 /* Configure Port Clock Select */
341 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel); 341 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
342 WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL); 342 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
343 343
344 /* Start the training iterating through available voltages and emphasis, 344 /* Start the training iterating through available voltages and emphasis,
345 * testing each value twice. */ 345 * testing each value twice. */
@@ -357,7 +357,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
357 * port reversal bit */ 357 * port reversal bit */
358 I915_WRITE(DDI_BUF_CTL(PORT_E), 358 I915_WRITE(DDI_BUF_CTL(PORT_E),
359 DDI_BUF_CTL_ENABLE | 359 DDI_BUF_CTL_ENABLE |
360 ((intel_crtc->config.fdi_lanes - 1) << 1) | 360 ((intel_crtc->config->fdi_lanes - 1) << 1) |
361 DDI_BUF_TRANS_SELECT(i / 2)); 361 DDI_BUF_TRANS_SELECT(i / 2));
362 POSTING_READ(DDI_BUF_CTL(PORT_E)); 362 POSTING_READ(DDI_BUF_CTL(PORT_E));
363 363
@@ -732,7 +732,7 @@ static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
732 732
733 733
734static void skl_ddi_clock_get(struct intel_encoder *encoder, 734static void skl_ddi_clock_get(struct intel_encoder *encoder,
735 struct intel_crtc_config *pipe_config) 735 struct intel_crtc_state *pipe_config)
736{ 736{
737 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 737 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
738 int link_clock = 0; 738 int link_clock = 0;
@@ -768,15 +768,15 @@ static void skl_ddi_clock_get(struct intel_encoder *encoder,
768 pipe_config->port_clock = link_clock; 768 pipe_config->port_clock = link_clock;
769 769
770 if (pipe_config->has_dp_encoder) 770 if (pipe_config->has_dp_encoder)
771 pipe_config->adjusted_mode.crtc_clock = 771 pipe_config->base.adjusted_mode.crtc_clock =
772 intel_dotclock_calculate(pipe_config->port_clock, 772 intel_dotclock_calculate(pipe_config->port_clock,
773 &pipe_config->dp_m_n); 773 &pipe_config->dp_m_n);
774 else 774 else
775 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock; 775 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
776} 776}
777 777
778static void hsw_ddi_clock_get(struct intel_encoder *encoder, 778static void hsw_ddi_clock_get(struct intel_encoder *encoder,
779 struct intel_crtc_config *pipe_config) 779 struct intel_crtc_state *pipe_config)
780{ 780{
781 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 781 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
782 int link_clock = 0; 782 int link_clock = 0;
@@ -820,19 +820,19 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder,
820 pipe_config->port_clock = link_clock * 2; 820 pipe_config->port_clock = link_clock * 2;
821 821
822 if (pipe_config->has_pch_encoder) 822 if (pipe_config->has_pch_encoder)
823 pipe_config->adjusted_mode.crtc_clock = 823 pipe_config->base.adjusted_mode.crtc_clock =
824 intel_dotclock_calculate(pipe_config->port_clock, 824 intel_dotclock_calculate(pipe_config->port_clock,
825 &pipe_config->fdi_m_n); 825 &pipe_config->fdi_m_n);
826 else if (pipe_config->has_dp_encoder) 826 else if (pipe_config->has_dp_encoder)
827 pipe_config->adjusted_mode.crtc_clock = 827 pipe_config->base.adjusted_mode.crtc_clock =
828 intel_dotclock_calculate(pipe_config->port_clock, 828 intel_dotclock_calculate(pipe_config->port_clock,
829 &pipe_config->dp_m_n); 829 &pipe_config->dp_m_n);
830 else 830 else
831 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock; 831 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
832} 832}
833 833
834void intel_ddi_clock_get(struct intel_encoder *encoder, 834void intel_ddi_clock_get(struct intel_encoder *encoder,
835 struct intel_crtc_config *pipe_config) 835 struct intel_crtc_state *pipe_config)
836{ 836{
837 struct drm_device *dev = encoder->base.dev; 837 struct drm_device *dev = encoder->base.dev;
838 838
@@ -909,6 +909,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
909 909
910static bool 910static bool
911hsw_ddi_pll_select(struct intel_crtc *intel_crtc, 911hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
912 struct intel_crtc_state *crtc_state,
912 struct intel_encoder *intel_encoder, 913 struct intel_encoder *intel_encoder,
913 int clock) 914 int clock)
914{ 915{
@@ -923,16 +924,16 @@ hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
923 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | 924 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
924 WRPLL_DIVIDER_POST(p); 925 WRPLL_DIVIDER_POST(p);
925 926
926 intel_crtc->new_config->dpll_hw_state.wrpll = val; 927 crtc_state->dpll_hw_state.wrpll = val;
927 928
928 pll = intel_get_shared_dpll(intel_crtc); 929 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
929 if (pll == NULL) { 930 if (pll == NULL) {
930 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 931 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
931 pipe_name(intel_crtc->pipe)); 932 pipe_name(intel_crtc->pipe));
932 return false; 933 return false;
933 } 934 }
934 935
935 intel_crtc->new_config->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); 936 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
936 } 937 }
937 938
938 return true; 939 return true;
@@ -1095,6 +1096,7 @@ found:
1095 1096
1096static bool 1097static bool
1097skl_ddi_pll_select(struct intel_crtc *intel_crtc, 1098skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1099 struct intel_crtc_state *crtc_state,
1098 struct intel_encoder *intel_encoder, 1100 struct intel_encoder *intel_encoder,
1099 int clock) 1101 int clock)
1100{ 1102{
@@ -1144,11 +1146,11 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1144 } else /* eDP */ 1146 } else /* eDP */
1145 return true; 1147 return true;
1146 1148
1147 intel_crtc->new_config->dpll_hw_state.ctrl1 = ctrl1; 1149 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1148 intel_crtc->new_config->dpll_hw_state.cfgcr1 = cfgcr1; 1150 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1149 intel_crtc->new_config->dpll_hw_state.cfgcr2 = cfgcr2; 1151 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
1150 1152
1151 pll = intel_get_shared_dpll(intel_crtc); 1153 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1152 if (pll == NULL) { 1154 if (pll == NULL) {
1153 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 1155 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1154 pipe_name(intel_crtc->pipe)); 1156 pipe_name(intel_crtc->pipe));
@@ -1156,7 +1158,7 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1156 } 1158 }
1157 1159
1158 /* shared DPLL id 0 is DPLL 1 */ 1160 /* shared DPLL id 0 is DPLL 1 */
1159 intel_crtc->new_config->ddi_pll_sel = pll->id + 1; 1161 crtc_state->ddi_pll_sel = pll->id + 1;
1160 1162
1161 return true; 1163 return true;
1162} 1164}
@@ -1168,17 +1170,20 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
1168 * For private DPLLs, compute_config() should do the selection for us. This 1170 * For private DPLLs, compute_config() should do the selection for us. This
1169 * function should be folded into compute_config() eventually. 1171 * function should be folded into compute_config() eventually.
1170 */ 1172 */
1171bool intel_ddi_pll_select(struct intel_crtc *intel_crtc) 1173bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1174 struct intel_crtc_state *crtc_state)
1172{ 1175{
1173 struct drm_device *dev = intel_crtc->base.dev; 1176 struct drm_device *dev = intel_crtc->base.dev;
1174 struct intel_encoder *intel_encoder = 1177 struct intel_encoder *intel_encoder =
1175 intel_ddi_get_crtc_new_encoder(intel_crtc); 1178 intel_ddi_get_crtc_new_encoder(intel_crtc);
1176 int clock = intel_crtc->new_config->port_clock; 1179 int clock = crtc_state->port_clock;
1177 1180
1178 if (IS_SKYLAKE(dev)) 1181 if (IS_SKYLAKE(dev))
1179 return skl_ddi_pll_select(intel_crtc, intel_encoder, clock); 1182 return skl_ddi_pll_select(intel_crtc, crtc_state,
1183 intel_encoder, clock);
1180 else 1184 else
1181 return hsw_ddi_pll_select(intel_crtc, intel_encoder, clock); 1185 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1186 intel_encoder, clock);
1182} 1187}
1183 1188
1184void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) 1189void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
@@ -1186,13 +1191,13 @@ void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1186 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 1191 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1188 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1193 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1189 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 1194 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1190 int type = intel_encoder->type; 1195 int type = intel_encoder->type;
1191 uint32_t temp; 1196 uint32_t temp;
1192 1197
1193 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { 1198 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
1194 temp = TRANS_MSA_SYNC_CLK; 1199 temp = TRANS_MSA_SYNC_CLK;
1195 switch (intel_crtc->config.pipe_bpp) { 1200 switch (intel_crtc->config->pipe_bpp) {
1196 case 18: 1201 case 18:
1197 temp |= TRANS_MSA_6_BPC; 1202 temp |= TRANS_MSA_6_BPC;
1198 break; 1203 break;
@@ -1217,7 +1222,7 @@ void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1218 struct drm_device *dev = crtc->dev; 1223 struct drm_device *dev = crtc->dev;
1219 struct drm_i915_private *dev_priv = dev->dev_private; 1224 struct drm_i915_private *dev_priv = dev->dev_private;
1220 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 1225 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1221 uint32_t temp; 1226 uint32_t temp;
1222 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1227 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1223 if (state == true) 1228 if (state == true)
@@ -1235,7 +1240,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1235 struct drm_device *dev = crtc->dev; 1240 struct drm_device *dev = crtc->dev;
1236 struct drm_i915_private *dev_priv = dev->dev_private; 1241 struct drm_i915_private *dev_priv = dev->dev_private;
1237 enum pipe pipe = intel_crtc->pipe; 1242 enum pipe pipe = intel_crtc->pipe;
1238 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 1243 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1239 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1244 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1240 int type = intel_encoder->type; 1245 int type = intel_encoder->type;
1241 uint32_t temp; 1246 uint32_t temp;
@@ -1244,7 +1249,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1244 temp = TRANS_DDI_FUNC_ENABLE; 1249 temp = TRANS_DDI_FUNC_ENABLE;
1245 temp |= TRANS_DDI_SELECT_PORT(port); 1250 temp |= TRANS_DDI_SELECT_PORT(port);
1246 1251
1247 switch (intel_crtc->config.pipe_bpp) { 1252 switch (intel_crtc->config->pipe_bpp) {
1248 case 18: 1253 case 18:
1249 temp |= TRANS_DDI_BPC_6; 1254 temp |= TRANS_DDI_BPC_6;
1250 break; 1255 break;
@@ -1261,9 +1266,9 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1261 BUG(); 1266 BUG();
1262 } 1267 }
1263 1268
1264 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1269 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1265 temp |= TRANS_DDI_PVSYNC; 1270 temp |= TRANS_DDI_PVSYNC;
1266 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1271 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1267 temp |= TRANS_DDI_PHSYNC; 1272 temp |= TRANS_DDI_PHSYNC;
1268 1273
1269 if (cpu_transcoder == TRANSCODER_EDP) { 1274 if (cpu_transcoder == TRANSCODER_EDP) {
@@ -1274,8 +1279,8 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1274 * using motion blur mitigation (which we don't 1279 * using motion blur mitigation (which we don't
1275 * support). */ 1280 * support). */
1276 if (IS_HASWELL(dev) && 1281 if (IS_HASWELL(dev) &&
1277 (intel_crtc->config.pch_pfit.enabled || 1282 (intel_crtc->config->pch_pfit.enabled ||
1278 intel_crtc->config.pch_pfit.force_thru)) 1283 intel_crtc->config->pch_pfit.force_thru))
1279 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1284 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1280 else 1285 else
1281 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1286 temp |= TRANS_DDI_EDP_INPUT_A_ON;
@@ -1293,14 +1298,14 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
1293 } 1298 }
1294 1299
1295 if (type == INTEL_OUTPUT_HDMI) { 1300 if (type == INTEL_OUTPUT_HDMI) {
1296 if (intel_crtc->config.has_hdmi_sink) 1301 if (intel_crtc->config->has_hdmi_sink)
1297 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1302 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1298 else 1303 else
1299 temp |= TRANS_DDI_MODE_SELECT_DVI; 1304 temp |= TRANS_DDI_MODE_SELECT_DVI;
1300 1305
1301 } else if (type == INTEL_OUTPUT_ANALOG) { 1306 } else if (type == INTEL_OUTPUT_ANALOG) {
1302 temp |= TRANS_DDI_MODE_SELECT_FDI; 1307 temp |= TRANS_DDI_MODE_SELECT_FDI;
1303 temp |= (intel_crtc->config.fdi_lanes - 1) << 1; 1308 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
1304 1309
1305 } else if (type == INTEL_OUTPUT_DISPLAYPORT || 1310 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1306 type == INTEL_OUTPUT_EDP) { 1311 type == INTEL_OUTPUT_EDP) {
@@ -1450,7 +1455,7 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1450 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 1455 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1451 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1456 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1452 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1457 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1453 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 1458 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1454 1459
1455 if (cpu_transcoder != TRANSCODER_EDP) 1460 if (cpu_transcoder != TRANSCODER_EDP)
1456 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 1461 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
@@ -1460,7 +1465,7 @@ void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1460void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) 1465void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1461{ 1466{
1462 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 1467 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1463 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 1468 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1464 1469
1465 if (cpu_transcoder != TRANSCODER_EDP) 1470 if (cpu_transcoder != TRANSCODER_EDP)
1466 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 1471 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
@@ -1482,7 +1487,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1482 } 1487 }
1483 1488
1484 if (IS_SKYLAKE(dev)) { 1489 if (IS_SKYLAKE(dev)) {
1485 uint32_t dpll = crtc->config.ddi_pll_sel; 1490 uint32_t dpll = crtc->config->ddi_pll_sel;
1486 uint32_t val; 1491 uint32_t val;
1487 1492
1488 /* 1493 /*
@@ -1497,7 +1502,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1497 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | 1502 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
1498 DPLL_CTRL1_SSC(dpll) | 1503 DPLL_CTRL1_SSC(dpll) |
1499 DPLL_CRTL1_LINK_RATE_MASK(dpll)); 1504 DPLL_CRTL1_LINK_RATE_MASK(dpll));
1500 val |= crtc->config.dpll_hw_state.ctrl1 << (dpll * 6); 1505 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
1501 1506
1502 I915_WRITE(DPLL_CTRL1, val); 1507 I915_WRITE(DPLL_CTRL1, val);
1503 POSTING_READ(DPLL_CTRL1); 1508 POSTING_READ(DPLL_CTRL1);
@@ -1514,8 +1519,8 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1514 I915_WRITE(DPLL_CTRL2, val); 1519 I915_WRITE(DPLL_CTRL2, val);
1515 1520
1516 } else { 1521 } else {
1517 WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE); 1522 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
1518 I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel); 1523 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
1519 } 1524 }
1520 1525
1521 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 1526 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
@@ -1532,8 +1537,8 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1532 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1537 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1533 1538
1534 intel_hdmi->set_infoframes(encoder, 1539 intel_hdmi->set_infoframes(encoder,
1535 crtc->config.has_hdmi_sink, 1540 crtc->config->has_hdmi_sink,
1536 &crtc->config.adjusted_mode); 1541 &crtc->config->base.adjusted_mode);
1537 } 1542 }
1538} 1543}
1539 1544
@@ -1605,9 +1610,10 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder)
1605 1610
1606 intel_edp_backlight_on(intel_dp); 1611 intel_edp_backlight_on(intel_dp);
1607 intel_psr_enable(intel_dp); 1612 intel_psr_enable(intel_dp);
1613 intel_edp_drrs_enable(intel_dp);
1608 } 1614 }
1609 1615
1610 if (intel_crtc->config.has_audio) { 1616 if (intel_crtc->config->has_audio) {
1611 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); 1617 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
1612 intel_audio_codec_enable(intel_encoder); 1618 intel_audio_codec_enable(intel_encoder);
1613 } 1619 }
@@ -1622,7 +1628,7 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1622 struct drm_device *dev = encoder->dev; 1628 struct drm_device *dev = encoder->dev;
1623 struct drm_i915_private *dev_priv = dev->dev_private; 1629 struct drm_i915_private *dev_priv = dev->dev_private;
1624 1630
1625 if (intel_crtc->config.has_audio) { 1631 if (intel_crtc->config->has_audio) {
1626 intel_audio_codec_disable(intel_encoder); 1632 intel_audio_codec_disable(intel_encoder);
1627 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); 1633 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1628 } 1634 }
@@ -1630,6 +1636,7 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
1630 if (type == INTEL_OUTPUT_EDP) { 1636 if (type == INTEL_OUTPUT_EDP) {
1631 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1637 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1632 1638
1639 intel_edp_drrs_disable(intel_dp);
1633 intel_psr_disable(intel_dp); 1640 intel_psr_disable(intel_dp);
1634 intel_edp_backlight_off(intel_dp); 1641 intel_edp_backlight_off(intel_dp);
1635 } 1642 }
@@ -2027,11 +2034,11 @@ static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder)
2027} 2034}
2028 2035
2029void intel_ddi_get_config(struct intel_encoder *encoder, 2036void intel_ddi_get_config(struct intel_encoder *encoder,
2030 struct intel_crtc_config *pipe_config) 2037 struct intel_crtc_state *pipe_config)
2031{ 2038{
2032 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 2039 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
2033 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 2040 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2034 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 2041 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2035 struct intel_hdmi *intel_hdmi; 2042 struct intel_hdmi *intel_hdmi;
2036 u32 temp, flags = 0; 2043 u32 temp, flags = 0;
2037 2044
@@ -2045,7 +2052,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
2045 else 2052 else
2046 flags |= DRM_MODE_FLAG_NVSYNC; 2053 flags |= DRM_MODE_FLAG_NVSYNC;
2047 2054
2048 pipe_config->adjusted_mode.flags |= flags; 2055 pipe_config->base.adjusted_mode.flags |= flags;
2049 2056
2050 switch (temp & TRANS_DDI_BPC_MASK) { 2057 switch (temp & TRANS_DDI_BPC_MASK) {
2051 case TRANS_DDI_BPC_6: 2058 case TRANS_DDI_BPC_6:
@@ -2120,7 +2127,7 @@ static void intel_ddi_destroy(struct drm_encoder *encoder)
2120} 2127}
2121 2128
2122static bool intel_ddi_compute_config(struct intel_encoder *encoder, 2129static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2123 struct intel_crtc_config *pipe_config) 2130 struct intel_crtc_state *pipe_config)
2124{ 2131{
2125 int type = encoder->type; 2132 int type = encoder->type;
2126 int port = intel_ddi_get_encoder_port(encoder); 2133 int port = intel_ddi_get_encoder_port(encoder);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 91d8ada8fe6d..3d220a67f865 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -37,6 +37,7 @@
37#include <drm/i915_drm.h> 37#include <drm/i915_drm.h>
38#include "i915_drv.h" 38#include "i915_drv.h"
39#include "i915_trace.h" 39#include "i915_trace.h"
40#include <drm/drm_atomic_helper.h>
40#include <drm/drm_dp_helper.h> 41#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h> 42#include <drm/drm_crtc_helper.h>
42#include <drm/drm_plane_helper.h> 43#include <drm/drm_plane_helper.h>
@@ -76,9 +77,9 @@ static const uint32_t intel_cursor_formats[] = {
76static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); 77static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
77 78
78static void i9xx_crtc_clock_get(struct intel_crtc *crtc, 79static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
79 struct intel_crtc_config *pipe_config); 80 struct intel_crtc_state *pipe_config);
80static void ironlake_pch_clock_get(struct intel_crtc *crtc, 81static void ironlake_pch_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_config *pipe_config); 82 struct intel_crtc_state *pipe_config);
82 83
83static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, 84static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
84 int x, int y, struct drm_framebuffer *old_fb); 85 int x, int y, struct drm_framebuffer *old_fb);
@@ -95,9 +96,9 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc);
95static void haswell_set_pipeconf(struct drm_crtc *crtc); 96static void haswell_set_pipeconf(struct drm_crtc *crtc);
96static void intel_set_pipe_csc(struct drm_crtc *crtc); 97static void intel_set_pipe_csc(struct drm_crtc *crtc);
97static void vlv_prepare_pll(struct intel_crtc *crtc, 98static void vlv_prepare_pll(struct intel_crtc *crtc,
98 const struct intel_crtc_config *pipe_config); 99 const struct intel_crtc_state *pipe_config);
99static void chv_prepare_pll(struct intel_crtc *crtc, 100static void chv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_config *pipe_config); 101 const struct intel_crtc_state *pipe_config);
101static void intel_begin_crtc_commit(struct drm_crtc *crtc); 102static void intel_begin_crtc_commit(struct drm_crtc *crtc);
102static void intel_finish_crtc_commit(struct drm_crtc *crtc); 103static void intel_finish_crtc_commit(struct drm_crtc *crtc);
103 104
@@ -897,7 +898,7 @@ bool intel_crtc_active(struct drm_crtc *crtc)
897 * properly reconstruct framebuffers. 898 * properly reconstruct framebuffers.
898 */ 899 */
899 return intel_crtc->active && crtc->primary->fb && 900 return intel_crtc->active && crtc->primary->fb &&
900 intel_crtc->config.adjusted_mode.crtc_clock; 901 intel_crtc->config->base.adjusted_mode.crtc_clock;
901} 902}
902 903
903enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, 904enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
@@ -906,7 +907,7 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
906 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 907 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
908 909
909 return intel_crtc->config.cpu_transcoder; 910 return intel_crtc->config->cpu_transcoder;
910} 911}
911 912
912static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) 913static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
@@ -948,7 +949,7 @@ static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
948{ 949{
949 struct drm_device *dev = crtc->base.dev; 950 struct drm_device *dev = crtc->base.dev;
950 struct drm_i915_private *dev_priv = dev->dev_private; 951 struct drm_i915_private *dev_priv = dev->dev_private;
951 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; 952 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
952 enum pipe pipe = crtc->pipe; 953 enum pipe pipe = crtc->pipe;
953 954
954 if (INTEL_INFO(dev)->gen >= 4) { 955 if (INTEL_INFO(dev)->gen >= 4) {
@@ -1054,10 +1055,10 @@ intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1054{ 1055{
1055 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 1056 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1056 1057
1057 if (crtc->config.shared_dpll < 0) 1058 if (crtc->config->shared_dpll < 0)
1058 return NULL; 1059 return NULL;
1059 1060
1060 return &dev_priv->shared_dplls[crtc->config.shared_dpll]; 1061 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1061} 1062}
1062 1063
1063/* For ILK+ */ 1064/* For ILK+ */
@@ -1507,7 +1508,7 @@ static void intel_init_dpio(struct drm_device *dev)
1507} 1508}
1508 1509
1509static void vlv_enable_pll(struct intel_crtc *crtc, 1510static void vlv_enable_pll(struct intel_crtc *crtc,
1510 const struct intel_crtc_config *pipe_config) 1511 const struct intel_crtc_state *pipe_config)
1511{ 1512{
1512 struct drm_device *dev = crtc->base.dev; 1513 struct drm_device *dev = crtc->base.dev;
1513 struct drm_i915_private *dev_priv = dev->dev_private; 1514 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1546,7 +1547,7 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
1546} 1547}
1547 1548
1548static void chv_enable_pll(struct intel_crtc *crtc, 1549static void chv_enable_pll(struct intel_crtc *crtc,
1549 const struct intel_crtc_config *pipe_config) 1550 const struct intel_crtc_state *pipe_config)
1550{ 1551{
1551 struct drm_device *dev = crtc->base.dev; 1552 struct drm_device *dev = crtc->base.dev;
1552 struct drm_i915_private *dev_priv = dev->dev_private; 1553 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1601,7 +1602,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
1601 struct drm_device *dev = crtc->base.dev; 1602 struct drm_device *dev = crtc->base.dev;
1602 struct drm_i915_private *dev_priv = dev->dev_private; 1603 struct drm_i915_private *dev_priv = dev->dev_private;
1603 int reg = DPLL(crtc->pipe); 1604 int reg = DPLL(crtc->pipe);
1604 u32 dpll = crtc->config.dpll_hw_state.dpll; 1605 u32 dpll = crtc->config->dpll_hw_state.dpll;
1605 1606
1606 assert_pipe_disabled(dev_priv, crtc->pipe); 1607 assert_pipe_disabled(dev_priv, crtc->pipe);
1607 1608
@@ -1631,7 +1632,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
1631 1632
1632 if (INTEL_INFO(dev)->gen >= 4) { 1633 if (INTEL_INFO(dev)->gen >= 4) {
1633 I915_WRITE(DPLL_MD(crtc->pipe), 1634 I915_WRITE(DPLL_MD(crtc->pipe),
1634 crtc->config.dpll_hw_state.dpll_md); 1635 crtc->config->dpll_hw_state.dpll_md);
1635 } else { 1636 } else {
1636 /* The pixel multiplier can only be updated once the 1637 /* The pixel multiplier can only be updated once the
1637 * DPLL is enabled and the clocks are stable. 1638 * DPLL is enabled and the clocks are stable.
@@ -2036,7 +2037,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
2036 else 2037 else
2037 assert_pll_enabled(dev_priv, pipe); 2038 assert_pll_enabled(dev_priv, pipe);
2038 else { 2039 else {
2039 if (crtc->config.has_pch_encoder) { 2040 if (crtc->config->has_pch_encoder) {
2040 /* if driving the PCH, we need FDI enabled */ 2041 /* if driving the PCH, we need FDI enabled */
2041 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); 2042 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2042 assert_fdi_tx_pll_enabled(dev_priv, 2043 assert_fdi_tx_pll_enabled(dev_priv,
@@ -2070,7 +2071,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
2070static void intel_disable_pipe(struct intel_crtc *crtc) 2071static void intel_disable_pipe(struct intel_crtc *crtc)
2071{ 2072{
2072 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 2073 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2073 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; 2074 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2074 enum pipe pipe = crtc->pipe; 2075 enum pipe pipe = crtc->pipe;
2075 int reg; 2076 int reg;
2076 u32 val; 2077 u32 val;
@@ -2092,7 +2093,7 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
2092 * Double wide has implications for planes 2093 * Double wide has implications for planes
2093 * so best keep it disabled when not needed. 2094 * so best keep it disabled when not needed.
2094 */ 2095 */
2095 if (crtc->config.double_wide) 2096 if (crtc->config->double_wide)
2096 val &= ~PIPECONF_DOUBLE_WIDE; 2097 val &= ~PIPECONF_DOUBLE_WIDE;
2097 2098
2098 /* Don't disable pipe or pipe PLLs if needed */ 2099 /* Don't disable pipe or pipe PLLs if needed */
@@ -2188,11 +2189,12 @@ static bool need_vtd_wa(struct drm_device *dev)
2188 return false; 2189 return false;
2189} 2190}
2190 2191
2191static int intel_align_height(struct drm_device *dev, int height, bool tiled) 2192int
2193intel_fb_align_height(struct drm_device *dev, int height, unsigned int tiling)
2192{ 2194{
2193 int tile_height; 2195 int tile_height;
2194 2196
2195 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; 2197 tile_height = tiling ? (IS_GEN2(dev) ? 16 : 8) : 1;
2196 return ALIGN(height, tile_height); 2198 return ALIGN(height, tile_height);
2197} 2199}
2198 2200
@@ -2315,7 +2317,7 @@ unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2315 } 2317 }
2316} 2318}
2317 2319
2318int intel_format_to_fourcc(int format) 2320static int i9xx_format_to_fourcc(int format)
2319{ 2321{
2320 switch (format) { 2322 switch (format) {
2321 case DISPPLANE_8BPP: 2323 case DISPPLANE_8BPP:
@@ -2336,8 +2338,35 @@ int intel_format_to_fourcc(int format)
2336 } 2338 }
2337} 2339}
2338 2340
2339static bool intel_alloc_plane_obj(struct intel_crtc *crtc, 2341static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2340 struct intel_plane_config *plane_config) 2342{
2343 switch (format) {
2344 case PLANE_CTL_FORMAT_RGB_565:
2345 return DRM_FORMAT_RGB565;
2346 default:
2347 case PLANE_CTL_FORMAT_XRGB_8888:
2348 if (rgb_order) {
2349 if (alpha)
2350 return DRM_FORMAT_ABGR8888;
2351 else
2352 return DRM_FORMAT_XBGR8888;
2353 } else {
2354 if (alpha)
2355 return DRM_FORMAT_ARGB8888;
2356 else
2357 return DRM_FORMAT_XRGB8888;
2358 }
2359 case PLANE_CTL_FORMAT_XRGB_2101010:
2360 if (rgb_order)
2361 return DRM_FORMAT_XBGR2101010;
2362 else
2363 return DRM_FORMAT_XRGB2101010;
2364 }
2365}
2366
2367static bool
2368intel_alloc_plane_obj(struct intel_crtc *crtc,
2369 struct intel_initial_plane_config *plane_config)
2341{ 2370{
2342 struct drm_device *dev = crtc->base.dev; 2371 struct drm_device *dev = crtc->base.dev;
2343 struct drm_i915_gem_object *obj = NULL; 2372 struct drm_i915_gem_object *obj = NULL;
@@ -2352,10 +2381,9 @@ static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2352 if (!obj) 2381 if (!obj)
2353 return false; 2382 return false;
2354 2383
2355 if (plane_config->tiled) { 2384 obj->tiling_mode = plane_config->tiling;
2356 obj->tiling_mode = I915_TILING_X; 2385 if (obj->tiling_mode == I915_TILING_X)
2357 obj->stride = crtc->base.primary->fb->pitches[0]; 2386 obj->stride = crtc->base.primary->fb->pitches[0];
2358 }
2359 2387
2360 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format; 2388 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2361 mode_cmd.width = crtc->base.primary->fb->width; 2389 mode_cmd.width = crtc->base.primary->fb->width;
@@ -2382,8 +2410,9 @@ out_unref_obj:
2382 return false; 2410 return false;
2383} 2411}
2384 2412
2385static void intel_find_plane_obj(struct intel_crtc *intel_crtc, 2413static void
2386 struct intel_plane_config *plane_config) 2414intel_find_plane_obj(struct intel_crtc *intel_crtc,
2415 struct intel_initial_plane_config *plane_config)
2387{ 2416{
2388 struct drm_device *dev = intel_crtc->base.dev; 2417 struct drm_device *dev = intel_crtc->base.dev;
2389 struct drm_i915_private *dev_priv = dev->dev_private; 2418 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2471,13 +2500,13 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2471 * which should always be the user's requested size. 2500 * which should always be the user's requested size.
2472 */ 2501 */
2473 I915_WRITE(DSPSIZE(plane), 2502 I915_WRITE(DSPSIZE(plane),
2474 ((intel_crtc->config.pipe_src_h - 1) << 16) | 2503 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2475 (intel_crtc->config.pipe_src_w - 1)); 2504 (intel_crtc->config->pipe_src_w - 1));
2476 I915_WRITE(DSPPOS(plane), 0); 2505 I915_WRITE(DSPPOS(plane), 0);
2477 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { 2506 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2478 I915_WRITE(PRIMSIZE(plane), 2507 I915_WRITE(PRIMSIZE(plane),
2479 ((intel_crtc->config.pipe_src_h - 1) << 16) | 2508 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2480 (intel_crtc->config.pipe_src_w - 1)); 2509 (intel_crtc->config->pipe_src_w - 1));
2481 I915_WRITE(PRIMPOS(plane), 0); 2510 I915_WRITE(PRIMPOS(plane), 0);
2482 I915_WRITE(PRIMCNSTALPHA(plane), 0); 2511 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2483 } 2512 }
@@ -2532,17 +2561,17 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2532 intel_crtc->dspaddr_offset = linear_offset; 2561 intel_crtc->dspaddr_offset = linear_offset;
2533 } 2562 }
2534 2563
2535 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) { 2564 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2536 dspcntr |= DISPPLANE_ROTATE_180; 2565 dspcntr |= DISPPLANE_ROTATE_180;
2537 2566
2538 x += (intel_crtc->config.pipe_src_w - 1); 2567 x += (intel_crtc->config->pipe_src_w - 1);
2539 y += (intel_crtc->config.pipe_src_h - 1); 2568 y += (intel_crtc->config->pipe_src_h - 1);
2540 2569
2541 /* Finding the last pixel of the last line of the display 2570 /* Finding the last pixel of the last line of the display
2542 data and adding to linear_offset*/ 2571 data and adding to linear_offset*/
2543 linear_offset += 2572 linear_offset +=
2544 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] + 2573 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2545 (intel_crtc->config.pipe_src_w - 1) * pixel_size; 2574 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2546 } 2575 }
2547 2576
2548 I915_WRITE(reg, dspcntr); 2577 I915_WRITE(reg, dspcntr);
@@ -2634,18 +2663,18 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2634 pixel_size, 2663 pixel_size,
2635 fb->pitches[0]); 2664 fb->pitches[0]);
2636 linear_offset -= intel_crtc->dspaddr_offset; 2665 linear_offset -= intel_crtc->dspaddr_offset;
2637 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) { 2666 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2638 dspcntr |= DISPPLANE_ROTATE_180; 2667 dspcntr |= DISPPLANE_ROTATE_180;
2639 2668
2640 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { 2669 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2641 x += (intel_crtc->config.pipe_src_w - 1); 2670 x += (intel_crtc->config->pipe_src_w - 1);
2642 y += (intel_crtc->config.pipe_src_h - 1); 2671 y += (intel_crtc->config->pipe_src_h - 1);
2643 2672
2644 /* Finding the last pixel of the last line of the display 2673 /* Finding the last pixel of the last line of the display
2645 data and adding to linear_offset*/ 2674 data and adding to linear_offset*/
2646 linear_offset += 2675 linear_offset +=
2647 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] + 2676 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2648 (intel_crtc->config.pipe_src_w - 1) * pixel_size; 2677 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2649 } 2678 }
2650 } 2679 }
2651 2680
@@ -2731,7 +2760,7 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
2731 } 2760 }
2732 2761
2733 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; 2762 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2734 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) 2763 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2735 plane_ctl |= PLANE_CTL_ROTATE_180; 2764 plane_ctl |= PLANE_CTL_ROTATE_180;
2736 2765
2737 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); 2766 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
@@ -2744,8 +2773,8 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
2744 I915_WRITE(PLANE_POS(pipe, 0), 0); 2773 I915_WRITE(PLANE_POS(pipe, 0), 0);
2745 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x); 2774 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2746 I915_WRITE(PLANE_SIZE(pipe, 0), 2775 I915_WRITE(PLANE_SIZE(pipe, 0),
2747 (intel_crtc->config.pipe_src_h - 1) << 16 | 2776 (intel_crtc->config->pipe_src_h - 1) << 16 |
2748 (intel_crtc->config.pipe_src_w - 1)); 2777 (intel_crtc->config->pipe_src_w - 1));
2749 I915_WRITE(PLANE_STRIDE(pipe, 0), stride); 2778 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2750 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj)); 2779 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2751 2780
@@ -2941,20 +2970,20 @@ static void intel_update_pipe_size(struct intel_crtc *crtc)
2941 * then update the pipesrc and pfit state, even on the flip path. 2970 * then update the pipesrc and pfit state, even on the flip path.
2942 */ 2971 */
2943 2972
2944 adjusted_mode = &crtc->config.adjusted_mode; 2973 adjusted_mode = &crtc->config->base.adjusted_mode;
2945 2974
2946 I915_WRITE(PIPESRC(crtc->pipe), 2975 I915_WRITE(PIPESRC(crtc->pipe),
2947 ((adjusted_mode->crtc_hdisplay - 1) << 16) | 2976 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2948 (adjusted_mode->crtc_vdisplay - 1)); 2977 (adjusted_mode->crtc_vdisplay - 1));
2949 if (!crtc->config.pch_pfit.enabled && 2978 if (!crtc->config->pch_pfit.enabled &&
2950 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || 2979 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2951 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { 2980 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2952 I915_WRITE(PF_CTL(crtc->pipe), 0); 2981 I915_WRITE(PF_CTL(crtc->pipe), 0);
2953 I915_WRITE(PF_WIN_POS(crtc->pipe), 0); 2982 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2954 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); 2983 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2955 } 2984 }
2956 crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; 2985 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
2957 crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; 2986 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
2958} 2987}
2959 2988
2960static void intel_fdi_normal_train(struct drm_crtc *crtc) 2989static void intel_fdi_normal_train(struct drm_crtc *crtc)
@@ -3001,7 +3030,7 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
3001static bool pipe_has_enabled_pch(struct intel_crtc *crtc) 3030static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3002{ 3031{
3003 return crtc->base.enabled && crtc->active && 3032 return crtc->base.enabled && crtc->active &&
3004 crtc->config.has_pch_encoder; 3033 crtc->config->has_pch_encoder;
3005} 3034}
3006 3035
3007static void ivb_modeset_global_resources(struct drm_device *dev) 3036static void ivb_modeset_global_resources(struct drm_device *dev)
@@ -3056,7 +3085,7 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3056 reg = FDI_TX_CTL(pipe); 3085 reg = FDI_TX_CTL(pipe);
3057 temp = I915_READ(reg); 3086 temp = I915_READ(reg);
3058 temp &= ~FDI_DP_PORT_WIDTH_MASK; 3087 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3059 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); 3088 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3060 temp &= ~FDI_LINK_TRAIN_NONE; 3089 temp &= ~FDI_LINK_TRAIN_NONE;
3061 temp |= FDI_LINK_TRAIN_PATTERN_1; 3090 temp |= FDI_LINK_TRAIN_PATTERN_1;
3062 I915_WRITE(reg, temp | FDI_TX_ENABLE); 3091 I915_WRITE(reg, temp | FDI_TX_ENABLE);
@@ -3154,7 +3183,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
3154 reg = FDI_TX_CTL(pipe); 3183 reg = FDI_TX_CTL(pipe);
3155 temp = I915_READ(reg); 3184 temp = I915_READ(reg);
3156 temp &= ~FDI_DP_PORT_WIDTH_MASK; 3185 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3157 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); 3186 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3158 temp &= ~FDI_LINK_TRAIN_NONE; 3187 temp &= ~FDI_LINK_TRAIN_NONE;
3159 temp |= FDI_LINK_TRAIN_PATTERN_1; 3188 temp |= FDI_LINK_TRAIN_PATTERN_1;
3160 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 3189 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
@@ -3305,7 +3334,7 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3305 reg = FDI_TX_CTL(pipe); 3334 reg = FDI_TX_CTL(pipe);
3306 temp = I915_READ(reg); 3335 temp = I915_READ(reg);
3307 temp &= ~FDI_DP_PORT_WIDTH_MASK; 3336 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3308 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); 3337 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3309 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; 3338 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3310 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 3339 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3311 temp |= snb_b_fdi_train_param[j/2]; 3340 temp |= snb_b_fdi_train_param[j/2];
@@ -3393,7 +3422,7 @@ static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3393 reg = FDI_RX_CTL(pipe); 3422 reg = FDI_RX_CTL(pipe);
3394 temp = I915_READ(reg); 3423 temp = I915_READ(reg);
3395 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); 3424 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3396 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); 3425 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3397 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; 3426 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3398 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); 3427 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3399 3428
@@ -3577,7 +3606,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
3577{ 3606{
3578 struct drm_device *dev = crtc->dev; 3607 struct drm_device *dev = crtc->dev;
3579 struct drm_i915_private *dev_priv = dev->dev_private; 3608 struct drm_i915_private *dev_priv = dev->dev_private;
3580 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; 3609 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3581 u32 divsel, phaseinc, auxdiv, phasedir = 0; 3610 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3582 u32 temp; 3611 u32 temp;
3583 3612
@@ -3666,7 +3695,7 @@ static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3666{ 3695{
3667 struct drm_device *dev = crtc->base.dev; 3696 struct drm_device *dev = crtc->base.dev;
3668 struct drm_i915_private *dev_priv = dev->dev_private; 3697 struct drm_i915_private *dev_priv = dev->dev_private;
3669 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; 3698 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3670 3699
3671 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), 3700 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3672 I915_READ(HTOTAL(cpu_transcoder))); 3701 I915_READ(HTOTAL(cpu_transcoder)));
@@ -3712,7 +3741,7 @@ static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3712 case PIPE_A: 3741 case PIPE_A:
3713 break; 3742 break;
3714 case PIPE_B: 3743 case PIPE_B:
3715 if (intel_crtc->config.fdi_lanes > 2) 3744 if (intel_crtc->config->fdi_lanes > 2)
3716 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); 3745 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3717 else 3746 else
3718 cpt_enable_fdi_bc_bifurcation(dev); 3747 cpt_enable_fdi_bc_bifurcation(dev);
@@ -3764,7 +3793,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
3764 temp = I915_READ(PCH_DPLL_SEL); 3793 temp = I915_READ(PCH_DPLL_SEL);
3765 temp |= TRANS_DPLL_ENABLE(pipe); 3794 temp |= TRANS_DPLL_ENABLE(pipe);
3766 sel = TRANS_DPLLB_SEL(pipe); 3795 sel = TRANS_DPLLB_SEL(pipe);
3767 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) 3796 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3768 temp |= sel; 3797 temp |= sel;
3769 else 3798 else
3770 temp &= ~sel; 3799 temp &= ~sel;
@@ -3787,7 +3816,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
3787 intel_fdi_normal_train(crtc); 3816 intel_fdi_normal_train(crtc);
3788 3817
3789 /* For PCH DP, enable TRANS_DP_CTL */ 3818 /* For PCH DP, enable TRANS_DP_CTL */
3790 if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) { 3819 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3791 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; 3820 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3792 reg = TRANS_DP_CTL(pipe); 3821 reg = TRANS_DP_CTL(pipe);
3793 temp = I915_READ(reg); 3822 temp = I915_READ(reg);
@@ -3828,7 +3857,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
3828 struct drm_device *dev = crtc->dev; 3857 struct drm_device *dev = crtc->dev;
3829 struct drm_i915_private *dev_priv = dev->dev_private; 3858 struct drm_i915_private *dev_priv = dev->dev_private;
3830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3831 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 3860 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3832 3861
3833 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); 3862 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3834 3863
@@ -3858,10 +3887,11 @@ void intel_put_shared_dpll(struct intel_crtc *crtc)
3858 WARN_ON(pll->active); 3887 WARN_ON(pll->active);
3859 } 3888 }
3860 3889
3861 crtc->config.shared_dpll = DPLL_ID_PRIVATE; 3890 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
3862} 3891}
3863 3892
3864struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) 3893struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
3894 struct intel_crtc_state *crtc_state)
3865{ 3895{
3866 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 3896 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3867 struct intel_shared_dpll *pll; 3897 struct intel_shared_dpll *pll;
@@ -3887,7 +3917,7 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3887 if (pll->new_config->crtc_mask == 0) 3917 if (pll->new_config->crtc_mask == 0)
3888 continue; 3918 continue;
3889 3919
3890 if (memcmp(&crtc->new_config->dpll_hw_state, 3920 if (memcmp(&crtc_state->dpll_hw_state,
3891 &pll->new_config->hw_state, 3921 &pll->new_config->hw_state,
3892 sizeof(pll->new_config->hw_state)) == 0) { 3922 sizeof(pll->new_config->hw_state)) == 0) {
3893 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", 3923 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
@@ -3912,9 +3942,9 @@ struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3912 3942
3913found: 3943found:
3914 if (pll->new_config->crtc_mask == 0) 3944 if (pll->new_config->crtc_mask == 0)
3915 pll->new_config->hw_state = crtc->new_config->dpll_hw_state; 3945 pll->new_config->hw_state = crtc_state->dpll_hw_state;
3916 3946
3917 crtc->new_config->shared_dpll = i; 3947 crtc_state->shared_dpll = i;
3918 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, 3948 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3919 pipe_name(crtc->pipe)); 3949 pipe_name(crtc->pipe));
3920 3950
@@ -4011,10 +4041,10 @@ static void skylake_pfit_enable(struct intel_crtc *crtc)
4011 struct drm_i915_private *dev_priv = dev->dev_private; 4041 struct drm_i915_private *dev_priv = dev->dev_private;
4012 int pipe = crtc->pipe; 4042 int pipe = crtc->pipe;
4013 4043
4014 if (crtc->config.pch_pfit.enabled) { 4044 if (crtc->config->pch_pfit.enabled) {
4015 I915_WRITE(PS_CTL(pipe), PS_ENABLE); 4045 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4016 I915_WRITE(PS_WIN_POS(pipe), crtc->config.pch_pfit.pos); 4046 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4017 I915_WRITE(PS_WIN_SZ(pipe), crtc->config.pch_pfit.size); 4047 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4018 } 4048 }
4019} 4049}
4020 4050
@@ -4024,7 +4054,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc)
4024 struct drm_i915_private *dev_priv = dev->dev_private; 4054 struct drm_i915_private *dev_priv = dev->dev_private;
4025 int pipe = crtc->pipe; 4055 int pipe = crtc->pipe;
4026 4056
4027 if (crtc->config.pch_pfit.enabled) { 4057 if (crtc->config->pch_pfit.enabled) {
4028 /* Force use of hard-coded filter coefficients 4058 /* Force use of hard-coded filter coefficients
4029 * as some pre-programmed values are broken, 4059 * as some pre-programmed values are broken,
4030 * e.g. x201. 4060 * e.g. x201.
@@ -4034,8 +4064,8 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc)
4034 PF_PIPE_SEL_IVB(pipe)); 4064 PF_PIPE_SEL_IVB(pipe));
4035 else 4065 else
4036 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); 4066 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4037 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); 4067 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4038 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); 4068 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4039 } 4069 }
4040} 4070}
4041 4071
@@ -4072,7 +4102,7 @@ void hsw_enable_ips(struct intel_crtc *crtc)
4072 struct drm_device *dev = crtc->base.dev; 4102 struct drm_device *dev = crtc->base.dev;
4073 struct drm_i915_private *dev_priv = dev->dev_private; 4103 struct drm_i915_private *dev_priv = dev->dev_private;
4074 4104
4075 if (!crtc->config.ips_enabled) 4105 if (!crtc->config->ips_enabled)
4076 return; 4106 return;
4077 4107
4078 /* We can only enable IPS after we enable a plane and wait for a vblank */ 4108 /* We can only enable IPS after we enable a plane and wait for a vblank */
@@ -4105,7 +4135,7 @@ void hsw_disable_ips(struct intel_crtc *crtc)
4105 struct drm_device *dev = crtc->base.dev; 4135 struct drm_device *dev = crtc->base.dev;
4106 struct drm_i915_private *dev_priv = dev->dev_private; 4136 struct drm_i915_private *dev_priv = dev->dev_private;
4107 4137
4108 if (!crtc->config.ips_enabled) 4138 if (!crtc->config->ips_enabled)
4109 return; 4139 return;
4110 4140
4111 assert_plane_enabled(dev_priv, crtc->plane); 4141 assert_plane_enabled(dev_priv, crtc->plane);
@@ -4154,7 +4184,7 @@ static void intel_crtc_load_lut(struct drm_crtc *crtc)
4154 /* Workaround : Do not read or write the pipe palette/gamma data while 4184 /* Workaround : Do not read or write the pipe palette/gamma data while
4155 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. 4185 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4156 */ 4186 */
4157 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && 4187 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4158 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == 4188 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4159 GAMMA_MODE_MODE_SPLIT)) { 4189 GAMMA_MODE_MODE_SPLIT)) {
4160 hsw_disable_ips(intel_crtc); 4190 hsw_disable_ips(intel_crtc);
@@ -4256,17 +4286,17 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
4256 if (intel_crtc->active) 4286 if (intel_crtc->active)
4257 return; 4287 return;
4258 4288
4259 if (intel_crtc->config.has_pch_encoder) 4289 if (intel_crtc->config->has_pch_encoder)
4260 intel_prepare_shared_dpll(intel_crtc); 4290 intel_prepare_shared_dpll(intel_crtc);
4261 4291
4262 if (intel_crtc->config.has_dp_encoder) 4292 if (intel_crtc->config->has_dp_encoder)
4263 intel_dp_set_m_n(intel_crtc); 4293 intel_dp_set_m_n(intel_crtc);
4264 4294
4265 intel_set_pipe_timings(intel_crtc); 4295 intel_set_pipe_timings(intel_crtc);
4266 4296
4267 if (intel_crtc->config.has_pch_encoder) { 4297 if (intel_crtc->config->has_pch_encoder) {
4268 intel_cpu_transcoder_set_m_n(intel_crtc, 4298 intel_cpu_transcoder_set_m_n(intel_crtc,
4269 &intel_crtc->config.fdi_m_n, NULL); 4299 &intel_crtc->config->fdi_m_n, NULL);
4270 } 4300 }
4271 4301
4272 ironlake_set_pipeconf(crtc); 4302 ironlake_set_pipeconf(crtc);
@@ -4280,7 +4310,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
4280 if (encoder->pre_enable) 4310 if (encoder->pre_enable)
4281 encoder->pre_enable(encoder); 4311 encoder->pre_enable(encoder);
4282 4312
4283 if (intel_crtc->config.has_pch_encoder) { 4313 if (intel_crtc->config->has_pch_encoder) {
4284 /* Note: FDI PLL enabling _must_ be done before we enable the 4314 /* Note: FDI PLL enabling _must_ be done before we enable the
4285 * cpu pipes, hence this is separate from all the other fdi/pch 4315 * cpu pipes, hence this is separate from all the other fdi/pch
4286 * enabling. */ 4316 * enabling. */
@@ -4301,7 +4331,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
4301 intel_update_watermarks(crtc); 4331 intel_update_watermarks(crtc);
4302 intel_enable_pipe(intel_crtc); 4332 intel_enable_pipe(intel_crtc);
4303 4333
4304 if (intel_crtc->config.has_pch_encoder) 4334 if (intel_crtc->config->has_pch_encoder)
4305 ironlake_pch_enable(crtc); 4335 ironlake_pch_enable(crtc);
4306 4336
4307 assert_vblank_disabled(crtc); 4337 assert_vblank_disabled(crtc);
@@ -4367,19 +4397,19 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
4367 if (intel_crtc_to_shared_dpll(intel_crtc)) 4397 if (intel_crtc_to_shared_dpll(intel_crtc))
4368 intel_enable_shared_dpll(intel_crtc); 4398 intel_enable_shared_dpll(intel_crtc);
4369 4399
4370 if (intel_crtc->config.has_dp_encoder) 4400 if (intel_crtc->config->has_dp_encoder)
4371 intel_dp_set_m_n(intel_crtc); 4401 intel_dp_set_m_n(intel_crtc);
4372 4402
4373 intel_set_pipe_timings(intel_crtc); 4403 intel_set_pipe_timings(intel_crtc);
4374 4404
4375 if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) { 4405 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4376 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder), 4406 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4377 intel_crtc->config.pixel_multiplier - 1); 4407 intel_crtc->config->pixel_multiplier - 1);
4378 } 4408 }
4379 4409
4380 if (intel_crtc->config.has_pch_encoder) { 4410 if (intel_crtc->config->has_pch_encoder) {
4381 intel_cpu_transcoder_set_m_n(intel_crtc, 4411 intel_cpu_transcoder_set_m_n(intel_crtc,
4382 &intel_crtc->config.fdi_m_n, NULL); 4412 &intel_crtc->config->fdi_m_n, NULL);
4383 } 4413 }
4384 4414
4385 haswell_set_pipeconf(crtc); 4415 haswell_set_pipeconf(crtc);
@@ -4393,7 +4423,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
4393 if (encoder->pre_enable) 4423 if (encoder->pre_enable)
4394 encoder->pre_enable(encoder); 4424 encoder->pre_enable(encoder);
4395 4425
4396 if (intel_crtc->config.has_pch_encoder) { 4426 if (intel_crtc->config->has_pch_encoder) {
4397 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, 4427 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4398 true); 4428 true);
4399 dev_priv->display.fdi_link_train(crtc); 4429 dev_priv->display.fdi_link_train(crtc);
@@ -4418,10 +4448,10 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
4418 intel_update_watermarks(crtc); 4448 intel_update_watermarks(crtc);
4419 intel_enable_pipe(intel_crtc); 4449 intel_enable_pipe(intel_crtc);
4420 4450
4421 if (intel_crtc->config.has_pch_encoder) 4451 if (intel_crtc->config->has_pch_encoder)
4422 lpt_pch_enable(crtc); 4452 lpt_pch_enable(crtc);
4423 4453
4424 if (intel_crtc->config.dp_encoder_is_mst) 4454 if (intel_crtc->config->dp_encoder_is_mst)
4425 intel_ddi_set_vc_payload_alloc(crtc, true); 4455 intel_ddi_set_vc_payload_alloc(crtc, true);
4426 4456
4427 assert_vblank_disabled(crtc); 4457 assert_vblank_disabled(crtc);
@@ -4446,7 +4476,7 @@ static void skylake_pfit_disable(struct intel_crtc *crtc)
4446 4476
4447 /* To avoid upsetting the power well on haswell only disable the pfit if 4477 /* To avoid upsetting the power well on haswell only disable the pfit if
4448 * it's in use. The hw state code will make sure we get this right. */ 4478 * it's in use. The hw state code will make sure we get this right. */
4449 if (crtc->config.pch_pfit.enabled) { 4479 if (crtc->config->pch_pfit.enabled) {
4450 I915_WRITE(PS_CTL(pipe), 0); 4480 I915_WRITE(PS_CTL(pipe), 0);
4451 I915_WRITE(PS_WIN_POS(pipe), 0); 4481 I915_WRITE(PS_WIN_POS(pipe), 0);
4452 I915_WRITE(PS_WIN_SZ(pipe), 0); 4482 I915_WRITE(PS_WIN_SZ(pipe), 0);
@@ -4461,7 +4491,7 @@ static void ironlake_pfit_disable(struct intel_crtc *crtc)
4461 4491
4462 /* To avoid upsetting the power well on haswell only disable the pfit if 4492 /* To avoid upsetting the power well on haswell only disable the pfit if
4463 * it's in use. The hw state code will make sure we get this right. */ 4493 * it's in use. The hw state code will make sure we get this right. */
4464 if (crtc->config.pch_pfit.enabled) { 4494 if (crtc->config->pch_pfit.enabled) {
4465 I915_WRITE(PF_CTL(pipe), 0); 4495 I915_WRITE(PF_CTL(pipe), 0);
4466 I915_WRITE(PF_WIN_POS(pipe), 0); 4496 I915_WRITE(PF_WIN_POS(pipe), 0);
4467 I915_WRITE(PF_WIN_SZ(pipe), 0); 4497 I915_WRITE(PF_WIN_SZ(pipe), 0);
@@ -4488,7 +4518,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
4488 drm_crtc_vblank_off(crtc); 4518 drm_crtc_vblank_off(crtc);
4489 assert_vblank_disabled(crtc); 4519 assert_vblank_disabled(crtc);
4490 4520
4491 if (intel_crtc->config.has_pch_encoder) 4521 if (intel_crtc->config->has_pch_encoder)
4492 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); 4522 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4493 4523
4494 intel_disable_pipe(intel_crtc); 4524 intel_disable_pipe(intel_crtc);
@@ -4499,7 +4529,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
4499 if (encoder->post_disable) 4529 if (encoder->post_disable)
4500 encoder->post_disable(encoder); 4530 encoder->post_disable(encoder);
4501 4531
4502 if (intel_crtc->config.has_pch_encoder) { 4532 if (intel_crtc->config->has_pch_encoder) {
4503 ironlake_fdi_disable(crtc); 4533 ironlake_fdi_disable(crtc);
4504 4534
4505 ironlake_disable_pch_transcoder(dev_priv, pipe); 4535 ironlake_disable_pch_transcoder(dev_priv, pipe);
@@ -4539,7 +4569,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
4539 struct drm_i915_private *dev_priv = dev->dev_private; 4569 struct drm_i915_private *dev_priv = dev->dev_private;
4540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4541 struct intel_encoder *encoder; 4571 struct intel_encoder *encoder;
4542 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 4572 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4543 4573
4544 if (!intel_crtc->active) 4574 if (!intel_crtc->active)
4545 return; 4575 return;
@@ -4554,12 +4584,12 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
4554 drm_crtc_vblank_off(crtc); 4584 drm_crtc_vblank_off(crtc);
4555 assert_vblank_disabled(crtc); 4585 assert_vblank_disabled(crtc);
4556 4586
4557 if (intel_crtc->config.has_pch_encoder) 4587 if (intel_crtc->config->has_pch_encoder)
4558 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, 4588 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4559 false); 4589 false);
4560 intel_disable_pipe(intel_crtc); 4590 intel_disable_pipe(intel_crtc);
4561 4591
4562 if (intel_crtc->config.dp_encoder_is_mst) 4592 if (intel_crtc->config->dp_encoder_is_mst)
4563 intel_ddi_set_vc_payload_alloc(crtc, false); 4593 intel_ddi_set_vc_payload_alloc(crtc, false);
4564 4594
4565 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); 4595 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
@@ -4571,7 +4601,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
4571 4601
4572 intel_ddi_disable_pipe_clock(intel_crtc); 4602 intel_ddi_disable_pipe_clock(intel_crtc);
4573 4603
4574 if (intel_crtc->config.has_pch_encoder) { 4604 if (intel_crtc->config->has_pch_encoder) {
4575 lpt_disable_pch_transcoder(dev_priv); 4605 lpt_disable_pch_transcoder(dev_priv);
4576 intel_ddi_fdi_disable(crtc); 4606 intel_ddi_fdi_disable(crtc);
4577 } 4607 }
@@ -4602,9 +4632,9 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc)
4602{ 4632{
4603 struct drm_device *dev = crtc->base.dev; 4633 struct drm_device *dev = crtc->base.dev;
4604 struct drm_i915_private *dev_priv = dev->dev_private; 4634 struct drm_i915_private *dev_priv = dev->dev_private;
4605 struct intel_crtc_config *pipe_config = &crtc->config; 4635 struct intel_crtc_state *pipe_config = crtc->config;
4606 4636
4607 if (!crtc->config.gmch_pfit.control) 4637 if (!pipe_config->gmch_pfit.control)
4608 return; 4638 return;
4609 4639
4610 /* 4640 /*
@@ -4683,8 +4713,8 @@ static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4683 4713
4684 mask = BIT(POWER_DOMAIN_PIPE(pipe)); 4714 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4685 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); 4715 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4686 if (intel_crtc->config.pch_pfit.enabled || 4716 if (intel_crtc->config->pch_pfit.enabled ||
4687 intel_crtc->config.pch_pfit.force_thru) 4717 intel_crtc->config->pch_pfit.force_thru)
4688 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); 4718 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4689 4719
4690 for_each_encoder_on_crtc(dev, crtc, intel_encoder) 4720 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
@@ -4908,7 +4938,7 @@ static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4908 for_each_intel_crtc(dev, intel_crtc) { 4938 for_each_intel_crtc(dev, intel_crtc) {
4909 if (intel_crtc->new_enabled) 4939 if (intel_crtc->new_enabled)
4910 max_pixclk = max(max_pixclk, 4940 max_pixclk = max(max_pixclk,
4911 intel_crtc->new_config->adjusted_mode.crtc_clock); 4941 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
4912 } 4942 }
4913 4943
4914 return max_pixclk; 4944 return max_pixclk;
@@ -4976,12 +5006,12 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
4976 5006
4977 if (!is_dsi) { 5007 if (!is_dsi) {
4978 if (IS_CHERRYVIEW(dev)) 5008 if (IS_CHERRYVIEW(dev))
4979 chv_prepare_pll(intel_crtc, &intel_crtc->config); 5009 chv_prepare_pll(intel_crtc, intel_crtc->config);
4980 else 5010 else
4981 vlv_prepare_pll(intel_crtc, &intel_crtc->config); 5011 vlv_prepare_pll(intel_crtc, intel_crtc->config);
4982 } 5012 }
4983 5013
4984 if (intel_crtc->config.has_dp_encoder) 5014 if (intel_crtc->config->has_dp_encoder)
4985 intel_dp_set_m_n(intel_crtc); 5015 intel_dp_set_m_n(intel_crtc);
4986 5016
4987 intel_set_pipe_timings(intel_crtc); 5017 intel_set_pipe_timings(intel_crtc);
@@ -5005,9 +5035,9 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
5005 5035
5006 if (!is_dsi) { 5036 if (!is_dsi) {
5007 if (IS_CHERRYVIEW(dev)) 5037 if (IS_CHERRYVIEW(dev))
5008 chv_enable_pll(intel_crtc, &intel_crtc->config); 5038 chv_enable_pll(intel_crtc, intel_crtc->config);
5009 else 5039 else
5010 vlv_enable_pll(intel_crtc, &intel_crtc->config); 5040 vlv_enable_pll(intel_crtc, intel_crtc->config);
5011 } 5041 }
5012 5042
5013 for_each_encoder_on_crtc(dev, crtc, encoder) 5043 for_each_encoder_on_crtc(dev, crtc, encoder)
@@ -5038,8 +5068,8 @@ static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5038 struct drm_device *dev = crtc->base.dev; 5068 struct drm_device *dev = crtc->base.dev;
5039 struct drm_i915_private *dev_priv = dev->dev_private; 5069 struct drm_i915_private *dev_priv = dev->dev_private;
5040 5070
5041 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0); 5071 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5042 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1); 5072 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5043} 5073}
5044 5074
5045static void i9xx_crtc_enable(struct drm_crtc *crtc) 5075static void i9xx_crtc_enable(struct drm_crtc *crtc)
@@ -5057,7 +5087,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
5057 5087
5058 i9xx_set_pll_dividers(intel_crtc); 5088 i9xx_set_pll_dividers(intel_crtc);
5059 5089
5060 if (intel_crtc->config.has_dp_encoder) 5090 if (intel_crtc->config->has_dp_encoder)
5061 intel_dp_set_m_n(intel_crtc); 5091 intel_dp_set_m_n(intel_crtc);
5062 5092
5063 intel_set_pipe_timings(intel_crtc); 5093 intel_set_pipe_timings(intel_crtc);
@@ -5109,7 +5139,7 @@ static void i9xx_pfit_disable(struct intel_crtc *crtc)
5109 struct drm_device *dev = crtc->base.dev; 5139 struct drm_device *dev = crtc->base.dev;
5110 struct drm_i915_private *dev_priv = dev->dev_private; 5140 struct drm_i915_private *dev_priv = dev->dev_private;
5111 5141
5112 if (!crtc->config.gmch_pfit.control) 5142 if (!crtc->config->gmch_pfit.control)
5113 return; 5143 return;
5114 5144
5115 assert_pipe_disabled(dev_priv, crtc->pipe); 5145 assert_pipe_disabled(dev_priv, crtc->pipe);
@@ -5367,7 +5397,7 @@ bool intel_connector_get_hw_state(struct intel_connector *connector)
5367} 5397}
5368 5398
5369static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, 5399static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5370 struct intel_crtc_config *pipe_config) 5400 struct intel_crtc_state *pipe_config)
5371{ 5401{
5372 struct drm_i915_private *dev_priv = dev->dev_private; 5402 struct drm_i915_private *dev_priv = dev->dev_private;
5373 struct intel_crtc *pipe_B_crtc = 5403 struct intel_crtc *pipe_B_crtc =
@@ -5408,7 +5438,7 @@ static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5408 return true; 5438 return true;
5409 case PIPE_C: 5439 case PIPE_C:
5410 if (!pipe_has_enabled_pch(pipe_B_crtc) || 5440 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5411 pipe_B_crtc->config.fdi_lanes <= 2) { 5441 pipe_B_crtc->config->fdi_lanes <= 2) {
5412 if (pipe_config->fdi_lanes > 2) { 5442 if (pipe_config->fdi_lanes > 2) {
5413 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", 5443 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5414 pipe_name(pipe), pipe_config->fdi_lanes); 5444 pipe_name(pipe), pipe_config->fdi_lanes);
@@ -5426,10 +5456,10 @@ static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5426 5456
5427#define RETRY 1 5457#define RETRY 1
5428static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, 5458static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5429 struct intel_crtc_config *pipe_config) 5459 struct intel_crtc_state *pipe_config)
5430{ 5460{
5431 struct drm_device *dev = intel_crtc->base.dev; 5461 struct drm_device *dev = intel_crtc->base.dev;
5432 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 5462 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5433 int lane, link_bw, fdi_dotclock; 5463 int lane, link_bw, fdi_dotclock;
5434 bool setup_ok, needs_recompute = false; 5464 bool setup_ok, needs_recompute = false;
5435 5465
@@ -5472,7 +5502,7 @@ retry:
5472} 5502}
5473 5503
5474static void hsw_compute_ips_config(struct intel_crtc *crtc, 5504static void hsw_compute_ips_config(struct intel_crtc *crtc,
5475 struct intel_crtc_config *pipe_config) 5505 struct intel_crtc_state *pipe_config)
5476{ 5506{
5477 pipe_config->ips_enabled = i915.enable_ips && 5507 pipe_config->ips_enabled = i915.enable_ips &&
5478 hsw_crtc_supports_ips(crtc) && 5508 hsw_crtc_supports_ips(crtc) &&
@@ -5480,11 +5510,11 @@ static void hsw_compute_ips_config(struct intel_crtc *crtc,
5480} 5510}
5481 5511
5482static int intel_crtc_compute_config(struct intel_crtc *crtc, 5512static int intel_crtc_compute_config(struct intel_crtc *crtc,
5483 struct intel_crtc_config *pipe_config) 5513 struct intel_crtc_state *pipe_config)
5484{ 5514{
5485 struct drm_device *dev = crtc->base.dev; 5515 struct drm_device *dev = crtc->base.dev;
5486 struct drm_i915_private *dev_priv = dev->dev_private; 5516 struct drm_i915_private *dev_priv = dev->dev_private;
5487 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 5517 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5488 5518
5489 /* FIXME should check pixel clock limits on all platforms */ 5519 /* FIXME should check pixel clock limits on all platforms */
5490 if (INTEL_INFO(dev)->gen < 4) { 5520 if (INTEL_INFO(dev)->gen < 4) {
@@ -5729,30 +5759,31 @@ static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5729} 5759}
5730 5760
5731static void i9xx_update_pll_dividers(struct intel_crtc *crtc, 5761static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5762 struct intel_crtc_state *crtc_state,
5732 intel_clock_t *reduced_clock) 5763 intel_clock_t *reduced_clock)
5733{ 5764{
5734 struct drm_device *dev = crtc->base.dev; 5765 struct drm_device *dev = crtc->base.dev;
5735 u32 fp, fp2 = 0; 5766 u32 fp, fp2 = 0;
5736 5767
5737 if (IS_PINEVIEW(dev)) { 5768 if (IS_PINEVIEW(dev)) {
5738 fp = pnv_dpll_compute_fp(&crtc->new_config->dpll); 5769 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5739 if (reduced_clock) 5770 if (reduced_clock)
5740 fp2 = pnv_dpll_compute_fp(reduced_clock); 5771 fp2 = pnv_dpll_compute_fp(reduced_clock);
5741 } else { 5772 } else {
5742 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll); 5773 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5743 if (reduced_clock) 5774 if (reduced_clock)
5744 fp2 = i9xx_dpll_compute_fp(reduced_clock); 5775 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5745 } 5776 }
5746 5777
5747 crtc->new_config->dpll_hw_state.fp0 = fp; 5778 crtc_state->dpll_hw_state.fp0 = fp;
5748 5779
5749 crtc->lowfreq_avail = false; 5780 crtc->lowfreq_avail = false;
5750 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && 5781 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5751 reduced_clock && i915.powersave) { 5782 reduced_clock && i915.powersave) {
5752 crtc->new_config->dpll_hw_state.fp1 = fp2; 5783 crtc_state->dpll_hw_state.fp1 = fp2;
5753 crtc->lowfreq_avail = true; 5784 crtc->lowfreq_avail = true;
5754 } else { 5785 } else {
5755 crtc->new_config->dpll_hw_state.fp1 = fp; 5786 crtc_state->dpll_hw_state.fp1 = fp;
5756 } 5787 }
5757} 5788}
5758 5789
@@ -5805,7 +5836,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5805 struct drm_device *dev = crtc->base.dev; 5836 struct drm_device *dev = crtc->base.dev;
5806 struct drm_i915_private *dev_priv = dev->dev_private; 5837 struct drm_i915_private *dev_priv = dev->dev_private;
5807 int pipe = crtc->pipe; 5838 int pipe = crtc->pipe;
5808 enum transcoder transcoder = crtc->config.cpu_transcoder; 5839 enum transcoder transcoder = crtc->config->cpu_transcoder;
5809 5840
5810 if (INTEL_INFO(dev)->gen >= 5) { 5841 if (INTEL_INFO(dev)->gen >= 5) {
5811 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); 5842 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
@@ -5817,7 +5848,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5817 * registers are not unnecessarily accessed). 5848 * registers are not unnecessarily accessed).
5818 */ 5849 */
5819 if (m2_n2 && INTEL_INFO(dev)->gen < 8 && 5850 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5820 crtc->config.has_drrs) { 5851 crtc->config->has_drrs) {
5821 I915_WRITE(PIPE_DATA_M2(transcoder), 5852 I915_WRITE(PIPE_DATA_M2(transcoder),
5822 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); 5853 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5823 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); 5854 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
@@ -5834,15 +5865,15 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5834 5865
5835void intel_dp_set_m_n(struct intel_crtc *crtc) 5866void intel_dp_set_m_n(struct intel_crtc *crtc)
5836{ 5867{
5837 if (crtc->config.has_pch_encoder) 5868 if (crtc->config->has_pch_encoder)
5838 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); 5869 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
5839 else 5870 else
5840 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n, 5871 intel_cpu_transcoder_set_m_n(crtc, &crtc->config->dp_m_n,
5841 &crtc->config.dp_m2_n2); 5872 &crtc->config->dp_m2_n2);
5842} 5873}
5843 5874
5844static void vlv_update_pll(struct intel_crtc *crtc, 5875static void vlv_update_pll(struct intel_crtc *crtc,
5845 struct intel_crtc_config *pipe_config) 5876 struct intel_crtc_state *pipe_config)
5846{ 5877{
5847 u32 dpll, dpll_md; 5878 u32 dpll, dpll_md;
5848 5879
@@ -5865,7 +5896,7 @@ static void vlv_update_pll(struct intel_crtc *crtc,
5865} 5896}
5866 5897
5867static void vlv_prepare_pll(struct intel_crtc *crtc, 5898static void vlv_prepare_pll(struct intel_crtc *crtc,
5868 const struct intel_crtc_config *pipe_config) 5899 const struct intel_crtc_state *pipe_config)
5869{ 5900{
5870 struct drm_device *dev = crtc->base.dev; 5901 struct drm_device *dev = crtc->base.dev;
5871 struct drm_i915_private *dev_priv = dev->dev_private; 5902 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5926,7 +5957,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
5926 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), 5957 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5927 0x00d0000f); 5958 0x00d0000f);
5928 5959
5929 if (crtc->config.has_dp_encoder) { 5960 if (pipe_config->has_dp_encoder) {
5930 /* Use SSC source */ 5961 /* Use SSC source */
5931 if (pipe == PIPE_A) 5962 if (pipe == PIPE_A)
5932 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 5963 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
@@ -5956,7 +5987,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
5956} 5987}
5957 5988
5958static void chv_update_pll(struct intel_crtc *crtc, 5989static void chv_update_pll(struct intel_crtc *crtc,
5959 struct intel_crtc_config *pipe_config) 5990 struct intel_crtc_state *pipe_config)
5960{ 5991{
5961 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | 5992 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5962 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | 5993 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
@@ -5969,7 +6000,7 @@ static void chv_update_pll(struct intel_crtc *crtc,
5969} 6000}
5970 6001
5971static void chv_prepare_pll(struct intel_crtc *crtc, 6002static void chv_prepare_pll(struct intel_crtc *crtc,
5972 const struct intel_crtc_config *pipe_config) 6003 const struct intel_crtc_state *pipe_config)
5973{ 6004{
5974 struct drm_device *dev = crtc->base.dev; 6005 struct drm_device *dev = crtc->base.dev;
5975 struct drm_i915_private *dev_priv = dev->dev_private; 6006 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6054,7 +6085,7 @@ void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6054{ 6085{
6055 struct intel_crtc *crtc = 6086 struct intel_crtc *crtc =
6056 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); 6087 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6057 struct intel_crtc_config pipe_config = { 6088 struct intel_crtc_state pipe_config = {
6058 .pixel_multiplier = 1, 6089 .pixel_multiplier = 1,
6059 .dpll = *dpll, 6090 .dpll = *dpll,
6060 }; 6091 };
@@ -6087,6 +6118,7 @@ void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6087} 6118}
6088 6119
6089static void i9xx_update_pll(struct intel_crtc *crtc, 6120static void i9xx_update_pll(struct intel_crtc *crtc,
6121 struct intel_crtc_state *crtc_state,
6090 intel_clock_t *reduced_clock, 6122 intel_clock_t *reduced_clock,
6091 int num_connectors) 6123 int num_connectors)
6092{ 6124{
@@ -6094,9 +6126,9 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
6094 struct drm_i915_private *dev_priv = dev->dev_private; 6126 struct drm_i915_private *dev_priv = dev->dev_private;
6095 u32 dpll; 6127 u32 dpll;
6096 bool is_sdvo; 6128 bool is_sdvo;
6097 struct dpll *clock = &crtc->new_config->dpll; 6129 struct dpll *clock = &crtc_state->dpll;
6098 6130
6099 i9xx_update_pll_dividers(crtc, reduced_clock); 6131 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6100 6132
6101 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) || 6133 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6102 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI); 6134 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
@@ -6109,14 +6141,14 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
6109 dpll |= DPLLB_MODE_DAC_SERIAL; 6141 dpll |= DPLLB_MODE_DAC_SERIAL;
6110 6142
6111 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { 6143 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6112 dpll |= (crtc->new_config->pixel_multiplier - 1) 6144 dpll |= (crtc_state->pixel_multiplier - 1)
6113 << SDVO_MULTIPLIER_SHIFT_HIRES; 6145 << SDVO_MULTIPLIER_SHIFT_HIRES;
6114 } 6146 }
6115 6147
6116 if (is_sdvo) 6148 if (is_sdvo)
6117 dpll |= DPLL_SDVO_HIGH_SPEED; 6149 dpll |= DPLL_SDVO_HIGH_SPEED;
6118 6150
6119 if (crtc->new_config->has_dp_encoder) 6151 if (crtc_state->has_dp_encoder)
6120 dpll |= DPLL_SDVO_HIGH_SPEED; 6152 dpll |= DPLL_SDVO_HIGH_SPEED;
6121 6153
6122 /* compute bitmask from p1 value */ 6154 /* compute bitmask from p1 value */
@@ -6144,7 +6176,7 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
6144 if (INTEL_INFO(dev)->gen >= 4) 6176 if (INTEL_INFO(dev)->gen >= 4)
6145 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); 6177 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6146 6178
6147 if (crtc->new_config->sdvo_tv_clock) 6179 if (crtc_state->sdvo_tv_clock)
6148 dpll |= PLL_REF_INPUT_TVCLKINBC; 6180 dpll |= PLL_REF_INPUT_TVCLKINBC;
6149 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && 6181 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6150 intel_panel_use_ssc(dev_priv) && num_connectors < 2) 6182 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
@@ -6153,25 +6185,26 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
6153 dpll |= PLL_REF_INPUT_DREFCLK; 6185 dpll |= PLL_REF_INPUT_DREFCLK;
6154 6186
6155 dpll |= DPLL_VCO_ENABLE; 6187 dpll |= DPLL_VCO_ENABLE;
6156 crtc->new_config->dpll_hw_state.dpll = dpll; 6188 crtc_state->dpll_hw_state.dpll = dpll;
6157 6189
6158 if (INTEL_INFO(dev)->gen >= 4) { 6190 if (INTEL_INFO(dev)->gen >= 4) {
6159 u32 dpll_md = (crtc->new_config->pixel_multiplier - 1) 6191 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6160 << DPLL_MD_UDI_MULTIPLIER_SHIFT; 6192 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6161 crtc->new_config->dpll_hw_state.dpll_md = dpll_md; 6193 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6162 } 6194 }
6163} 6195}
6164 6196
6165static void i8xx_update_pll(struct intel_crtc *crtc, 6197static void i8xx_update_pll(struct intel_crtc *crtc,
6198 struct intel_crtc_state *crtc_state,
6166 intel_clock_t *reduced_clock, 6199 intel_clock_t *reduced_clock,
6167 int num_connectors) 6200 int num_connectors)
6168{ 6201{
6169 struct drm_device *dev = crtc->base.dev; 6202 struct drm_device *dev = crtc->base.dev;
6170 struct drm_i915_private *dev_priv = dev->dev_private; 6203 struct drm_i915_private *dev_priv = dev->dev_private;
6171 u32 dpll; 6204 u32 dpll;
6172 struct dpll *clock = &crtc->new_config->dpll; 6205 struct dpll *clock = &crtc_state->dpll;
6173 6206
6174 i9xx_update_pll_dividers(crtc, reduced_clock); 6207 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6175 6208
6176 dpll = DPLL_VGA_MODE_DIS; 6209 dpll = DPLL_VGA_MODE_DIS;
6177 6210
@@ -6196,7 +6229,7 @@ static void i8xx_update_pll(struct intel_crtc *crtc,
6196 dpll |= PLL_REF_INPUT_DREFCLK; 6229 dpll |= PLL_REF_INPUT_DREFCLK;
6197 6230
6198 dpll |= DPLL_VCO_ENABLE; 6231 dpll |= DPLL_VCO_ENABLE;
6199 crtc->new_config->dpll_hw_state.dpll = dpll; 6232 crtc_state->dpll_hw_state.dpll = dpll;
6200} 6233}
6201 6234
6202static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) 6235static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
@@ -6204,9 +6237,9 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6204 struct drm_device *dev = intel_crtc->base.dev; 6237 struct drm_device *dev = intel_crtc->base.dev;
6205 struct drm_i915_private *dev_priv = dev->dev_private; 6238 struct drm_i915_private *dev_priv = dev->dev_private;
6206 enum pipe pipe = intel_crtc->pipe; 6239 enum pipe pipe = intel_crtc->pipe;
6207 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 6240 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6208 struct drm_display_mode *adjusted_mode = 6241 struct drm_display_mode *adjusted_mode =
6209 &intel_crtc->config.adjusted_mode; 6242 &intel_crtc->config->base.adjusted_mode;
6210 uint32_t crtc_vtotal, crtc_vblank_end; 6243 uint32_t crtc_vtotal, crtc_vblank_end;
6211 int vsyncshift = 0; 6244 int vsyncshift = 0;
6212 6245
@@ -6264,12 +6297,12 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6264 * always be the user's requested size. 6297 * always be the user's requested size.
6265 */ 6298 */
6266 I915_WRITE(PIPESRC(pipe), 6299 I915_WRITE(PIPESRC(pipe),
6267 ((intel_crtc->config.pipe_src_w - 1) << 16) | 6300 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6268 (intel_crtc->config.pipe_src_h - 1)); 6301 (intel_crtc->config->pipe_src_h - 1));
6269} 6302}
6270 6303
6271static void intel_get_pipe_timings(struct intel_crtc *crtc, 6304static void intel_get_pipe_timings(struct intel_crtc *crtc,
6272 struct intel_crtc_config *pipe_config) 6305 struct intel_crtc_state *pipe_config)
6273{ 6306{
6274 struct drm_device *dev = crtc->base.dev; 6307 struct drm_device *dev = crtc->base.dev;
6275 struct drm_i915_private *dev_priv = dev->dev_private; 6308 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6277,56 +6310,56 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
6277 uint32_t tmp; 6310 uint32_t tmp;
6278 6311
6279 tmp = I915_READ(HTOTAL(cpu_transcoder)); 6312 tmp = I915_READ(HTOTAL(cpu_transcoder));
6280 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; 6313 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6281 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; 6314 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6282 tmp = I915_READ(HBLANK(cpu_transcoder)); 6315 tmp = I915_READ(HBLANK(cpu_transcoder));
6283 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; 6316 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6284 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; 6317 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6285 tmp = I915_READ(HSYNC(cpu_transcoder)); 6318 tmp = I915_READ(HSYNC(cpu_transcoder));
6286 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; 6319 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6287 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; 6320 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6288 6321
6289 tmp = I915_READ(VTOTAL(cpu_transcoder)); 6322 tmp = I915_READ(VTOTAL(cpu_transcoder));
6290 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; 6323 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6291 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; 6324 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6292 tmp = I915_READ(VBLANK(cpu_transcoder)); 6325 tmp = I915_READ(VBLANK(cpu_transcoder));
6293 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; 6326 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6294 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; 6327 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6295 tmp = I915_READ(VSYNC(cpu_transcoder)); 6328 tmp = I915_READ(VSYNC(cpu_transcoder));
6296 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; 6329 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6297 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; 6330 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6298 6331
6299 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { 6332 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6300 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; 6333 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6301 pipe_config->adjusted_mode.crtc_vtotal += 1; 6334 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6302 pipe_config->adjusted_mode.crtc_vblank_end += 1; 6335 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6303 } 6336 }
6304 6337
6305 tmp = I915_READ(PIPESRC(crtc->pipe)); 6338 tmp = I915_READ(PIPESRC(crtc->pipe));
6306 pipe_config->pipe_src_h = (tmp & 0xffff) + 1; 6339 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6307 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; 6340 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6308 6341
6309 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; 6342 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6310 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; 6343 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6311} 6344}
6312 6345
6313void intel_mode_from_pipe_config(struct drm_display_mode *mode, 6346void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6314 struct intel_crtc_config *pipe_config) 6347 struct intel_crtc_state *pipe_config)
6315{ 6348{
6316 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; 6349 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6317 mode->htotal = pipe_config->adjusted_mode.crtc_htotal; 6350 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6318 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; 6351 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6319 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; 6352 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6320 6353
6321 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; 6354 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6322 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal; 6355 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6323 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; 6356 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6324 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; 6357 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6325 6358
6326 mode->flags = pipe_config->adjusted_mode.flags; 6359 mode->flags = pipe_config->base.adjusted_mode.flags;
6327 6360
6328 mode->clock = pipe_config->adjusted_mode.crtc_clock; 6361 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6329 mode->flags |= pipe_config->adjusted_mode.flags; 6362 mode->flags |= pipe_config->base.adjusted_mode.flags;
6330} 6363}
6331 6364
6332static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) 6365static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
@@ -6341,17 +6374,17 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6341 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) 6374 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6342 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; 6375 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6343 6376
6344 if (intel_crtc->config.double_wide) 6377 if (intel_crtc->config->double_wide)
6345 pipeconf |= PIPECONF_DOUBLE_WIDE; 6378 pipeconf |= PIPECONF_DOUBLE_WIDE;
6346 6379
6347 /* only g4x and later have fancy bpc/dither controls */ 6380 /* only g4x and later have fancy bpc/dither controls */
6348 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { 6381 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6349 /* Bspec claims that we can't use dithering for 30bpp pipes. */ 6382 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6350 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) 6383 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6351 pipeconf |= PIPECONF_DITHER_EN | 6384 pipeconf |= PIPECONF_DITHER_EN |
6352 PIPECONF_DITHER_TYPE_SP; 6385 PIPECONF_DITHER_TYPE_SP;
6353 6386
6354 switch (intel_crtc->config.pipe_bpp) { 6387 switch (intel_crtc->config->pipe_bpp) {
6355 case 18: 6388 case 18:
6356 pipeconf |= PIPECONF_6BPC; 6389 pipeconf |= PIPECONF_6BPC;
6357 break; 6390 break;
@@ -6376,7 +6409,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6376 } 6409 }
6377 } 6410 }
6378 6411
6379 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 6412 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6380 if (INTEL_INFO(dev)->gen < 4 || 6413 if (INTEL_INFO(dev)->gen < 4 ||
6381 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) 6414 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6382 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 6415 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
@@ -6385,14 +6418,15 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6385 } else 6418 } else
6386 pipeconf |= PIPECONF_PROGRESSIVE; 6419 pipeconf |= PIPECONF_PROGRESSIVE;
6387 6420
6388 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) 6421 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6389 pipeconf |= PIPECONF_COLOR_RANGE_SELECT; 6422 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6390 6423
6391 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); 6424 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6392 POSTING_READ(PIPECONF(intel_crtc->pipe)); 6425 POSTING_READ(PIPECONF(intel_crtc->pipe));
6393} 6426}
6394 6427
6395static int i9xx_crtc_compute_clock(struct intel_crtc *crtc) 6428static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6429 struct intel_crtc_state *crtc_state)
6396{ 6430{
6397 struct drm_device *dev = crtc->base.dev; 6431 struct drm_device *dev = crtc->base.dev;
6398 struct drm_i915_private *dev_priv = dev->dev_private; 6432 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6424,7 +6458,7 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
6424 if (is_dsi) 6458 if (is_dsi)
6425 return 0; 6459 return 0;
6426 6460
6427 if (!crtc->new_config->clock_set) { 6461 if (!crtc_state->clock_set) {
6428 refclk = i9xx_get_refclk(crtc, num_connectors); 6462 refclk = i9xx_get_refclk(crtc, num_connectors);
6429 6463
6430 /* 6464 /*
@@ -6435,7 +6469,7 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
6435 */ 6469 */
6436 limit = intel_limit(crtc, refclk); 6470 limit = intel_limit(crtc, refclk);
6437 ok = dev_priv->display.find_dpll(limit, crtc, 6471 ok = dev_priv->display.find_dpll(limit, crtc,
6438 crtc->new_config->port_clock, 6472 crtc_state->port_clock,
6439 refclk, NULL, &clock); 6473 refclk, NULL, &clock);
6440 if (!ok) { 6474 if (!ok) {
6441 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 6475 DRM_ERROR("Couldn't find PLL settings for mode!\n");
@@ -6456,23 +6490,23 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
6456 &reduced_clock); 6490 &reduced_clock);
6457 } 6491 }
6458 /* Compat-code for transition, will disappear. */ 6492 /* Compat-code for transition, will disappear. */
6459 crtc->new_config->dpll.n = clock.n; 6493 crtc_state->dpll.n = clock.n;
6460 crtc->new_config->dpll.m1 = clock.m1; 6494 crtc_state->dpll.m1 = clock.m1;
6461 crtc->new_config->dpll.m2 = clock.m2; 6495 crtc_state->dpll.m2 = clock.m2;
6462 crtc->new_config->dpll.p1 = clock.p1; 6496 crtc_state->dpll.p1 = clock.p1;
6463 crtc->new_config->dpll.p2 = clock.p2; 6497 crtc_state->dpll.p2 = clock.p2;
6464 } 6498 }
6465 6499
6466 if (IS_GEN2(dev)) { 6500 if (IS_GEN2(dev)) {
6467 i8xx_update_pll(crtc, 6501 i8xx_update_pll(crtc, crtc_state,
6468 has_reduced_clock ? &reduced_clock : NULL, 6502 has_reduced_clock ? &reduced_clock : NULL,
6469 num_connectors); 6503 num_connectors);
6470 } else if (IS_CHERRYVIEW(dev)) { 6504 } else if (IS_CHERRYVIEW(dev)) {
6471 chv_update_pll(crtc, crtc->new_config); 6505 chv_update_pll(crtc, crtc_state);
6472 } else if (IS_VALLEYVIEW(dev)) { 6506 } else if (IS_VALLEYVIEW(dev)) {
6473 vlv_update_pll(crtc, crtc->new_config); 6507 vlv_update_pll(crtc, crtc_state);
6474 } else { 6508 } else {
6475 i9xx_update_pll(crtc, 6509 i9xx_update_pll(crtc, crtc_state,
6476 has_reduced_clock ? &reduced_clock : NULL, 6510 has_reduced_clock ? &reduced_clock : NULL,
6477 num_connectors); 6511 num_connectors);
6478 } 6512 }
@@ -6481,7 +6515,7 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
6481} 6515}
6482 6516
6483static void i9xx_get_pfit_config(struct intel_crtc *crtc, 6517static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6484 struct intel_crtc_config *pipe_config) 6518 struct intel_crtc_state *pipe_config)
6485{ 6519{
6486 struct drm_device *dev = crtc->base.dev; 6520 struct drm_device *dev = crtc->base.dev;
6487 struct drm_i915_private *dev_priv = dev->dev_private; 6521 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6511,7 +6545,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6511} 6545}
6512 6546
6513static void vlv_crtc_clock_get(struct intel_crtc *crtc, 6547static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6514 struct intel_crtc_config *pipe_config) 6548 struct intel_crtc_state *pipe_config)
6515{ 6549{
6516 struct drm_device *dev = crtc->base.dev; 6550 struct drm_device *dev = crtc->base.dev;
6517 struct drm_i915_private *dev_priv = dev->dev_private; 6551 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6540,8 +6574,9 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6540 pipe_config->port_clock = clock.dot / 5; 6574 pipe_config->port_clock = clock.dot / 5;
6541} 6575}
6542 6576
6543static void i9xx_get_plane_config(struct intel_crtc *crtc, 6577static void
6544 struct intel_plane_config *plane_config) 6578i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6579 struct intel_initial_plane_config *plane_config)
6545{ 6580{
6546 struct drm_device *dev = crtc->base.dev; 6581 struct drm_device *dev = crtc->base.dev;
6547 struct drm_i915_private *dev_priv = dev->dev_private; 6582 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6549,27 +6584,30 @@ static void i9xx_get_plane_config(struct intel_crtc *crtc,
6549 int pipe = crtc->pipe, plane = crtc->plane; 6584 int pipe = crtc->pipe, plane = crtc->plane;
6550 int fourcc, pixel_format; 6585 int fourcc, pixel_format;
6551 int aligned_height; 6586 int aligned_height;
6587 struct drm_framebuffer *fb;
6588 struct intel_framebuffer *intel_fb;
6552 6589
6553 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); 6590 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6554 if (!crtc->base.primary->fb) { 6591 if (!intel_fb) {
6555 DRM_DEBUG_KMS("failed to alloc fb\n"); 6592 DRM_DEBUG_KMS("failed to alloc fb\n");
6556 return; 6593 return;
6557 } 6594 }
6558 6595
6596 fb = &intel_fb->base;
6597
6559 val = I915_READ(DSPCNTR(plane)); 6598 val = I915_READ(DSPCNTR(plane));
6560 6599
6561 if (INTEL_INFO(dev)->gen >= 4) 6600 if (INTEL_INFO(dev)->gen >= 4)
6562 if (val & DISPPLANE_TILED) 6601 if (val & DISPPLANE_TILED)
6563 plane_config->tiled = true; 6602 plane_config->tiling = I915_TILING_X;
6564 6603
6565 pixel_format = val & DISPPLANE_PIXFORMAT_MASK; 6604 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6566 fourcc = intel_format_to_fourcc(pixel_format); 6605 fourcc = i9xx_format_to_fourcc(pixel_format);
6567 crtc->base.primary->fb->pixel_format = fourcc; 6606 fb->pixel_format = fourcc;
6568 crtc->base.primary->fb->bits_per_pixel = 6607 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6569 drm_format_plane_cpp(fourcc, 0) * 8;
6570 6608
6571 if (INTEL_INFO(dev)->gen >= 4) { 6609 if (INTEL_INFO(dev)->gen >= 4) {
6572 if (plane_config->tiled) 6610 if (plane_config->tiling)
6573 offset = I915_READ(DSPTILEOFF(plane)); 6611 offset = I915_READ(DSPTILEOFF(plane));
6574 else 6612 else
6575 offset = I915_READ(DSPLINOFF(plane)); 6613 offset = I915_READ(DSPLINOFF(plane));
@@ -6580,29 +6618,27 @@ static void i9xx_get_plane_config(struct intel_crtc *crtc,
6580 plane_config->base = base; 6618 plane_config->base = base;
6581 6619
6582 val = I915_READ(PIPESRC(pipe)); 6620 val = I915_READ(PIPESRC(pipe));
6583 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; 6621 fb->width = ((val >> 16) & 0xfff) + 1;
6584 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; 6622 fb->height = ((val >> 0) & 0xfff) + 1;
6585 6623
6586 val = I915_READ(DSPSTRIDE(pipe)); 6624 val = I915_READ(DSPSTRIDE(pipe));
6587 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0; 6625 fb->pitches[0] = val & 0xffffffc0;
6588 6626
6589 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, 6627 aligned_height = intel_fb_align_height(dev, fb->height,
6590 plane_config->tiled); 6628 plane_config->tiling);
6591 6629
6592 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * 6630 plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
6593 aligned_height);
6594 6631
6595 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 6632 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6596 pipe, plane, crtc->base.primary->fb->width, 6633 pipe_name(pipe), plane, fb->width, fb->height,
6597 crtc->base.primary->fb->height, 6634 fb->bits_per_pixel, base, fb->pitches[0],
6598 crtc->base.primary->fb->bits_per_pixel, base,
6599 crtc->base.primary->fb->pitches[0],
6600 plane_config->size); 6635 plane_config->size);
6601 6636
6637 crtc->base.primary->fb = fb;
6602} 6638}
6603 6639
6604static void chv_crtc_clock_get(struct intel_crtc *crtc, 6640static void chv_crtc_clock_get(struct intel_crtc *crtc,
6605 struct intel_crtc_config *pipe_config) 6641 struct intel_crtc_state *pipe_config)
6606{ 6642{
6607 struct drm_device *dev = crtc->base.dev; 6643 struct drm_device *dev = crtc->base.dev;
6608 struct drm_i915_private *dev_priv = dev->dev_private; 6644 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6632,7 +6668,7 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
6632} 6668}
6633 6669
6634static bool i9xx_get_pipe_config(struct intel_crtc *crtc, 6670static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6635 struct intel_crtc_config *pipe_config) 6671 struct intel_crtc_state *pipe_config)
6636{ 6672{
6637 struct drm_device *dev = crtc->base.dev; 6673 struct drm_device *dev = crtc->base.dev;
6638 struct drm_i915_private *dev_priv = dev->dev_private; 6674 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -7112,7 +7148,7 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7112 7148
7113 val = 0; 7149 val = 0;
7114 7150
7115 switch (intel_crtc->config.pipe_bpp) { 7151 switch (intel_crtc->config->pipe_bpp) {
7116 case 18: 7152 case 18:
7117 val |= PIPECONF_6BPC; 7153 val |= PIPECONF_6BPC;
7118 break; 7154 break;
@@ -7130,15 +7166,15 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7130 BUG(); 7166 BUG();
7131 } 7167 }
7132 7168
7133 if (intel_crtc->config.dither) 7169 if (intel_crtc->config->dither)
7134 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); 7170 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7135 7171
7136 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 7172 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7137 val |= PIPECONF_INTERLACED_ILK; 7173 val |= PIPECONF_INTERLACED_ILK;
7138 else 7174 else
7139 val |= PIPECONF_PROGRESSIVE; 7175 val |= PIPECONF_PROGRESSIVE;
7140 7176
7141 if (intel_crtc->config.limited_color_range) 7177 if (intel_crtc->config->limited_color_range)
7142 val |= PIPECONF_COLOR_RANGE_SELECT; 7178 val |= PIPECONF_COLOR_RANGE_SELECT;
7143 7179
7144 I915_WRITE(PIPECONF(pipe), val); 7180 I915_WRITE(PIPECONF(pipe), val);
@@ -7167,7 +7203,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
7167 * consideration. 7203 * consideration.
7168 */ 7204 */
7169 7205
7170 if (intel_crtc->config.limited_color_range) 7206 if (intel_crtc->config->limited_color_range)
7171 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ 7207 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7172 7208
7173 /* 7209 /*
@@ -7191,7 +7227,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
7191 if (INTEL_INFO(dev)->gen > 6) { 7227 if (INTEL_INFO(dev)->gen > 6) {
7192 uint16_t postoff = 0; 7228 uint16_t postoff = 0;
7193 7229
7194 if (intel_crtc->config.limited_color_range) 7230 if (intel_crtc->config->limited_color_range)
7195 postoff = (16 * (1 << 12) / 255) & 0x1fff; 7231 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7196 7232
7197 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); 7233 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
@@ -7202,7 +7238,7 @@ static void intel_set_pipe_csc(struct drm_crtc *crtc)
7202 } else { 7238 } else {
7203 uint32_t mode = CSC_MODE_YUV_TO_RGB; 7239 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7204 7240
7205 if (intel_crtc->config.limited_color_range) 7241 if (intel_crtc->config->limited_color_range)
7206 mode |= CSC_BLACK_SCREEN_OFFSET; 7242 mode |= CSC_BLACK_SCREEN_OFFSET;
7207 7243
7208 I915_WRITE(PIPE_CSC_MODE(pipe), mode); 7244 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
@@ -7215,15 +7251,15 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
7215 struct drm_i915_private *dev_priv = dev->dev_private; 7251 struct drm_i915_private *dev_priv = dev->dev_private;
7216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 7252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7217 enum pipe pipe = intel_crtc->pipe; 7253 enum pipe pipe = intel_crtc->pipe;
7218 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 7254 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7219 uint32_t val; 7255 uint32_t val;
7220 7256
7221 val = 0; 7257 val = 0;
7222 7258
7223 if (IS_HASWELL(dev) && intel_crtc->config.dither) 7259 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7224 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); 7260 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7225 7261
7226 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) 7262 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7227 val |= PIPECONF_INTERLACED_ILK; 7263 val |= PIPECONF_INTERLACED_ILK;
7228 else 7264 else
7229 val |= PIPECONF_PROGRESSIVE; 7265 val |= PIPECONF_PROGRESSIVE;
@@ -7237,7 +7273,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
7237 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { 7273 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7238 val = 0; 7274 val = 0;
7239 7275
7240 switch (intel_crtc->config.pipe_bpp) { 7276 switch (intel_crtc->config->pipe_bpp) {
7241 case 18: 7277 case 18:
7242 val |= PIPEMISC_DITHER_6_BPC; 7278 val |= PIPEMISC_DITHER_6_BPC;
7243 break; 7279 break;
@@ -7255,7 +7291,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
7255 BUG(); 7291 BUG();
7256 } 7292 }
7257 7293
7258 if (intel_crtc->config.dither) 7294 if (intel_crtc->config->dither)
7259 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; 7295 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7260 7296
7261 I915_WRITE(PIPEMISC(pipe), val); 7297 I915_WRITE(PIPEMISC(pipe), val);
@@ -7263,6 +7299,7 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc)
7263} 7299}
7264 7300
7265static bool ironlake_compute_clocks(struct drm_crtc *crtc, 7301static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7302 struct intel_crtc_state *crtc_state,
7266 intel_clock_t *clock, 7303 intel_clock_t *clock,
7267 bool *has_reduced_clock, 7304 bool *has_reduced_clock,
7268 intel_clock_t *reduced_clock) 7305 intel_clock_t *reduced_clock)
@@ -7285,7 +7322,7 @@ static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7285 */ 7322 */
7286 limit = intel_limit(intel_crtc, refclk); 7323 limit = intel_limit(intel_crtc, refclk);
7287 ret = dev_priv->display.find_dpll(limit, intel_crtc, 7324 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7288 intel_crtc->new_config->port_clock, 7325 crtc_state->port_clock,
7289 refclk, NULL, clock); 7326 refclk, NULL, clock);
7290 if (!ret) 7327 if (!ret)
7291 return false; 7328 return false;
@@ -7324,6 +7361,7 @@ static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7324} 7361}
7325 7362
7326static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, 7363static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7364 struct intel_crtc_state *crtc_state,
7327 u32 *fp, 7365 u32 *fp,
7328 intel_clock_t *reduced_clock, u32 *fp2) 7366 intel_clock_t *reduced_clock, u32 *fp2)
7329{ 7367{
@@ -7361,10 +7399,10 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7361 dev_priv->vbt.lvds_ssc_freq == 100000) || 7399 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7362 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) 7400 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7363 factor = 25; 7401 factor = 25;
7364 } else if (intel_crtc->new_config->sdvo_tv_clock) 7402 } else if (crtc_state->sdvo_tv_clock)
7365 factor = 20; 7403 factor = 20;
7366 7404
7367 if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor)) 7405 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7368 *fp |= FP_CB_TUNE; 7406 *fp |= FP_CB_TUNE;
7369 7407
7370 if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) 7408 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
@@ -7377,20 +7415,20 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7377 else 7415 else
7378 dpll |= DPLLB_MODE_DAC_SERIAL; 7416 dpll |= DPLLB_MODE_DAC_SERIAL;
7379 7417
7380 dpll |= (intel_crtc->new_config->pixel_multiplier - 1) 7418 dpll |= (crtc_state->pixel_multiplier - 1)
7381 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 7419 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7382 7420
7383 if (is_sdvo) 7421 if (is_sdvo)
7384 dpll |= DPLL_SDVO_HIGH_SPEED; 7422 dpll |= DPLL_SDVO_HIGH_SPEED;
7385 if (intel_crtc->new_config->has_dp_encoder) 7423 if (crtc_state->has_dp_encoder)
7386 dpll |= DPLL_SDVO_HIGH_SPEED; 7424 dpll |= DPLL_SDVO_HIGH_SPEED;
7387 7425
7388 /* compute bitmask from p1 value */ 7426 /* compute bitmask from p1 value */
7389 dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 7427 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7390 /* also FPA1 */ 7428 /* also FPA1 */
7391 dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 7429 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7392 7430
7393 switch (intel_crtc->new_config->dpll.p2) { 7431 switch (crtc_state->dpll.p2) {
7394 case 5: 7432 case 5:
7395 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 7433 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7396 break; 7434 break;
@@ -7413,7 +7451,8 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7413 return dpll | DPLL_VCO_ENABLE; 7451 return dpll | DPLL_VCO_ENABLE;
7414} 7452}
7415 7453
7416static int ironlake_crtc_compute_clock(struct intel_crtc *crtc) 7454static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7455 struct intel_crtc_state *crtc_state)
7417{ 7456{
7418 struct drm_device *dev = crtc->base.dev; 7457 struct drm_device *dev = crtc->base.dev;
7419 intel_clock_t clock, reduced_clock; 7458 intel_clock_t clock, reduced_clock;
@@ -7427,39 +7466,39 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
7427 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), 7466 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7428 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); 7467 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7429 7468
7430 ok = ironlake_compute_clocks(&crtc->base, &clock, 7469 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7431 &has_reduced_clock, &reduced_clock); 7470 &has_reduced_clock, &reduced_clock);
7432 if (!ok && !crtc->new_config->clock_set) { 7471 if (!ok && !crtc_state->clock_set) {
7433 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 7472 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7434 return -EINVAL; 7473 return -EINVAL;
7435 } 7474 }
7436 /* Compat-code for transition, will disappear. */ 7475 /* Compat-code for transition, will disappear. */
7437 if (!crtc->new_config->clock_set) { 7476 if (!crtc_state->clock_set) {
7438 crtc->new_config->dpll.n = clock.n; 7477 crtc_state->dpll.n = clock.n;
7439 crtc->new_config->dpll.m1 = clock.m1; 7478 crtc_state->dpll.m1 = clock.m1;
7440 crtc->new_config->dpll.m2 = clock.m2; 7479 crtc_state->dpll.m2 = clock.m2;
7441 crtc->new_config->dpll.p1 = clock.p1; 7480 crtc_state->dpll.p1 = clock.p1;
7442 crtc->new_config->dpll.p2 = clock.p2; 7481 crtc_state->dpll.p2 = clock.p2;
7443 } 7482 }
7444 7483
7445 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ 7484 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7446 if (crtc->new_config->has_pch_encoder) { 7485 if (crtc_state->has_pch_encoder) {
7447 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll); 7486 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7448 if (has_reduced_clock) 7487 if (has_reduced_clock)
7449 fp2 = i9xx_dpll_compute_fp(&reduced_clock); 7488 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7450 7489
7451 dpll = ironlake_compute_dpll(crtc, 7490 dpll = ironlake_compute_dpll(crtc, crtc_state,
7452 &fp, &reduced_clock, 7491 &fp, &reduced_clock,
7453 has_reduced_clock ? &fp2 : NULL); 7492 has_reduced_clock ? &fp2 : NULL);
7454 7493
7455 crtc->new_config->dpll_hw_state.dpll = dpll; 7494 crtc_state->dpll_hw_state.dpll = dpll;
7456 crtc->new_config->dpll_hw_state.fp0 = fp; 7495 crtc_state->dpll_hw_state.fp0 = fp;
7457 if (has_reduced_clock) 7496 if (has_reduced_clock)
7458 crtc->new_config->dpll_hw_state.fp1 = fp2; 7497 crtc_state->dpll_hw_state.fp1 = fp2;
7459 else 7498 else
7460 crtc->new_config->dpll_hw_state.fp1 = fp; 7499 crtc_state->dpll_hw_state.fp1 = fp;
7461 7500
7462 pll = intel_get_shared_dpll(crtc); 7501 pll = intel_get_shared_dpll(crtc, crtc_state);
7463 if (pll == NULL) { 7502 if (pll == NULL) {
7464 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 7503 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7465 pipe_name(crtc->pipe)); 7504 pipe_name(crtc->pipe));
@@ -7513,7 +7552,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7513 * registers are not unnecessarily read). 7552 * registers are not unnecessarily read).
7514 */ 7553 */
7515 if (m2_n2 && INTEL_INFO(dev)->gen < 8 && 7554 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7516 crtc->config.has_drrs) { 7555 crtc->config->has_drrs) {
7517 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); 7556 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7518 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); 7557 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7519 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) 7558 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
@@ -7534,9 +7573,9 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7534} 7573}
7535 7574
7536void intel_dp_get_m_n(struct intel_crtc *crtc, 7575void intel_dp_get_m_n(struct intel_crtc *crtc,
7537 struct intel_crtc_config *pipe_config) 7576 struct intel_crtc_state *pipe_config)
7538{ 7577{
7539 if (crtc->config.has_pch_encoder) 7578 if (pipe_config->has_pch_encoder)
7540 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); 7579 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7541 else 7580 else
7542 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, 7581 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
@@ -7545,14 +7584,14 @@ void intel_dp_get_m_n(struct intel_crtc *crtc,
7545} 7584}
7546 7585
7547static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, 7586static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7548 struct intel_crtc_config *pipe_config) 7587 struct intel_crtc_state *pipe_config)
7549{ 7588{
7550 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, 7589 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7551 &pipe_config->fdi_m_n, NULL); 7590 &pipe_config->fdi_m_n, NULL);
7552} 7591}
7553 7592
7554static void skylake_get_pfit_config(struct intel_crtc *crtc, 7593static void skylake_get_pfit_config(struct intel_crtc *crtc,
7555 struct intel_crtc_config *pipe_config) 7594 struct intel_crtc_state *pipe_config)
7556{ 7595{
7557 struct drm_device *dev = crtc->base.dev; 7596 struct drm_device *dev = crtc->base.dev;
7558 struct drm_i915_private *dev_priv = dev->dev_private; 7597 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -7567,8 +7606,80 @@ static void skylake_get_pfit_config(struct intel_crtc *crtc,
7567 } 7606 }
7568} 7607}
7569 7608
7609static void
7610skylake_get_initial_plane_config(struct intel_crtc *crtc,
7611 struct intel_initial_plane_config *plane_config)
7612{
7613 struct drm_device *dev = crtc->base.dev;
7614 struct drm_i915_private *dev_priv = dev->dev_private;
7615 u32 val, base, offset, stride_mult;
7616 int pipe = crtc->pipe;
7617 int fourcc, pixel_format;
7618 int aligned_height;
7619 struct drm_framebuffer *fb;
7620 struct intel_framebuffer *intel_fb;
7621
7622 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7623 if (!intel_fb) {
7624 DRM_DEBUG_KMS("failed to alloc fb\n");
7625 return;
7626 }
7627
7628 fb = &intel_fb->base;
7629
7630 val = I915_READ(PLANE_CTL(pipe, 0));
7631 if (val & PLANE_CTL_TILED_MASK)
7632 plane_config->tiling = I915_TILING_X;
7633
7634 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7635 fourcc = skl_format_to_fourcc(pixel_format,
7636 val & PLANE_CTL_ORDER_RGBX,
7637 val & PLANE_CTL_ALPHA_MASK);
7638 fb->pixel_format = fourcc;
7639 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7640
7641 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7642 plane_config->base = base;
7643
7644 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7645
7646 val = I915_READ(PLANE_SIZE(pipe, 0));
7647 fb->height = ((val >> 16) & 0xfff) + 1;
7648 fb->width = ((val >> 0) & 0x1fff) + 1;
7649
7650 val = I915_READ(PLANE_STRIDE(pipe, 0));
7651 switch (plane_config->tiling) {
7652 case I915_TILING_NONE:
7653 stride_mult = 64;
7654 break;
7655 case I915_TILING_X:
7656 stride_mult = 512;
7657 break;
7658 default:
7659 MISSING_CASE(plane_config->tiling);
7660 goto error;
7661 }
7662 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7663
7664 aligned_height = intel_fb_align_height(dev, fb->height,
7665 plane_config->tiling);
7666
7667 plane_config->size = ALIGN(fb->pitches[0] * aligned_height, PAGE_SIZE);
7668
7669 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7670 pipe_name(pipe), fb->width, fb->height,
7671 fb->bits_per_pixel, base, fb->pitches[0],
7672 plane_config->size);
7673
7674 crtc->base.primary->fb = fb;
7675 return;
7676
7677error:
7678 kfree(fb);
7679}
7680
7570static void ironlake_get_pfit_config(struct intel_crtc *crtc, 7681static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7571 struct intel_crtc_config *pipe_config) 7682 struct intel_crtc_state *pipe_config)
7572{ 7683{
7573 struct drm_device *dev = crtc->base.dev; 7684 struct drm_device *dev = crtc->base.dev;
7574 struct drm_i915_private *dev_priv = dev->dev_private; 7685 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -7591,68 +7702,71 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7591 } 7702 }
7592} 7703}
7593 7704
7594static void ironlake_get_plane_config(struct intel_crtc *crtc, 7705static void
7595 struct intel_plane_config *plane_config) 7706ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7707 struct intel_initial_plane_config *plane_config)
7596{ 7708{
7597 struct drm_device *dev = crtc->base.dev; 7709 struct drm_device *dev = crtc->base.dev;
7598 struct drm_i915_private *dev_priv = dev->dev_private; 7710 struct drm_i915_private *dev_priv = dev->dev_private;
7599 u32 val, base, offset; 7711 u32 val, base, offset;
7600 int pipe = crtc->pipe, plane = crtc->plane; 7712 int pipe = crtc->pipe;
7601 int fourcc, pixel_format; 7713 int fourcc, pixel_format;
7602 int aligned_height; 7714 int aligned_height;
7715 struct drm_framebuffer *fb;
7716 struct intel_framebuffer *intel_fb;
7603 7717
7604 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); 7718 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7605 if (!crtc->base.primary->fb) { 7719 if (!intel_fb) {
7606 DRM_DEBUG_KMS("failed to alloc fb\n"); 7720 DRM_DEBUG_KMS("failed to alloc fb\n");
7607 return; 7721 return;
7608 } 7722 }
7609 7723
7610 val = I915_READ(DSPCNTR(plane)); 7724 fb = &intel_fb->base;
7725
7726 val = I915_READ(DSPCNTR(pipe));
7611 7727
7612 if (INTEL_INFO(dev)->gen >= 4) 7728 if (INTEL_INFO(dev)->gen >= 4)
7613 if (val & DISPPLANE_TILED) 7729 if (val & DISPPLANE_TILED)
7614 plane_config->tiled = true; 7730 plane_config->tiling = I915_TILING_X;
7615 7731
7616 pixel_format = val & DISPPLANE_PIXFORMAT_MASK; 7732 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7617 fourcc = intel_format_to_fourcc(pixel_format); 7733 fourcc = i9xx_format_to_fourcc(pixel_format);
7618 crtc->base.primary->fb->pixel_format = fourcc; 7734 fb->pixel_format = fourcc;
7619 crtc->base.primary->fb->bits_per_pixel = 7735 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7620 drm_format_plane_cpp(fourcc, 0) * 8;
7621 7736
7622 base = I915_READ(DSPSURF(plane)) & 0xfffff000; 7737 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7623 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 7738 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7624 offset = I915_READ(DSPOFFSET(plane)); 7739 offset = I915_READ(DSPOFFSET(pipe));
7625 } else { 7740 } else {
7626 if (plane_config->tiled) 7741 if (plane_config->tiling)
7627 offset = I915_READ(DSPTILEOFF(plane)); 7742 offset = I915_READ(DSPTILEOFF(pipe));
7628 else 7743 else
7629 offset = I915_READ(DSPLINOFF(plane)); 7744 offset = I915_READ(DSPLINOFF(pipe));
7630 } 7745 }
7631 plane_config->base = base; 7746 plane_config->base = base;
7632 7747
7633 val = I915_READ(PIPESRC(pipe)); 7748 val = I915_READ(PIPESRC(pipe));
7634 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; 7749 fb->width = ((val >> 16) & 0xfff) + 1;
7635 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; 7750 fb->height = ((val >> 0) & 0xfff) + 1;
7636 7751
7637 val = I915_READ(DSPSTRIDE(pipe)); 7752 val = I915_READ(DSPSTRIDE(pipe));
7638 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0; 7753 fb->pitches[0] = val & 0xffffffc0;
7639 7754
7640 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, 7755 aligned_height = intel_fb_align_height(dev, fb->height,
7641 plane_config->tiled); 7756 plane_config->tiling);
7642 7757
7643 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * 7758 plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height);
7644 aligned_height);
7645 7759
7646 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 7760 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7647 pipe, plane, crtc->base.primary->fb->width, 7761 pipe_name(pipe), fb->width, fb->height,
7648 crtc->base.primary->fb->height, 7762 fb->bits_per_pixel, base, fb->pitches[0],
7649 crtc->base.primary->fb->bits_per_pixel, base,
7650 crtc->base.primary->fb->pitches[0],
7651 plane_config->size); 7763 plane_config->size);
7764
7765 crtc->base.primary->fb = fb;
7652} 7766}
7653 7767
7654static bool ironlake_get_pipe_config(struct intel_crtc *crtc, 7768static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7655 struct intel_crtc_config *pipe_config) 7769 struct intel_crtc_state *pipe_config)
7656{ 7770{
7657 struct drm_device *dev = crtc->base.dev; 7771 struct drm_device *dev = crtc->base.dev;
7658 struct drm_i915_private *dev_priv = dev->dev_private; 7772 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -7862,19 +7976,8 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7862 /* 7976 /*
7863 * Make sure we're not on PC8 state before disabling PC8, otherwise 7977 * Make sure we're not on PC8 state before disabling PC8, otherwise
7864 * we'll hang the machine. To prevent PC8 state, just enable force_wake. 7978 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7865 *
7866 * The other problem is that hsw_restore_lcpll() is called as part of
7867 * the runtime PM resume sequence, so we can't just call
7868 * gen6_gt_force_wake_get() because that function calls
7869 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7870 * while we are on the resume sequence. So to solve this problem we have
7871 * to call special forcewake code that doesn't touch runtime PM and
7872 * doesn't enable the forcewake delayed work.
7873 */ 7979 */
7874 spin_lock_irq(&dev_priv->uncore.lock); 7980 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
7875 if (dev_priv->uncore.forcewake_count++ == 0)
7876 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7877 spin_unlock_irq(&dev_priv->uncore.lock);
7878 7981
7879 if (val & LCPLL_POWER_DOWN_ALLOW) { 7982 if (val & LCPLL_POWER_DOWN_ALLOW) {
7880 val &= ~LCPLL_POWER_DOWN_ALLOW; 7983 val &= ~LCPLL_POWER_DOWN_ALLOW;
@@ -7904,11 +8007,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7904 DRM_ERROR("Switching back to LCPLL failed\n"); 8007 DRM_ERROR("Switching back to LCPLL failed\n");
7905 } 8008 }
7906 8009
7907 /* See the big comment above. */ 8010 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
7908 spin_lock_irq(&dev_priv->uncore.lock);
7909 if (--dev_priv->uncore.forcewake_count == 0)
7910 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7911 spin_unlock_irq(&dev_priv->uncore.lock);
7912} 8011}
7913 8012
7914/* 8013/*
@@ -7970,9 +8069,10 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7970 intel_prepare_ddi(dev); 8069 intel_prepare_ddi(dev);
7971} 8070}
7972 8071
7973static int haswell_crtc_compute_clock(struct intel_crtc *crtc) 8072static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8073 struct intel_crtc_state *crtc_state)
7974{ 8074{
7975 if (!intel_ddi_pll_select(crtc)) 8075 if (!intel_ddi_pll_select(crtc, crtc_state))
7976 return -EINVAL; 8076 return -EINVAL;
7977 8077
7978 crtc->lowfreq_avail = false; 8078 crtc->lowfreq_avail = false;
@@ -7982,7 +8082,7 @@ static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
7982 8082
7983static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, 8083static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
7984 enum port port, 8084 enum port port,
7985 struct intel_crtc_config *pipe_config) 8085 struct intel_crtc_state *pipe_config)
7986{ 8086{
7987 u32 temp, dpll_ctl1; 8087 u32 temp, dpll_ctl1;
7988 8088
@@ -8013,7 +8113,7 @@ static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8013 8113
8014static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, 8114static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8015 enum port port, 8115 enum port port,
8016 struct intel_crtc_config *pipe_config) 8116 struct intel_crtc_state *pipe_config)
8017{ 8117{
8018 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); 8118 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8019 8119
@@ -8028,7 +8128,7 @@ static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8028} 8128}
8029 8129
8030static void haswell_get_ddi_port_state(struct intel_crtc *crtc, 8130static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8031 struct intel_crtc_config *pipe_config) 8131 struct intel_crtc_state *pipe_config)
8032{ 8132{
8033 struct drm_device *dev = crtc->base.dev; 8133 struct drm_device *dev = crtc->base.dev;
8034 struct drm_i915_private *dev_priv = dev->dev_private; 8134 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -8070,7 +8170,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8070} 8170}
8071 8171
8072static bool haswell_get_pipe_config(struct intel_crtc *crtc, 8172static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8073 struct intel_crtc_config *pipe_config) 8173 struct intel_crtc_state *pipe_config)
8074{ 8174{
8075 struct drm_device *dev = crtc->base.dev; 8175 struct drm_device *dev = crtc->base.dev;
8076 struct drm_i915_private *dev_priv = dev->dev_private; 8176 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -8233,7 +8333,7 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8233 cntl |= CURSOR_PIPE_CSC_ENABLE; 8333 cntl |= CURSOR_PIPE_CSC_ENABLE;
8234 } 8334 }
8235 8335
8236 if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) 8336 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8237 cntl |= CURSOR_ROTATE_180; 8337 cntl |= CURSOR_ROTATE_180;
8238 8338
8239 if (intel_crtc->cursor_cntl != cntl) { 8339 if (intel_crtc->cursor_cntl != cntl) {
@@ -8264,10 +8364,10 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8264 if (on) 8364 if (on)
8265 base = intel_crtc->cursor_addr; 8365 base = intel_crtc->cursor_addr;
8266 8366
8267 if (x >= intel_crtc->config.pipe_src_w) 8367 if (x >= intel_crtc->config->pipe_src_w)
8268 base = 0; 8368 base = 0;
8269 8369
8270 if (y >= intel_crtc->config.pipe_src_h) 8370 if (y >= intel_crtc->config->pipe_src_h)
8271 base = 0; 8371 base = 0;
8272 8372
8273 if (x < 0) { 8373 if (x < 0) {
@@ -8295,7 +8395,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8295 8395
8296 /* ILK+ do this automagically */ 8396 /* ILK+ do this automagically */
8297 if (HAS_GMCH_DISPLAY(dev) && 8397 if (HAS_GMCH_DISPLAY(dev) &&
8298 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) { 8398 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8299 base += (intel_crtc->cursor_height * 8399 base += (intel_crtc->cursor_height *
8300 intel_crtc->cursor_width - 1) * 4; 8400 intel_crtc->cursor_width - 1) * 4;
8301 } 8401 }
@@ -8565,7 +8665,7 @@ retry:
8565 8665
8566 intel_crtc = to_intel_crtc(crtc); 8666 intel_crtc = to_intel_crtc(crtc);
8567 intel_crtc->new_enabled = true; 8667 intel_crtc->new_enabled = true;
8568 intel_crtc->new_config = &intel_crtc->config; 8668 intel_crtc->new_config = intel_crtc->config;
8569 old->dpms_mode = connector->dpms; 8669 old->dpms_mode = connector->dpms;
8570 old->load_detect_temp = true; 8670 old->load_detect_temp = true;
8571 old->release_fb = NULL; 8671 old->release_fb = NULL;
@@ -8606,7 +8706,7 @@ retry:
8606 fail: 8706 fail:
8607 intel_crtc->new_enabled = crtc->enabled; 8707 intel_crtc->new_enabled = crtc->enabled;
8608 if (intel_crtc->new_enabled) 8708 if (intel_crtc->new_enabled)
8609 intel_crtc->new_config = &intel_crtc->config; 8709 intel_crtc->new_config = intel_crtc->config;
8610 else 8710 else
8611 intel_crtc->new_config = NULL; 8711 intel_crtc->new_config = NULL;
8612fail_unlock: 8712fail_unlock:
@@ -8652,7 +8752,7 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
8652} 8752}
8653 8753
8654static int i9xx_pll_refclk(struct drm_device *dev, 8754static int i9xx_pll_refclk(struct drm_device *dev,
8655 const struct intel_crtc_config *pipe_config) 8755 const struct intel_crtc_state *pipe_config)
8656{ 8756{
8657 struct drm_i915_private *dev_priv = dev->dev_private; 8757 struct drm_i915_private *dev_priv = dev->dev_private;
8658 u32 dpll = pipe_config->dpll_hw_state.dpll; 8758 u32 dpll = pipe_config->dpll_hw_state.dpll;
@@ -8669,7 +8769,7 @@ static int i9xx_pll_refclk(struct drm_device *dev,
8669 8769
8670/* Returns the clock of the currently programmed mode of the given pipe. */ 8770/* Returns the clock of the currently programmed mode of the given pipe. */
8671static void i9xx_crtc_clock_get(struct intel_crtc *crtc, 8771static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8672 struct intel_crtc_config *pipe_config) 8772 struct intel_crtc_state *pipe_config)
8673{ 8773{
8674 struct drm_device *dev = crtc->base.dev; 8774 struct drm_device *dev = crtc->base.dev;
8675 struct drm_i915_private *dev_priv = dev->dev_private; 8775 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -8776,7 +8876,7 @@ int intel_dotclock_calculate(int link_freq,
8776} 8876}
8777 8877
8778static void ironlake_pch_clock_get(struct intel_crtc *crtc, 8878static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8779 struct intel_crtc_config *pipe_config) 8879 struct intel_crtc_state *pipe_config)
8780{ 8880{
8781 struct drm_device *dev = crtc->base.dev; 8881 struct drm_device *dev = crtc->base.dev;
8782 8882
@@ -8789,7 +8889,7 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8789 * agree once we know their relationship in the encoder's 8889 * agree once we know their relationship in the encoder's
8790 * get_config() function. 8890 * get_config() function.
8791 */ 8891 */
8792 pipe_config->adjusted_mode.crtc_clock = 8892 pipe_config->base.adjusted_mode.crtc_clock =
8793 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, 8893 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8794 &pipe_config->fdi_m_n); 8894 &pipe_config->fdi_m_n);
8795} 8895}
@@ -8800,9 +8900,9 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8800{ 8900{
8801 struct drm_i915_private *dev_priv = dev->dev_private; 8901 struct drm_i915_private *dev_priv = dev->dev_private;
8802 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 8902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8803 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; 8903 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8804 struct drm_display_mode *mode; 8904 struct drm_display_mode *mode;
8805 struct intel_crtc_config pipe_config; 8905 struct intel_crtc_state pipe_config;
8806 int htot = I915_READ(HTOTAL(cpu_transcoder)); 8906 int htot = I915_READ(HTOTAL(cpu_transcoder));
8807 int hsync = I915_READ(HSYNC(cpu_transcoder)); 8907 int hsync = I915_READ(HSYNC(cpu_transcoder));
8808 int vtot = I915_READ(VTOTAL(cpu_transcoder)); 8908 int vtot = I915_READ(VTOTAL(cpu_transcoder));
@@ -8917,6 +9017,14 @@ out:
8917 intel_runtime_pm_put(dev_priv); 9017 intel_runtime_pm_put(dev_priv);
8918} 9018}
8919 9019
9020static void intel_crtc_set_state(struct intel_crtc *crtc,
9021 struct intel_crtc_state *crtc_state)
9022{
9023 kfree(crtc->config);
9024 crtc->config = crtc_state;
9025 crtc->base.state = &crtc_state->base;
9026}
9027
8920static void intel_crtc_destroy(struct drm_crtc *crtc) 9028static void intel_crtc_destroy(struct drm_crtc *crtc)
8921{ 9029{
8922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 9030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -8933,6 +9041,7 @@ static void intel_crtc_destroy(struct drm_crtc *crtc)
8933 kfree(work); 9041 kfree(work);
8934 } 9042 }
8935 9043
9044 intel_crtc_set_state(intel_crtc, NULL);
8936 drm_crtc_cleanup(crtc); 9045 drm_crtc_cleanup(crtc);
8937 9046
8938 kfree(intel_crtc); 9047 kfree(intel_crtc);
@@ -9818,7 +9927,7 @@ static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9818 crtc->new_enabled = crtc->base.enabled; 9927 crtc->new_enabled = crtc->base.enabled;
9819 9928
9820 if (crtc->new_enabled) 9929 if (crtc->new_enabled)
9821 crtc->new_config = &crtc->config; 9930 crtc->new_config = crtc->config;
9822 else 9931 else
9823 crtc->new_config = NULL; 9932 crtc->new_config = NULL;
9824 } 9933 }
@@ -9851,7 +9960,7 @@ static void intel_modeset_commit_output_state(struct drm_device *dev)
9851 9960
9852static void 9961static void
9853connected_sink_compute_bpp(struct intel_connector *connector, 9962connected_sink_compute_bpp(struct intel_connector *connector,
9854 struct intel_crtc_config *pipe_config) 9963 struct intel_crtc_state *pipe_config)
9855{ 9964{
9856 int bpp = pipe_config->pipe_bpp; 9965 int bpp = pipe_config->pipe_bpp;
9857 9966
@@ -9878,7 +9987,7 @@ connected_sink_compute_bpp(struct intel_connector *connector,
9878static int 9987static int
9879compute_baseline_pipe_bpp(struct intel_crtc *crtc, 9988compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9880 struct drm_framebuffer *fb, 9989 struct drm_framebuffer *fb,
9881 struct intel_crtc_config *pipe_config) 9990 struct intel_crtc_state *pipe_config)
9882{ 9991{
9883 struct drm_device *dev = crtc->base.dev; 9992 struct drm_device *dev = crtc->base.dev;
9884 struct intel_connector *connector; 9993 struct intel_connector *connector;
@@ -9947,7 +10056,7 @@ static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9947} 10056}
9948 10057
9949static void intel_dump_pipe_config(struct intel_crtc *crtc, 10058static void intel_dump_pipe_config(struct intel_crtc *crtc,
9950 struct intel_crtc_config *pipe_config, 10059 struct intel_crtc_state *pipe_config,
9951 const char *context) 10060 const char *context)
9952{ 10061{
9953 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, 10062 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
@@ -9981,10 +10090,10 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
9981 pipe_config->has_infoframe); 10090 pipe_config->has_infoframe);
9982 10091
9983 DRM_DEBUG_KMS("requested mode:\n"); 10092 DRM_DEBUG_KMS("requested mode:\n");
9984 drm_mode_debug_printmodeline(&pipe_config->requested_mode); 10093 drm_mode_debug_printmodeline(&pipe_config->base.mode);
9985 DRM_DEBUG_KMS("adjusted mode:\n"); 10094 DRM_DEBUG_KMS("adjusted mode:\n");
9986 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); 10095 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
9987 intel_dump_crtc_timings(&pipe_config->adjusted_mode); 10096 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
9988 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); 10097 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9989 DRM_DEBUG_KMS("pipe src size: %dx%d\n", 10098 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9990 pipe_config->pipe_src_w, pipe_config->pipe_src_h); 10099 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
@@ -10083,14 +10192,14 @@ static bool check_digital_port_conflicts(struct drm_device *dev)
10083 return true; 10192 return true;
10084} 10193}
10085 10194
10086static struct intel_crtc_config * 10195static struct intel_crtc_state *
10087intel_modeset_pipe_config(struct drm_crtc *crtc, 10196intel_modeset_pipe_config(struct drm_crtc *crtc,
10088 struct drm_framebuffer *fb, 10197 struct drm_framebuffer *fb,
10089 struct drm_display_mode *mode) 10198 struct drm_display_mode *mode)
10090{ 10199{
10091 struct drm_device *dev = crtc->dev; 10200 struct drm_device *dev = crtc->dev;
10092 struct intel_encoder *encoder; 10201 struct intel_encoder *encoder;
10093 struct intel_crtc_config *pipe_config; 10202 struct intel_crtc_state *pipe_config;
10094 int plane_bpp, ret = -EINVAL; 10203 int plane_bpp, ret = -EINVAL;
10095 bool retry = true; 10204 bool retry = true;
10096 10205
@@ -10108,8 +10217,8 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
10108 if (!pipe_config) 10217 if (!pipe_config)
10109 return ERR_PTR(-ENOMEM); 10218 return ERR_PTR(-ENOMEM);
10110 10219
10111 drm_mode_copy(&pipe_config->adjusted_mode, mode); 10220 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10112 drm_mode_copy(&pipe_config->requested_mode, mode); 10221 drm_mode_copy(&pipe_config->base.mode, mode);
10113 10222
10114 pipe_config->cpu_transcoder = 10223 pipe_config->cpu_transcoder =
10115 (enum transcoder) to_intel_crtc(crtc)->pipe; 10224 (enum transcoder) to_intel_crtc(crtc)->pipe;
@@ -10120,13 +10229,13 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
10120 * positive or negative polarity is requested, treat this as meaning 10229 * positive or negative polarity is requested, treat this as meaning
10121 * negative polarity. 10230 * negative polarity.
10122 */ 10231 */
10123 if (!(pipe_config->adjusted_mode.flags & 10232 if (!(pipe_config->base.adjusted_mode.flags &
10124 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 10233 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10125 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; 10234 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10126 10235
10127 if (!(pipe_config->adjusted_mode.flags & 10236 if (!(pipe_config->base.adjusted_mode.flags &
10128 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 10237 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10129 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; 10238 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10130 10239
10131 /* Compute a starting value for pipe_config->pipe_bpp taking the source 10240 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10132 * plane pixel format and any sink constraints into account. Returns the 10241 * plane pixel format and any sink constraints into account. Returns the
@@ -10145,7 +10254,7 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
10145 * computation to clearly distinguish it from the adjusted mode, which 10254 * computation to clearly distinguish it from the adjusted mode, which
10146 * can be changed by the connectors in the below retry loop. 10255 * can be changed by the connectors in the below retry loop.
10147 */ 10256 */
10148 drm_crtc_get_hv_timing(&pipe_config->requested_mode, 10257 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10149 &pipe_config->pipe_src_w, 10258 &pipe_config->pipe_src_w,
10150 &pipe_config->pipe_src_h); 10259 &pipe_config->pipe_src_h);
10151 10260
@@ -10155,7 +10264,8 @@ encoder_retry:
10155 pipe_config->pixel_multiplier = 1; 10264 pipe_config->pixel_multiplier = 1;
10156 10265
10157 /* Fill in default crtc timings, allow encoders to overwrite them. */ 10266 /* Fill in default crtc timings, allow encoders to overwrite them. */
10158 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); 10267 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10268 CRTC_STEREO_DOUBLE);
10159 10269
10160 /* Pass our mode to the connectors and the CRTC to give them a chance to 10270 /* Pass our mode to the connectors and the CRTC to give them a chance to
10161 * adjust it according to limitations or connector properties, and also 10271 * adjust it according to limitations or connector properties, and also
@@ -10175,7 +10285,7 @@ encoder_retry:
10175 /* Set default port clock if not overwritten by the encoder. Needs to be 10285 /* Set default port clock if not overwritten by the encoder. Needs to be
10176 * done afterwards in case the encoder adjusts the mode. */ 10286 * done afterwards in case the encoder adjusts the mode. */
10177 if (!pipe_config->port_clock) 10287 if (!pipe_config->port_clock)
10178 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock 10288 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10179 * pipe_config->pixel_multiplier; 10289 * pipe_config->pixel_multiplier;
10180 10290
10181 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); 10291 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
@@ -10332,7 +10442,7 @@ intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10332 for_each_intel_crtc(dev, intel_crtc) { 10442 for_each_intel_crtc(dev, intel_crtc) {
10333 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); 10443 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10334 WARN_ON(intel_crtc->new_config && 10444 WARN_ON(intel_crtc->new_config &&
10335 intel_crtc->new_config != &intel_crtc->config); 10445 intel_crtc->new_config != intel_crtc->config);
10336 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); 10446 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10337 } 10447 }
10338 10448
@@ -10384,8 +10494,8 @@ static bool intel_fuzzy_clock_check(int clock1, int clock2)
10384 10494
10385static bool 10495static bool
10386intel_pipe_config_compare(struct drm_device *dev, 10496intel_pipe_config_compare(struct drm_device *dev,
10387 struct intel_crtc_config *current_config, 10497 struct intel_crtc_state *current_config,
10388 struct intel_crtc_config *pipe_config) 10498 struct intel_crtc_state *pipe_config)
10389{ 10499{
10390#define PIPE_CONF_CHECK_X(name) \ 10500#define PIPE_CONF_CHECK_X(name) \
10391 if (current_config->name != pipe_config->name) { \ 10501 if (current_config->name != pipe_config->name) { \
@@ -10476,19 +10586,19 @@ intel_pipe_config_compare(struct drm_device *dev,
10476 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); 10586 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10477 } 10587 }
10478 10588
10479 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); 10589 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10480 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); 10590 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10481 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); 10591 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10482 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); 10592 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10483 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); 10593 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10484 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); 10594 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10485 10595
10486 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); 10596 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10487 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); 10597 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10488 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); 10598 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10489 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); 10599 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10490 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); 10600 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10491 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); 10601 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10492 10602
10493 PIPE_CONF_CHECK_I(pixel_multiplier); 10603 PIPE_CONF_CHECK_I(pixel_multiplier);
10494 PIPE_CONF_CHECK_I(has_hdmi_sink); 10604 PIPE_CONF_CHECK_I(has_hdmi_sink);
@@ -10499,17 +10609,17 @@ intel_pipe_config_compare(struct drm_device *dev,
10499 10609
10500 PIPE_CONF_CHECK_I(has_audio); 10610 PIPE_CONF_CHECK_I(has_audio);
10501 10611
10502 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, 10612 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10503 DRM_MODE_FLAG_INTERLACE); 10613 DRM_MODE_FLAG_INTERLACE);
10504 10614
10505 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { 10615 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10506 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, 10616 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10507 DRM_MODE_FLAG_PHSYNC); 10617 DRM_MODE_FLAG_PHSYNC);
10508 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, 10618 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10509 DRM_MODE_FLAG_NHSYNC); 10619 DRM_MODE_FLAG_NHSYNC);
10510 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, 10620 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10511 DRM_MODE_FLAG_PVSYNC); 10621 DRM_MODE_FLAG_PVSYNC);
10512 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, 10622 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10513 DRM_MODE_FLAG_NVSYNC); 10623 DRM_MODE_FLAG_NVSYNC);
10514 } 10624 }
10515 10625
@@ -10559,7 +10669,7 @@ intel_pipe_config_compare(struct drm_device *dev,
10559 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) 10669 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10560 PIPE_CONF_CHECK_I(pipe_bpp); 10670 PIPE_CONF_CHECK_I(pipe_bpp);
10561 10671
10562 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); 10672 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10563 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); 10673 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10564 10674
10565#undef PIPE_CONF_CHECK_X 10675#undef PIPE_CONF_CHECK_X
@@ -10709,7 +10819,7 @@ check_crtc_state(struct drm_device *dev)
10709 struct drm_i915_private *dev_priv = dev->dev_private; 10819 struct drm_i915_private *dev_priv = dev->dev_private;
10710 struct intel_crtc *crtc; 10820 struct intel_crtc *crtc;
10711 struct intel_encoder *encoder; 10821 struct intel_encoder *encoder;
10712 struct intel_crtc_config pipe_config; 10822 struct intel_crtc_state pipe_config;
10713 10823
10714 for_each_intel_crtc(dev, crtc) { 10824 for_each_intel_crtc(dev, crtc) {
10715 bool enabled = false; 10825 bool enabled = false;
@@ -10759,11 +10869,11 @@ check_crtc_state(struct drm_device *dev)
10759 "(expected %i, found %i)\n", crtc->active, active); 10869 "(expected %i, found %i)\n", crtc->active, active);
10760 10870
10761 if (active && 10871 if (active &&
10762 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { 10872 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
10763 I915_STATE_WARN(1, "pipe state doesn't match!\n"); 10873 I915_STATE_WARN(1, "pipe state doesn't match!\n");
10764 intel_dump_pipe_config(crtc, &pipe_config, 10874 intel_dump_pipe_config(crtc, &pipe_config,
10765 "[hw state]"); 10875 "[hw state]");
10766 intel_dump_pipe_config(crtc, &crtc->config, 10876 intel_dump_pipe_config(crtc, crtc->config,
10767 "[sw state]"); 10877 "[sw state]");
10768 } 10878 }
10769 } 10879 }
@@ -10828,16 +10938,16 @@ intel_modeset_check_state(struct drm_device *dev)
10828 check_shared_dpll_state(dev); 10938 check_shared_dpll_state(dev);
10829} 10939}
10830 10940
10831void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, 10941void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
10832 int dotclock) 10942 int dotclock)
10833{ 10943{
10834 /* 10944 /*
10835 * FDI already provided one idea for the dotclock. 10945 * FDI already provided one idea for the dotclock.
10836 * Yell if the encoder disagrees. 10946 * Yell if the encoder disagrees.
10837 */ 10947 */
10838 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), 10948 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
10839 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", 10949 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10840 pipe_config->adjusted_mode.crtc_clock, dotclock); 10950 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
10841} 10951}
10842 10952
10843static void update_scanline_offset(struct intel_crtc *crtc) 10953static void update_scanline_offset(struct intel_crtc *crtc)
@@ -10863,7 +10973,7 @@ static void update_scanline_offset(struct intel_crtc *crtc)
10863 * one to the value. 10973 * one to the value.
10864 */ 10974 */
10865 if (IS_GEN2(dev)) { 10975 if (IS_GEN2(dev)) {
10866 const struct drm_display_mode *mode = &crtc->config.adjusted_mode; 10976 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
10867 int vtotal; 10977 int vtotal;
10868 10978
10869 vtotal = mode->crtc_vtotal; 10979 vtotal = mode->crtc_vtotal;
@@ -10878,7 +10988,7 @@ static void update_scanline_offset(struct intel_crtc *crtc)
10878 crtc->scanline_offset = 1; 10988 crtc->scanline_offset = 1;
10879} 10989}
10880 10990
10881static struct intel_crtc_config * 10991static struct intel_crtc_state *
10882intel_modeset_compute_config(struct drm_crtc *crtc, 10992intel_modeset_compute_config(struct drm_crtc *crtc,
10883 struct drm_display_mode *mode, 10993 struct drm_display_mode *mode,
10884 struct drm_framebuffer *fb, 10994 struct drm_framebuffer *fb,
@@ -10886,7 +10996,7 @@ intel_modeset_compute_config(struct drm_crtc *crtc,
10886 unsigned *prepare_pipes, 10996 unsigned *prepare_pipes,
10887 unsigned *disable_pipes) 10997 unsigned *disable_pipes)
10888{ 10998{
10889 struct intel_crtc_config *pipe_config = NULL; 10999 struct intel_crtc_state *pipe_config = NULL;
10890 11000
10891 intel_modeset_affected_pipes(crtc, modeset_pipes, 11001 intel_modeset_affected_pipes(crtc, modeset_pipes,
10892 prepare_pipes, disable_pipes); 11002 prepare_pipes, disable_pipes);
@@ -10911,10 +11021,40 @@ out:
10911 return pipe_config; 11021 return pipe_config;
10912} 11022}
10913 11023
11024static int __intel_set_mode_setup_plls(struct drm_device *dev,
11025 unsigned modeset_pipes,
11026 unsigned disable_pipes)
11027{
11028 struct drm_i915_private *dev_priv = to_i915(dev);
11029 unsigned clear_pipes = modeset_pipes | disable_pipes;
11030 struct intel_crtc *intel_crtc;
11031 int ret = 0;
11032
11033 if (!dev_priv->display.crtc_compute_clock)
11034 return 0;
11035
11036 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11037 if (ret)
11038 goto done;
11039
11040 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11041 struct intel_crtc_state *state = intel_crtc->new_config;
11042 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11043 state);
11044 if (ret) {
11045 intel_shared_dpll_abort_config(dev_priv);
11046 goto done;
11047 }
11048 }
11049
11050done:
11051 return ret;
11052}
11053
10914static int __intel_set_mode(struct drm_crtc *crtc, 11054static int __intel_set_mode(struct drm_crtc *crtc,
10915 struct drm_display_mode *mode, 11055 struct drm_display_mode *mode,
10916 int x, int y, struct drm_framebuffer *fb, 11056 int x, int y, struct drm_framebuffer *fb,
10917 struct intel_crtc_config *pipe_config, 11057 struct intel_crtc_state *pipe_config,
10918 unsigned modeset_pipes, 11058 unsigned modeset_pipes,
10919 unsigned prepare_pipes, 11059 unsigned prepare_pipes,
10920 unsigned disable_pipes) 11060 unsigned disable_pipes)
@@ -10948,21 +11088,9 @@ static int __intel_set_mode(struct drm_crtc *crtc,
10948 prepare_pipes &= ~disable_pipes; 11088 prepare_pipes &= ~disable_pipes;
10949 } 11089 }
10950 11090
10951 if (dev_priv->display.crtc_compute_clock) { 11091 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
10952 unsigned clear_pipes = modeset_pipes | disable_pipes; 11092 if (ret)
10953 11093 goto done;
10954 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
10955 if (ret)
10956 goto done;
10957
10958 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10959 ret = dev_priv->display.crtc_compute_clock(intel_crtc);
10960 if (ret) {
10961 intel_shared_dpll_abort_config(dev_priv);
10962 goto done;
10963 }
10964 }
10965 }
10966 11094
10967 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) 11095 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10968 intel_crtc_disable(&intel_crtc->base); 11096 intel_crtc_disable(&intel_crtc->base);
@@ -10983,8 +11111,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
10983 crtc->mode = *mode; 11111 crtc->mode = *mode;
10984 /* mode_set/enable/disable functions rely on a correct pipe 11112 /* mode_set/enable/disable functions rely on a correct pipe
10985 * config. */ 11113 * config. */
10986 to_intel_crtc(crtc)->config = *pipe_config; 11114 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
10987 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10988 11115
10989 /* 11116 /*
10990 * Calculate and store various constants which 11117 * Calculate and store various constants which
@@ -10992,7 +11119,7 @@ static int __intel_set_mode(struct drm_crtc *crtc,
10992 * timestamping. They are derived from true hwmode. 11119 * timestamping. They are derived from true hwmode.
10993 */ 11120 */
10994 drm_calc_timestamping_constants(crtc, 11121 drm_calc_timestamping_constants(crtc,
10995 &pipe_config->adjusted_mode); 11122 &pipe_config->base.adjusted_mode);
10996 } 11123 }
10997 11124
10998 /* Only after disabling all output pipelines that will be changed can we 11125 /* Only after disabling all output pipelines that will be changed can we
@@ -11028,7 +11155,6 @@ done:
11028 if (ret && crtc->enabled) 11155 if (ret && crtc->enabled)
11029 crtc->mode = *saved_mode; 11156 crtc->mode = *saved_mode;
11030 11157
11031 kfree(pipe_config);
11032 kfree(saved_mode); 11158 kfree(saved_mode);
11033 return ret; 11159 return ret;
11034} 11160}
@@ -11036,7 +11162,7 @@ done:
11036static int intel_set_mode_pipes(struct drm_crtc *crtc, 11162static int intel_set_mode_pipes(struct drm_crtc *crtc,
11037 struct drm_display_mode *mode, 11163 struct drm_display_mode *mode,
11038 int x, int y, struct drm_framebuffer *fb, 11164 int x, int y, struct drm_framebuffer *fb,
11039 struct intel_crtc_config *pipe_config, 11165 struct intel_crtc_state *pipe_config,
11040 unsigned modeset_pipes, 11166 unsigned modeset_pipes,
11041 unsigned prepare_pipes, 11167 unsigned prepare_pipes,
11042 unsigned disable_pipes) 11168 unsigned disable_pipes)
@@ -11056,7 +11182,7 @@ static int intel_set_mode(struct drm_crtc *crtc,
11056 struct drm_display_mode *mode, 11182 struct drm_display_mode *mode,
11057 int x, int y, struct drm_framebuffer *fb) 11183 int x, int y, struct drm_framebuffer *fb)
11058{ 11184{
11059 struct intel_crtc_config *pipe_config; 11185 struct intel_crtc_state *pipe_config;
11060 unsigned modeset_pipes, prepare_pipes, disable_pipes; 11186 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11061 11187
11062 pipe_config = intel_modeset_compute_config(crtc, mode, fb, 11188 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
@@ -11151,7 +11277,7 @@ static void intel_set_config_restore_state(struct drm_device *dev,
11151 crtc->new_enabled = config->save_crtc_enabled[count++]; 11277 crtc->new_enabled = config->save_crtc_enabled[count++];
11152 11278
11153 if (crtc->new_enabled) 11279 if (crtc->new_enabled)
11154 crtc->new_config = &crtc->config; 11280 crtc->new_config = crtc->config;
11155 else 11281 else
11156 crtc->new_config = NULL; 11282 crtc->new_config = NULL;
11157 } 11283 }
@@ -11363,7 +11489,7 @@ intel_modeset_stage_output_state(struct drm_device *dev,
11363 } 11489 }
11364 11490
11365 if (crtc->new_enabled) 11491 if (crtc->new_enabled)
11366 crtc->new_config = &crtc->config; 11492 crtc->new_config = crtc->config;
11367 else 11493 else
11368 crtc->new_config = NULL; 11494 crtc->new_config = NULL;
11369 } 11495 }
@@ -11400,7 +11526,7 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
11400 struct drm_device *dev; 11526 struct drm_device *dev;
11401 struct drm_mode_set save_set; 11527 struct drm_mode_set save_set;
11402 struct intel_set_config *config; 11528 struct intel_set_config *config;
11403 struct intel_crtc_config *pipe_config; 11529 struct intel_crtc_state *pipe_config;
11404 unsigned modeset_pipes, prepare_pipes, disable_pipes; 11530 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11405 int ret; 11531 int ret;
11406 11532
@@ -11457,7 +11583,7 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
11457 goto fail; 11583 goto fail;
11458 } else if (pipe_config) { 11584 } else if (pipe_config) {
11459 if (pipe_config->has_audio != 11585 if (pipe_config->has_audio !=
11460 to_intel_crtc(set->crtc)->config.has_audio) 11586 to_intel_crtc(set->crtc)->config->has_audio)
11461 config->mode_changed = true; 11587 config->mode_changed = true;
11462 11588
11463 /* 11589 /*
@@ -11543,6 +11669,8 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
11543 .set_config = intel_crtc_set_config, 11669 .set_config = intel_crtc_set_config,
11544 .destroy = intel_crtc_destroy, 11670 .destroy = intel_crtc_destroy,
11545 .page_flip = intel_crtc_page_flip, 11671 .page_flip = intel_crtc_page_flip,
11672 .atomic_duplicate_state = intel_crtc_duplicate_state,
11673 .atomic_destroy_state = intel_crtc_destroy_state,
11546}; 11674};
11547 11675
11548static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, 11676static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
@@ -11737,7 +11865,6 @@ intel_check_primary_plane(struct drm_plane *plane,
11737 struct drm_i915_private *dev_priv = dev->dev_private; 11865 struct drm_i915_private *dev_priv = dev->dev_private;
11738 struct drm_crtc *crtc = state->base.crtc; 11866 struct drm_crtc *crtc = state->base.crtc;
11739 struct intel_crtc *intel_crtc; 11867 struct intel_crtc *intel_crtc;
11740 struct intel_plane *intel_plane = to_intel_plane(plane);
11741 struct drm_framebuffer *fb = state->base.fb; 11868 struct drm_framebuffer *fb = state->base.fb;
11742 struct drm_rect *dest = &state->dst; 11869 struct drm_rect *dest = &state->dst;
11743 struct drm_rect *src = &state->src; 11870 struct drm_rect *src = &state->src;
@@ -11771,7 +11898,7 @@ intel_check_primary_plane(struct drm_plane *plane,
11771 if (intel_crtc->primary_enabled && 11898 if (intel_crtc->primary_enabled &&
11772 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && 11899 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11773 dev_priv->fbc.plane == intel_crtc->plane && 11900 dev_priv->fbc.plane == intel_crtc->plane &&
11774 intel_plane->rotation != BIT(DRM_ROTATE_0)) { 11901 state->base.rotation != BIT(DRM_ROTATE_0)) {
11775 intel_crtc->atomic.disable_fbc = true; 11902 intel_crtc->atomic.disable_fbc = true;
11776 } 11903 }
11777 11904
@@ -11937,16 +12064,17 @@ static void intel_finish_crtc_commit(struct drm_crtc *crtc)
11937void intel_plane_destroy(struct drm_plane *plane) 12064void intel_plane_destroy(struct drm_plane *plane)
11938{ 12065{
11939 struct intel_plane *intel_plane = to_intel_plane(plane); 12066 struct intel_plane *intel_plane = to_intel_plane(plane);
11940 intel_plane_destroy_state(plane, plane->state);
11941 drm_plane_cleanup(plane); 12067 drm_plane_cleanup(plane);
11942 kfree(intel_plane); 12068 kfree(intel_plane);
11943} 12069}
11944 12070
11945static const struct drm_plane_funcs intel_primary_plane_funcs = { 12071const struct drm_plane_funcs intel_plane_funcs = {
11946 .update_plane = drm_plane_helper_update, 12072 .update_plane = drm_plane_helper_update,
11947 .disable_plane = drm_plane_helper_disable, 12073 .disable_plane = drm_plane_helper_disable,
11948 .destroy = intel_plane_destroy, 12074 .destroy = intel_plane_destroy,
11949 .set_property = intel_plane_set_property, 12075 .set_property = drm_atomic_helper_plane_set_property,
12076 .atomic_get_property = intel_plane_atomic_get_property,
12077 .atomic_set_property = intel_plane_atomic_set_property,
11950 .atomic_duplicate_state = intel_plane_duplicate_state, 12078 .atomic_duplicate_state = intel_plane_duplicate_state,
11951 .atomic_destroy_state = intel_plane_destroy_state, 12079 .atomic_destroy_state = intel_plane_destroy_state,
11952 12080
@@ -11956,6 +12084,7 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11956 int pipe) 12084 int pipe)
11957{ 12085{
11958 struct intel_plane *primary; 12086 struct intel_plane *primary;
12087 struct intel_plane_state *state;
11959 const uint32_t *intel_primary_formats; 12088 const uint32_t *intel_primary_formats;
11960 int num_formats; 12089 int num_formats;
11961 12090
@@ -11963,17 +12092,17 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11963 if (primary == NULL) 12092 if (primary == NULL)
11964 return NULL; 12093 return NULL;
11965 12094
11966 primary->base.state = intel_plane_duplicate_state(&primary->base); 12095 state = intel_create_plane_state(&primary->base);
11967 if (primary->base.state == NULL) { 12096 if (!state) {
11968 kfree(primary); 12097 kfree(primary);
11969 return NULL; 12098 return NULL;
11970 } 12099 }
12100 primary->base.state = &state->base;
11971 12101
11972 primary->can_scale = false; 12102 primary->can_scale = false;
11973 primary->max_downscale = 1; 12103 primary->max_downscale = 1;
11974 primary->pipe = pipe; 12104 primary->pipe = pipe;
11975 primary->plane = pipe; 12105 primary->plane = pipe;
11976 primary->rotation = BIT(DRM_ROTATE_0);
11977 primary->check_plane = intel_check_primary_plane; 12106 primary->check_plane = intel_check_primary_plane;
11978 primary->commit_plane = intel_commit_primary_plane; 12107 primary->commit_plane = intel_commit_primary_plane;
11979 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) 12108 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
@@ -11988,7 +12117,7 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11988 } 12117 }
11989 12118
11990 drm_universal_plane_init(dev, &primary->base, 0, 12119 drm_universal_plane_init(dev, &primary->base, 0,
11991 &intel_primary_plane_funcs, 12120 &intel_plane_funcs,
11992 intel_primary_formats, num_formats, 12121 intel_primary_formats, num_formats,
11993 DRM_PLANE_TYPE_PRIMARY); 12122 DRM_PLANE_TYPE_PRIMARY);
11994 12123
@@ -12001,7 +12130,7 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12001 if (dev->mode_config.rotation_property) 12130 if (dev->mode_config.rotation_property)
12002 drm_object_attach_property(&primary->base.base, 12131 drm_object_attach_property(&primary->base.base,
12003 dev->mode_config.rotation_property, 12132 dev->mode_config.rotation_property,
12004 primary->rotation); 12133 state->base.rotation);
12005 } 12134 }
12006 12135
12007 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); 12136 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
@@ -12116,40 +12245,32 @@ update:
12116 intel_crtc_update_cursor(crtc, state->visible); 12245 intel_crtc_update_cursor(crtc, state->visible);
12117} 12246}
12118 12247
12119static const struct drm_plane_funcs intel_cursor_plane_funcs = {
12120 .update_plane = drm_plane_helper_update,
12121 .disable_plane = drm_plane_helper_disable,
12122 .destroy = intel_plane_destroy,
12123 .set_property = intel_plane_set_property,
12124 .atomic_duplicate_state = intel_plane_duplicate_state,
12125 .atomic_destroy_state = intel_plane_destroy_state,
12126};
12127
12128static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, 12248static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12129 int pipe) 12249 int pipe)
12130{ 12250{
12131 struct intel_plane *cursor; 12251 struct intel_plane *cursor;
12252 struct intel_plane_state *state;
12132 12253
12133 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); 12254 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12134 if (cursor == NULL) 12255 if (cursor == NULL)
12135 return NULL; 12256 return NULL;
12136 12257
12137 cursor->base.state = intel_plane_duplicate_state(&cursor->base); 12258 state = intel_create_plane_state(&cursor->base);
12138 if (cursor->base.state == NULL) { 12259 if (!state) {
12139 kfree(cursor); 12260 kfree(cursor);
12140 return NULL; 12261 return NULL;
12141 } 12262 }
12263 cursor->base.state = &state->base;
12142 12264
12143 cursor->can_scale = false; 12265 cursor->can_scale = false;
12144 cursor->max_downscale = 1; 12266 cursor->max_downscale = 1;
12145 cursor->pipe = pipe; 12267 cursor->pipe = pipe;
12146 cursor->plane = pipe; 12268 cursor->plane = pipe;
12147 cursor->rotation = BIT(DRM_ROTATE_0);
12148 cursor->check_plane = intel_check_cursor_plane; 12269 cursor->check_plane = intel_check_cursor_plane;
12149 cursor->commit_plane = intel_commit_cursor_plane; 12270 cursor->commit_plane = intel_commit_cursor_plane;
12150 12271
12151 drm_universal_plane_init(dev, &cursor->base, 0, 12272 drm_universal_plane_init(dev, &cursor->base, 0,
12152 &intel_cursor_plane_funcs, 12273 &intel_plane_funcs,
12153 intel_cursor_formats, 12274 intel_cursor_formats,
12154 ARRAY_SIZE(intel_cursor_formats), 12275 ARRAY_SIZE(intel_cursor_formats),
12155 DRM_PLANE_TYPE_CURSOR); 12276 DRM_PLANE_TYPE_CURSOR);
@@ -12163,7 +12284,7 @@ static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12163 if (dev->mode_config.rotation_property) 12284 if (dev->mode_config.rotation_property)
12164 drm_object_attach_property(&cursor->base.base, 12285 drm_object_attach_property(&cursor->base.base,
12165 dev->mode_config.rotation_property, 12286 dev->mode_config.rotation_property,
12166 cursor->rotation); 12287 state->base.rotation);
12167 } 12288 }
12168 12289
12169 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); 12290 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
@@ -12175,6 +12296,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
12175{ 12296{
12176 struct drm_i915_private *dev_priv = dev->dev_private; 12297 struct drm_i915_private *dev_priv = dev->dev_private;
12177 struct intel_crtc *intel_crtc; 12298 struct intel_crtc *intel_crtc;
12299 struct intel_crtc_state *crtc_state = NULL;
12178 struct drm_plane *primary = NULL; 12300 struct drm_plane *primary = NULL;
12179 struct drm_plane *cursor = NULL; 12301 struct drm_plane *cursor = NULL;
12180 int i, ret; 12302 int i, ret;
@@ -12183,6 +12305,11 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
12183 if (intel_crtc == NULL) 12305 if (intel_crtc == NULL)
12184 return; 12306 return;
12185 12307
12308 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12309 if (!crtc_state)
12310 goto fail;
12311 intel_crtc_set_state(intel_crtc, crtc_state);
12312
12186 primary = intel_primary_plane_create(dev, pipe); 12313 primary = intel_primary_plane_create(dev, pipe);
12187 if (!primary) 12314 if (!primary)
12188 goto fail; 12315 goto fail;
@@ -12235,6 +12362,7 @@ fail:
12235 drm_plane_cleanup(primary); 12362 drm_plane_cleanup(primary);
12236 if (cursor) 12363 if (cursor)
12237 drm_plane_cleanup(cursor); 12364 drm_plane_cleanup(cursor);
12365 kfree(crtc_state);
12238 kfree(intel_crtc); 12366 kfree(intel_crtc);
12239} 12367}
12240 12368
@@ -12330,6 +12458,7 @@ static void intel_setup_outputs(struct drm_device *dev)
12330{ 12458{
12331 struct drm_i915_private *dev_priv = dev->dev_private; 12459 struct drm_i915_private *dev_priv = dev->dev_private;
12332 struct intel_encoder *encoder; 12460 struct intel_encoder *encoder;
12461 struct drm_connector *connector;
12333 bool dpd_is_edp = false; 12462 bool dpd_is_edp = false;
12334 12463
12335 intel_lvds_init(dev); 12464 intel_lvds_init(dev);
@@ -12460,6 +12589,37 @@ static void intel_setup_outputs(struct drm_device *dev)
12460 if (SUPPORTS_TV(dev)) 12589 if (SUPPORTS_TV(dev))
12461 intel_tv_init(dev); 12590 intel_tv_init(dev);
12462 12591
12592 /*
12593 * FIXME: We don't have full atomic support yet, but we want to be
12594 * able to enable/test plane updates via the atomic interface in the
12595 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12596 * will take some atomic codepaths to lookup properties during
12597 * drmModeGetConnector() that unconditionally dereference
12598 * connector->state.
12599 *
12600 * We create a dummy connector state here for each connector to ensure
12601 * the DRM core doesn't try to dereference a NULL connector->state.
12602 * The actual connector properties will never be updated or contain
12603 * useful information, but since we're doing this specifically for
12604 * testing/debug of the plane operations (and only when a specific
12605 * kernel module option is given), that shouldn't really matter.
12606 *
12607 * Once atomic support for crtc's + connectors lands, this loop should
12608 * be removed since we'll be setting up real connector state, which
12609 * will contain Intel-specific properties.
12610 */
12611 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12612 list_for_each_entry(connector,
12613 &dev->mode_config.connector_list,
12614 head) {
12615 if (!WARN_ON(connector->state)) {
12616 connector->state =
12617 kzalloc(sizeof(*connector->state),
12618 GFP_KERNEL);
12619 }
12620 }
12621 }
12622
12463 intel_psr_init(dev); 12623 intel_psr_init(dev);
12464 12624
12465 for_each_intel_encoder(dev, encoder) { 12625 for_each_intel_encoder(dev, encoder) {
@@ -12600,8 +12760,8 @@ static int intel_framebuffer_init(struct drm_device *dev,
12600 if (mode_cmd->offsets[0] != 0) 12760 if (mode_cmd->offsets[0] != 0)
12601 return -EINVAL; 12761 return -EINVAL;
12602 12762
12603 aligned_height = intel_align_height(dev, mode_cmd->height, 12763 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12604 obj->tiling_mode); 12764 obj->tiling_mode);
12605 /* FIXME drm helper for size checks (especially planar formats)? */ 12765 /* FIXME drm helper for size checks (especially planar formats)? */
12606 if (obj->base.size < aligned_height * mode_cmd->pitches[0]) 12766 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12607 return -EINVAL; 12767 return -EINVAL;
@@ -12643,6 +12803,8 @@ static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12643static const struct drm_mode_config_funcs intel_mode_funcs = { 12803static const struct drm_mode_config_funcs intel_mode_funcs = {
12644 .fb_create = intel_user_framebuffer_create, 12804 .fb_create = intel_user_framebuffer_create,
12645 .output_poll_changed = intel_fbdev_output_poll_changed, 12805 .output_poll_changed = intel_fbdev_output_poll_changed,
12806 .atomic_check = intel_atomic_check,
12807 .atomic_commit = intel_atomic_commit,
12646}; 12808};
12647 12809
12648/* Set up chip specific display functions */ 12810/* Set up chip specific display functions */
@@ -12661,23 +12823,32 @@ static void intel_init_display(struct drm_device *dev)
12661 else 12823 else
12662 dev_priv->display.find_dpll = i9xx_find_best_dpll; 12824 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12663 12825
12664 if (HAS_DDI(dev)) { 12826 if (INTEL_INFO(dev)->gen >= 9) {
12665 dev_priv->display.get_pipe_config = haswell_get_pipe_config; 12827 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12666 dev_priv->display.get_plane_config = ironlake_get_plane_config; 12828 dev_priv->display.get_initial_plane_config =
12829 skylake_get_initial_plane_config;
12667 dev_priv->display.crtc_compute_clock = 12830 dev_priv->display.crtc_compute_clock =
12668 haswell_crtc_compute_clock; 12831 haswell_crtc_compute_clock;
12669 dev_priv->display.crtc_enable = haswell_crtc_enable; 12832 dev_priv->display.crtc_enable = haswell_crtc_enable;
12670 dev_priv->display.crtc_disable = haswell_crtc_disable; 12833 dev_priv->display.crtc_disable = haswell_crtc_disable;
12671 dev_priv->display.off = ironlake_crtc_off; 12834 dev_priv->display.off = ironlake_crtc_off;
12672 if (INTEL_INFO(dev)->gen >= 9) 12835 dev_priv->display.update_primary_plane =
12673 dev_priv->display.update_primary_plane = 12836 skylake_update_primary_plane;
12674 skylake_update_primary_plane; 12837 } else if (HAS_DDI(dev)) {
12675 else 12838 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12676 dev_priv->display.update_primary_plane = 12839 dev_priv->display.get_initial_plane_config =
12677 ironlake_update_primary_plane; 12840 ironlake_get_initial_plane_config;
12841 dev_priv->display.crtc_compute_clock =
12842 haswell_crtc_compute_clock;
12843 dev_priv->display.crtc_enable = haswell_crtc_enable;
12844 dev_priv->display.crtc_disable = haswell_crtc_disable;
12845 dev_priv->display.off = ironlake_crtc_off;
12846 dev_priv->display.update_primary_plane =
12847 ironlake_update_primary_plane;
12678 } else if (HAS_PCH_SPLIT(dev)) { 12848 } else if (HAS_PCH_SPLIT(dev)) {
12679 dev_priv->display.get_pipe_config = ironlake_get_pipe_config; 12849 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12680 dev_priv->display.get_plane_config = ironlake_get_plane_config; 12850 dev_priv->display.get_initial_plane_config =
12851 ironlake_get_initial_plane_config;
12681 dev_priv->display.crtc_compute_clock = 12852 dev_priv->display.crtc_compute_clock =
12682 ironlake_crtc_compute_clock; 12853 ironlake_crtc_compute_clock;
12683 dev_priv->display.crtc_enable = ironlake_crtc_enable; 12854 dev_priv->display.crtc_enable = ironlake_crtc_enable;
@@ -12687,7 +12858,8 @@ static void intel_init_display(struct drm_device *dev)
12687 ironlake_update_primary_plane; 12858 ironlake_update_primary_plane;
12688 } else if (IS_VALLEYVIEW(dev)) { 12859 } else if (IS_VALLEYVIEW(dev)) {
12689 dev_priv->display.get_pipe_config = i9xx_get_pipe_config; 12860 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12690 dev_priv->display.get_plane_config = i9xx_get_plane_config; 12861 dev_priv->display.get_initial_plane_config =
12862 i9xx_get_initial_plane_config;
12691 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; 12863 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12692 dev_priv->display.crtc_enable = valleyview_crtc_enable; 12864 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12693 dev_priv->display.crtc_disable = i9xx_crtc_disable; 12865 dev_priv->display.crtc_disable = i9xx_crtc_disable;
@@ -12696,7 +12868,8 @@ static void intel_init_display(struct drm_device *dev)
12696 i9xx_update_primary_plane; 12868 i9xx_update_primary_plane;
12697 } else { 12869 } else {
12698 dev_priv->display.get_pipe_config = i9xx_get_pipe_config; 12870 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12699 dev_priv->display.get_plane_config = i9xx_get_plane_config; 12871 dev_priv->display.get_initial_plane_config =
12872 i9xx_get_initial_plane_config;
12700 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; 12873 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12701 dev_priv->display.crtc_enable = i9xx_crtc_enable; 12874 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12702 dev_priv->display.crtc_disable = i9xx_crtc_disable; 12875 dev_priv->display.crtc_disable = i9xx_crtc_disable;
@@ -13068,8 +13241,8 @@ void intel_modeset_init(struct drm_device *dev)
13068 * can even allow for smooth boot transitions if the BIOS 13241 * can even allow for smooth boot transitions if the BIOS
13069 * fb is large enough for the active pipe configuration. 13242 * fb is large enough for the active pipe configuration.
13070 */ 13243 */
13071 if (dev_priv->display.get_plane_config) { 13244 if (dev_priv->display.get_initial_plane_config) {
13072 dev_priv->display.get_plane_config(crtc, 13245 dev_priv->display.get_initial_plane_config(crtc,
13073 &crtc->plane_config); 13246 &crtc->plane_config);
13074 /* 13247 /*
13075 * If the fb is shared between multiple heads, we'll 13248 * If the fb is shared between multiple heads, we'll
@@ -13133,7 +13306,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
13133 u32 reg; 13306 u32 reg;
13134 13307
13135 /* Clear any frame start delays used for debugging left by the BIOS */ 13308 /* Clear any frame start delays used for debugging left by the BIOS */
13136 reg = PIPECONF(crtc->config.cpu_transcoder); 13309 reg = PIPECONF(crtc->config->cpu_transcoder);
13137 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); 13310 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13138 13311
13139 /* restore vblank interrupts to correct state */ 13312 /* restore vblank interrupts to correct state */
@@ -13337,12 +13510,12 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
13337 int i; 13510 int i;
13338 13511
13339 for_each_intel_crtc(dev, crtc) { 13512 for_each_intel_crtc(dev, crtc) {
13340 memset(&crtc->config, 0, sizeof(crtc->config)); 13513 memset(crtc->config, 0, sizeof(*crtc->config));
13341 13514
13342 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; 13515 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13343 13516
13344 crtc->active = dev_priv->display.get_pipe_config(crtc, 13517 crtc->active = dev_priv->display.get_pipe_config(crtc,
13345 &crtc->config); 13518 crtc->config);
13346 13519
13347 crtc->base.enabled = crtc->active; 13520 crtc->base.enabled = crtc->active;
13348 crtc->primary_enabled = primary_get_hw_state(crtc); 13521 crtc->primary_enabled = primary_get_hw_state(crtc);
@@ -13379,7 +13552,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
13379 if (encoder->get_hw_state(encoder, &pipe)) { 13552 if (encoder->get_hw_state(encoder, &pipe)) {
13380 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 13553 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13381 encoder->base.crtc = &crtc->base; 13554 encoder->base.crtc = &crtc->base;
13382 encoder->get_config(encoder, &crtc->config); 13555 encoder->get_config(encoder, crtc->config);
13383 } else { 13556 } else {
13384 encoder->base.crtc = NULL; 13557 encoder->base.crtc = NULL;
13385 } 13558 }
@@ -13429,7 +13602,8 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
13429 */ 13602 */
13430 for_each_intel_crtc(dev, crtc) { 13603 for_each_intel_crtc(dev, crtc) {
13431 if (crtc->active && i915.fastboot) { 13604 if (crtc->active && i915.fastboot) {
13432 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); 13605 intel_mode_from_pipe_config(&crtc->base.mode,
13606 crtc->config);
13433 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", 13607 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13434 crtc->base.base.id); 13608 crtc->base.base.id);
13435 drm_mode_debug_printmodeline(&crtc->base.mode); 13609 drm_mode_debug_printmodeline(&crtc->base.mode);
@@ -13444,7 +13618,8 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
13444 for_each_pipe(dev_priv, pipe) { 13618 for_each_pipe(dev_priv, pipe) {
13445 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 13619 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13446 intel_sanitize_crtc(crtc); 13620 intel_sanitize_crtc(crtc);
13447 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); 13621 intel_dump_pipe_config(crtc, crtc->config,
13622 "[setup_hw_state]");
13448 } 13623 }
13449 13624
13450 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 13625 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index df7b558f3222..eea9e366a109 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -31,6 +31,7 @@
31#include <linux/notifier.h> 31#include <linux/notifier.h>
32#include <linux/reboot.h> 32#include <linux/reboot.h>
33#include <drm/drmP.h> 33#include <drm/drmP.h>
34#include <drm/drm_atomic_helper.h>
34#include <drm/drm_crtc.h> 35#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h> 36#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h> 37#include <drm/drm_edid.h>
@@ -1074,7 +1075,7 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector)
1074} 1075}
1075 1076
1076static void 1077static void
1077skl_edp_set_pll_config(struct intel_crtc_config *pipe_config, int link_bw) 1078skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_bw)
1078{ 1079{
1079 u32 ctrl1; 1080 u32 ctrl1;
1080 1081
@@ -1101,7 +1102,7 @@ skl_edp_set_pll_config(struct intel_crtc_config *pipe_config, int link_bw)
1101} 1102}
1102 1103
1103static void 1104static void
1104hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw) 1105hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
1105{ 1106{
1106 switch (link_bw) { 1107 switch (link_bw) {
1107 case DP_LINK_BW_1_62: 1108 case DP_LINK_BW_1_62:
@@ -1118,7 +1119,7 @@ hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
1118 1119
1119static void 1120static void
1120intel_dp_set_clock(struct intel_encoder *encoder, 1121intel_dp_set_clock(struct intel_encoder *encoder,
1121 struct intel_crtc_config *pipe_config, int link_bw) 1122 struct intel_crtc_state *pipe_config, int link_bw)
1122{ 1123{
1123 struct drm_device *dev = encoder->base.dev; 1124 struct drm_device *dev = encoder->base.dev;
1124 const struct dp_link_dpll *divisor = NULL; 1125 const struct dp_link_dpll *divisor = NULL;
@@ -1151,11 +1152,11 @@ intel_dp_set_clock(struct intel_encoder *encoder,
1151 1152
1152bool 1153bool
1153intel_dp_compute_config(struct intel_encoder *encoder, 1154intel_dp_compute_config(struct intel_encoder *encoder,
1154 struct intel_crtc_config *pipe_config) 1155 struct intel_crtc_state *pipe_config)
1155{ 1156{
1156 struct drm_device *dev = encoder->base.dev; 1157 struct drm_device *dev = encoder->base.dev;
1157 struct drm_i915_private *dev_priv = dev->dev_private; 1158 struct drm_i915_private *dev_priv = dev->dev_private;
1158 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 1159 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1159 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1160 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1160 enum port port = dp_to_dig_port(intel_dp)->port; 1161 enum port port = dp_to_dig_port(intel_dp)->port;
1161 struct intel_crtc *intel_crtc = encoder->new_crtc; 1162 struct intel_crtc *intel_crtc = encoder->new_crtc;
@@ -1269,7 +1270,7 @@ found:
1269 &pipe_config->dp_m_n); 1270 &pipe_config->dp_m_n);
1270 1271
1271 if (intel_connector->panel.downclock_mode != NULL && 1272 if (intel_connector->panel.downclock_mode != NULL &&
1272 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) { 1273 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1273 pipe_config->has_drrs = true; 1274 pipe_config->has_drrs = true;
1274 intel_link_compute_m_n(bpp, lane_count, 1275 intel_link_compute_m_n(bpp, lane_count,
1275 intel_connector->panel.downclock_mode->clock, 1276 intel_connector->panel.downclock_mode->clock,
@@ -1295,11 +1296,12 @@ static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
1295 struct drm_i915_private *dev_priv = dev->dev_private; 1296 struct drm_i915_private *dev_priv = dev->dev_private;
1296 u32 dpa_ctl; 1297 u32 dpa_ctl;
1297 1298
1298 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); 1299 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1300 crtc->config->port_clock);
1299 dpa_ctl = I915_READ(DP_A); 1301 dpa_ctl = I915_READ(DP_A);
1300 dpa_ctl &= ~DP_PLL_FREQ_MASK; 1302 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1301 1303
1302 if (crtc->config.port_clock == 162000) { 1304 if (crtc->config->port_clock == 162000) {
1303 /* For a long time we've carried around a ILK-DevA w/a for the 1305 /* For a long time we've carried around a ILK-DevA w/a for the
1304 * 160MHz clock. If we're really unlucky, it's still required. 1306 * 160MHz clock. If we're really unlucky, it's still required.
1305 */ 1307 */
@@ -1324,7 +1326,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
1324 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1326 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1325 enum port port = dp_to_dig_port(intel_dp)->port; 1327 enum port port = dp_to_dig_port(intel_dp)->port;
1326 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1328 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1327 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; 1329 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1328 1330
1329 /* 1331 /*
1330 * There are four kinds of DP registers: 1332 * There are four kinds of DP registers:
@@ -1352,7 +1354,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
1352 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 1354 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1353 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); 1355 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1354 1356
1355 if (crtc->config.has_audio) 1357 if (crtc->config->has_audio)
1356 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 1358 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1357 1359
1358 /* Split out the IBX/CPU vs CPT settings */ 1360 /* Split out the IBX/CPU vs CPT settings */
@@ -2013,7 +2015,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2013} 2015}
2014 2016
2015static void intel_dp_get_config(struct intel_encoder *encoder, 2017static void intel_dp_get_config(struct intel_encoder *encoder,
2016 struct intel_crtc_config *pipe_config) 2018 struct intel_crtc_state *pipe_config)
2017{ 2019{
2018 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2020 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2019 u32 tmp, flags = 0; 2021 u32 tmp, flags = 0;
@@ -2050,7 +2052,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
2050 flags |= DRM_MODE_FLAG_NVSYNC; 2052 flags |= DRM_MODE_FLAG_NVSYNC;
2051 } 2053 }
2052 2054
2053 pipe_config->adjusted_mode.flags |= flags; 2055 pipe_config->base.adjusted_mode.flags |= flags;
2054 2056
2055 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && 2057 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2056 tmp & DP_COLOR_RANGE_16_235) 2058 tmp & DP_COLOR_RANGE_16_235)
@@ -2073,7 +2075,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
2073 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) 2075 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2074 ironlake_check_encoder_dotclock(pipe_config, dotclock); 2076 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2075 2077
2076 pipe_config->adjusted_mode.crtc_clock = dotclock; 2078 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
2077 2079
2078 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && 2080 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2079 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { 2081 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
@@ -2102,7 +2104,7 @@ static void intel_disable_dp(struct intel_encoder *encoder)
2102 struct drm_device *dev = encoder->base.dev; 2104 struct drm_device *dev = encoder->base.dev;
2103 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 2105 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2104 2106
2105 if (crtc->config.has_audio) 2107 if (crtc->config->has_audio)
2106 intel_audio_codec_disable(encoder); 2108 intel_audio_codec_disable(encoder);
2107 2109
2108 if (HAS_PSR(dev) && !HAS_DDI(dev)) 2110 if (HAS_PSR(dev) && !HAS_DDI(dev))
@@ -2312,7 +2314,7 @@ static void intel_enable_dp(struct intel_encoder *encoder)
2312 intel_dp_complete_link_train(intel_dp); 2314 intel_dp_complete_link_train(intel_dp);
2313 intel_dp_stop_link_train(intel_dp); 2315 intel_dp_stop_link_train(intel_dp);
2314 2316
2315 if (crtc->config.has_audio) { 2317 if (crtc->config->has_audio) {
2316 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", 2318 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2317 pipe_name(crtc->pipe)); 2319 pipe_name(crtc->pipe));
2318 intel_audio_codec_enable(encoder); 2320 intel_audio_codec_enable(encoder);
@@ -4400,7 +4402,9 @@ static const struct drm_connector_funcs intel_dp_connector_funcs = {
4400 .force = intel_dp_force, 4402 .force = intel_dp_force,
4401 .fill_modes = drm_helper_probe_single_connector_modes, 4403 .fill_modes = drm_helper_probe_single_connector_modes,
4402 .set_property = intel_dp_set_property, 4404 .set_property = intel_dp_set_property,
4405 .atomic_get_property = intel_connector_atomic_get_property,
4403 .destroy = intel_dp_connector_destroy, 4406 .destroy = intel_dp_connector_destroy,
4407 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4404}; 4408};
4405 4409
4406static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 4410static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
@@ -4420,7 +4424,7 @@ intel_dp_hot_plug(struct intel_encoder *intel_encoder)
4420 return; 4424 return;
4421} 4425}
4422 4426
4423bool 4427enum irqreturn
4424intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) 4428intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4425{ 4429{
4426 struct intel_dp *intel_dp = &intel_dig_port->dp; 4430 struct intel_dp *intel_dp = &intel_dig_port->dp;
@@ -4428,7 +4432,7 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4428 struct drm_device *dev = intel_dig_port->base.base.dev; 4432 struct drm_device *dev = intel_dig_port->base.base.dev;
4429 struct drm_i915_private *dev_priv = dev->dev_private; 4433 struct drm_i915_private *dev_priv = dev->dev_private;
4430 enum intel_display_power_domain power_domain; 4434 enum intel_display_power_domain power_domain;
4431 bool ret = true; 4435 enum irqreturn ret = IRQ_NONE;
4432 4436
4433 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP) 4437 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4434 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; 4438 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
@@ -4487,7 +4491,9 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4487 drm_modeset_unlock(&dev->mode_config.connection_mutex); 4491 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4488 } 4492 }
4489 } 4493 }
4490 ret = false; 4494
4495 ret = IRQ_HANDLED;
4496
4491 goto put_power; 4497 goto put_power;
4492mst_fail: 4498mst_fail:
4493 /* if we were in MST mode, and device is not there get out of MST mode */ 4499 /* if we were in MST mode, and device is not there get out of MST mode */
@@ -4745,24 +4751,24 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4745 I915_READ(pp_div_reg)); 4751 I915_READ(pp_div_reg));
4746} 4752}
4747 4753
4748void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) 4754static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4749{ 4755{
4750 struct drm_i915_private *dev_priv = dev->dev_private; 4756 struct drm_i915_private *dev_priv = dev->dev_private;
4751 struct intel_encoder *encoder; 4757 struct intel_encoder *encoder;
4752 struct intel_dp *intel_dp = NULL; 4758 struct intel_digital_port *dig_port = NULL;
4753 struct intel_crtc_config *config = NULL; 4759 struct intel_dp *intel_dp = dev_priv->drrs.dp;
4760 struct intel_crtc_state *config = NULL;
4754 struct intel_crtc *intel_crtc = NULL; 4761 struct intel_crtc *intel_crtc = NULL;
4755 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4756 u32 reg, val; 4762 u32 reg, val;
4757 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR; 4763 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
4758 4764
4759 if (refresh_rate <= 0) { 4765 if (refresh_rate <= 0) {
4760 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); 4766 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4761 return; 4767 return;
4762 } 4768 }
4763 4769
4764 if (intel_connector == NULL) { 4770 if (intel_dp == NULL) {
4765 DRM_DEBUG_KMS("DRRS supported for eDP only.\n"); 4771 DRM_DEBUG_KMS("DRRS not supported.\n");
4766 return; 4772 return;
4767 } 4773 }
4768 4774
@@ -4771,8 +4777,8 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4771 * platforms that cannot have PSR and DRRS enabled at the same time. 4777 * platforms that cannot have PSR and DRRS enabled at the same time.
4772 */ 4778 */
4773 4779
4774 encoder = intel_attached_encoder(&intel_connector->base); 4780 dig_port = dp_to_dig_port(intel_dp);
4775 intel_dp = enc_to_intel_dp(&encoder->base); 4781 encoder = &dig_port->base;
4776 intel_crtc = encoder->new_crtc; 4782 intel_crtc = encoder->new_crtc;
4777 4783
4778 if (!intel_crtc) { 4784 if (!intel_crtc) {
@@ -4780,17 +4786,18 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4780 return; 4786 return;
4781 } 4787 }
4782 4788
4783 config = &intel_crtc->config; 4789 config = intel_crtc->config;
4784 4790
4785 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) { 4791 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
4786 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); 4792 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4787 return; 4793 return;
4788 } 4794 }
4789 4795
4790 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate) 4796 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
4797 refresh_rate)
4791 index = DRRS_LOW_RR; 4798 index = DRRS_LOW_RR;
4792 4799
4793 if (index == intel_dp->drrs_state.refresh_rate_type) { 4800 if (index == dev_priv->drrs.refresh_rate_type) {
4794 DRM_DEBUG_KMS( 4801 DRM_DEBUG_KMS(
4795 "DRRS requested for previously set RR...ignoring\n"); 4802 "DRRS requested for previously set RR...ignoring\n");
4796 return; 4803 return;
@@ -4802,7 +4809,7 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4802 } 4809 }
4803 4810
4804 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) { 4811 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4805 reg = PIPECONF(intel_crtc->config.cpu_transcoder); 4812 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
4806 val = I915_READ(reg); 4813 val = I915_READ(reg);
4807 if (index > DRRS_HIGH_RR) { 4814 if (index > DRRS_HIGH_RR) {
4808 val |= PIPECONF_EDP_RR_MODE_SWITCH; 4815 val |= PIPECONF_EDP_RR_MODE_SWITCH;
@@ -4813,30 +4820,154 @@ void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4813 I915_WRITE(reg, val); 4820 I915_WRITE(reg, val);
4814 } 4821 }
4815 4822
4823 dev_priv->drrs.refresh_rate_type = index;
4824
4825 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4826}
4827
4828void intel_edp_drrs_enable(struct intel_dp *intel_dp)
4829{
4830 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4831 struct drm_i915_private *dev_priv = dev->dev_private;
4832 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4833 struct drm_crtc *crtc = dig_port->base.base.crtc;
4834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4835
4836 if (!intel_crtc->config->has_drrs) {
4837 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
4838 return;
4839 }
4840
4841 mutex_lock(&dev_priv->drrs.mutex);
4842 if (WARN_ON(dev_priv->drrs.dp)) {
4843 DRM_ERROR("DRRS already enabled\n");
4844 goto unlock;
4845 }
4846
4847 dev_priv->drrs.busy_frontbuffer_bits = 0;
4848
4849 dev_priv->drrs.dp = intel_dp;
4850
4851unlock:
4852 mutex_unlock(&dev_priv->drrs.mutex);
4853}
4854
4855void intel_edp_drrs_disable(struct intel_dp *intel_dp)
4856{
4857 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4858 struct drm_i915_private *dev_priv = dev->dev_private;
4859 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4860 struct drm_crtc *crtc = dig_port->base.base.crtc;
4861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4862
4863 if (!intel_crtc->config->has_drrs)
4864 return;
4865
4866 mutex_lock(&dev_priv->drrs.mutex);
4867 if (!dev_priv->drrs.dp) {
4868 mutex_unlock(&dev_priv->drrs.mutex);
4869 return;
4870 }
4871
4872 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
4873 intel_dp_set_drrs_state(dev_priv->dev,
4874 intel_dp->attached_connector->panel.
4875 fixed_mode->vrefresh);
4876
4877 dev_priv->drrs.dp = NULL;
4878 mutex_unlock(&dev_priv->drrs.mutex);
4879
4880 cancel_delayed_work_sync(&dev_priv->drrs.work);
4881}
4882
4883static void intel_edp_drrs_downclock_work(struct work_struct *work)
4884{
4885 struct drm_i915_private *dev_priv =
4886 container_of(work, typeof(*dev_priv), drrs.work.work);
4887 struct intel_dp *intel_dp;
4888
4889 mutex_lock(&dev_priv->drrs.mutex);
4890
4891 intel_dp = dev_priv->drrs.dp;
4892
4893 if (!intel_dp)
4894 goto unlock;
4895
4816 /* 4896 /*
4817 * mutex taken to ensure that there is no race between differnt 4897 * The delayed work can race with an invalidate hence we need to
4818 * drrs calls trying to update refresh rate. This scenario may occur 4898 * recheck.
4819 * in future when idleness detection based DRRS in kernel and
4820 * possible calls from user space to set differnt RR are made.
4821 */ 4899 */
4822 4900
4823 mutex_lock(&intel_dp->drrs_state.mutex); 4901 if (dev_priv->drrs.busy_frontbuffer_bits)
4902 goto unlock;
4824 4903
4825 intel_dp->drrs_state.refresh_rate_type = index; 4904 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
4905 intel_dp_set_drrs_state(dev_priv->dev,
4906 intel_dp->attached_connector->panel.
4907 downclock_mode->vrefresh);
4826 4908
4827 mutex_unlock(&intel_dp->drrs_state.mutex); 4909unlock:
4828 4910
4829 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); 4911 mutex_unlock(&dev_priv->drrs.mutex);
4912}
4913
4914void intel_edp_drrs_invalidate(struct drm_device *dev,
4915 unsigned frontbuffer_bits)
4916{
4917 struct drm_i915_private *dev_priv = dev->dev_private;
4918 struct drm_crtc *crtc;
4919 enum pipe pipe;
4920
4921 if (!dev_priv->drrs.dp)
4922 return;
4923
4924 mutex_lock(&dev_priv->drrs.mutex);
4925 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
4926 pipe = to_intel_crtc(crtc)->pipe;
4927
4928 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
4929 cancel_delayed_work_sync(&dev_priv->drrs.work);
4930 intel_dp_set_drrs_state(dev_priv->dev,
4931 dev_priv->drrs.dp->attached_connector->panel.
4932 fixed_mode->vrefresh);
4933 }
4934
4935 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
4936
4937 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
4938 mutex_unlock(&dev_priv->drrs.mutex);
4939}
4940
4941void intel_edp_drrs_flush(struct drm_device *dev,
4942 unsigned frontbuffer_bits)
4943{
4944 struct drm_i915_private *dev_priv = dev->dev_private;
4945 struct drm_crtc *crtc;
4946 enum pipe pipe;
4947
4948 if (!dev_priv->drrs.dp)
4949 return;
4950
4951 mutex_lock(&dev_priv->drrs.mutex);
4952 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
4953 pipe = to_intel_crtc(crtc)->pipe;
4954 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
4955
4956 cancel_delayed_work_sync(&dev_priv->drrs.work);
4957
4958 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR &&
4959 !dev_priv->drrs.busy_frontbuffer_bits)
4960 schedule_delayed_work(&dev_priv->drrs.work,
4961 msecs_to_jiffies(1000));
4962 mutex_unlock(&dev_priv->drrs.mutex);
4830} 4963}
4831 4964
4832static struct drm_display_mode * 4965static struct drm_display_mode *
4833intel_dp_drrs_init(struct intel_digital_port *intel_dig_port, 4966intel_dp_drrs_init(struct intel_connector *intel_connector,
4834 struct intel_connector *intel_connector, 4967 struct drm_display_mode *fixed_mode)
4835 struct drm_display_mode *fixed_mode)
4836{ 4968{
4837 struct drm_connector *connector = &intel_connector->base; 4969 struct drm_connector *connector = &intel_connector->base;
4838 struct intel_dp *intel_dp = &intel_dig_port->dp; 4970 struct drm_device *dev = connector->dev;
4839 struct drm_device *dev = intel_dig_port->base.base.dev;
4840 struct drm_i915_private *dev_priv = dev->dev_private; 4971 struct drm_i915_private *dev_priv = dev->dev_private;
4841 struct drm_display_mode *downclock_mode = NULL; 4972 struct drm_display_mode *downclock_mode = NULL;
4842 4973
@@ -4858,13 +4989,13 @@ intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4858 return NULL; 4989 return NULL;
4859 } 4990 }
4860 4991
4861 dev_priv->drrs.connector = intel_connector; 4992 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
4862 4993
4863 mutex_init(&intel_dp->drrs_state.mutex); 4994 mutex_init(&dev_priv->drrs.mutex);
4864 4995
4865 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type; 4996 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4866 4997
4867 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR; 4998 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4868 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); 4999 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4869 return downclock_mode; 5000 return downclock_mode;
4870} 5001}
@@ -4884,7 +5015,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4884 struct edid *edid; 5015 struct edid *edid;
4885 enum pipe pipe = INVALID_PIPE; 5016 enum pipe pipe = INVALID_PIPE;
4886 5017
4887 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED; 5018 dev_priv->drrs.type = DRRS_NOT_SUPPORTED;
4888 5019
4889 if (!is_edp(intel_dp)) 5020 if (!is_edp(intel_dp))
4890 return true; 5021 return true;
@@ -4933,7 +5064,6 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4933 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { 5064 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4934 fixed_mode = drm_mode_duplicate(dev, scan); 5065 fixed_mode = drm_mode_duplicate(dev, scan);
4935 downclock_mode = intel_dp_drrs_init( 5066 downclock_mode = intel_dp_drrs_init(
4936 intel_dig_port,
4937 intel_connector, fixed_mode); 5067 intel_connector, fixed_mode);
4938 break; 5068 break;
4939 } 5069 }
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
index 7f8c6a66680a..9f67a379a9a5 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -26,11 +26,12 @@
26#include <drm/drmP.h> 26#include <drm/drmP.h>
27#include "i915_drv.h" 27#include "i915_drv.h"
28#include "intel_drv.h" 28#include "intel_drv.h"
29#include <drm/drm_atomic_helper.h>
29#include <drm/drm_crtc_helper.h> 30#include <drm/drm_crtc_helper.h>
30#include <drm/drm_edid.h> 31#include <drm/drm_edid.h>
31 32
32static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, 33static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
33 struct intel_crtc_config *pipe_config) 34 struct intel_crtc_state *pipe_config)
34{ 35{
35 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); 36 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
36 struct intel_digital_port *intel_dig_port = intel_mst->primary; 37 struct intel_digital_port *intel_dig_port = intel_mst->primary;
@@ -38,7 +39,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
38 struct drm_device *dev = encoder->base.dev; 39 struct drm_device *dev = encoder->base.dev;
39 int bpp; 40 int bpp;
40 int lane_count, slots; 41 int lane_count, slots;
41 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 42 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
42 struct intel_connector *found = NULL, *intel_connector; 43 struct intel_connector *found = NULL, *intel_connector;
43 int mst_pbn; 44 int mst_pbn;
44 45
@@ -157,7 +158,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder)
157 if (intel_dp->active_mst_links == 0) { 158 if (intel_dp->active_mst_links == 0) {
158 enum port port = intel_ddi_get_encoder_port(encoder); 159 enum port port = intel_ddi_get_encoder_port(encoder);
159 160
160 I915_WRITE(PORT_CLK_SEL(port), intel_crtc->config.ddi_pll_sel); 161 I915_WRITE(PORT_CLK_SEL(port),
162 intel_crtc->config->ddi_pll_sel);
161 163
162 intel_ddi_init_dp_buf_reg(&intel_dig_port->base); 164 intel_ddi_init_dp_buf_reg(&intel_dig_port->base);
163 165
@@ -170,7 +172,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder)
170 } 172 }
171 173
172 ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr, 174 ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr,
173 intel_mst->port, intel_crtc->config.pbn, &slots); 175 intel_mst->port,
176 intel_crtc->config->pbn, &slots);
174 if (ret == false) { 177 if (ret == false) {
175 DRM_ERROR("failed to allocate vcpi\n"); 178 DRM_ERROR("failed to allocate vcpi\n");
176 return; 179 return;
@@ -216,14 +219,14 @@ static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder,
216} 219}
217 220
218static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder, 221static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
219 struct intel_crtc_config *pipe_config) 222 struct intel_crtc_state *pipe_config)
220{ 223{
221 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); 224 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
222 struct intel_digital_port *intel_dig_port = intel_mst->primary; 225 struct intel_digital_port *intel_dig_port = intel_mst->primary;
223 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 226 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
224 struct drm_device *dev = encoder->base.dev; 227 struct drm_device *dev = encoder->base.dev;
225 struct drm_i915_private *dev_priv = dev->dev_private; 228 struct drm_i915_private *dev_priv = dev->dev_private;
226 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; 229 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
227 u32 temp, flags = 0; 230 u32 temp, flags = 0;
228 231
229 pipe_config->has_dp_encoder = true; 232 pipe_config->has_dp_encoder = true;
@@ -254,7 +257,7 @@ static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
254 default: 257 default:
255 break; 258 break;
256 } 259 }
257 pipe_config->adjusted_mode.flags |= flags; 260 pipe_config->base.adjusted_mode.flags |= flags;
258 intel_dp_get_m_n(crtc, pipe_config); 261 intel_dp_get_m_n(crtc, pipe_config);
259 262
260 intel_ddi_clock_get(&intel_dig_port->base, pipe_config); 263 intel_ddi_clock_get(&intel_dig_port->base, pipe_config);
@@ -311,7 +314,9 @@ static const struct drm_connector_funcs intel_dp_mst_connector_funcs = {
311 .detect = intel_dp_mst_detect, 314 .detect = intel_dp_mst_detect,
312 .fill_modes = drm_helper_probe_single_connector_modes, 315 .fill_modes = drm_helper_probe_single_connector_modes,
313 .set_property = intel_dp_mst_set_property, 316 .set_property = intel_dp_mst_set_property,
317 .atomic_get_property = intel_connector_atomic_get_property,
314 .destroy = intel_dp_mst_connector_destroy, 318 .destroy = intel_dp_mst_connector_destroy,
319 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
315}; 320};
316 321
317static int intel_dp_mst_get_modes(struct drm_connector *connector) 322static int intel_dp_mst_get_modes(struct drm_connector *connector)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 30e968f8c55e..eef79ccd0b7c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -143,7 +143,7 @@ struct intel_encoder {
143 bool connectors_active; 143 bool connectors_active;
144 void (*hot_plug)(struct intel_encoder *); 144 void (*hot_plug)(struct intel_encoder *);
145 bool (*compute_config)(struct intel_encoder *, 145 bool (*compute_config)(struct intel_encoder *,
146 struct intel_crtc_config *); 146 struct intel_crtc_state *);
147 void (*pre_pll_enable)(struct intel_encoder *); 147 void (*pre_pll_enable)(struct intel_encoder *);
148 void (*pre_enable)(struct intel_encoder *); 148 void (*pre_enable)(struct intel_encoder *);
149 void (*enable)(struct intel_encoder *); 149 void (*enable)(struct intel_encoder *);
@@ -159,7 +159,7 @@ struct intel_encoder {
159 * pre-filled the pipe config. Note that intel_encoder->base.crtc must 159 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
160 * be set correctly before calling this function. */ 160 * be set correctly before calling this function. */
161 void (*get_config)(struct intel_encoder *, 161 void (*get_config)(struct intel_encoder *,
162 struct intel_crtc_config *pipe_config); 162 struct intel_crtc_state *pipe_config);
163 /* 163 /*
164 * Called during system suspend after all pending requests for the 164 * Called during system suspend after all pending requests for the
165 * encoder are flushed (for example for DP AUX transactions) and 165 * encoder are flushed (for example for DP AUX transactions) and
@@ -257,13 +257,15 @@ struct intel_plane_state {
257 bool hides_primary; 257 bool hides_primary;
258}; 258};
259 259
260struct intel_plane_config { 260struct intel_initial_plane_config {
261 bool tiled; 261 unsigned int tiling;
262 int size; 262 int size;
263 u32 base; 263 u32 base;
264}; 264};
265 265
266struct intel_crtc_config { 266struct intel_crtc_state {
267 struct drm_crtc_state base;
268
267 /** 269 /**
268 * quirks - bitfield with hw state readout quirks 270 * quirks - bitfield with hw state readout quirks
269 * 271 *
@@ -276,16 +278,6 @@ struct intel_crtc_config {
276#define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */ 278#define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
277 unsigned long quirks; 279 unsigned long quirks;
278 280
279 /* User requested mode, only valid as a starting point to
280 * compute adjusted_mode, except in the case of (S)DVO where
281 * it's also for the output timings of the (S)DVO chip.
282 * adjusted_mode will then correspond to the S(DVO) chip's
283 * preferred input timings. */
284 struct drm_display_mode requested_mode;
285 /* Actual pipe timings ie. what we program into the pipe timing
286 * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
287 struct drm_display_mode adjusted_mode;
288
289 /* Pipe source size (ie. panel fitter input size) 281 /* Pipe source size (ie. panel fitter input size)
290 * All planes will be positioned inside this space, 282 * All planes will be positioned inside this space,
291 * and get clipped at the edges. */ 283 * and get clipped at the edges. */
@@ -476,9 +468,9 @@ struct intel_crtc {
476 uint32_t cursor_size; 468 uint32_t cursor_size;
477 uint32_t cursor_base; 469 uint32_t cursor_base;
478 470
479 struct intel_plane_config plane_config; 471 struct intel_initial_plane_config plane_config;
480 struct intel_crtc_config config; 472 struct intel_crtc_state *config;
481 struct intel_crtc_config *new_config; 473 struct intel_crtc_state *new_config;
482 bool new_enabled; 474 bool new_enabled;
483 475
484 /* reset counter value when the last flip was submitted */ 476 /* reset counter value when the last flip was submitted */
@@ -517,7 +509,6 @@ struct intel_plane {
517 struct drm_i915_gem_object *obj; 509 struct drm_i915_gem_object *obj;
518 bool can_scale; 510 bool can_scale;
519 int max_downscale; 511 int max_downscale;
520 unsigned int rotation;
521 512
522 /* Since we need to change the watermarks before/after 513 /* Since we need to change the watermarks before/after
523 * enabling/disabling the planes, we need to store the parameters here 514 * enabling/disabling the planes, we need to store the parameters here
@@ -526,6 +517,12 @@ struct intel_plane {
526 */ 517 */
527 struct intel_plane_wm_parameters wm; 518 struct intel_plane_wm_parameters wm;
528 519
520 /*
521 * NOTE: Do not place new plane state fields here (e.g., when adding
522 * new plane properties). New runtime state should now be placed in
523 * the intel_plane_state structure and accessed via drm_plane->state.
524 */
525
529 void (*update_plane)(struct drm_plane *plane, 526 void (*update_plane)(struct drm_plane *plane,
530 struct drm_crtc *crtc, 527 struct drm_crtc *crtc,
531 struct drm_framebuffer *fb, 528 struct drm_framebuffer *fb,
@@ -595,17 +592,6 @@ struct intel_hdmi {
595struct intel_dp_mst_encoder; 592struct intel_dp_mst_encoder;
596#define DP_MAX_DOWNSTREAM_PORTS 0x10 593#define DP_MAX_DOWNSTREAM_PORTS 0x10
597 594
598/**
599 * HIGH_RR is the highest eDP panel refresh rate read from EDID
600 * LOW_RR is the lowest eDP panel refresh rate found from EDID
601 * parsing for same resolution.
602 */
603enum edp_drrs_refresh_rate_type {
604 DRRS_HIGH_RR,
605 DRRS_LOW_RR,
606 DRRS_MAX_RR, /* RR count */
607};
608
609struct intel_dp { 595struct intel_dp {
610 uint32_t output_reg; 596 uint32_t output_reg;
611 uint32_t aux_ch_ctl_reg; 597 uint32_t aux_ch_ctl_reg;
@@ -661,12 +647,6 @@ struct intel_dp {
661 bool has_aux_irq, 647 bool has_aux_irq,
662 int send_bytes, 648 int send_bytes,
663 uint32_t aux_clock_divider); 649 uint32_t aux_clock_divider);
664 struct {
665 enum drrs_support_type type;
666 enum edp_drrs_refresh_rate_type refresh_rate_type;
667 struct mutex mutex;
668 } drrs_state;
669
670}; 650};
671 651
672struct intel_digital_port { 652struct intel_digital_port {
@@ -675,7 +655,7 @@ struct intel_digital_port {
675 u32 saved_port_bits; 655 u32 saved_port_bits;
676 struct intel_dp dp; 656 struct intel_dp dp;
677 struct intel_hdmi hdmi; 657 struct intel_hdmi hdmi;
678 bool (*hpd_pulse)(struct intel_digital_port *, bool); 658 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
679}; 659};
680 660
681struct intel_dp_mst_encoder { 661struct intel_dp_mst_encoder {
@@ -856,17 +836,18 @@ void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
856 enum transcoder cpu_transcoder); 836 enum transcoder cpu_transcoder);
857void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); 837void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
858void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); 838void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
859bool intel_ddi_pll_select(struct intel_crtc *crtc); 839bool intel_ddi_pll_select(struct intel_crtc *crtc,
840 struct intel_crtc_state *crtc_state);
860void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); 841void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
861void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); 842void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
862bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); 843bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
863void intel_ddi_fdi_disable(struct drm_crtc *crtc); 844void intel_ddi_fdi_disable(struct drm_crtc *crtc);
864void intel_ddi_get_config(struct intel_encoder *encoder, 845void intel_ddi_get_config(struct intel_encoder *encoder,
865 struct intel_crtc_config *pipe_config); 846 struct intel_crtc_state *pipe_config);
866 847
867void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder); 848void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
868void intel_ddi_clock_get(struct intel_encoder *encoder, 849void intel_ddi_clock_get(struct intel_encoder *encoder,
869 struct intel_crtc_config *pipe_config); 850 struct intel_crtc_state *pipe_config);
870void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state); 851void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
871 852
872/* intel_frontbuffer.c */ 853/* intel_frontbuffer.c */
@@ -896,6 +877,8 @@ void intel_frontbuffer_flip(struct drm_device *dev,
896 intel_frontbuffer_flush(dev, frontbuffer_bits); 877 intel_frontbuffer_flush(dev, frontbuffer_bits);
897} 878}
898 879
880int intel_fb_align_height(struct drm_device *dev, int height,
881 unsigned int tiling);
899void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire); 882void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
900 883
901 884
@@ -907,6 +890,7 @@ void i915_audio_component_init(struct drm_i915_private *dev_priv);
907void i915_audio_component_cleanup(struct drm_i915_private *dev_priv); 890void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
908 891
909/* intel_display.c */ 892/* intel_display.c */
893extern const struct drm_plane_funcs intel_plane_funcs;
910bool intel_has_pending_fb_unpin(struct drm_device *dev); 894bool intel_has_pending_fb_unpin(struct drm_device *dev);
911int intel_pch_rawclk(struct drm_device *dev); 895int intel_pch_rawclk(struct drm_device *dev);
912void intel_mark_busy(struct drm_device *dev); 896void intel_mark_busy(struct drm_device *dev);
@@ -961,6 +945,14 @@ int intel_prepare_plane_fb(struct drm_plane *plane,
961 struct drm_framebuffer *fb); 945 struct drm_framebuffer *fb);
962void intel_cleanup_plane_fb(struct drm_plane *plane, 946void intel_cleanup_plane_fb(struct drm_plane *plane,
963 struct drm_framebuffer *fb); 947 struct drm_framebuffer *fb);
948int intel_plane_atomic_get_property(struct drm_plane *plane,
949 const struct drm_plane_state *state,
950 struct drm_property *property,
951 uint64_t *val);
952int intel_plane_atomic_set_property(struct drm_plane *plane,
953 struct drm_plane_state *state,
954 struct drm_property *property,
955 uint64_t val);
964 956
965/* shared dpll functions */ 957/* shared dpll functions */
966struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc); 958struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
@@ -969,7 +961,8 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
969 bool state); 961 bool state);
970#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) 962#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
971#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) 963#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
972struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc); 964struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
965 struct intel_crtc_state *state);
973void intel_put_shared_dpll(struct intel_crtc *crtc); 966void intel_put_shared_dpll(struct intel_crtc *crtc);
974 967
975void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, 968void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
@@ -999,11 +992,11 @@ void intel_finish_reset(struct drm_device *dev);
999void hsw_enable_pc8(struct drm_i915_private *dev_priv); 992void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1000void hsw_disable_pc8(struct drm_i915_private *dev_priv); 993void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1001void intel_dp_get_m_n(struct intel_crtc *crtc, 994void intel_dp_get_m_n(struct intel_crtc *crtc,
1002 struct intel_crtc_config *pipe_config); 995 struct intel_crtc_state *pipe_config);
1003void intel_dp_set_m_n(struct intel_crtc *crtc); 996void intel_dp_set_m_n(struct intel_crtc *crtc);
1004int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); 997int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1005void 998void
1006ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, 999ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
1007 int dotclock); 1000 int dotclock);
1008bool intel_crtc_active(struct drm_crtc *crtc); 1001bool intel_crtc_active(struct drm_crtc *crtc);
1009void hsw_enable_ips(struct intel_crtc *crtc); 1002void hsw_enable_ips(struct intel_crtc *crtc);
@@ -1011,8 +1004,7 @@ void hsw_disable_ips(struct intel_crtc *crtc);
1011enum intel_display_power_domain 1004enum intel_display_power_domain
1012intel_display_port_power_domain(struct intel_encoder *intel_encoder); 1005intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1013void intel_mode_from_pipe_config(struct drm_display_mode *mode, 1006void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1014 struct intel_crtc_config *pipe_config); 1007 struct intel_crtc_state *pipe_config);
1015int intel_format_to_fourcc(int format);
1016void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); 1008void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
1017void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file); 1009void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
1018 1010
@@ -1028,16 +1020,15 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1028void intel_dp_check_link_status(struct intel_dp *intel_dp); 1020void intel_dp_check_link_status(struct intel_dp *intel_dp);
1029int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); 1021int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1030bool intel_dp_compute_config(struct intel_encoder *encoder, 1022bool intel_dp_compute_config(struct intel_encoder *encoder,
1031 struct intel_crtc_config *pipe_config); 1023 struct intel_crtc_state *pipe_config);
1032bool intel_dp_is_edp(struct drm_device *dev, enum port port); 1024bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1033bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, 1025enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1034 bool long_hpd); 1026 bool long_hpd);
1035void intel_edp_backlight_on(struct intel_dp *intel_dp); 1027void intel_edp_backlight_on(struct intel_dp *intel_dp);
1036void intel_edp_backlight_off(struct intel_dp *intel_dp); 1028void intel_edp_backlight_off(struct intel_dp *intel_dp);
1037void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); 1029void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1038void intel_edp_panel_on(struct intel_dp *intel_dp); 1030void intel_edp_panel_on(struct intel_dp *intel_dp);
1039void intel_edp_panel_off(struct intel_dp *intel_dp); 1031void intel_edp_panel_off(struct intel_dp *intel_dp);
1040void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
1041void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector); 1032void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1042void intel_dp_mst_suspend(struct drm_device *dev); 1033void intel_dp_mst_suspend(struct drm_device *dev);
1043void intel_dp_mst_resume(struct drm_device *dev); 1034void intel_dp_mst_resume(struct drm_device *dev);
@@ -1053,6 +1044,11 @@ int intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
1053 uint32_t src_w, uint32_t src_h); 1044 uint32_t src_w, uint32_t src_h);
1054int intel_disable_plane(struct drm_plane *plane); 1045int intel_disable_plane(struct drm_plane *plane);
1055void intel_plane_destroy(struct drm_plane *plane); 1046void intel_plane_destroy(struct drm_plane *plane);
1047void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1048void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1049void intel_edp_drrs_invalidate(struct drm_device *dev,
1050 unsigned frontbuffer_bits);
1051void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1056 1052
1057/* intel_dp_mst.c */ 1053/* intel_dp_mst.c */
1058int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); 1054int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
@@ -1109,7 +1105,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1109 struct intel_connector *intel_connector); 1105 struct intel_connector *intel_connector);
1110struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); 1106struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1111bool intel_hdmi_compute_config(struct intel_encoder *encoder, 1107bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1112 struct intel_crtc_config *pipe_config); 1108 struct intel_crtc_state *pipe_config);
1113 1109
1114 1110
1115/* intel_lvds.c */ 1111/* intel_lvds.c */
@@ -1144,10 +1140,10 @@ void intel_panel_fini(struct intel_panel *panel);
1144void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, 1140void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1145 struct drm_display_mode *adjusted_mode); 1141 struct drm_display_mode *adjusted_mode);
1146void intel_pch_panel_fitting(struct intel_crtc *crtc, 1142void intel_pch_panel_fitting(struct intel_crtc *crtc,
1147 struct intel_crtc_config *pipe_config, 1143 struct intel_crtc_state *pipe_config,
1148 int fitting_mode); 1144 int fitting_mode);
1149void intel_gmch_panel_fitting(struct intel_crtc *crtc, 1145void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1150 struct intel_crtc_config *pipe_config, 1146 struct intel_crtc_state *pipe_config,
1151 int fitting_mode); 1147 int fitting_mode);
1152void intel_panel_set_backlight_acpi(struct intel_connector *connector, 1148void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1153 u32 level, u32 max); 1149 u32 level, u32 max);
@@ -1253,6 +1249,21 @@ void intel_pre_disable_primary(struct drm_crtc *crtc);
1253void intel_tv_init(struct drm_device *dev); 1249void intel_tv_init(struct drm_device *dev);
1254 1250
1255/* intel_atomic.c */ 1251/* intel_atomic.c */
1252int intel_atomic_check(struct drm_device *dev,
1253 struct drm_atomic_state *state);
1254int intel_atomic_commit(struct drm_device *dev,
1255 struct drm_atomic_state *state,
1256 bool async);
1257int intel_connector_atomic_get_property(struct drm_connector *connector,
1258 const struct drm_connector_state *state,
1259 struct drm_property *property,
1260 uint64_t *val);
1261struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1262void intel_crtc_destroy_state(struct drm_crtc *crtc,
1263 struct drm_crtc_state *state);
1264
1265/* intel_atomic_plane.c */
1266struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1256struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane); 1267struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1257void intel_plane_destroy_state(struct drm_plane *plane, 1268void intel_plane_destroy_state(struct drm_plane *plane,
1258 struct drm_plane_state *state); 1269 struct drm_plane_state *state);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 42b6d6f5cecc..ef3df5e3d819 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -24,24 +24,219 @@
24 */ 24 */
25 25
26#include <drm/drmP.h> 26#include <drm/drmP.h>
27#include <drm/drm_atomic_helper.h>
27#include <drm/drm_crtc.h> 28#include <drm/drm_crtc.h>
28#include <drm/drm_edid.h> 29#include <drm/drm_edid.h>
29#include <drm/i915_drm.h> 30#include <drm/i915_drm.h>
31#include <drm/drm_panel.h>
32#include <drm/drm_mipi_dsi.h>
30#include <linux/slab.h> 33#include <linux/slab.h>
31#include "i915_drv.h" 34#include "i915_drv.h"
32#include "intel_drv.h" 35#include "intel_drv.h"
33#include "intel_dsi.h" 36#include "intel_dsi.h"
34#include "intel_dsi_cmd.h"
35 37
36/* the sub-encoders aka panel drivers */ 38static const struct {
37static const struct intel_dsi_device intel_dsi_devices[] = { 39 u16 panel_id;
40 struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id);
41} intel_dsi_drivers[] = {
38 { 42 {
39 .panel_id = MIPI_DSI_GENERIC_PANEL_ID, 43 .panel_id = MIPI_DSI_GENERIC_PANEL_ID,
40 .name = "vbt-generic-dsi-vid-mode-display", 44 .init = vbt_panel_init,
41 .dev_ops = &vbt_generic_dsi_display_ops,
42 }, 45 },
43}; 46};
44 47
48static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
49{
50 struct drm_encoder *encoder = &intel_dsi->base.base;
51 struct drm_device *dev = encoder->dev;
52 struct drm_i915_private *dev_priv = dev->dev_private;
53 u32 mask;
54
55 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
56 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
57
58 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100))
59 DRM_ERROR("DPI FIFOs are not empty\n");
60}
61
62static void write_data(struct drm_i915_private *dev_priv, u32 reg,
63 const u8 *data, u32 len)
64{
65 u32 i, j;
66
67 for (i = 0; i < len; i += 4) {
68 u32 val = 0;
69
70 for (j = 0; j < min_t(u32, len - i, 4); j++)
71 val |= *data++ << 8 * j;
72
73 I915_WRITE(reg, val);
74 }
75}
76
77static void read_data(struct drm_i915_private *dev_priv, u32 reg,
78 u8 *data, u32 len)
79{
80 u32 i, j;
81
82 for (i = 0; i < len; i += 4) {
83 u32 val = I915_READ(reg);
84
85 for (j = 0; j < min_t(u32, len - i, 4); j++)
86 *data++ = val >> 8 * j;
87 }
88}
89
90static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
91 const struct mipi_dsi_msg *msg)
92{
93 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
94 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
95 struct drm_i915_private *dev_priv = dev->dev_private;
96 enum port port = intel_dsi_host->port;
97 struct mipi_dsi_packet packet;
98 ssize_t ret;
99 const u8 *header, *data;
100 u32 data_reg, data_mask, ctrl_reg, ctrl_mask;
101
102 ret = mipi_dsi_create_packet(&packet, msg);
103 if (ret < 0)
104 return ret;
105
106 header = packet.header;
107 data = packet.payload;
108
109 if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
110 data_reg = MIPI_LP_GEN_DATA(port);
111 data_mask = LP_DATA_FIFO_FULL;
112 ctrl_reg = MIPI_LP_GEN_CTRL(port);
113 ctrl_mask = LP_CTRL_FIFO_FULL;
114 } else {
115 data_reg = MIPI_HS_GEN_DATA(port);
116 data_mask = HS_DATA_FIFO_FULL;
117 ctrl_reg = MIPI_HS_GEN_CTRL(port);
118 ctrl_mask = HS_CTRL_FIFO_FULL;
119 }
120
121 /* note: this is never true for reads */
122 if (packet.payload_length) {
123
124 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50))
125 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
126
127 write_data(dev_priv, data_reg, packet.payload,
128 packet.payload_length);
129 }
130
131 if (msg->rx_len) {
132 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
133 }
134
135 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) {
136 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
137 }
138
139 I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
140
141 /* ->rx_len is set only for reads */
142 if (msg->rx_len) {
143 data_mask = GEN_READ_DATA_AVAIL;
144 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50))
145 DRM_ERROR("Timeout waiting for read data.\n");
146
147 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
148 }
149
150 /* XXX: fix for reads and writes */
151 return 4 + packet.payload_length;
152}
153
154static int intel_dsi_host_attach(struct mipi_dsi_host *host,
155 struct mipi_dsi_device *dsi)
156{
157 return 0;
158}
159
160static int intel_dsi_host_detach(struct mipi_dsi_host *host,
161 struct mipi_dsi_device *dsi)
162{
163 return 0;
164}
165
166static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
167 .attach = intel_dsi_host_attach,
168 .detach = intel_dsi_host_detach,
169 .transfer = intel_dsi_host_transfer,
170};
171
172static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
173 enum port port)
174{
175 struct intel_dsi_host *host;
176 struct mipi_dsi_device *device;
177
178 host = kzalloc(sizeof(*host), GFP_KERNEL);
179 if (!host)
180 return NULL;
181
182 host->base.ops = &intel_dsi_host_ops;
183 host->intel_dsi = intel_dsi;
184 host->port = port;
185
186 /*
187 * We should call mipi_dsi_host_register(&host->base) here, but we don't
188 * have a host->dev, and we don't have OF stuff either. So just use the
189 * dsi framework as a library and hope for the best. Create the dsi
190 * devices by ourselves here too. Need to be careful though, because we
191 * don't initialize any of the driver model devices here.
192 */
193 device = kzalloc(sizeof(*device), GFP_KERNEL);
194 if (!device) {
195 kfree(host);
196 return NULL;
197 }
198
199 device->host = &host->base;
200 host->device = device;
201
202 return host;
203}
204
205/*
206 * send a video mode command
207 *
208 * XXX: commands with data in MIPI_DPI_DATA?
209 */
210static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
211 enum port port)
212{
213 struct drm_encoder *encoder = &intel_dsi->base.base;
214 struct drm_device *dev = encoder->dev;
215 struct drm_i915_private *dev_priv = dev->dev_private;
216 u32 mask;
217
218 /* XXX: pipe, hs */
219 if (hs)
220 cmd &= ~DPI_LP_MODE;
221 else
222 cmd |= DPI_LP_MODE;
223
224 /* clear bit */
225 I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
226
227 /* XXX: old code skips write if control unchanged */
228 if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
229 DRM_ERROR("Same special packet %02x twice in a row.\n", cmd);
230
231 I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
232
233 mask = SPL_PKT_SENT_INTERRUPT;
234 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100))
235 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
236
237 return 0;
238}
239
45static void band_gap_reset(struct drm_i915_private *dev_priv) 240static void band_gap_reset(struct drm_i915_private *dev_priv)
46{ 241{
47 mutex_lock(&dev_priv->dpio_lock); 242 mutex_lock(&dev_priv->dpio_lock);
@@ -56,12 +251,6 @@ static void band_gap_reset(struct drm_i915_private *dev_priv)
56 mutex_unlock(&dev_priv->dpio_lock); 251 mutex_unlock(&dev_priv->dpio_lock);
57} 252}
58 253
59static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
60{
61 return container_of(intel_attached_encoder(connector),
62 struct intel_dsi, base);
63}
64
65static inline bool is_vid_mode(struct intel_dsi *intel_dsi) 254static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
66{ 255{
67 return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; 256 return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
@@ -78,14 +267,13 @@ static void intel_dsi_hot_plug(struct intel_encoder *encoder)
78} 267}
79 268
80static bool intel_dsi_compute_config(struct intel_encoder *encoder, 269static bool intel_dsi_compute_config(struct intel_encoder *encoder,
81 struct intel_crtc_config *config) 270 struct intel_crtc_state *config)
82{ 271{
83 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 272 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
84 base); 273 base);
85 struct intel_connector *intel_connector = intel_dsi->attached_connector; 274 struct intel_connector *intel_connector = intel_dsi->attached_connector;
86 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 275 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
87 struct drm_display_mode *adjusted_mode = &config->adjusted_mode; 276 struct drm_display_mode *adjusted_mode = &config->base.adjusted_mode;
88 struct drm_display_mode *mode = &config->requested_mode;
89 277
90 DRM_DEBUG_KMS("\n"); 278 DRM_DEBUG_KMS("\n");
91 279
@@ -95,10 +283,6 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
95 /* DSI uses short packets for sync events, so clear mode flags for DSI */ 283 /* DSI uses short packets for sync events, so clear mode flags for DSI */
96 adjusted_mode->flags = 0; 284 adjusted_mode->flags = 0;
97 285
98 if (intel_dsi->dev.dev_ops->mode_fixup)
99 return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev,
100 mode, adjusted_mode);
101
102 return true; 286 return true;
103} 287}
104 288
@@ -197,23 +381,24 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
197{ 381{
198 struct drm_device *dev = encoder->base.dev; 382 struct drm_device *dev = encoder->base.dev;
199 struct drm_i915_private *dev_priv = dev->dev_private; 383 struct drm_i915_private *dev_priv = dev->dev_private;
200 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
201 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 384 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
202 enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); 385 enum port port;
203 386
204 DRM_DEBUG_KMS("\n"); 387 DRM_DEBUG_KMS("\n");
205 388
206 if (is_cmd_mode(intel_dsi)) 389 if (is_cmd_mode(intel_dsi)) {
207 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); 390 for_each_dsi_port(port, intel_dsi->ports)
208 else { 391 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
392 } else {
209 msleep(20); /* XXX */ 393 msleep(20); /* XXX */
210 dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN); 394 for_each_dsi_port(port, intel_dsi->ports)
395 dpi_send_cmd(intel_dsi, TURN_ON, false, port);
211 msleep(100); 396 msleep(100);
212 397
213 if (intel_dsi->dev.dev_ops->enable) 398 drm_panel_enable(intel_dsi->panel);
214 intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
215 399
216 wait_for_dsi_fifo_empty(intel_dsi); 400 for_each_dsi_port(port, intel_dsi->ports)
401 wait_for_dsi_fifo_empty(intel_dsi, port);
217 402
218 intel_dsi_port_enable(encoder); 403 intel_dsi_port_enable(encoder);
219 } 404 }
@@ -226,6 +411,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
226 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 411 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
227 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 412 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
228 enum pipe pipe = intel_crtc->pipe; 413 enum pipe pipe = intel_crtc->pipe;
414 enum port port;
229 u32 tmp; 415 u32 tmp;
230 416
231 DRM_DEBUG_KMS("\n"); 417 DRM_DEBUG_KMS("\n");
@@ -237,7 +423,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
237 I915_WRITE(DPLL(pipe), tmp); 423 I915_WRITE(DPLL(pipe), tmp);
238 424
239 /* update the hw state for DPLL */ 425 /* update the hw state for DPLL */
240 intel_crtc->config.dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV | 426 intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV |
241 DPLL_REFA_CLK_ENABLE_VLV; 427 DPLL_REFA_CLK_ENABLE_VLV;
242 428
243 tmp = I915_READ(DSPCLK_GATE_D); 429 tmp = I915_READ(DSPCLK_GATE_D);
@@ -249,13 +435,10 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
249 435
250 msleep(intel_dsi->panel_on_delay); 436 msleep(intel_dsi->panel_on_delay);
251 437
252 if (intel_dsi->dev.dev_ops->panel_reset) 438 drm_panel_prepare(intel_dsi->panel);
253 intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
254 439
255 if (intel_dsi->dev.dev_ops->send_otp_cmds) 440 for_each_dsi_port(port, intel_dsi->ports)
256 intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev); 441 wait_for_dsi_fifo_empty(intel_dsi, port);
257
258 wait_for_dsi_fifo_empty(intel_dsi);
259 442
260 /* Enable port in pre-enable phase itself because as per hw team 443 /* Enable port in pre-enable phase itself because as per hw team
261 * recommendation, port should be enabled befor plane & pipe */ 444 * recommendation, port should be enabled befor plane & pipe */
@@ -275,12 +458,14 @@ static void intel_dsi_enable_nop(struct intel_encoder *encoder)
275static void intel_dsi_pre_disable(struct intel_encoder *encoder) 458static void intel_dsi_pre_disable(struct intel_encoder *encoder)
276{ 459{
277 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 460 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
461 enum port port;
278 462
279 DRM_DEBUG_KMS("\n"); 463 DRM_DEBUG_KMS("\n");
280 464
281 if (is_vid_mode(intel_dsi)) { 465 if (is_vid_mode(intel_dsi)) {
282 /* Send Shutdown command to the panel in LP mode */ 466 /* Send Shutdown command to the panel in LP mode */
283 dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN); 467 for_each_dsi_port(port, intel_dsi->ports)
468 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
284 msleep(10); 469 msleep(10);
285 } 470 }
286} 471}
@@ -296,7 +481,8 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
296 DRM_DEBUG_KMS("\n"); 481 DRM_DEBUG_KMS("\n");
297 482
298 if (is_vid_mode(intel_dsi)) { 483 if (is_vid_mode(intel_dsi)) {
299 wait_for_dsi_fifo_empty(intel_dsi); 484 for_each_dsi_port(port, intel_dsi->ports)
485 wait_for_dsi_fifo_empty(intel_dsi, port);
300 486
301 intel_dsi_port_disable(encoder); 487 intel_dsi_port_disable(encoder);
302 msleep(2); 488 msleep(2);
@@ -322,10 +508,10 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
322 } 508 }
323 /* if disable packets are sent before sending shutdown packet then in 509 /* if disable packets are sent before sending shutdown packet then in
324 * some next enable sequence send turn on packet error is observed */ 510 * some next enable sequence send turn on packet error is observed */
325 if (intel_dsi->dev.dev_ops->disable) 511 drm_panel_disable(intel_dsi->panel);
326 intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);
327 512
328 wait_for_dsi_fifo_empty(intel_dsi); 513 for_each_dsi_port(port, intel_dsi->ports)
514 wait_for_dsi_fifo_empty(intel_dsi, port);
329} 515}
330 516
331static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) 517static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
@@ -387,8 +573,7 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder)
387 val &= ~DPOUNIT_CLOCK_GATE_DISABLE; 573 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
388 I915_WRITE(DSPCLK_GATE_D, val); 574 I915_WRITE(DSPCLK_GATE_D, val);
389 575
390 if (intel_dsi->dev.dev_ops->disable_panel_power) 576 drm_panel_unprepare(intel_dsi->panel);
391 intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev);
392 577
393 msleep(intel_dsi->panel_off_delay); 578 msleep(intel_dsi->panel_off_delay);
394 msleep(intel_dsi->panel_pwr_cycle_delay); 579 msleep(intel_dsi->panel_pwr_cycle_delay);
@@ -437,7 +622,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
437} 622}
438 623
439static void intel_dsi_get_config(struct intel_encoder *encoder, 624static void intel_dsi_get_config(struct intel_encoder *encoder,
440 struct intel_crtc_config *pipe_config) 625 struct intel_crtc_state *pipe_config)
441{ 626{
442 u32 pclk; 627 u32 pclk;
443 DRM_DEBUG_KMS("\n"); 628 DRM_DEBUG_KMS("\n");
@@ -452,7 +637,7 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
452 if (!pclk) 637 if (!pclk)
453 return; 638 return;
454 639
455 pipe_config->adjusted_mode.crtc_clock = pclk; 640 pipe_config->base.adjusted_mode.crtc_clock = pclk;
456 pipe_config->port_clock = pclk; 641 pipe_config->port_clock = pclk;
457} 642}
458 643
@@ -462,7 +647,6 @@ intel_dsi_mode_valid(struct drm_connector *connector,
462{ 647{
463 struct intel_connector *intel_connector = to_intel_connector(connector); 648 struct intel_connector *intel_connector = to_intel_connector(connector);
464 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 649 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
465 struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
466 650
467 DRM_DEBUG_KMS("\n"); 651 DRM_DEBUG_KMS("\n");
468 652
@@ -478,7 +662,7 @@ intel_dsi_mode_valid(struct drm_connector *connector,
478 return MODE_PANEL; 662 return MODE_PANEL;
479 } 663 }
480 664
481 return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode); 665 return MODE_OK;
482} 666}
483 667
484/* return txclkesc cycles in terms of divider and duration in us */ 668/* return txclkesc cycles in terms of divider and duration in us */
@@ -511,7 +695,7 @@ static void set_dsi_timings(struct drm_encoder *encoder,
511 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 695 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
512 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 696 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
513 enum port port; 697 enum port port;
514 unsigned int bpp = intel_crtc->config.pipe_bpp; 698 unsigned int bpp = intel_crtc->config->pipe_bpp;
515 unsigned int lane_count = intel_dsi->lane_count; 699 unsigned int lane_count = intel_dsi->lane_count;
516 700
517 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 701 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
@@ -566,9 +750,9 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
566 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 750 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
567 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 751 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
568 struct drm_display_mode *adjusted_mode = 752 struct drm_display_mode *adjusted_mode =
569 &intel_crtc->config.adjusted_mode; 753 &intel_crtc->config->base.adjusted_mode;
570 enum port port; 754 enum port port;
571 unsigned int bpp = intel_crtc->config.pipe_bpp; 755 unsigned int bpp = intel_crtc->config->pipe_bpp;
572 u32 val, tmp; 756 u32 val, tmp;
573 u16 mode_hdisplay; 757 u16 mode_hdisplay;
574 758
@@ -727,20 +911,7 @@ static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
727static enum drm_connector_status 911static enum drm_connector_status
728intel_dsi_detect(struct drm_connector *connector, bool force) 912intel_dsi_detect(struct drm_connector *connector, bool force)
729{ 913{
730 struct intel_dsi *intel_dsi = intel_attached_dsi(connector); 914 return connector_status_connected;
731 struct intel_encoder *intel_encoder = &intel_dsi->base;
732 enum intel_display_power_domain power_domain;
733 enum drm_connector_status connector_status;
734 struct drm_i915_private *dev_priv = intel_encoder->base.dev->dev_private;
735
736 DRM_DEBUG_KMS("\n");
737 power_domain = intel_display_port_power_domain(intel_encoder);
738
739 intel_display_power_get(dev_priv, power_domain);
740 connector_status = intel_dsi->dev.dev_ops->detect(&intel_dsi->dev);
741 intel_display_power_put(dev_priv, power_domain);
742
743 return connector_status;
744} 915}
745 916
746static int intel_dsi_get_modes(struct drm_connector *connector) 917static int intel_dsi_get_modes(struct drm_connector *connector)
@@ -766,7 +937,7 @@ static int intel_dsi_get_modes(struct drm_connector *connector)
766 return 1; 937 return 1;
767} 938}
768 939
769static void intel_dsi_destroy(struct drm_connector *connector) 940static void intel_dsi_connector_destroy(struct drm_connector *connector)
770{ 941{
771 struct intel_connector *intel_connector = to_intel_connector(connector); 942 struct intel_connector *intel_connector = to_intel_connector(connector);
772 943
@@ -776,8 +947,20 @@ static void intel_dsi_destroy(struct drm_connector *connector)
776 kfree(connector); 947 kfree(connector);
777} 948}
778 949
950static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
951{
952 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
953
954 if (intel_dsi->panel) {
955 drm_panel_detach(intel_dsi->panel);
956 /* XXX: Logically this call belongs in the panel driver. */
957 drm_panel_remove(intel_dsi->panel);
958 }
959 intel_encoder_destroy(encoder);
960}
961
779static const struct drm_encoder_funcs intel_dsi_funcs = { 962static const struct drm_encoder_funcs intel_dsi_funcs = {
780 .destroy = intel_encoder_destroy, 963 .destroy = intel_dsi_encoder_destroy,
781}; 964};
782 965
783static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { 966static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
@@ -789,8 +972,10 @@ static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs
789static const struct drm_connector_funcs intel_dsi_connector_funcs = { 972static const struct drm_connector_funcs intel_dsi_connector_funcs = {
790 .dpms = intel_connector_dpms, 973 .dpms = intel_connector_dpms,
791 .detect = intel_dsi_detect, 974 .detect = intel_dsi_detect,
792 .destroy = intel_dsi_destroy, 975 .destroy = intel_dsi_connector_destroy,
793 .fill_modes = drm_helper_probe_single_connector_modes, 976 .fill_modes = drm_helper_probe_single_connector_modes,
977 .atomic_get_property = intel_connector_atomic_get_property,
978 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
794}; 979};
795 980
796void intel_dsi_init(struct drm_device *dev) 981void intel_dsi_init(struct drm_device *dev)
@@ -800,9 +985,9 @@ void intel_dsi_init(struct drm_device *dev)
800 struct drm_encoder *encoder; 985 struct drm_encoder *encoder;
801 struct intel_connector *intel_connector; 986 struct intel_connector *intel_connector;
802 struct drm_connector *connector; 987 struct drm_connector *connector;
803 struct drm_display_mode *fixed_mode = NULL; 988 struct drm_display_mode *scan, *fixed_mode = NULL;
804 struct drm_i915_private *dev_priv = dev->dev_private; 989 struct drm_i915_private *dev_priv = dev->dev_private;
805 const struct intel_dsi_device *dsi; 990 enum port port;
806 unsigned int i; 991 unsigned int i;
807 992
808 DRM_DEBUG_KMS("\n"); 993 DRM_DEBUG_KMS("\n");
@@ -851,7 +1036,11 @@ void intel_dsi_init(struct drm_device *dev)
851 intel_connector->unregister = intel_connector_unregister; 1036 intel_connector->unregister = intel_connector_unregister;
852 1037
853 /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */ 1038 /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */
854 if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) { 1039 if (dev_priv->vbt.dsi.config->dual_link) {
1040 /* XXX: does dual link work on either pipe? */
1041 intel_encoder->crtc_mask = (1 << PIPE_A);
1042 intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
1043 } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) {
855 intel_encoder->crtc_mask = (1 << PIPE_A); 1044 intel_encoder->crtc_mask = (1 << PIPE_A);
856 intel_dsi->ports = (1 << PORT_A); 1045 intel_dsi->ports = (1 << PORT_A);
857 } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) { 1046 } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) {
@@ -859,15 +1048,25 @@ void intel_dsi_init(struct drm_device *dev)
859 intel_dsi->ports = (1 << PORT_C); 1048 intel_dsi->ports = (1 << PORT_C);
860 } 1049 }
861 1050
862 for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) { 1051 /* Create a DSI host (and a device) for each port. */
863 dsi = &intel_dsi_devices[i]; 1052 for_each_dsi_port(port, intel_dsi->ports) {
864 intel_dsi->dev = *dsi; 1053 struct intel_dsi_host *host;
1054
1055 host = intel_dsi_host_init(intel_dsi, port);
1056 if (!host)
1057 goto err;
865 1058
866 if (dsi->dev_ops->init(&intel_dsi->dev)) 1059 intel_dsi->dsi_hosts[port] = host;
1060 }
1061
1062 for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) {
1063 intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi,
1064 intel_dsi_drivers[i].panel_id);
1065 if (intel_dsi->panel)
867 break; 1066 break;
868 } 1067 }
869 1068
870 if (i == ARRAY_SIZE(intel_dsi_devices)) { 1069 if (!intel_dsi->panel) {
871 DRM_DEBUG_KMS("no device found\n"); 1070 DRM_DEBUG_KMS("no device found\n");
872 goto err; 1071 goto err;
873 } 1072 }
@@ -887,13 +1086,23 @@ void intel_dsi_init(struct drm_device *dev)
887 1086
888 drm_connector_register(connector); 1087 drm_connector_register(connector);
889 1088
890 fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev); 1089 drm_panel_attach(intel_dsi->panel, connector);
1090
1091 mutex_lock(&dev->mode_config.mutex);
1092 drm_panel_get_modes(intel_dsi->panel);
1093 list_for_each_entry(scan, &connector->probed_modes, head) {
1094 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
1095 fixed_mode = drm_mode_duplicate(dev, scan);
1096 break;
1097 }
1098 }
1099 mutex_unlock(&dev->mode_config.mutex);
1100
891 if (!fixed_mode) { 1101 if (!fixed_mode) {
892 DRM_DEBUG_KMS("no fixed mode\n"); 1102 DRM_DEBUG_KMS("no fixed mode\n");
893 goto err; 1103 goto err;
894 } 1104 }
895 1105
896 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
897 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); 1106 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
898 1107
899 return; 1108 return;
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 8fe2064dd804..2784ac442368 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -26,6 +26,7 @@
26 26
27#include <drm/drmP.h> 27#include <drm/drmP.h>
28#include <drm/drm_crtc.h> 28#include <drm/drm_crtc.h>
29#include <drm/drm_mipi_dsi.h>
29#include "intel_drv.h" 30#include "intel_drv.h"
30 31
31/* Dual Link support */ 32/* Dual Link support */
@@ -33,53 +34,13 @@
33#define DSI_DUAL_LINK_FRONT_BACK 1 34#define DSI_DUAL_LINK_FRONT_BACK 1
34#define DSI_DUAL_LINK_PIXEL_ALT 2 35#define DSI_DUAL_LINK_PIXEL_ALT 2
35 36
36struct intel_dsi_device { 37struct intel_dsi_host;
37 unsigned int panel_id;
38 const char *name;
39 const struct intel_dsi_dev_ops *dev_ops;
40 void *dev_priv;
41};
42
43struct intel_dsi_dev_ops {
44 bool (*init)(struct intel_dsi_device *dsi);
45
46 void (*panel_reset)(struct intel_dsi_device *dsi);
47
48 void (*disable_panel_power)(struct intel_dsi_device *dsi);
49
50 /* one time programmable commands if needed */
51 void (*send_otp_cmds)(struct intel_dsi_device *dsi);
52
53 /* This callback must be able to assume DSI commands can be sent */
54 void (*enable)(struct intel_dsi_device *dsi);
55
56 /* This callback must be able to assume DSI commands can be sent */
57 void (*disable)(struct intel_dsi_device *dsi);
58
59 int (*mode_valid)(struct intel_dsi_device *dsi,
60 struct drm_display_mode *mode);
61
62 bool (*mode_fixup)(struct intel_dsi_device *dsi,
63 const struct drm_display_mode *mode,
64 struct drm_display_mode *adjusted_mode);
65
66 void (*mode_set)(struct intel_dsi_device *dsi,
67 struct drm_display_mode *mode,
68 struct drm_display_mode *adjusted_mode);
69
70 enum drm_connector_status (*detect)(struct intel_dsi_device *dsi);
71
72 bool (*get_hw_state)(struct intel_dsi_device *dev);
73
74 struct drm_display_mode *(*get_modes)(struct intel_dsi_device *dsi);
75
76 void (*destroy) (struct intel_dsi_device *dsi);
77};
78 38
79struct intel_dsi { 39struct intel_dsi {
80 struct intel_encoder base; 40 struct intel_encoder base;
81 41
82 struct intel_dsi_device dev; 42 struct drm_panel *panel;
43 struct intel_dsi_host *dsi_hosts[I915_MAX_PORTS];
83 44
84 struct intel_connector *attached_connector; 45 struct intel_connector *attached_connector;
85 46
@@ -137,16 +98,18 @@ struct intel_dsi {
137 u16 panel_pwr_cycle_delay; 98 u16 panel_pwr_cycle_delay;
138}; 99};
139 100
140/* XXX: Transitional before dual port configuration */ 101struct intel_dsi_host {
141static inline enum port intel_dsi_pipe_to_port(enum pipe pipe) 102 struct mipi_dsi_host base;
142{ 103 struct intel_dsi *intel_dsi;
143 if (pipe == PIPE_A) 104 enum port port;
144 return PORT_A; 105
145 else if (pipe == PIPE_B) 106 /* our little hack */
146 return PORT_C; 107 struct mipi_dsi_device *device;
108};
147 109
148 WARN(1, "DSI on pipe %c, assuming port C\n", pipe_name(pipe)); 110static inline struct intel_dsi_host *to_intel_dsi_host(struct mipi_dsi_host *h)
149 return PORT_C; 111{
112 return container_of(h, struct intel_dsi_host, base);
150} 113}
151 114
152#define for_each_dsi_port(__port, __ports_mask) \ 115#define for_each_dsi_port(__port, __ports_mask) \
@@ -162,6 +125,6 @@ extern void vlv_enable_dsi_pll(struct intel_encoder *encoder);
162extern void vlv_disable_dsi_pll(struct intel_encoder *encoder); 125extern void vlv_disable_dsi_pll(struct intel_encoder *encoder);
163extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp); 126extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
164 127
165extern struct intel_dsi_dev_ops vbt_generic_dsi_display_ops; 128struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id);
166 129
167#endif /* _INTEL_DSI_H */ 130#endif /* _INTEL_DSI_H */
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c
deleted file mode 100644
index 562811c1a9d2..000000000000
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.c
+++ /dev/null
@@ -1,432 +0,0 @@
1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Jani Nikula <jani.nikula@intel.com>
24 */
25
26#include <linux/export.h>
27#include <drm/drmP.h>
28#include <drm/drm_crtc.h>
29#include <video/mipi_display.h>
30#include "i915_drv.h"
31#include "intel_drv.h"
32#include "intel_dsi.h"
33#include "intel_dsi_cmd.h"
34
35/*
36 * XXX: MIPI_DATA_ADDRESS, MIPI_DATA_LENGTH, MIPI_COMMAND_LENGTH, and
37 * MIPI_COMMAND_ADDRESS registers.
38 *
39 * Apparently these registers provide a MIPI adapter level way to send (lots of)
40 * commands and data to the receiver, without having to write the commands and
41 * data to MIPI_{HS,LP}_GEN_{CTRL,DATA} registers word by word.
42 *
43 * Presumably for anything other than MIPI_DCS_WRITE_MEMORY_START and
44 * MIPI_DCS_WRITE_MEMORY_CONTINUE (which are used to update the external
45 * framebuffer in command mode displays) these are just an optimization that can
46 * come later.
47 *
48 * For memory writes, these should probably be used for performance.
49 */
50
51static void print_stat(struct intel_dsi *intel_dsi, enum port port)
52{
53 struct drm_encoder *encoder = &intel_dsi->base.base;
54 struct drm_device *dev = encoder->dev;
55 struct drm_i915_private *dev_priv = dev->dev_private;
56 u32 val;
57
58 val = I915_READ(MIPI_INTR_STAT(port));
59
60#define STAT_BIT(val, bit) (val) & (bit) ? " " #bit : ""
61 DRM_DEBUG_KMS("MIPI_INTR_STAT(%c) = %08x"
62 "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s"
63 "\n", port_name(port), val,
64 STAT_BIT(val, TEARING_EFFECT),
65 STAT_BIT(val, SPL_PKT_SENT_INTERRUPT),
66 STAT_BIT(val, GEN_READ_DATA_AVAIL),
67 STAT_BIT(val, LP_GENERIC_WR_FIFO_FULL),
68 STAT_BIT(val, HS_GENERIC_WR_FIFO_FULL),
69 STAT_BIT(val, RX_PROT_VIOLATION),
70 STAT_BIT(val, RX_INVALID_TX_LENGTH),
71 STAT_BIT(val, ACK_WITH_NO_ERROR),
72 STAT_BIT(val, TURN_AROUND_ACK_TIMEOUT),
73 STAT_BIT(val, LP_RX_TIMEOUT),
74 STAT_BIT(val, HS_TX_TIMEOUT),
75 STAT_BIT(val, DPI_FIFO_UNDERRUN),
76 STAT_BIT(val, LOW_CONTENTION),
77 STAT_BIT(val, HIGH_CONTENTION),
78 STAT_BIT(val, TXDSI_VC_ID_INVALID),
79 STAT_BIT(val, TXDSI_DATA_TYPE_NOT_RECOGNISED),
80 STAT_BIT(val, TXCHECKSUM_ERROR),
81 STAT_BIT(val, TXECC_MULTIBIT_ERROR),
82 STAT_BIT(val, TXECC_SINGLE_BIT_ERROR),
83 STAT_BIT(val, TXFALSE_CONTROL_ERROR),
84 STAT_BIT(val, RXDSI_VC_ID_INVALID),
85 STAT_BIT(val, RXDSI_DATA_TYPE_NOT_REGOGNISED),
86 STAT_BIT(val, RXCHECKSUM_ERROR),
87 STAT_BIT(val, RXECC_MULTIBIT_ERROR),
88 STAT_BIT(val, RXECC_SINGLE_BIT_ERROR),
89 STAT_BIT(val, RXFALSE_CONTROL_ERROR),
90 STAT_BIT(val, RXHS_RECEIVE_TIMEOUT_ERROR),
91 STAT_BIT(val, RX_LP_TX_SYNC_ERROR),
92 STAT_BIT(val, RXEXCAPE_MODE_ENTRY_ERROR),
93 STAT_BIT(val, RXEOT_SYNC_ERROR),
94 STAT_BIT(val, RXSOT_SYNC_ERROR),
95 STAT_BIT(val, RXSOT_ERROR));
96#undef STAT_BIT
97}
98
99enum dsi_type {
100 DSI_DCS,
101 DSI_GENERIC,
102};
103
104/* enable or disable command mode hs transmissions */
105void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable,
106 enum port port)
107{
108 struct drm_encoder *encoder = &intel_dsi->base.base;
109 struct drm_device *dev = encoder->dev;
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 u32 temp;
112 u32 mask = DBI_FIFO_EMPTY;
113
114 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 50))
115 DRM_ERROR("Timeout waiting for DBI FIFO empty\n");
116
117 temp = I915_READ(MIPI_HS_LP_DBI_ENABLE(port));
118 temp &= DBI_HS_LP_MODE_MASK;
119 I915_WRITE(MIPI_HS_LP_DBI_ENABLE(port), enable ? DBI_HS_MODE : DBI_LP_MODE);
120
121 intel_dsi->hs = enable;
122}
123
124static int dsi_vc_send_short(struct intel_dsi *intel_dsi, int channel,
125 u8 data_type, u16 data, enum port port)
126{
127 struct drm_encoder *encoder = &intel_dsi->base.base;
128 struct drm_device *dev = encoder->dev;
129 struct drm_i915_private *dev_priv = dev->dev_private;
130 u32 ctrl_reg;
131 u32 ctrl;
132 u32 mask;
133
134 DRM_DEBUG_KMS("channel %d, data_type %d, data %04x\n",
135 channel, data_type, data);
136
137 if (intel_dsi->hs) {
138 ctrl_reg = MIPI_HS_GEN_CTRL(port);
139 mask = HS_CTRL_FIFO_FULL;
140 } else {
141 ctrl_reg = MIPI_LP_GEN_CTRL(port);
142 mask = LP_CTRL_FIFO_FULL;
143 }
144
145 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == 0, 50)) {
146 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
147 print_stat(intel_dsi, port);
148 }
149
150 /*
151 * Note: This function is also used for long packets, with length passed
152 * as data, since SHORT_PACKET_PARAM_SHIFT ==
153 * LONG_PACKET_WORD_COUNT_SHIFT.
154 */
155 ctrl = data << SHORT_PACKET_PARAM_SHIFT |
156 channel << VIRTUAL_CHANNEL_SHIFT |
157 data_type << DATA_TYPE_SHIFT;
158
159 I915_WRITE(ctrl_reg, ctrl);
160
161 return 0;
162}
163
164static int dsi_vc_send_long(struct intel_dsi *intel_dsi, int channel,
165 u8 data_type, const u8 *data, int len, enum port port)
166{
167 struct drm_encoder *encoder = &intel_dsi->base.base;
168 struct drm_device *dev = encoder->dev;
169 struct drm_i915_private *dev_priv = dev->dev_private;
170 u32 data_reg;
171 int i, j, n;
172 u32 mask;
173
174 DRM_DEBUG_KMS("channel %d, data_type %d, len %04x\n",
175 channel, data_type, len);
176
177 if (intel_dsi->hs) {
178 data_reg = MIPI_HS_GEN_DATA(port);
179 mask = HS_DATA_FIFO_FULL;
180 } else {
181 data_reg = MIPI_LP_GEN_DATA(port);
182 mask = LP_DATA_FIFO_FULL;
183 }
184
185 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == 0, 50))
186 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
187
188 for (i = 0; i < len; i += n) {
189 u32 val = 0;
190 n = min_t(int, len - i, 4);
191
192 for (j = 0; j < n; j++)
193 val |= *data++ << 8 * j;
194
195 I915_WRITE(data_reg, val);
196 /* XXX: check for data fifo full, once that is set, write 4
197 * dwords, then wait for not set, then continue. */
198 }
199
200 return dsi_vc_send_short(intel_dsi, channel, data_type, len, port);
201}
202
203static int dsi_vc_write_common(struct intel_dsi *intel_dsi,
204 int channel, const u8 *data, int len,
205 enum dsi_type type, enum port port)
206{
207 int ret;
208
209 if (len == 0) {
210 BUG_ON(type == DSI_GENERIC);
211 ret = dsi_vc_send_short(intel_dsi, channel,
212 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM,
213 0, port);
214 } else if (len == 1) {
215 ret = dsi_vc_send_short(intel_dsi, channel,
216 type == DSI_GENERIC ?
217 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
218 MIPI_DSI_DCS_SHORT_WRITE, data[0],
219 port);
220 } else if (len == 2) {
221 ret = dsi_vc_send_short(intel_dsi, channel,
222 type == DSI_GENERIC ?
223 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
224 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
225 (data[1] << 8) | data[0], port);
226 } else {
227 ret = dsi_vc_send_long(intel_dsi, channel,
228 type == DSI_GENERIC ?
229 MIPI_DSI_GENERIC_LONG_WRITE :
230 MIPI_DSI_DCS_LONG_WRITE, data, len,
231 port);
232 }
233
234 return ret;
235}
236
237int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
238 const u8 *data, int len, enum port port)
239{
240 return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_DCS,
241 port);
242}
243
244int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
245 const u8 *data, int len, enum port port)
246{
247 return dsi_vc_write_common(intel_dsi, channel, data, len, DSI_GENERIC,
248 port);
249}
250
251static int dsi_vc_dcs_send_read_request(struct intel_dsi *intel_dsi,
252 int channel, u8 dcs_cmd, enum port port)
253{
254 return dsi_vc_send_short(intel_dsi, channel, MIPI_DSI_DCS_READ,
255 dcs_cmd, port);
256}
257
258static int dsi_vc_generic_send_read_request(struct intel_dsi *intel_dsi,
259 int channel, u8 *reqdata,
260 int reqlen, enum port port)
261{
262 u16 data;
263 u8 data_type;
264
265 switch (reqlen) {
266 case 0:
267 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
268 data = 0;
269 break;
270 case 1:
271 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
272 data = reqdata[0];
273 break;
274 case 2:
275 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
276 data = (reqdata[1] << 8) | reqdata[0];
277 break;
278 default:
279 BUG();
280 }
281
282 return dsi_vc_send_short(intel_dsi, channel, data_type, data, port);
283}
284
285static int dsi_read_data_return(struct intel_dsi *intel_dsi,
286 u8 *buf, int buflen, enum port port)
287{
288 struct drm_encoder *encoder = &intel_dsi->base.base;
289 struct drm_device *dev = encoder->dev;
290 struct drm_i915_private *dev_priv = dev->dev_private;
291 int i, len = 0;
292 u32 data_reg, val;
293
294 if (intel_dsi->hs) {
295 data_reg = MIPI_HS_GEN_DATA(port);
296 } else {
297 data_reg = MIPI_LP_GEN_DATA(port);
298 }
299
300 while (len < buflen) {
301 val = I915_READ(data_reg);
302 for (i = 0; i < 4 && len < buflen; i++, len++)
303 buf[len] = val >> 8 * i;
304 }
305
306 return len;
307}
308
309int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
310 u8 *buf, int buflen, enum port port)
311{
312 struct drm_encoder *encoder = &intel_dsi->base.base;
313 struct drm_device *dev = encoder->dev;
314 struct drm_i915_private *dev_priv = dev->dev_private;
315 u32 mask;
316 int ret;
317
318 /*
319 * XXX: should issue multiple read requests and reads if request is
320 * longer than MIPI_MAX_RETURN_PKT_SIZE
321 */
322
323 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
324
325 ret = dsi_vc_dcs_send_read_request(intel_dsi, channel, dcs_cmd, port);
326 if (ret)
327 return ret;
328
329 mask = GEN_READ_DATA_AVAIL;
330 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 50))
331 DRM_ERROR("Timeout waiting for read data.\n");
332
333 ret = dsi_read_data_return(intel_dsi, buf, buflen, port);
334 if (ret < 0)
335 return ret;
336
337 if (ret != buflen)
338 return -EIO;
339
340 return 0;
341}
342
343int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
344 u8 *reqdata, int reqlen, u8 *buf, int buflen, enum port port)
345{
346 struct drm_encoder *encoder = &intel_dsi->base.base;
347 struct drm_device *dev = encoder->dev;
348 struct drm_i915_private *dev_priv = dev->dev_private;
349 u32 mask;
350 int ret;
351
352 /*
353 * XXX: should issue multiple read requests and reads if request is
354 * longer than MIPI_MAX_RETURN_PKT_SIZE
355 */
356
357 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
358
359 ret = dsi_vc_generic_send_read_request(intel_dsi, channel, reqdata,
360 reqlen, port);
361 if (ret)
362 return ret;
363
364 mask = GEN_READ_DATA_AVAIL;
365 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 50))
366 DRM_ERROR("Timeout waiting for read data.\n");
367
368 ret = dsi_read_data_return(intel_dsi, buf, buflen, port);
369 if (ret < 0)
370 return ret;
371
372 if (ret != buflen)
373 return -EIO;
374
375 return 0;
376}
377
378/*
379 * send a video mode command
380 *
381 * XXX: commands with data in MIPI_DPI_DATA?
382 */
383int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs)
384{
385 struct drm_encoder *encoder = &intel_dsi->base.base;
386 struct drm_device *dev = encoder->dev;
387 struct drm_i915_private *dev_priv = dev->dev_private;
388 enum port port;
389 u32 mask;
390
391 /* XXX: pipe, hs */
392 if (hs)
393 cmd &= ~DPI_LP_MODE;
394 else
395 cmd |= DPI_LP_MODE;
396
397 for_each_dsi_port(port, intel_dsi->ports) {
398 /* clear bit */
399 I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
400
401 /* XXX: old code skips write if control unchanged */
402 if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
403 DRM_ERROR("Same special packet %02x twice in a row.\n",
404 cmd);
405
406 I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
407
408 mask = SPL_PKT_SENT_INTERRUPT;
409 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask,
410 100))
411 DRM_ERROR("Video mode command 0x%08x send failed.\n",
412 cmd);
413 }
414
415 return 0;
416}
417
418void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi)
419{
420 struct drm_encoder *encoder = &intel_dsi->base.base;
421 struct drm_device *dev = encoder->dev;
422 struct drm_i915_private *dev_priv = dev->dev_private;
423 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
424 enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe);
425 u32 mask;
426
427 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
428 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
429
430 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100))
431 DRM_ERROR("DPI FIFOs are not empty\n");
432}
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.h b/drivers/gpu/drm/i915/intel_dsi_cmd.h
index 326a5ac55561..886779030f1a 100644
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.h
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.h
@@ -33,85 +33,7 @@
33#include "intel_drv.h" 33#include "intel_drv.h"
34#include "intel_dsi.h" 34#include "intel_dsi.h"
35 35
36#define DPI_LP_MODE_EN false
37#define DPI_HS_MODE_EN true
38
39void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable, 36void dsi_hs_mode_enable(struct intel_dsi *intel_dsi, bool enable,
40 enum port port); 37 enum port port);
41 38
42int dsi_vc_dcs_write(struct intel_dsi *intel_dsi, int channel,
43 const u8 *data, int len, enum port port);
44
45int dsi_vc_generic_write(struct intel_dsi *intel_dsi, int channel,
46 const u8 *data, int len, enum port port);
47
48int dsi_vc_dcs_read(struct intel_dsi *intel_dsi, int channel, u8 dcs_cmd,
49 u8 *buf, int buflen, enum port port);
50
51int dsi_vc_generic_read(struct intel_dsi *intel_dsi, int channel,
52 u8 *reqdata, int reqlen, u8 *buf, int buflen, enum port port);
53
54int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs);
55void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi);
56
57/* XXX: questionable write helpers */
58static inline int dsi_vc_dcs_write_0(struct intel_dsi *intel_dsi,
59 int channel, u8 dcs_cmd, enum port port)
60{
61 return dsi_vc_dcs_write(intel_dsi, channel, &dcs_cmd, 1, port);
62}
63
64static inline int dsi_vc_dcs_write_1(struct intel_dsi *intel_dsi,
65 int channel, u8 dcs_cmd, u8 param, enum port port)
66{
67 u8 buf[2] = { dcs_cmd, param };
68 return dsi_vc_dcs_write(intel_dsi, channel, buf, 2, port);
69}
70
71static inline int dsi_vc_generic_write_0(struct intel_dsi *intel_dsi,
72 int channel, enum port port)
73{
74 return dsi_vc_generic_write(intel_dsi, channel, NULL, 0, port);
75}
76
77static inline int dsi_vc_generic_write_1(struct intel_dsi *intel_dsi,
78 int channel, u8 param, enum port port)
79{
80 return dsi_vc_generic_write(intel_dsi, channel, &param, 1, port);
81}
82
83static inline int dsi_vc_generic_write_2(struct intel_dsi *intel_dsi,
84 int channel, u8 param1, u8 param2, enum port port)
85{
86 u8 buf[2] = { param1, param2 };
87 return dsi_vc_generic_write(intel_dsi, channel, buf, 2, port);
88}
89
90/* XXX: questionable read helpers */
91static inline int dsi_vc_generic_read_0(struct intel_dsi *intel_dsi,
92 int channel, u8 *buf, int buflen, enum port port)
93{
94 return dsi_vc_generic_read(intel_dsi, channel, NULL, 0, buf, buflen,
95 port);
96}
97
98static inline int dsi_vc_generic_read_1(struct intel_dsi *intel_dsi,
99 int channel, u8 param, u8 *buf,
100 int buflen, enum port port)
101{
102 return dsi_vc_generic_read(intel_dsi, channel, &param, 1, buf, buflen,
103 port);
104}
105
106static inline int dsi_vc_generic_read_2(struct intel_dsi *intel_dsi,
107 int channel, u8 param1, u8 param2,
108 u8 *buf, int buflen, enum port port)
109{
110 u8 req[2] = { param1, param2 };
111
112 return dsi_vc_generic_read(intel_dsi, channel, req, 2, buf, buflen,
113 port);
114}
115
116
117#endif /* _INTEL_DSI_DSI_H */ 39#endif /* _INTEL_DSI_DSI_H */
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 5493aef5a6a3..d2cd8d5b27a1 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -28,6 +28,7 @@
28#include <drm/drm_crtc.h> 28#include <drm/drm_crtc.h>
29#include <drm/drm_edid.h> 29#include <drm/drm_edid.h>
30#include <drm/i915_drm.h> 30#include <drm/i915_drm.h>
31#include <drm/drm_panel.h>
31#include <linux/slab.h> 32#include <linux/slab.h>
32#include <video/mipi_display.h> 33#include <video/mipi_display.h>
33#include <asm/intel-mid.h> 34#include <asm/intel-mid.h>
@@ -35,7 +36,16 @@
35#include "i915_drv.h" 36#include "i915_drv.h"
36#include "intel_drv.h" 37#include "intel_drv.h"
37#include "intel_dsi.h" 38#include "intel_dsi.h"
38#include "intel_dsi_cmd.h" 39
40struct vbt_panel {
41 struct drm_panel panel;
42 struct intel_dsi *intel_dsi;
43};
44
45static inline struct vbt_panel *to_vbt_panel(struct drm_panel *panel)
46{
47 return container_of(panel, struct vbt_panel, panel);
48}
39 49
40#define MIPI_TRANSFER_MODE_SHIFT 0 50#define MIPI_TRANSFER_MODE_SHIFT 0
41#define MIPI_VIRTUAL_CHANNEL_SHIFT 1 51#define MIPI_VIRTUAL_CHANNEL_SHIFT 1
@@ -99,16 +109,21 @@ static inline enum port intel_dsi_seq_port_to_port(u8 port)
99 return port ? PORT_C : PORT_A; 109 return port ? PORT_C : PORT_A;
100} 110}
101 111
102static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data) 112static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
113 const u8 *data)
103{ 114{
104 u8 type, byte, mode, vc, seq_port; 115 struct mipi_dsi_device *dsi_device;
116 u8 type, flags, seq_port;
105 u16 len; 117 u16 len;
106 enum port port; 118 enum port port;
107 119
108 byte = *data++; 120 flags = *data++;
109 mode = (byte >> MIPI_TRANSFER_MODE_SHIFT) & 0x1; 121 type = *data++;
110 vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3; 122
111 seq_port = (byte >> MIPI_PORT_SHIFT) & 0x3; 123 len = *((u16 *) data);
124 data += 2;
125
126 seq_port = (flags >> MIPI_PORT_SHIFT) & 3;
112 127
113 /* For DSI single link on Port A & C, the seq_port value which is 128 /* For DSI single link on Port A & C, the seq_port value which is
114 * parsed from Sequence Block#53 of VBT has been set to 0 129 * parsed from Sequence Block#53 of VBT has been set to 0
@@ -119,24 +134,29 @@ static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
119 port = PORT_C; 134 port = PORT_C;
120 else 135 else
121 port = intel_dsi_seq_port_to_port(seq_port); 136 port = intel_dsi_seq_port_to_port(seq_port);
122 /* LP or HS mode */
123 intel_dsi->hs = mode;
124 137
125 /* get packet type and increment the pointer */ 138 dsi_device = intel_dsi->dsi_hosts[port]->device;
126 type = *data++; 139 if (!dsi_device) {
140 DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port));
141 goto out;
142 }
127 143
128 len = *((u16 *) data); 144 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1)
129 data += 2; 145 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM;
146 else
147 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM;
148
149 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3;
130 150
131 switch (type) { 151 switch (type) {
132 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 152 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
133 dsi_vc_generic_write_0(intel_dsi, vc, port); 153 mipi_dsi_generic_write(dsi_device, NULL, 0);
134 break; 154 break;
135 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 155 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
136 dsi_vc_generic_write_1(intel_dsi, vc, *data, port); 156 mipi_dsi_generic_write(dsi_device, data, 1);
137 break; 157 break;
138 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 158 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
139 dsi_vc_generic_write_2(intel_dsi, vc, *data, *(data + 1), port); 159 mipi_dsi_generic_write(dsi_device, data, 2);
140 break; 160 break;
141 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 161 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
142 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 162 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
@@ -144,30 +164,31 @@ static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
144 DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n"); 164 DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n");
145 break; 165 break;
146 case MIPI_DSI_GENERIC_LONG_WRITE: 166 case MIPI_DSI_GENERIC_LONG_WRITE:
147 dsi_vc_generic_write(intel_dsi, vc, data, len, port); 167 mipi_dsi_generic_write(dsi_device, data, len);
148 break; 168 break;
149 case MIPI_DSI_DCS_SHORT_WRITE: 169 case MIPI_DSI_DCS_SHORT_WRITE:
150 dsi_vc_dcs_write_0(intel_dsi, vc, *data, port); 170 mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
151 break; 171 break;
152 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 172 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
153 dsi_vc_dcs_write_1(intel_dsi, vc, *data, *(data + 1), port); 173 mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
154 break; 174 break;
155 case MIPI_DSI_DCS_READ: 175 case MIPI_DSI_DCS_READ:
156 DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n"); 176 DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n");
157 break; 177 break;
158 case MIPI_DSI_DCS_LONG_WRITE: 178 case MIPI_DSI_DCS_LONG_WRITE:
159 dsi_vc_dcs_write(intel_dsi, vc, data, len, port); 179 mipi_dsi_dcs_write_buffer(dsi_device, data, len);
160 break; 180 break;
161 } 181 }
162 182
183out:
163 data += len; 184 data += len;
164 185
165 return data; 186 return data;
166} 187}
167 188
168static u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, u8 *data) 189static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
169{ 190{
170 u32 delay = *((u32 *) data); 191 u32 delay = *((const u32 *) data);
171 192
172 usleep_range(delay, delay + 10); 193 usleep_range(delay, delay + 10);
173 data += 4; 194 data += 4;
@@ -175,7 +196,7 @@ static u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, u8 *data)
175 return data; 196 return data;
176} 197}
177 198
178static u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, u8 *data) 199static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
179{ 200{
180 u8 gpio, action; 201 u8 gpio, action;
181 u16 function, pad; 202 u16 function, pad;
@@ -208,7 +229,8 @@ static u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, u8 *data)
208 return data; 229 return data;
209} 230}
210 231
211typedef u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, u8 *data); 232typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
233 const u8 *data);
212static const fn_mipi_elem_exec exec_elem[] = { 234static const fn_mipi_elem_exec exec_elem[] = {
213 NULL, /* reserved */ 235 NULL, /* reserved */
214 mipi_exec_send_packet, 236 mipi_exec_send_packet,
@@ -232,13 +254,12 @@ static const char * const seq_name[] = {
232 "MIPI_SEQ_DEASSERT_RESET" 254 "MIPI_SEQ_DEASSERT_RESET"
233}; 255};
234 256
235static void generic_exec_sequence(struct intel_dsi *intel_dsi, char *sequence) 257static void generic_exec_sequence(struct intel_dsi *intel_dsi, const u8 *data)
236{ 258{
237 u8 *data = sequence;
238 fn_mipi_elem_exec mipi_elem_exec; 259 fn_mipi_elem_exec mipi_elem_exec;
239 int index; 260 int index;
240 261
241 if (!sequence) 262 if (!data)
242 return; 263 return;
243 264
244 DRM_DEBUG_DRIVER("Starting MIPI sequence - %s\n", seq_name[*data]); 265 DRM_DEBUG_DRIVER("Starting MIPI sequence - %s\n", seq_name[*data]);
@@ -271,14 +292,103 @@ static void generic_exec_sequence(struct intel_dsi *intel_dsi, char *sequence)
271 } 292 }
272} 293}
273 294
274static bool generic_init(struct intel_dsi_device *dsi) 295static int vbt_panel_prepare(struct drm_panel *panel)
296{
297 struct vbt_panel *vbt_panel = to_vbt_panel(panel);
298 struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
299 struct drm_device *dev = intel_dsi->base.base.dev;
300 struct drm_i915_private *dev_priv = dev->dev_private;
301 const u8 *sequence;
302
303 sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET];
304 generic_exec_sequence(intel_dsi, sequence);
305
306 sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
307 generic_exec_sequence(intel_dsi, sequence);
308
309 return 0;
310}
311
312static int vbt_panel_unprepare(struct drm_panel *panel)
313{
314 struct vbt_panel *vbt_panel = to_vbt_panel(panel);
315 struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
316 struct drm_device *dev = intel_dsi->base.base.dev;
317 struct drm_i915_private *dev_priv = dev->dev_private;
318 const u8 *sequence;
319
320 sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET];
321 generic_exec_sequence(intel_dsi, sequence);
322
323 return 0;
324}
325
326static int vbt_panel_enable(struct drm_panel *panel)
327{
328 struct vbt_panel *vbt_panel = to_vbt_panel(panel);
329 struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
330 struct drm_device *dev = intel_dsi->base.base.dev;
331 struct drm_i915_private *dev_priv = dev->dev_private;
332 const u8 *sequence;
333
334 sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_ON];
335 generic_exec_sequence(intel_dsi, sequence);
336
337 return 0;
338}
339
340static int vbt_panel_disable(struct drm_panel *panel)
341{
342 struct vbt_panel *vbt_panel = to_vbt_panel(panel);
343 struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
344 struct drm_device *dev = intel_dsi->base.base.dev;
345 struct drm_i915_private *dev_priv = dev->dev_private;
346 const u8 *sequence;
347
348 sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_OFF];
349 generic_exec_sequence(intel_dsi, sequence);
350
351 return 0;
352}
353
354static int vbt_panel_get_modes(struct drm_panel *panel)
355{
356 struct vbt_panel *vbt_panel = to_vbt_panel(panel);
357 struct intel_dsi *intel_dsi = vbt_panel->intel_dsi;
358 struct drm_device *dev = intel_dsi->base.base.dev;
359 struct drm_i915_private *dev_priv = dev->dev_private;
360 struct drm_display_mode *mode;
361
362 if (!panel->connector)
363 return 0;
364
365 mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
366 if (!mode)
367 return 0;
368
369 mode->type |= DRM_MODE_TYPE_PREFERRED;
370
371 drm_mode_probed_add(panel->connector, mode);
372
373 return 1;
374}
375
376static const struct drm_panel_funcs vbt_panel_funcs = {
377 .disable = vbt_panel_disable,
378 .unprepare = vbt_panel_unprepare,
379 .prepare = vbt_panel_prepare,
380 .enable = vbt_panel_enable,
381 .get_modes = vbt_panel_get_modes,
382};
383
384struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id)
275{ 385{
276 struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
277 struct drm_device *dev = intel_dsi->base.base.dev; 386 struct drm_device *dev = intel_dsi->base.base.dev;
278 struct drm_i915_private *dev_priv = dev->dev_private; 387 struct drm_i915_private *dev_priv = dev->dev_private;
279 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 388 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
280 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps; 389 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
281 struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode; 390 struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
391 struct vbt_panel *vbt_panel;
282 u32 bits_per_pixel = 24; 392 u32 bits_per_pixel = 24;
283 u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui; 393 u32 tlpx_ns, extra_byte_count, bitrate, tlpx_ui;
284 u32 ui_num, ui_den; 394 u32 ui_num, ui_den;
@@ -288,6 +398,7 @@ static bool generic_init(struct intel_dsi_device *dsi)
288 u32 lp_to_hs_switch, hs_to_lp_switch; 398 u32 lp_to_hs_switch, hs_to_lp_switch;
289 u32 pclk, computed_ddr; 399 u32 pclk, computed_ddr;
290 u16 burst_mode_ratio; 400 u16 burst_mode_ratio;
401 enum port port;
291 402
292 DRM_DEBUG_KMS("\n"); 403 DRM_DEBUG_KMS("\n");
293 404
@@ -298,9 +409,6 @@ static bool generic_init(struct intel_dsi_device *dsi)
298 intel_dsi->dual_link = mipi_config->dual_link; 409 intel_dsi->dual_link = mipi_config->dual_link;
299 intel_dsi->pixel_overlap = mipi_config->pixel_overlap; 410 intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
300 411
301 if (intel_dsi->dual_link)
302 intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C));
303
304 if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666) 412 if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
305 bits_per_pixel = 18; 413 bits_per_pixel = 18;
306 else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565) 414 else if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB565)
@@ -345,7 +453,7 @@ static bool generic_init(struct intel_dsi_device *dsi)
345 if (mipi_config->target_burst_mode_freq < 453 if (mipi_config->target_burst_mode_freq <
346 computed_ddr) { 454 computed_ddr) {
347 DRM_ERROR("Burst mode freq is less than computed\n"); 455 DRM_ERROR("Burst mode freq is less than computed\n");
348 return false; 456 return NULL;
349 } 457 }
350 458
351 burst_mode_ratio = DIV_ROUND_UP( 459 burst_mode_ratio = DIV_ROUND_UP(
@@ -355,7 +463,7 @@ static bool generic_init(struct intel_dsi_device *dsi)
355 pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100); 463 pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100);
356 } else { 464 } else {
357 DRM_ERROR("Burst mode target is not set\n"); 465 DRM_ERROR("Burst mode target is not set\n");
358 return false; 466 return NULL;
359 } 467 }
360 } else 468 } else
361 burst_mode_ratio = 100; 469 burst_mode_ratio = 100;
@@ -556,110 +664,18 @@ static bool generic_init(struct intel_dsi_device *dsi)
556 intel_dsi->panel_off_delay = pps->panel_off_delay / 10; 664 intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
557 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10; 665 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
558 666
559 return true; 667 /* This is cheating a bit with the cleanup. */
560} 668 vbt_panel = devm_kzalloc(dev->dev, sizeof(*vbt_panel), GFP_KERNEL);
561
562static int generic_mode_valid(struct intel_dsi_device *dsi,
563 struct drm_display_mode *mode)
564{
565 return MODE_OK;
566}
567
568static bool generic_mode_fixup(struct intel_dsi_device *dsi,
569 const struct drm_display_mode *mode,
570 struct drm_display_mode *adjusted_mode) {
571 return true;
572}
573
574static void generic_panel_reset(struct intel_dsi_device *dsi)
575{
576 struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
577 struct drm_device *dev = intel_dsi->base.base.dev;
578 struct drm_i915_private *dev_priv = dev->dev_private;
579
580 char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET];
581
582 generic_exec_sequence(intel_dsi, sequence);
583}
584
585static void generic_disable_panel_power(struct intel_dsi_device *dsi)
586{
587 struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
588 struct drm_device *dev = intel_dsi->base.base.dev;
589 struct drm_i915_private *dev_priv = dev->dev_private;
590
591 char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET];
592
593 generic_exec_sequence(intel_dsi, sequence);
594}
595
596static void generic_send_otp_cmds(struct intel_dsi_device *dsi)
597{
598 struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
599 struct drm_device *dev = intel_dsi->base.base.dev;
600 struct drm_i915_private *dev_priv = dev->dev_private;
601
602 char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];
603 669
604 generic_exec_sequence(intel_dsi, sequence); 670 vbt_panel->intel_dsi = intel_dsi;
605} 671 drm_panel_init(&vbt_panel->panel);
606 672 vbt_panel->panel.funcs = &vbt_panel_funcs;
607static void generic_enable(struct intel_dsi_device *dsi) 673 drm_panel_add(&vbt_panel->panel);
608{
609 struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
610 struct drm_device *dev = intel_dsi->base.base.dev;
611 struct drm_i915_private *dev_priv = dev->dev_private;
612
613 char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_ON];
614
615 generic_exec_sequence(intel_dsi, sequence);
616}
617
618static void generic_disable(struct intel_dsi_device *dsi)
619{
620 struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
621 struct drm_device *dev = intel_dsi->base.base.dev;
622 struct drm_i915_private *dev_priv = dev->dev_private;
623
624 char *sequence = dev_priv->vbt.dsi.sequence[MIPI_SEQ_DISPLAY_OFF];
625 674
626 generic_exec_sequence(intel_dsi, sequence); 675 /* a regular driver would get the device in probe */
627} 676 for_each_dsi_port(port, intel_dsi->ports) {
628 677 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
629static enum drm_connector_status generic_detect(struct intel_dsi_device *dsi) 678 }
630{
631 return connector_status_connected;
632}
633
634static bool generic_get_hw_state(struct intel_dsi_device *dev)
635{
636 return true;
637}
638
639static struct drm_display_mode *generic_get_modes(struct intel_dsi_device *dsi)
640{
641 struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
642 struct drm_device *dev = intel_dsi->base.base.dev;
643 struct drm_i915_private *dev_priv = dev->dev_private;
644 679
645 dev_priv->vbt.lfp_lvds_vbt_mode->type |= DRM_MODE_TYPE_PREFERRED; 680 return &vbt_panel->panel;
646 return dev_priv->vbt.lfp_lvds_vbt_mode;
647} 681}
648
649static void generic_destroy(struct intel_dsi_device *dsi) { }
650
651/* Callbacks. We might not need them all. */
652struct intel_dsi_dev_ops vbt_generic_dsi_display_ops = {
653 .init = generic_init,
654 .mode_valid = generic_mode_valid,
655 .mode_fixup = generic_mode_fixup,
656 .panel_reset = generic_panel_reset,
657 .disable_panel_power = generic_disable_panel_power,
658 .send_otp_cmds = generic_send_otp_cmds,
659 .enable = generic_enable,
660 .disable = generic_disable,
661 .detect = generic_detect,
662 .get_hw_state = generic_get_hw_state,
663 .get_modes = generic_get_modes,
664 .destroy = generic_destroy,
665};
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index e40e3df33517..d8579510beb0 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -27,6 +27,7 @@
27#include <linux/i2c.h> 27#include <linux/i2c.h>
28#include <linux/slab.h> 28#include <linux/slab.h>
29#include <drm/drmP.h> 29#include <drm/drmP.h>
30#include <drm/drm_atomic_helper.h>
30#include <drm/drm_crtc.h> 31#include <drm/drm_crtc.h>
31#include "intel_drv.h" 32#include "intel_drv.h"
32#include <drm/i915_drm.h> 33#include <drm/i915_drm.h>
@@ -144,7 +145,7 @@ static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
144} 145}
145 146
146static void intel_dvo_get_config(struct intel_encoder *encoder, 147static void intel_dvo_get_config(struct intel_encoder *encoder,
147 struct intel_crtc_config *pipe_config) 148 struct intel_crtc_state *pipe_config)
148{ 149{
149 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 150 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
150 struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 151 struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
@@ -160,9 +161,9 @@ static void intel_dvo_get_config(struct intel_encoder *encoder,
160 else 161 else
161 flags |= DRM_MODE_FLAG_NVSYNC; 162 flags |= DRM_MODE_FLAG_NVSYNC;
162 163
163 pipe_config->adjusted_mode.flags |= flags; 164 pipe_config->base.adjusted_mode.flags |= flags;
164 165
165 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock; 166 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
166} 167}
167 168
168static void intel_disable_dvo(struct intel_encoder *encoder) 169static void intel_disable_dvo(struct intel_encoder *encoder)
@@ -186,8 +187,8 @@ static void intel_enable_dvo(struct intel_encoder *encoder)
186 u32 temp = I915_READ(dvo_reg); 187 u32 temp = I915_READ(dvo_reg);
187 188
188 intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, 189 intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
189 &crtc->config.requested_mode, 190 &crtc->config->base.mode,
190 &crtc->config.adjusted_mode); 191 &crtc->config->base.adjusted_mode);
191 192
192 I915_WRITE(dvo_reg, temp | DVO_ENABLE); 193 I915_WRITE(dvo_reg, temp | DVO_ENABLE);
193 I915_READ(dvo_reg); 194 I915_READ(dvo_reg);
@@ -200,7 +201,7 @@ static void intel_dvo_dpms(struct drm_connector *connector, int mode)
200{ 201{
201 struct intel_dvo *intel_dvo = intel_attached_dvo(connector); 202 struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
202 struct drm_crtc *crtc; 203 struct drm_crtc *crtc;
203 struct intel_crtc_config *config; 204 struct intel_crtc_state *config;
204 205
205 /* dvo supports only 2 dpms states. */ 206 /* dvo supports only 2 dpms states. */
206 if (mode != DRM_MODE_DPMS_ON) 207 if (mode != DRM_MODE_DPMS_ON)
@@ -221,7 +222,7 @@ static void intel_dvo_dpms(struct drm_connector *connector, int mode)
221 /* We call connector dpms manually below in case pipe dpms doesn't 222 /* We call connector dpms manually below in case pipe dpms doesn't
222 * change due to cloning. */ 223 * change due to cloning. */
223 if (mode == DRM_MODE_DPMS_ON) { 224 if (mode == DRM_MODE_DPMS_ON) {
224 config = &to_intel_crtc(crtc)->config; 225 config = to_intel_crtc(crtc)->config;
225 226
226 intel_dvo->base.connectors_active = true; 227 intel_dvo->base.connectors_active = true;
227 228
@@ -261,10 +262,10 @@ intel_dvo_mode_valid(struct drm_connector *connector,
261} 262}
262 263
263static bool intel_dvo_compute_config(struct intel_encoder *encoder, 264static bool intel_dvo_compute_config(struct intel_encoder *encoder,
264 struct intel_crtc_config *pipe_config) 265 struct intel_crtc_state *pipe_config)
265{ 266{
266 struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 267 struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
267 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 268 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
268 269
269 /* If we have timings from the BIOS for the panel, put them in 270 /* If we have timings from the BIOS for the panel, put them in
270 * to the adjusted mode. The CRTC will be set up for this mode, 271 * to the adjusted mode. The CRTC will be set up for this mode,
@@ -295,7 +296,7 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder)
295 struct drm_device *dev = encoder->base.dev; 296 struct drm_device *dev = encoder->base.dev;
296 struct drm_i915_private *dev_priv = dev->dev_private; 297 struct drm_i915_private *dev_priv = dev->dev_private;
297 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 298 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
298 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; 299 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
299 struct intel_dvo *intel_dvo = enc_to_dvo(encoder); 300 struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
300 int pipe = crtc->pipe; 301 int pipe = crtc->pipe;
301 u32 dvo_val; 302 u32 dvo_val;
@@ -390,6 +391,8 @@ static const struct drm_connector_funcs intel_dvo_connector_funcs = {
390 .detect = intel_dvo_detect, 391 .detect = intel_dvo_detect,
391 .destroy = intel_dvo_destroy, 392 .destroy = intel_dvo_destroy,
392 .fill_modes = drm_helper_probe_single_connector_modes, 393 .fill_modes = drm_helper_probe_single_connector_modes,
394 .atomic_get_property = intel_connector_atomic_get_property,
395 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
393}; 396};
394 397
395static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = { 398static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = {
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 4daceaeeb30d..624d1d92d284 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -182,7 +182,7 @@ static void snb_fbc_blit_update(struct drm_device *dev)
182 182
183 /* Blitter is part of Media powerwell on VLV. No impact of 183 /* Blitter is part of Media powerwell on VLV. No impact of
184 * his param in other platforms for now */ 184 * his param in other platforms for now */
185 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA); 185 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
186 186
187 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); 187 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
188 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << 188 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
@@ -195,7 +195,7 @@ static void snb_fbc_blit_update(struct drm_device *dev)
195 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); 195 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
196 POSTING_READ(GEN6_BLITTER_ECOSKPD); 196 POSTING_READ(GEN6_BLITTER_ECOSKPD);
197 197
198 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA); 198 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
199} 199}
200 200
201static void ilk_fbc_enable(struct drm_crtc *crtc) 201static void ilk_fbc_enable(struct drm_crtc *crtc)
@@ -542,7 +542,7 @@ void intel_fbc_update(struct drm_device *dev)
542 intel_crtc = to_intel_crtc(crtc); 542 intel_crtc = to_intel_crtc(crtc);
543 fb = crtc->primary->fb; 543 fb = crtc->primary->fb;
544 obj = intel_fb_obj(fb); 544 obj = intel_fb_obj(fb);
545 adjusted_mode = &intel_crtc->config.adjusted_mode; 545 adjusted_mode = &intel_crtc->config->base.adjusted_mode;
546 546
547 if (i915.enable_fbc < 0) { 547 if (i915.enable_fbc < 0) {
548 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT)) 548 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
@@ -572,8 +572,8 @@ void intel_fbc_update(struct drm_device *dev)
572 max_width = 2048; 572 max_width = 2048;
573 max_height = 1536; 573 max_height = 1536;
574 } 574 }
575 if (intel_crtc->config.pipe_src_w > max_width || 575 if (intel_crtc->config->pipe_src_w > max_width ||
576 intel_crtc->config.pipe_src_h > max_height) { 576 intel_crtc->config->pipe_src_h > max_height) {
577 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE)) 577 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
578 DRM_DEBUG_KMS("mode too large for compression, disabling\n"); 578 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
579 goto out_disable; 579 goto out_disable;
@@ -595,7 +595,7 @@ void intel_fbc_update(struct drm_device *dev)
595 goto out_disable; 595 goto out_disable;
596 } 596 }
597 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && 597 if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
598 to_intel_plane(crtc->primary)->rotation != BIT(DRM_ROTATE_0)) { 598 crtc->primary->state->rotation != BIT(DRM_ROTATE_0)) {
599 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE)) 599 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
600 DRM_DEBUG_KMS("Rotation unsupported, disabling\n"); 600 DRM_DEBUG_KMS("Rotation unsupported, disabling\n");
601 goto out_disable; 601 goto out_disable;
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index 850cf7d6578c..3001a8674611 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -443,7 +443,7 @@ retry:
443 DRM_DEBUG_KMS("looking for current mode on connector %s\n", 443 DRM_DEBUG_KMS("looking for current mode on connector %s\n",
444 connector->name); 444 connector->name);
445 intel_mode_from_pipe_config(&encoder->crtc->hwmode, 445 intel_mode_from_pipe_config(&encoder->crtc->hwmode,
446 &to_intel_crtc(encoder->crtc)->config); 446 to_intel_crtc(encoder->crtc)->config);
447 modes[i] = &encoder->crtc->hwmode; 447 modes[i] = &encoder->crtc->hwmode;
448 } 448 }
449 crtcs[i] = new_crtc; 449 crtcs[i] = new_crtc;
@@ -531,7 +531,7 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
531 struct intel_framebuffer *fb = NULL; 531 struct intel_framebuffer *fb = NULL;
532 struct drm_crtc *crtc; 532 struct drm_crtc *crtc;
533 struct intel_crtc *intel_crtc; 533 struct intel_crtc *intel_crtc;
534 struct intel_plane_config *plane_config = NULL; 534 struct intel_initial_plane_config *plane_config = NULL;
535 unsigned int max_size = 0; 535 unsigned int max_size = 0;
536 536
537 if (!i915.fastboot) 537 if (!i915.fastboot)
@@ -581,7 +581,7 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
581 * pipe. Note we need to use the selected fb's pitch and bpp 581 * pipe. Note we need to use the selected fb's pitch and bpp
582 * rather than the current pipe's, since they differ. 582 * rather than the current pipe's, since they differ.
583 */ 583 */
584 cur_size = intel_crtc->config.adjusted_mode.crtc_hdisplay; 584 cur_size = intel_crtc->config->base.adjusted_mode.crtc_hdisplay;
585 cur_size = cur_size * fb->base.bits_per_pixel / 8; 585 cur_size = cur_size * fb->base.bits_per_pixel / 8;
586 if (fb->base.pitches[0] < cur_size) { 586 if (fb->base.pitches[0] < cur_size) {
587 DRM_DEBUG_KMS("fb not wide enough for plane %c (%d vs %d)\n", 587 DRM_DEBUG_KMS("fb not wide enough for plane %c (%d vs %d)\n",
@@ -592,13 +592,14 @@ static bool intel_fbdev_init_bios(struct drm_device *dev,
592 break; 592 break;
593 } 593 }
594 594
595 cur_size = intel_crtc->config.adjusted_mode.crtc_vdisplay; 595 cur_size = intel_crtc->config->base.adjusted_mode.crtc_vdisplay;
596 cur_size = ALIGN(cur_size, plane_config->tiled ? (IS_GEN2(dev) ? 16 : 8) : 1); 596 cur_size = intel_fb_align_height(dev, cur_size,
597 plane_config->tiling);
597 cur_size *= fb->base.pitches[0]; 598 cur_size *= fb->base.pitches[0];
598 DRM_DEBUG_KMS("pipe %c area: %dx%d, bpp: %d, size: %d\n", 599 DRM_DEBUG_KMS("pipe %c area: %dx%d, bpp: %d, size: %d\n",
599 pipe_name(intel_crtc->pipe), 600 pipe_name(intel_crtc->pipe),
600 intel_crtc->config.adjusted_mode.crtc_hdisplay, 601 intel_crtc->config->base.adjusted_mode.crtc_hdisplay,
601 intel_crtc->config.adjusted_mode.crtc_vdisplay, 602 intel_crtc->config->base.adjusted_mode.crtc_vdisplay,
602 fb->base.bits_per_pixel, 603 fb->base.bits_per_pixel,
603 cur_size); 604 cur_size);
604 605
diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
index 77af512d2d35..04e248dd2259 100644
--- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
@@ -341,7 +341,7 @@ bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
341} 341}
342 342
343/** 343/**
344 * intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt 344 * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
345 * @dev_priv: i915 device instance 345 * @dev_priv: i915 device instance
346 * @pipe: (CPU) pipe to set state for 346 * @pipe: (CPU) pipe to set state for
347 * 347 *
diff --git a/drivers/gpu/drm/i915/intel_frontbuffer.c b/drivers/gpu/drm/i915/intel_frontbuffer.c
index 79f6d72179c5..73cb6e036445 100644
--- a/drivers/gpu/drm/i915/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/intel_frontbuffer.c
@@ -157,6 +157,7 @@ void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
157 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring); 157 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
158 158
159 intel_psr_invalidate(dev, obj->frontbuffer_bits); 159 intel_psr_invalidate(dev, obj->frontbuffer_bits);
160 intel_edp_drrs_invalidate(dev, obj->frontbuffer_bits);
160} 161}
161 162
162/** 163/**
@@ -182,6 +183,7 @@ void intel_frontbuffer_flush(struct drm_device *dev,
182 183
183 intel_mark_fb_busy(dev, frontbuffer_bits, NULL); 184 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
184 185
186 intel_edp_drrs_flush(dev, frontbuffer_bits);
185 intel_psr_flush(dev, frontbuffer_bits); 187 intel_psr_flush(dev, frontbuffer_bits);
186 188
187 /* 189 /*
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 3abc2000fce9..995c5b261f4f 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -31,6 +31,7 @@
31#include <linux/delay.h> 31#include <linux/delay.h>
32#include <linux/hdmi.h> 32#include <linux/hdmi.h>
33#include <drm/drmP.h> 33#include <drm/drmP.h>
34#include <drm/drm_atomic_helper.h>
34#include <drm/drm_crtc.h> 35#include <drm/drm_crtc.h>
35#include <drm/drm_edid.h> 36#include <drm/drm_edid.h>
36#include "intel_drv.h" 37#include "intel_drv.h"
@@ -337,13 +338,13 @@ static void hsw_write_infoframe(struct drm_encoder *encoder,
337 struct drm_device *dev = encoder->dev; 338 struct drm_device *dev = encoder->dev;
338 struct drm_i915_private *dev_priv = dev->dev_private; 339 struct drm_i915_private *dev_priv = dev->dev_private;
339 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 340 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
340 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); 341 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
341 u32 data_reg; 342 u32 data_reg;
342 int i; 343 int i;
343 u32 val = I915_READ(ctl_reg); 344 u32 val = I915_READ(ctl_reg);
344 345
345 data_reg = hsw_infoframe_data_reg(type, 346 data_reg = hsw_infoframe_data_reg(type,
346 intel_crtc->config.cpu_transcoder, 347 intel_crtc->config->cpu_transcoder,
347 dev_priv); 348 dev_priv);
348 if (data_reg == 0) 349 if (data_reg == 0)
349 return; 350 return;
@@ -371,7 +372,7 @@ static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
371 struct drm_device *dev = encoder->dev; 372 struct drm_device *dev = encoder->dev;
372 struct drm_i915_private *dev_priv = dev->dev_private; 373 struct drm_i915_private *dev_priv = dev->dev_private;
373 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 374 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
374 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); 375 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
375 u32 val = I915_READ(ctl_reg); 376 u32 val = I915_READ(ctl_reg);
376 377
377 return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW | 378 return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
@@ -436,7 +437,7 @@ static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
436 } 437 }
437 438
438 if (intel_hdmi->rgb_quant_range_selectable) { 439 if (intel_hdmi->rgb_quant_range_selectable) {
439 if (intel_crtc->config.limited_color_range) 440 if (intel_crtc->config->limited_color_range)
440 frame.avi.quantization_range = 441 frame.avi.quantization_range =
441 HDMI_QUANTIZATION_RANGE_LIMITED; 442 HDMI_QUANTIZATION_RANGE_LIMITED;
442 else 443 else
@@ -672,7 +673,7 @@ static void hsw_set_infoframes(struct drm_encoder *encoder,
672 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 673 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
673 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 674 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
674 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 675 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
675 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); 676 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
676 u32 val = I915_READ(reg); 677 u32 val = I915_READ(reg);
677 678
678 assert_hdmi_port_disabled(intel_hdmi); 679 assert_hdmi_port_disabled(intel_hdmi);
@@ -700,7 +701,7 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
700 struct drm_i915_private *dev_priv = dev->dev_private; 701 struct drm_i915_private *dev_priv = dev->dev_private;
701 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 702 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
702 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 703 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
703 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; 704 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
704 u32 hdmi_val; 705 u32 hdmi_val;
705 706
706 hdmi_val = SDVO_ENCODING_HDMI; 707 hdmi_val = SDVO_ENCODING_HDMI;
@@ -711,12 +712,12 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder)
711 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 712 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
712 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 713 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
713 714
714 if (crtc->config.pipe_bpp > 24) 715 if (crtc->config->pipe_bpp > 24)
715 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 716 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
716 else 717 else
717 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 718 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
718 719
719 if (crtc->config.has_hdmi_sink) 720 if (crtc->config->has_hdmi_sink)
720 hdmi_val |= HDMI_MODE_SELECT_HDMI; 721 hdmi_val |= HDMI_MODE_SELECT_HDMI;
721 722
722 if (HAS_PCH_CPT(dev)) 723 if (HAS_PCH_CPT(dev))
@@ -759,7 +760,7 @@ static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
759} 760}
760 761
761static void intel_hdmi_get_config(struct intel_encoder *encoder, 762static void intel_hdmi_get_config(struct intel_encoder *encoder,
762 struct intel_crtc_config *pipe_config) 763 struct intel_crtc_state *pipe_config)
763{ 764{
764 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 765 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
765 struct drm_device *dev = encoder->base.dev; 766 struct drm_device *dev = encoder->base.dev;
@@ -792,7 +793,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
792 tmp & HDMI_COLOR_RANGE_16_235) 793 tmp & HDMI_COLOR_RANGE_16_235)
793 pipe_config->limited_color_range = true; 794 pipe_config->limited_color_range = true;
794 795
795 pipe_config->adjusted_mode.flags |= flags; 796 pipe_config->base.adjusted_mode.flags |= flags;
796 797
797 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 798 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
798 dotclock = pipe_config->port_clock * 2 / 3; 799 dotclock = pipe_config->port_clock * 2 / 3;
@@ -802,7 +803,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
802 if (HAS_PCH_SPLIT(dev_priv->dev)) 803 if (HAS_PCH_SPLIT(dev_priv->dev))
803 ironlake_check_encoder_dotclock(pipe_config, dotclock); 804 ironlake_check_encoder_dotclock(pipe_config, dotclock);
804 805
805 pipe_config->adjusted_mode.crtc_clock = dotclock; 806 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
806} 807}
807 808
808static void intel_enable_hdmi(struct intel_encoder *encoder) 809static void intel_enable_hdmi(struct intel_encoder *encoder)
@@ -814,7 +815,7 @@ static void intel_enable_hdmi(struct intel_encoder *encoder)
814 u32 temp; 815 u32 temp;
815 u32 enable_bits = SDVO_ENABLE; 816 u32 enable_bits = SDVO_ENABLE;
816 817
817 if (intel_crtc->config.has_audio) 818 if (intel_crtc->config->has_audio)
818 enable_bits |= SDVO_AUDIO_ENABLE; 819 enable_bits |= SDVO_AUDIO_ENABLE;
819 820
820 temp = I915_READ(intel_hdmi->hdmi_reg); 821 temp = I915_READ(intel_hdmi->hdmi_reg);
@@ -845,8 +846,8 @@ static void intel_enable_hdmi(struct intel_encoder *encoder)
845 POSTING_READ(intel_hdmi->hdmi_reg); 846 POSTING_READ(intel_hdmi->hdmi_reg);
846 } 847 }
847 848
848 if (intel_crtc->config.has_audio) { 849 if (intel_crtc->config->has_audio) {
849 WARN_ON(!intel_crtc->config.has_hdmi_sink); 850 WARN_ON(!intel_crtc->config->has_hdmi_sink);
850 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", 851 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
851 pipe_name(intel_crtc->pipe)); 852 pipe_name(intel_crtc->pipe));
852 intel_audio_codec_enable(encoder); 853 intel_audio_codec_enable(encoder);
@@ -866,7 +867,7 @@ static void intel_disable_hdmi(struct intel_encoder *encoder)
866 u32 temp; 867 u32 temp;
867 u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; 868 u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
868 869
869 if (crtc->config.has_audio) 870 if (crtc->config->has_audio)
870 intel_audio_codec_disable(encoder); 871 intel_audio_codec_disable(encoder);
871 872
872 temp = I915_READ(intel_hdmi->hdmi_reg); 873 temp = I915_READ(intel_hdmi->hdmi_reg);
@@ -975,12 +976,12 @@ static bool hdmi_12bpc_possible(struct intel_crtc *crtc)
975} 976}
976 977
977bool intel_hdmi_compute_config(struct intel_encoder *encoder, 978bool intel_hdmi_compute_config(struct intel_encoder *encoder,
978 struct intel_crtc_config *pipe_config) 979 struct intel_crtc_state *pipe_config)
979{ 980{
980 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 981 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
981 struct drm_device *dev = encoder->base.dev; 982 struct drm_device *dev = encoder->base.dev;
982 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 983 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
983 int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2; 984 int clock_12bpc = pipe_config->base.adjusted_mode.crtc_clock * 3 / 2;
984 int portclock_limit = hdmi_portclock_limit(intel_hdmi, false); 985 int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
985 int desired_bpp; 986 int desired_bpp;
986 987
@@ -1252,12 +1253,12 @@ static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1252 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); 1253 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1253 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1254 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1254 struct drm_display_mode *adjusted_mode = 1255 struct drm_display_mode *adjusted_mode =
1255 &intel_crtc->config.adjusted_mode; 1256 &intel_crtc->config->base.adjusted_mode;
1256 1257
1257 intel_hdmi_prepare(encoder); 1258 intel_hdmi_prepare(encoder);
1258 1259
1259 intel_hdmi->set_infoframes(&encoder->base, 1260 intel_hdmi->set_infoframes(&encoder->base,
1260 intel_crtc->config.has_hdmi_sink, 1261 intel_crtc->config->has_hdmi_sink,
1261 adjusted_mode); 1262 adjusted_mode);
1262} 1263}
1263 1264
@@ -1270,7 +1271,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1270 struct intel_crtc *intel_crtc = 1271 struct intel_crtc *intel_crtc =
1271 to_intel_crtc(encoder->base.crtc); 1272 to_intel_crtc(encoder->base.crtc);
1272 struct drm_display_mode *adjusted_mode = 1273 struct drm_display_mode *adjusted_mode =
1273 &intel_crtc->config.adjusted_mode; 1274 &intel_crtc->config->base.adjusted_mode;
1274 enum dpio_channel port = vlv_dport_to_channel(dport); 1275 enum dpio_channel port = vlv_dport_to_channel(dport);
1275 int pipe = intel_crtc->pipe; 1276 int pipe = intel_crtc->pipe;
1276 u32 val; 1277 u32 val;
@@ -1302,7 +1303,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1302 mutex_unlock(&dev_priv->dpio_lock); 1303 mutex_unlock(&dev_priv->dpio_lock);
1303 1304
1304 intel_hdmi->set_infoframes(&encoder->base, 1305 intel_hdmi->set_infoframes(&encoder->base,
1305 intel_crtc->config.has_hdmi_sink, 1306 intel_crtc->config->has_hdmi_sink,
1306 adjusted_mode); 1307 adjusted_mode);
1307 1308
1308 intel_enable_hdmi(encoder); 1309 intel_enable_hdmi(encoder);
@@ -1467,7 +1468,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1467 struct intel_crtc *intel_crtc = 1468 struct intel_crtc *intel_crtc =
1468 to_intel_crtc(encoder->base.crtc); 1469 to_intel_crtc(encoder->base.crtc);
1469 struct drm_display_mode *adjusted_mode = 1470 struct drm_display_mode *adjusted_mode =
1470 &intel_crtc->config.adjusted_mode; 1471 &intel_crtc->config->base.adjusted_mode;
1471 enum dpio_channel ch = vlv_dport_to_channel(dport); 1472 enum dpio_channel ch = vlv_dport_to_channel(dport);
1472 int pipe = intel_crtc->pipe; 1473 int pipe = intel_crtc->pipe;
1473 int data, i; 1474 int data, i;
@@ -1593,7 +1594,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1593 mutex_unlock(&dev_priv->dpio_lock); 1594 mutex_unlock(&dev_priv->dpio_lock);
1594 1595
1595 intel_hdmi->set_infoframes(&encoder->base, 1596 intel_hdmi->set_infoframes(&encoder->base,
1596 intel_crtc->config.has_hdmi_sink, 1597 intel_crtc->config->has_hdmi_sink,
1597 adjusted_mode); 1598 adjusted_mode);
1598 1599
1599 intel_enable_hdmi(encoder); 1600 intel_enable_hdmi(encoder);
@@ -1614,7 +1615,9 @@ static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1614 .force = intel_hdmi_force, 1615 .force = intel_hdmi_force,
1615 .fill_modes = drm_helper_probe_single_connector_modes, 1616 .fill_modes = drm_helper_probe_single_connector_modes,
1616 .set_property = intel_hdmi_set_property, 1617 .set_property = intel_hdmi_set_property,
1618 .atomic_get_property = intel_connector_atomic_get_property,
1617 .destroy = intel_hdmi_destroy, 1619 .destroy = intel_hdmi_destroy,
1620 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1618}; 1621};
1619 1622
1620static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 1623static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index e405b61cdac5..a94346fee160 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -283,7 +283,6 @@ static void execlists_elsp_write(struct intel_engine_cs *ring,
283 struct drm_i915_private *dev_priv = dev->dev_private; 283 struct drm_i915_private *dev_priv = dev->dev_private;
284 uint64_t temp = 0; 284 uint64_t temp = 0;
285 uint32_t desc[4]; 285 uint32_t desc[4];
286 unsigned long flags;
287 286
288 /* XXX: You must always write both descriptors in the order below. */ 287 /* XXX: You must always write both descriptors in the order below. */
289 if (ctx_obj1) 288 if (ctx_obj1)
@@ -297,63 +296,17 @@ static void execlists_elsp_write(struct intel_engine_cs *ring,
297 desc[3] = (u32)(temp >> 32); 296 desc[3] = (u32)(temp >> 32);
298 desc[2] = (u32)temp; 297 desc[2] = (u32)temp;
299 298
300 /* Set Force Wakeup bit to prevent GT from entering C6 while ELSP writes 299 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
301 * are in progress.
302 *
303 * The other problem is that we can't just call gen6_gt_force_wake_get()
304 * because that function calls intel_runtime_pm_get(), which might sleep.
305 * Instead, we do the runtime_pm_get/put when creating/destroying requests.
306 */
307 spin_lock_irqsave(&dev_priv->uncore.lock, flags);
308 if (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) {
309 if (dev_priv->uncore.fw_rendercount++ == 0)
310 dev_priv->uncore.funcs.force_wake_get(dev_priv,
311 FORCEWAKE_RENDER);
312 if (dev_priv->uncore.fw_mediacount++ == 0)
313 dev_priv->uncore.funcs.force_wake_get(dev_priv,
314 FORCEWAKE_MEDIA);
315 if (INTEL_INFO(dev)->gen >= 9) {
316 if (dev_priv->uncore.fw_blittercount++ == 0)
317 dev_priv->uncore.funcs.force_wake_get(dev_priv,
318 FORCEWAKE_BLITTER);
319 }
320 } else {
321 if (dev_priv->uncore.forcewake_count++ == 0)
322 dev_priv->uncore.funcs.force_wake_get(dev_priv,
323 FORCEWAKE_ALL);
324 }
325 spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
326
327 I915_WRITE(RING_ELSP(ring), desc[1]); 300 I915_WRITE(RING_ELSP(ring), desc[1]);
328 I915_WRITE(RING_ELSP(ring), desc[0]); 301 I915_WRITE(RING_ELSP(ring), desc[0]);
329 I915_WRITE(RING_ELSP(ring), desc[3]); 302 I915_WRITE(RING_ELSP(ring), desc[3]);
303
330 /* The context is automatically loaded after the following */ 304 /* The context is automatically loaded after the following */
331 I915_WRITE(RING_ELSP(ring), desc[2]); 305 I915_WRITE(RING_ELSP(ring), desc[2]);
332 306
333 /* ELSP is a wo register, so use another nearby reg for posting instead */ 307 /* ELSP is a wo register, so use another nearby reg for posting instead */
334 POSTING_READ(RING_EXECLIST_STATUS(ring)); 308 POSTING_READ(RING_EXECLIST_STATUS(ring));
335 309 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
336 /* Release Force Wakeup (see the big comment above). */
337 spin_lock_irqsave(&dev_priv->uncore.lock, flags);
338 if (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen >= 9) {
339 if (--dev_priv->uncore.fw_rendercount == 0)
340 dev_priv->uncore.funcs.force_wake_put(dev_priv,
341 FORCEWAKE_RENDER);
342 if (--dev_priv->uncore.fw_mediacount == 0)
343 dev_priv->uncore.funcs.force_wake_put(dev_priv,
344 FORCEWAKE_MEDIA);
345 if (INTEL_INFO(dev)->gen >= 9) {
346 if (--dev_priv->uncore.fw_blittercount == 0)
347 dev_priv->uncore.funcs.force_wake_put(dev_priv,
348 FORCEWAKE_BLITTER);
349 }
350 } else {
351 if (--dev_priv->uncore.forcewake_count == 0)
352 dev_priv->uncore.funcs.force_wake_put(dev_priv,
353 FORCEWAKE_ALL);
354 }
355
356 spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
357} 310}
358 311
359static int execlists_update_context(struct drm_i915_gem_object *ctx_obj, 312static int execlists_update_context(struct drm_i915_gem_object *ctx_obj,
@@ -404,8 +357,8 @@ static void execlists_submit_contexts(struct intel_engine_cs *ring,
404 357
405static void execlists_context_unqueue(struct intel_engine_cs *ring) 358static void execlists_context_unqueue(struct intel_engine_cs *ring)
406{ 359{
407 struct intel_ctx_submit_request *req0 = NULL, *req1 = NULL; 360 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
408 struct intel_ctx_submit_request *cursor = NULL, *tmp = NULL; 361 struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
409 362
410 assert_spin_locked(&ring->execlist_lock); 363 assert_spin_locked(&ring->execlist_lock);
411 364
@@ -445,12 +398,12 @@ static void execlists_context_unqueue(struct intel_engine_cs *ring)
445static bool execlists_check_remove_request(struct intel_engine_cs *ring, 398static bool execlists_check_remove_request(struct intel_engine_cs *ring,
446 u32 request_id) 399 u32 request_id)
447{ 400{
448 struct intel_ctx_submit_request *head_req; 401 struct drm_i915_gem_request *head_req;
449 402
450 assert_spin_locked(&ring->execlist_lock); 403 assert_spin_locked(&ring->execlist_lock);
451 404
452 head_req = list_first_entry_or_null(&ring->execlist_queue, 405 head_req = list_first_entry_or_null(&ring->execlist_queue,
453 struct intel_ctx_submit_request, 406 struct drm_i915_gem_request,
454 execlist_link); 407 execlist_link);
455 408
456 if (head_req != NULL) { 409 if (head_req != NULL) {
@@ -534,24 +487,34 @@ void intel_lrc_irq_handler(struct intel_engine_cs *ring)
534 487
535static int execlists_context_queue(struct intel_engine_cs *ring, 488static int execlists_context_queue(struct intel_engine_cs *ring,
536 struct intel_context *to, 489 struct intel_context *to,
537 u32 tail) 490 u32 tail,
491 struct drm_i915_gem_request *request)
538{ 492{
539 struct intel_ctx_submit_request *req = NULL, *cursor; 493 struct drm_i915_gem_request *cursor;
540 struct drm_i915_private *dev_priv = ring->dev->dev_private; 494 struct drm_i915_private *dev_priv = ring->dev->dev_private;
541 unsigned long flags; 495 unsigned long flags;
542 int num_elements = 0; 496 int num_elements = 0;
543 497
544 req = kzalloc(sizeof(*req), GFP_KERNEL);
545 if (req == NULL)
546 return -ENOMEM;
547 req->ctx = to;
548 i915_gem_context_reference(req->ctx);
549
550 if (to != ring->default_context) 498 if (to != ring->default_context)
551 intel_lr_context_pin(ring, to); 499 intel_lr_context_pin(ring, to);
552 500
553 req->ring = ring; 501 if (!request) {
554 req->tail = tail; 502 /*
503 * If there isn't a request associated with this submission,
504 * create one as a temporary holder.
505 */
506 WARN(1, "execlist context submission without request");
507 request = kzalloc(sizeof(*request), GFP_KERNEL);
508 if (request == NULL)
509 return -ENOMEM;
510 request->ring = ring;
511 request->ctx = to;
512 } else {
513 WARN_ON(to != request->ctx);
514 }
515 request->tail = tail;
516 i915_gem_request_reference(request);
517 i915_gem_context_reference(request->ctx);
555 518
556 intel_runtime_pm_get(dev_priv); 519 intel_runtime_pm_get(dev_priv);
557 520
@@ -562,10 +525,10 @@ static int execlists_context_queue(struct intel_engine_cs *ring,
562 break; 525 break;
563 526
564 if (num_elements > 2) { 527 if (num_elements > 2) {
565 struct intel_ctx_submit_request *tail_req; 528 struct drm_i915_gem_request *tail_req;
566 529
567 tail_req = list_last_entry(&ring->execlist_queue, 530 tail_req = list_last_entry(&ring->execlist_queue,
568 struct intel_ctx_submit_request, 531 struct drm_i915_gem_request,
569 execlist_link); 532 execlist_link);
570 533
571 if (to == tail_req->ctx) { 534 if (to == tail_req->ctx) {
@@ -577,7 +540,7 @@ static int execlists_context_queue(struct intel_engine_cs *ring,
577 } 540 }
578 } 541 }
579 542
580 list_add_tail(&req->execlist_link, &ring->execlist_queue); 543 list_add_tail(&request->execlist_link, &ring->execlist_queue);
581 if (num_elements == 0) 544 if (num_elements == 0)
582 execlists_context_unqueue(ring); 545 execlists_context_unqueue(ring);
583 546
@@ -586,7 +549,8 @@ static int execlists_context_queue(struct intel_engine_cs *ring,
586 return 0; 549 return 0;
587} 550}
588 551
589static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf) 552static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf,
553 struct intel_context *ctx)
590{ 554{
591 struct intel_engine_cs *ring = ringbuf->ring; 555 struct intel_engine_cs *ring = ringbuf->ring;
592 uint32_t flush_domains; 556 uint32_t flush_domains;
@@ -596,7 +560,8 @@ static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf)
596 if (ring->gpu_caches_dirty) 560 if (ring->gpu_caches_dirty)
597 flush_domains = I915_GEM_GPU_DOMAINS; 561 flush_domains = I915_GEM_GPU_DOMAINS;
598 562
599 ret = ring->emit_flush(ringbuf, I915_GEM_GPU_DOMAINS, flush_domains); 563 ret = ring->emit_flush(ringbuf, ctx,
564 I915_GEM_GPU_DOMAINS, flush_domains);
600 if (ret) 565 if (ret)
601 return ret; 566 return ret;
602 567
@@ -605,6 +570,7 @@ static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf)
605} 570}
606 571
607static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf, 572static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf,
573 struct intel_context *ctx,
608 struct list_head *vmas) 574 struct list_head *vmas)
609{ 575{
610 struct intel_engine_cs *ring = ringbuf->ring; 576 struct intel_engine_cs *ring = ringbuf->ring;
@@ -632,7 +598,7 @@ static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf,
632 /* Unconditionally invalidate gpu caches and ensure that we do flush 598 /* Unconditionally invalidate gpu caches and ensure that we do flush
633 * any residual writes from the previous batch. 599 * any residual writes from the previous batch.
634 */ 600 */
635 return logical_ring_invalidate_all_caches(ringbuf); 601 return logical_ring_invalidate_all_caches(ringbuf, ctx);
636} 602}
637 603
638/** 604/**
@@ -712,13 +678,13 @@ int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
712 return -EINVAL; 678 return -EINVAL;
713 } 679 }
714 680
715 ret = execlists_move_to_gpu(ringbuf, vmas); 681 ret = execlists_move_to_gpu(ringbuf, ctx, vmas);
716 if (ret) 682 if (ret)
717 return ret; 683 return ret;
718 684
719 if (ring == &dev_priv->ring[RCS] && 685 if (ring == &dev_priv->ring[RCS] &&
720 instp_mode != dev_priv->relative_constants_mode) { 686 instp_mode != dev_priv->relative_constants_mode) {
721 ret = intel_logical_ring_begin(ringbuf, 4); 687 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
722 if (ret) 688 if (ret)
723 return ret; 689 return ret;
724 690
@@ -731,7 +697,7 @@ int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
731 dev_priv->relative_constants_mode = instp_mode; 697 dev_priv->relative_constants_mode = instp_mode;
732 } 698 }
733 699
734 ret = ring->emit_bb_start(ringbuf, exec_start, flags); 700 ret = ring->emit_bb_start(ringbuf, ctx, exec_start, flags);
735 if (ret) 701 if (ret)
736 return ret; 702 return ret;
737 703
@@ -743,7 +709,7 @@ int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
743 709
744void intel_execlists_retire_requests(struct intel_engine_cs *ring) 710void intel_execlists_retire_requests(struct intel_engine_cs *ring)
745{ 711{
746 struct intel_ctx_submit_request *req, *tmp; 712 struct drm_i915_gem_request *req, *tmp;
747 struct drm_i915_private *dev_priv = ring->dev->dev_private; 713 struct drm_i915_private *dev_priv = ring->dev->dev_private;
748 unsigned long flags; 714 unsigned long flags;
749 struct list_head retired_list; 715 struct list_head retired_list;
@@ -765,9 +731,9 @@ void intel_execlists_retire_requests(struct intel_engine_cs *ring)
765 if (ctx_obj && (ctx != ring->default_context)) 731 if (ctx_obj && (ctx != ring->default_context))
766 intel_lr_context_unpin(ring, ctx); 732 intel_lr_context_unpin(ring, ctx);
767 intel_runtime_pm_put(dev_priv); 733 intel_runtime_pm_put(dev_priv);
768 i915_gem_context_unreference(req->ctx); 734 i915_gem_context_unreference(ctx);
769 list_del(&req->execlist_link); 735 list_del(&req->execlist_link);
770 kfree(req); 736 i915_gem_request_unreference(req);
771 } 737 }
772} 738}
773 739
@@ -793,7 +759,8 @@ void intel_logical_ring_stop(struct intel_engine_cs *ring)
793 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); 759 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
794} 760}
795 761
796int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf) 762int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf,
763 struct intel_context *ctx)
797{ 764{
798 struct intel_engine_cs *ring = ringbuf->ring; 765 struct intel_engine_cs *ring = ringbuf->ring;
799 int ret; 766 int ret;
@@ -801,7 +768,7 @@ int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf)
801 if (!ring->gpu_caches_dirty) 768 if (!ring->gpu_caches_dirty)
802 return 0; 769 return 0;
803 770
804 ret = ring->emit_flush(ringbuf, 0, I915_GEM_GPU_DOMAINS); 771 ret = ring->emit_flush(ringbuf, ctx, 0, I915_GEM_GPU_DOMAINS);
805 if (ret) 772 if (ret)
806 return ret; 773 return ret;
807 774
@@ -818,17 +785,18 @@ int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf)
818 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that 785 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
819 * point, the tail *inside* the context is updated and the ELSP written to. 786 * point, the tail *inside* the context is updated and the ELSP written to.
820 */ 787 */
821void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf) 788void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf,
789 struct intel_context *ctx,
790 struct drm_i915_gem_request *request)
822{ 791{
823 struct intel_engine_cs *ring = ringbuf->ring; 792 struct intel_engine_cs *ring = ringbuf->ring;
824 struct intel_context *ctx = ringbuf->FIXME_lrc_ctx;
825 793
826 intel_logical_ring_advance(ringbuf); 794 intel_logical_ring_advance(ringbuf);
827 795
828 if (intel_ring_stopped(ring)) 796 if (intel_ring_stopped(ring))
829 return; 797 return;
830 798
831 execlists_context_queue(ring, ctx, ringbuf->tail); 799 execlists_context_queue(ring, ctx, ringbuf->tail, request);
832} 800}
833 801
834static int intel_lr_context_pin(struct intel_engine_cs *ring, 802static int intel_lr_context_pin(struct intel_engine_cs *ring,
@@ -839,11 +807,11 @@ static int intel_lr_context_pin(struct intel_engine_cs *ring,
839 int ret = 0; 807 int ret = 0;
840 808
841 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); 809 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
842 if (ctx->engine[ring->id].unpin_count++ == 0) { 810 if (ctx->engine[ring->id].pin_count++ == 0) {
843 ret = i915_gem_obj_ggtt_pin(ctx_obj, 811 ret = i915_gem_obj_ggtt_pin(ctx_obj,
844 GEN8_LR_CONTEXT_ALIGN, 0); 812 GEN8_LR_CONTEXT_ALIGN, 0);
845 if (ret) 813 if (ret)
846 goto reset_unpin_count; 814 goto reset_pin_count;
847 815
848 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf); 816 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
849 if (ret) 817 if (ret)
@@ -854,8 +822,8 @@ static int intel_lr_context_pin(struct intel_engine_cs *ring,
854 822
855unpin_ctx_obj: 823unpin_ctx_obj:
856 i915_gem_object_ggtt_unpin(ctx_obj); 824 i915_gem_object_ggtt_unpin(ctx_obj);
857reset_unpin_count: 825reset_pin_count:
858 ctx->engine[ring->id].unpin_count = 0; 826 ctx->engine[ring->id].pin_count = 0;
859 827
860 return ret; 828 return ret;
861} 829}
@@ -868,7 +836,7 @@ void intel_lr_context_unpin(struct intel_engine_cs *ring,
868 836
869 if (ctx_obj) { 837 if (ctx_obj) {
870 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); 838 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
871 if (--ctx->engine[ring->id].unpin_count == 0) { 839 if (--ctx->engine[ring->id].pin_count == 0) {
872 intel_unpin_ringbuffer_obj(ringbuf); 840 intel_unpin_ringbuffer_obj(ringbuf);
873 i915_gem_object_ggtt_unpin(ctx_obj); 841 i915_gem_object_ggtt_unpin(ctx_obj);
874 } 842 }
@@ -959,6 +927,7 @@ static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf,
959} 927}
960 928
961static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf, 929static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf,
930 struct intel_context *ctx,
962 int bytes) 931 int bytes)
963{ 932{
964 struct intel_engine_cs *ring = ringbuf->ring; 933 struct intel_engine_cs *ring = ringbuf->ring;
@@ -972,7 +941,7 @@ static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf,
972 return ret; 941 return ret;
973 942
974 /* Force the context submission in case we have been skipping it */ 943 /* Force the context submission in case we have been skipping it */
975 intel_logical_ring_advance_and_submit(ringbuf); 944 intel_logical_ring_advance_and_submit(ringbuf, ctx, NULL);
976 945
977 /* With GEM the hangcheck timer should kick us out of the loop, 946 /* With GEM the hangcheck timer should kick us out of the loop,
978 * leaving it early runs the risk of corrupting GEM state (due 947 * leaving it early runs the risk of corrupting GEM state (due
@@ -1007,13 +976,14 @@ static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf,
1007 return ret; 976 return ret;
1008} 977}
1009 978
1010static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf) 979static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf,
980 struct intel_context *ctx)
1011{ 981{
1012 uint32_t __iomem *virt; 982 uint32_t __iomem *virt;
1013 int rem = ringbuf->size - ringbuf->tail; 983 int rem = ringbuf->size - ringbuf->tail;
1014 984
1015 if (ringbuf->space < rem) { 985 if (ringbuf->space < rem) {
1016 int ret = logical_ring_wait_for_space(ringbuf, rem); 986 int ret = logical_ring_wait_for_space(ringbuf, ctx, rem);
1017 987
1018 if (ret) 988 if (ret)
1019 return ret; 989 return ret;
@@ -1030,18 +1000,19 @@ static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf)
1030 return 0; 1000 return 0;
1031} 1001}
1032 1002
1033static int logical_ring_prepare(struct intel_ringbuffer *ringbuf, int bytes) 1003static int logical_ring_prepare(struct intel_ringbuffer *ringbuf,
1004 struct intel_context *ctx, int bytes)
1034{ 1005{
1035 int ret; 1006 int ret;
1036 1007
1037 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { 1008 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
1038 ret = logical_ring_wrap_buffer(ringbuf); 1009 ret = logical_ring_wrap_buffer(ringbuf, ctx);
1039 if (unlikely(ret)) 1010 if (unlikely(ret))
1040 return ret; 1011 return ret;
1041 } 1012 }
1042 1013
1043 if (unlikely(ringbuf->space < bytes)) { 1014 if (unlikely(ringbuf->space < bytes)) {
1044 ret = logical_ring_wait_for_space(ringbuf, bytes); 1015 ret = logical_ring_wait_for_space(ringbuf, ctx, bytes);
1045 if (unlikely(ret)) 1016 if (unlikely(ret))
1046 return ret; 1017 return ret;
1047 } 1018 }
@@ -1062,7 +1033,8 @@ static int logical_ring_prepare(struct intel_ringbuffer *ringbuf, int bytes)
1062 * 1033 *
1063 * Return: non-zero if the ringbuffer is not ready to be written to. 1034 * Return: non-zero if the ringbuffer is not ready to be written to.
1064 */ 1035 */
1065int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords) 1036int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf,
1037 struct intel_context *ctx, int num_dwords)
1066{ 1038{
1067 struct intel_engine_cs *ring = ringbuf->ring; 1039 struct intel_engine_cs *ring = ringbuf->ring;
1068 struct drm_device *dev = ring->dev; 1040 struct drm_device *dev = ring->dev;
@@ -1074,12 +1046,12 @@ int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords)
1074 if (ret) 1046 if (ret)
1075 return ret; 1047 return ret;
1076 1048
1077 ret = logical_ring_prepare(ringbuf, num_dwords * sizeof(uint32_t)); 1049 ret = logical_ring_prepare(ringbuf, ctx, num_dwords * sizeof(uint32_t));
1078 if (ret) 1050 if (ret)
1079 return ret; 1051 return ret;
1080 1052
1081 /* Preallocate the olr before touching the ring */ 1053 /* Preallocate the olr before touching the ring */
1082 ret = logical_ring_alloc_request(ring, ringbuf->FIXME_lrc_ctx); 1054 ret = logical_ring_alloc_request(ring, ctx);
1083 if (ret) 1055 if (ret)
1084 return ret; 1056 return ret;
1085 1057
@@ -1100,11 +1072,11 @@ static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring,
1100 return 0; 1072 return 0;
1101 1073
1102 ring->gpu_caches_dirty = true; 1074 ring->gpu_caches_dirty = true;
1103 ret = logical_ring_flush_all_caches(ringbuf); 1075 ret = logical_ring_flush_all_caches(ringbuf, ctx);
1104 if (ret) 1076 if (ret)
1105 return ret; 1077 return ret;
1106 1078
1107 ret = intel_logical_ring_begin(ringbuf, w->count * 2 + 2); 1079 ret = intel_logical_ring_begin(ringbuf, ctx, w->count * 2 + 2);
1108 if (ret) 1080 if (ret)
1109 return ret; 1081 return ret;
1110 1082
@@ -1118,7 +1090,7 @@ static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring,
1118 intel_logical_ring_advance(ringbuf); 1090 intel_logical_ring_advance(ringbuf);
1119 1091
1120 ring->gpu_caches_dirty = true; 1092 ring->gpu_caches_dirty = true;
1121 ret = logical_ring_flush_all_caches(ringbuf); 1093 ret = logical_ring_flush_all_caches(ringbuf, ctx);
1122 if (ret) 1094 if (ret)
1123 return ret; 1095 return ret;
1124 1096
@@ -1169,12 +1141,13 @@ static int gen8_init_render_ring(struct intel_engine_cs *ring)
1169} 1141}
1170 1142
1171static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf, 1143static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
1144 struct intel_context *ctx,
1172 u64 offset, unsigned flags) 1145 u64 offset, unsigned flags)
1173{ 1146{
1174 bool ppgtt = !(flags & I915_DISPATCH_SECURE); 1147 bool ppgtt = !(flags & I915_DISPATCH_SECURE);
1175 int ret; 1148 int ret;
1176 1149
1177 ret = intel_logical_ring_begin(ringbuf, 4); 1150 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
1178 if (ret) 1151 if (ret)
1179 return ret; 1152 return ret;
1180 1153
@@ -1222,6 +1195,7 @@ static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring)
1222} 1195}
1223 1196
1224static int gen8_emit_flush(struct intel_ringbuffer *ringbuf, 1197static int gen8_emit_flush(struct intel_ringbuffer *ringbuf,
1198 struct intel_context *ctx,
1225 u32 invalidate_domains, 1199 u32 invalidate_domains,
1226 u32 unused) 1200 u32 unused)
1227{ 1201{
@@ -1231,7 +1205,7 @@ static int gen8_emit_flush(struct intel_ringbuffer *ringbuf,
1231 uint32_t cmd; 1205 uint32_t cmd;
1232 int ret; 1206 int ret;
1233 1207
1234 ret = intel_logical_ring_begin(ringbuf, 4); 1208 ret = intel_logical_ring_begin(ringbuf, ctx, 4);
1235 if (ret) 1209 if (ret)
1236 return ret; 1210 return ret;
1237 1211
@@ -1260,6 +1234,7 @@ static int gen8_emit_flush(struct intel_ringbuffer *ringbuf,
1260} 1234}
1261 1235
1262static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf, 1236static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
1237 struct intel_context *ctx,
1263 u32 invalidate_domains, 1238 u32 invalidate_domains,
1264 u32 flush_domains) 1239 u32 flush_domains)
1265{ 1240{
@@ -1286,7 +1261,7 @@ static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf,
1286 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; 1261 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1287 } 1262 }
1288 1263
1289 ret = intel_logical_ring_begin(ringbuf, 6); 1264 ret = intel_logical_ring_begin(ringbuf, ctx, 6);
1290 if (ret) 1265 if (ret)
1291 return ret; 1266 return ret;
1292 1267
@@ -1311,13 +1286,14 @@ static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1311 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); 1286 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1312} 1287}
1313 1288
1314static int gen8_emit_request(struct intel_ringbuffer *ringbuf) 1289static int gen8_emit_request(struct intel_ringbuffer *ringbuf,
1290 struct drm_i915_gem_request *request)
1315{ 1291{
1316 struct intel_engine_cs *ring = ringbuf->ring; 1292 struct intel_engine_cs *ring = ringbuf->ring;
1317 u32 cmd; 1293 u32 cmd;
1318 int ret; 1294 int ret;
1319 1295
1320 ret = intel_logical_ring_begin(ringbuf, 6); 1296 ret = intel_logical_ring_begin(ringbuf, request->ctx, 6);
1321 if (ret) 1297 if (ret)
1322 return ret; 1298 return ret;
1323 1299
@@ -1333,7 +1309,7 @@ static int gen8_emit_request(struct intel_ringbuffer *ringbuf)
1333 i915_gem_request_get_seqno(ring->outstanding_lazy_request)); 1309 i915_gem_request_get_seqno(ring->outstanding_lazy_request));
1334 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); 1310 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
1335 intel_logical_ring_emit(ringbuf, MI_NOOP); 1311 intel_logical_ring_emit(ringbuf, MI_NOOP);
1336 intel_logical_ring_advance_and_submit(ringbuf); 1312 intel_logical_ring_advance_and_submit(ringbuf, request->ctx, request);
1337 1313
1338 return 0; 1314 return 0;
1339} 1315}
@@ -1620,6 +1596,7 @@ int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
1620 return 0; 1596 return 0;
1621 1597
1622 ret = ring->emit_bb_start(ringbuf, 1598 ret = ring->emit_bb_start(ringbuf,
1599 ctx,
1623 so.ggtt_offset, 1600 so.ggtt_offset,
1624 I915_DISPATCH_SECURE); 1601 I915_DISPATCH_SECURE);
1625 if (ret) 1602 if (ret)
@@ -1774,6 +1751,7 @@ void intel_lr_context_free(struct intel_context *ctx)
1774 intel_unpin_ringbuffer_obj(ringbuf); 1751 intel_unpin_ringbuffer_obj(ringbuf);
1775 i915_gem_object_ggtt_unpin(ctx_obj); 1752 i915_gem_object_ggtt_unpin(ctx_obj);
1776 } 1753 }
1754 WARN_ON(ctx->engine[ring->id].pin_count);
1777 intel_destroy_ringbuffer_obj(ringbuf); 1755 intel_destroy_ringbuffer_obj(ringbuf);
1778 kfree(ringbuf); 1756 kfree(ringbuf);
1779 drm_gem_object_unreference(&ctx_obj->base); 1757 drm_gem_object_unreference(&ctx_obj->base);
@@ -1876,7 +1854,6 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
1876 } 1854 }
1877 1855
1878 ringbuf->ring = ring; 1856 ringbuf->ring = ring;
1879 ringbuf->FIXME_lrc_ctx = ctx;
1880 1857
1881 ringbuf->size = 32 * PAGE_SIZE; 1858 ringbuf->size = 32 * PAGE_SIZE;
1882 ringbuf->effective_size = ringbuf->size; 1859 ringbuf->effective_size = ringbuf->size;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 960fcbd2c98a..6f2d7da594f6 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -38,8 +38,12 @@ void intel_logical_ring_stop(struct intel_engine_cs *ring);
38void intel_logical_ring_cleanup(struct intel_engine_cs *ring); 38void intel_logical_ring_cleanup(struct intel_engine_cs *ring);
39int intel_logical_rings_init(struct drm_device *dev); 39int intel_logical_rings_init(struct drm_device *dev);
40 40
41int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf); 41int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf,
42void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf); 42 struct intel_context *ctx);
43void intel_logical_ring_advance_and_submit(
44 struct intel_ringbuffer *ringbuf,
45 struct intel_context *ctx,
46 struct drm_i915_gem_request *request);
43/** 47/**
44 * intel_logical_ring_advance() - advance the ringbuffer tail 48 * intel_logical_ring_advance() - advance the ringbuffer tail
45 * @ringbuf: Ringbuffer to advance. 49 * @ringbuf: Ringbuffer to advance.
@@ -61,7 +65,9 @@ static inline void intel_logical_ring_emit(struct intel_ringbuffer *ringbuf,
61 iowrite32(data, ringbuf->virtual_start + ringbuf->tail); 65 iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
62 ringbuf->tail += 4; 66 ringbuf->tail += 4;
63} 67}
64int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords); 68int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf,
69 struct intel_context *ctx,
70 int num_dwords);
65 71
66/* Logical Ring Contexts */ 72/* Logical Ring Contexts */
67int intel_lr_context_render_state_init(struct intel_engine_cs *ring, 73int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
@@ -83,35 +89,6 @@ int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
83 u64 exec_start, u32 flags); 89 u64 exec_start, u32 flags);
84u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj); 90u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj);
85 91
86/**
87 * struct intel_ctx_submit_request - queued context submission request
88 * @ctx: Context to submit to the ELSP.
89 * @ring: Engine to submit it to.
90 * @tail: how far in the context's ringbuffer this request goes to.
91 * @execlist_link: link in the submission queue.
92 * @work: workqueue for processing this request in a bottom half.
93 * @elsp_submitted: no. of times this request has been sent to the ELSP.
94 *
95 * The ELSP only accepts two elements at a time, so we queue context/tail
96 * pairs on a given queue (ring->execlist_queue) until the hardware is
97 * available. The queue serves a double purpose: we also use it to keep track
98 * of the up to 2 contexts currently in the hardware (usually one in execution
99 * and the other queued up by the GPU): We only remove elements from the head
100 * of the queue when the hardware informs us that an element has been
101 * completed.
102 *
103 * All accesses to the queue are mediated by a spinlock (ring->execlist_lock).
104 */
105struct intel_ctx_submit_request {
106 struct intel_context *ctx;
107 struct intel_engine_cs *ring;
108 u32 tail;
109
110 struct list_head execlist_link;
111
112 int elsp_submitted;
113};
114
115void intel_lrc_irq_handler(struct intel_engine_cs *ring); 92void intel_lrc_irq_handler(struct intel_engine_cs *ring);
116void intel_execlists_retire_requests(struct intel_engine_cs *ring); 93void intel_execlists_retire_requests(struct intel_engine_cs *ring);
117 94
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 14654d628ca4..071b96d6e146 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -32,6 +32,7 @@
32#include <linux/i2c.h> 32#include <linux/i2c.h>
33#include <linux/slab.h> 33#include <linux/slab.h>
34#include <drm/drmP.h> 34#include <drm/drmP.h>
35#include <drm/drm_atomic_helper.h>
35#include <drm/drm_crtc.h> 36#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h> 37#include <drm/drm_edid.h>
37#include "intel_drv.h" 38#include "intel_drv.h"
@@ -93,7 +94,7 @@ static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
93} 94}
94 95
95static void intel_lvds_get_config(struct intel_encoder *encoder, 96static void intel_lvds_get_config(struct intel_encoder *encoder,
96 struct intel_crtc_config *pipe_config) 97 struct intel_crtc_state *pipe_config)
97{ 98{
98 struct drm_device *dev = encoder->base.dev; 99 struct drm_device *dev = encoder->base.dev;
99 struct drm_i915_private *dev_priv = dev->dev_private; 100 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -115,7 +116,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
115 else 116 else
116 flags |= DRM_MODE_FLAG_PVSYNC; 117 flags |= DRM_MODE_FLAG_PVSYNC;
117 118
118 pipe_config->adjusted_mode.flags |= flags; 119 pipe_config->base.adjusted_mode.flags |= flags;
119 120
120 /* gen2/3 store dither state in pfit control, needs to match */ 121 /* gen2/3 store dither state in pfit control, needs to match */
121 if (INTEL_INFO(dev)->gen < 4) { 122 if (INTEL_INFO(dev)->gen < 4) {
@@ -129,7 +130,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
129 if (HAS_PCH_SPLIT(dev_priv->dev)) 130 if (HAS_PCH_SPLIT(dev_priv->dev))
130 ironlake_check_encoder_dotclock(pipe_config, dotclock); 131 ironlake_check_encoder_dotclock(pipe_config, dotclock);
131 132
132 pipe_config->adjusted_mode.crtc_clock = dotclock; 133 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
133} 134}
134 135
135static void intel_pre_enable_lvds(struct intel_encoder *encoder) 136static void intel_pre_enable_lvds(struct intel_encoder *encoder)
@@ -139,7 +140,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder)
139 struct drm_i915_private *dev_priv = dev->dev_private; 140 struct drm_i915_private *dev_priv = dev->dev_private;
140 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 141 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
141 const struct drm_display_mode *adjusted_mode = 142 const struct drm_display_mode *adjusted_mode =
142 &crtc->config.adjusted_mode; 143 &crtc->config->base.adjusted_mode;
143 int pipe = crtc->pipe; 144 int pipe = crtc->pipe;
144 u32 temp; 145 u32 temp;
145 146
@@ -167,7 +168,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder)
167 168
168 /* set the corresponsding LVDS_BORDER bit */ 169 /* set the corresponsding LVDS_BORDER bit */
169 temp &= ~LVDS_BORDER_ENABLE; 170 temp &= ~LVDS_BORDER_ENABLE;
170 temp |= crtc->config.gmch_pfit.lvds_border_bits; 171 temp |= crtc->config->gmch_pfit.lvds_border_bits;
171 /* Set the B0-B3 data pairs corresponding to whether we're going to 172 /* Set the B0-B3 data pairs corresponding to whether we're going to
172 * set the DPLLs for dual-channel mode or not. 173 * set the DPLLs for dual-channel mode or not.
173 */ 174 */
@@ -190,7 +191,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder)
190 if (INTEL_INFO(dev)->gen == 4) { 191 if (INTEL_INFO(dev)->gen == 4) {
191 /* Bspec wording suggests that LVDS port dithering only exists 192 /* Bspec wording suggests that LVDS port dithering only exists
192 * for 18bpp panels. */ 193 * for 18bpp panels. */
193 if (crtc->config.dither && crtc->config.pipe_bpp == 18) 194 if (crtc->config->dither && crtc->config->pipe_bpp == 18)
194 temp |= LVDS_ENABLE_DITHER; 195 temp |= LVDS_ENABLE_DITHER;
195 else 196 else
196 temp &= ~LVDS_ENABLE_DITHER; 197 temp &= ~LVDS_ENABLE_DITHER;
@@ -277,14 +278,14 @@ intel_lvds_mode_valid(struct drm_connector *connector,
277} 278}
278 279
279static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, 280static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
280 struct intel_crtc_config *pipe_config) 281 struct intel_crtc_state *pipe_config)
281{ 282{
282 struct drm_device *dev = intel_encoder->base.dev; 283 struct drm_device *dev = intel_encoder->base.dev;
283 struct intel_lvds_encoder *lvds_encoder = 284 struct intel_lvds_encoder *lvds_encoder =
284 to_lvds_encoder(&intel_encoder->base); 285 to_lvds_encoder(&intel_encoder->base);
285 struct intel_connector *intel_connector = 286 struct intel_connector *intel_connector =
286 &lvds_encoder->attached_connector->base; 287 &lvds_encoder->attached_connector->base;
287 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 288 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
288 struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc; 289 struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
289 unsigned int lvds_bpp; 290 unsigned int lvds_bpp;
290 291
@@ -531,7 +532,9 @@ static const struct drm_connector_funcs intel_lvds_connector_funcs = {
531 .detect = intel_lvds_detect, 532 .detect = intel_lvds_detect,
532 .fill_modes = drm_helper_probe_single_connector_modes, 533 .fill_modes = drm_helper_probe_single_connector_modes,
533 .set_property = intel_lvds_set_property, 534 .set_property = intel_lvds_set_property,
535 .atomic_get_property = intel_connector_atomic_get_property,
534 .destroy = intel_lvds_destroy, 536 .destroy = intel_lvds_destroy,
537 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
535}; 538};
536 539
537static const struct drm_encoder_funcs intel_lvds_enc_funcs = { 540static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 973c9de3b87d..f93dfc174495 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -856,7 +856,7 @@ static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
856 return -EINVAL; 856 return -EINVAL;
857 857
858 /* can't use the overlay with double wide pipe */ 858 /* can't use the overlay with double wide pipe */
859 if (crtc->config.double_wide) 859 if (crtc->config->double_wide)
860 return -EINVAL; 860 return -EINVAL;
861 861
862 return 0; 862 return 0;
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 4d63839bd9b4..d7be68a7bbda 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -98,13 +98,13 @@ intel_find_panel_downclock(struct drm_device *dev,
98/* adjusted_mode has been preset to be the panel's fixed mode */ 98/* adjusted_mode has been preset to be the panel's fixed mode */
99void 99void
100intel_pch_panel_fitting(struct intel_crtc *intel_crtc, 100intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
101 struct intel_crtc_config *pipe_config, 101 struct intel_crtc_state *pipe_config,
102 int fitting_mode) 102 int fitting_mode)
103{ 103{
104 struct drm_display_mode *adjusted_mode; 104 struct drm_display_mode *adjusted_mode;
105 int x, y, width, height; 105 int x, y, width, height;
106 106
107 adjusted_mode = &pipe_config->adjusted_mode; 107 adjusted_mode = &pipe_config->base.adjusted_mode;
108 108
109 x = y = width = height = 0; 109 x = y = width = height = 0;
110 110
@@ -223,10 +223,10 @@ static inline u32 panel_fitter_scaling(u32 source, u32 target)
223 return (FACTOR * ratio + FACTOR/2) / FACTOR; 223 return (FACTOR * ratio + FACTOR/2) / FACTOR;
224} 224}
225 225
226static void i965_scale_aspect(struct intel_crtc_config *pipe_config, 226static void i965_scale_aspect(struct intel_crtc_state *pipe_config,
227 u32 *pfit_control) 227 u32 *pfit_control)
228{ 228{
229 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 229 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
230 u32 scaled_width = adjusted_mode->hdisplay * 230 u32 scaled_width = adjusted_mode->hdisplay *
231 pipe_config->pipe_src_h; 231 pipe_config->pipe_src_h;
232 u32 scaled_height = pipe_config->pipe_src_w * 232 u32 scaled_height = pipe_config->pipe_src_w *
@@ -243,11 +243,11 @@ static void i965_scale_aspect(struct intel_crtc_config *pipe_config,
243 *pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO; 243 *pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
244} 244}
245 245
246static void i9xx_scale_aspect(struct intel_crtc_config *pipe_config, 246static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config,
247 u32 *pfit_control, u32 *pfit_pgm_ratios, 247 u32 *pfit_control, u32 *pfit_pgm_ratios,
248 u32 *border) 248 u32 *border)
249{ 249{
250 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 250 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
251 u32 scaled_width = adjusted_mode->hdisplay * 251 u32 scaled_width = adjusted_mode->hdisplay *
252 pipe_config->pipe_src_h; 252 pipe_config->pipe_src_h;
253 u32 scaled_height = pipe_config->pipe_src_w * 253 u32 scaled_height = pipe_config->pipe_src_w *
@@ -301,14 +301,14 @@ static void i9xx_scale_aspect(struct intel_crtc_config *pipe_config,
301} 301}
302 302
303void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, 303void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
304 struct intel_crtc_config *pipe_config, 304 struct intel_crtc_state *pipe_config,
305 int fitting_mode) 305 int fitting_mode)
306{ 306{
307 struct drm_device *dev = intel_crtc->base.dev; 307 struct drm_device *dev = intel_crtc->base.dev;
308 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; 308 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
309 struct drm_display_mode *adjusted_mode; 309 struct drm_display_mode *adjusted_mode;
310 310
311 adjusted_mode = &pipe_config->adjusted_mode; 311 adjusted_mode = &pipe_config->base.adjusted_mode;
312 312
313 /* Native modes don't need fitting */ 313 /* Native modes don't need fitting */
314 if (adjusted_mode->hdisplay == pipe_config->pipe_src_w && 314 if (adjusted_mode->hdisplay == pipe_config->pipe_src_w &&
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 03fc7f2ee9d1..6ece663f3394 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -76,7 +76,6 @@ static void gen9_init_clock_gating(struct drm_device *dev)
76 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE)); 76 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
77} 77}
78 78
79
80static void i915_pineview_get_mem_freq(struct drm_device *dev) 79static void i915_pineview_get_mem_freq(struct drm_device *dev)
81{ 80{
82 struct drm_i915_private *dev_priv = dev->dev_private; 81 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -539,7 +538,7 @@ static void pineview_update_wm(struct drm_crtc *unused_crtc)
539 int pixel_size = crtc->primary->fb->bits_per_pixel / 8; 538 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
540 int clock; 539 int clock;
541 540
542 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; 541 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
543 clock = adjusted_mode->crtc_clock; 542 clock = adjusted_mode->crtc_clock;
544 543
545 /* Display SR */ 544 /* Display SR */
@@ -608,10 +607,10 @@ static bool g4x_compute_wm0(struct drm_device *dev,
608 return false; 607 return false;
609 } 608 }
610 609
611 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; 610 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
612 clock = adjusted_mode->crtc_clock; 611 clock = adjusted_mode->crtc_clock;
613 htotal = adjusted_mode->crtc_htotal; 612 htotal = adjusted_mode->crtc_htotal;
614 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; 613 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
615 pixel_size = crtc->primary->fb->bits_per_pixel / 8; 614 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
616 615
617 /* Use the small buffer method to calculate plane watermark */ 616 /* Use the small buffer method to calculate plane watermark */
@@ -695,10 +694,10 @@ static bool g4x_compute_srwm(struct drm_device *dev,
695 } 694 }
696 695
697 crtc = intel_get_crtc_for_plane(dev, plane); 696 crtc = intel_get_crtc_for_plane(dev, plane);
698 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; 697 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
699 clock = adjusted_mode->crtc_clock; 698 clock = adjusted_mode->crtc_clock;
700 htotal = adjusted_mode->crtc_htotal; 699 htotal = adjusted_mode->crtc_htotal;
701 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; 700 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
702 pixel_size = crtc->primary->fb->bits_per_pixel / 8; 701 pixel_size = crtc->primary->fb->bits_per_pixel / 8;
703 702
704 line_time_us = max(htotal * 1000 / clock, 1); 703 line_time_us = max(htotal * 1000 / clock, 1);
@@ -729,7 +728,7 @@ static bool vlv_compute_drain_latency(struct drm_crtc *crtc,
729{ 728{
730 struct drm_device *dev = crtc->dev; 729 struct drm_device *dev = crtc->dev;
731 int entries; 730 int entries;
732 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; 731 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
733 732
734 if (WARN(clock == 0, "Pixel clock is zero!\n")) 733 if (WARN(clock == 0, "Pixel clock is zero!\n"))
735 return false; 734 return false;
@@ -1059,10 +1058,10 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
1059 /* self-refresh has much higher latency */ 1058 /* self-refresh has much higher latency */
1060 static const int sr_latency_ns = 12000; 1059 static const int sr_latency_ns = 12000;
1061 const struct drm_display_mode *adjusted_mode = 1060 const struct drm_display_mode *adjusted_mode =
1062 &to_intel_crtc(crtc)->config.adjusted_mode; 1061 &to_intel_crtc(crtc)->config->base.adjusted_mode;
1063 int clock = adjusted_mode->crtc_clock; 1062 int clock = adjusted_mode->crtc_clock;
1064 int htotal = adjusted_mode->crtc_htotal; 1063 int htotal = adjusted_mode->crtc_htotal;
1065 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; 1064 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1066 int pixel_size = crtc->primary->fb->bits_per_pixel / 8; 1065 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1067 unsigned long line_time_us; 1066 unsigned long line_time_us;
1068 int entries; 1067 int entries;
@@ -1144,7 +1143,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1144 if (IS_GEN2(dev)) 1143 if (IS_GEN2(dev))
1145 cpp = 4; 1144 cpp = 4;
1146 1145
1147 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; 1146 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1148 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1147 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1149 wm_info, fifo_size, cpp, 1148 wm_info, fifo_size, cpp,
1150 pessimal_latency_ns); 1149 pessimal_latency_ns);
@@ -1166,7 +1165,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1166 if (IS_GEN2(dev)) 1165 if (IS_GEN2(dev))
1167 cpp = 4; 1166 cpp = 4;
1168 1167
1169 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; 1168 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1170 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1169 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1171 wm_info, fifo_size, cpp, 1170 wm_info, fifo_size, cpp,
1172 pessimal_latency_ns); 1171 pessimal_latency_ns);
@@ -1205,10 +1204,10 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1205 /* self-refresh has much higher latency */ 1204 /* self-refresh has much higher latency */
1206 static const int sr_latency_ns = 6000; 1205 static const int sr_latency_ns = 6000;
1207 const struct drm_display_mode *adjusted_mode = 1206 const struct drm_display_mode *adjusted_mode =
1208 &to_intel_crtc(enabled)->config.adjusted_mode; 1207 &to_intel_crtc(enabled)->config->base.adjusted_mode;
1209 int clock = adjusted_mode->crtc_clock; 1208 int clock = adjusted_mode->crtc_clock;
1210 int htotal = adjusted_mode->crtc_htotal; 1209 int htotal = adjusted_mode->crtc_htotal;
1211 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w; 1210 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1212 int pixel_size = enabled->primary->fb->bits_per_pixel / 8; 1211 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1213 unsigned long line_time_us; 1212 unsigned long line_time_us;
1214 int entries; 1213 int entries;
@@ -1261,7 +1260,7 @@ static void i845_update_wm(struct drm_crtc *unused_crtc)
1261 if (crtc == NULL) 1260 if (crtc == NULL)
1262 return; 1261 return;
1263 1262
1264 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; 1263 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1265 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1264 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1266 &i845_wm_info, 1265 &i845_wm_info,
1267 dev_priv->display.get_fifo_size(dev, 0), 1266 dev_priv->display.get_fifo_size(dev, 0),
@@ -1280,17 +1279,17 @@ static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1281 uint32_t pixel_rate; 1280 uint32_t pixel_rate;
1282 1281
1283 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock; 1282 pixel_rate = intel_crtc->config->base.adjusted_mode.crtc_clock;
1284 1283
1285 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to 1284 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1286 * adjust the pixel_rate here. */ 1285 * adjust the pixel_rate here. */
1287 1286
1288 if (intel_crtc->config.pch_pfit.enabled) { 1287 if (intel_crtc->config->pch_pfit.enabled) {
1289 uint64_t pipe_w, pipe_h, pfit_w, pfit_h; 1288 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1290 uint32_t pfit_size = intel_crtc->config.pch_pfit.size; 1289 uint32_t pfit_size = intel_crtc->config->pch_pfit.size;
1291 1290
1292 pipe_w = intel_crtc->config.pipe_src_w; 1291 pipe_w = intel_crtc->config->pipe_src_w;
1293 pipe_h = intel_crtc->config.pipe_src_h; 1292 pipe_h = intel_crtc->config->pipe_src_h;
1294 pfit_w = (pfit_size >> 16) & 0xFFFF; 1293 pfit_w = (pfit_size >> 16) & 0xFFFF;
1295 pfit_h = pfit_size & 0xFFFF; 1294 pfit_h = pfit_size & 0xFFFF;
1296 if (pipe_w < pfit_w) 1295 if (pipe_w < pfit_w)
@@ -1643,7 +1642,7 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1643{ 1642{
1644 struct drm_i915_private *dev_priv = dev->dev_private; 1643 struct drm_i915_private *dev_priv = dev->dev_private;
1645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1644 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1646 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; 1645 struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
1647 u32 linetime, ips_linetime; 1646 u32 linetime, ips_linetime;
1648 1647
1649 if (!intel_crtc_active(crtc)) 1648 if (!intel_crtc_active(crtc))
@@ -1903,11 +1902,11 @@ static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
1903 return; 1902 return;
1904 1903
1905 p->active = true; 1904 p->active = true;
1906 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal; 1905 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
1907 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc); 1906 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
1908 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8; 1907 p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
1909 p->cur.bytes_per_pixel = 4; 1908 p->cur.bytes_per_pixel = 4;
1910 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w; 1909 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
1911 p->cur.horiz_pixels = intel_crtc->cursor_width; 1910 p->cur.horiz_pixels = intel_crtc->cursor_width;
1912 /* TODO: for now, assume primary and cursor planes are always enabled. */ 1911 /* TODO: for now, assume primary and cursor planes are always enabled. */
1913 p->pri.enabled = true; 1912 p->pri.enabled = true;
@@ -2556,10 +2555,10 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2556 2555
2557} 2556}
2558 2557
2559static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_config *config) 2558static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2560{ 2559{
2561 /* TODO: Take into account the scalers once we support them */ 2560 /* TODO: Take into account the scalers once we support them */
2562 return config->adjusted_mode.crtc_clock; 2561 return config->base.adjusted_mode.crtc_clock;
2563} 2562}
2564 2563
2565/* 2564/*
@@ -2647,8 +2646,8 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
2647 2646
2648 p->active = intel_crtc_active(crtc); 2647 p->active = intel_crtc_active(crtc);
2649 if (p->active) { 2648 if (p->active) {
2650 p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal; 2649 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2651 p->pixel_rate = skl_pipe_pixel_rate(&intel_crtc->config); 2650 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
2652 2651
2653 /* 2652 /*
2654 * For now, assume primary and cursor planes are always enabled. 2653 * For now, assume primary and cursor planes are always enabled.
@@ -2656,8 +2655,8 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
2656 p->plane[0].enabled = true; 2655 p->plane[0].enabled = true;
2657 p->plane[0].bytes_per_pixel = 2656 p->plane[0].bytes_per_pixel =
2658 crtc->primary->fb->bits_per_pixel / 8; 2657 crtc->primary->fb->bits_per_pixel / 8;
2659 p->plane[0].horiz_pixels = intel_crtc->config.pipe_src_w; 2658 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
2660 p->plane[0].vert_pixels = intel_crtc->config.pipe_src_h; 2659 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
2661 2660
2662 p->cursor.enabled = true; 2661 p->cursor.enabled = true;
2663 p->cursor.bytes_per_pixel = 4; 2662 p->cursor.bytes_per_pixel = 4;
@@ -3800,8 +3799,8 @@ static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3800{ 3799{
3801 struct drm_device *dev = dev_priv->dev; 3800 struct drm_device *dev = dev_priv->dev;
3802 3801
3803 /* Latest VLV doesn't need to force the gfx clock */ 3802 /* CHV and latest VLV don't need to force the gfx clock */
3804 if (dev->pdev->revision >= 0xd) { 3803 if (IS_CHERRYVIEW(dev) || dev->pdev->revision >= 0xd) {
3805 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); 3804 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3806 return; 3805 return;
3807 } 3806 }
@@ -3840,9 +3839,7 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
3840 3839
3841 mutex_lock(&dev_priv->rps.hw_lock); 3840 mutex_lock(&dev_priv->rps.hw_lock);
3842 if (dev_priv->rps.enabled) { 3841 if (dev_priv->rps.enabled) {
3843 if (IS_CHERRYVIEW(dev)) 3842 if (IS_VALLEYVIEW(dev))
3844 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3845 else if (IS_VALLEYVIEW(dev))
3846 vlv_set_rps_idle(dev_priv); 3843 vlv_set_rps_idle(dev_priv);
3847 else 3844 else
3848 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); 3845 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
@@ -3884,7 +3881,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
3884 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); 3881 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3885 3882
3886 dev_priv->rps.cur_freq = val; 3883 dev_priv->rps.cur_freq = val;
3887 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val)); 3884 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
3888} 3885}
3889 3886
3890static void gen9_disable_rps(struct drm_device *dev) 3887static void gen9_disable_rps(struct drm_device *dev)
@@ -3892,6 +3889,7 @@ static void gen9_disable_rps(struct drm_device *dev)
3892 struct drm_i915_private *dev_priv = dev->dev_private; 3889 struct drm_i915_private *dev_priv = dev->dev_private;
3893 3890
3894 I915_WRITE(GEN6_RC_CONTROL, 0); 3891 I915_WRITE(GEN6_RC_CONTROL, 0);
3892 I915_WRITE(GEN9_PG_ENABLE, 0);
3895} 3893}
3896 3894
3897static void gen6_disable_rps(struct drm_device *dev) 3895static void gen6_disable_rps(struct drm_device *dev)
@@ -3915,11 +3913,11 @@ static void valleyview_disable_rps(struct drm_device *dev)
3915 3913
3916 /* we're doing forcewake before Disabling RC6, 3914 /* we're doing forcewake before Disabling RC6,
3917 * This what the BIOS expects when going into suspend */ 3915 * This what the BIOS expects when going into suspend */
3918 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); 3916 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
3919 3917
3920 I915_WRITE(GEN6_RC_CONTROL, 0); 3918 I915_WRITE(GEN6_RC_CONTROL, 0);
3921 3919
3922 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); 3920 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
3923} 3921}
3924 3922
3925static void intel_print_rc6_info(struct drm_device *dev, u32 mode) 3923static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
@@ -4025,9 +4023,39 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)
4025 } 4023 }
4026} 4024}
4027 4025
4026/* See the Gen9_GT_PM_Programming_Guide doc for the below */
4028static void gen9_enable_rps(struct drm_device *dev) 4027static void gen9_enable_rps(struct drm_device *dev)
4029{ 4028{
4030 struct drm_i915_private *dev_priv = dev->dev_private; 4029 struct drm_i915_private *dev_priv = dev->dev_private;
4030
4031 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4032
4033 gen6_init_rps_frequencies(dev);
4034
4035 I915_WRITE(GEN6_RPNSWREQ, 0xc800000);
4036 I915_WRITE(GEN6_RC_VIDEO_FREQ, 0xc800000);
4037
4038 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
4039 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 0x12060000);
4040 I915_WRITE(GEN6_RP_UP_THRESHOLD, 0xe808);
4041 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 0x3bd08);
4042 I915_WRITE(GEN6_RP_UP_EI, 0x101d0);
4043 I915_WRITE(GEN6_RP_DOWN_EI, 0x55730);
4044 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4045 I915_WRITE(GEN6_PMINTRMSK, 0x6);
4046 I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO |
4047 GEN6_RP_MEDIA_HW_MODE | GEN6_RP_MEDIA_IS_GFX |
4048 GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG |
4049 GEN6_RP_DOWN_IDLE_AVG);
4050
4051 gen6_enable_rps_interrupts(dev);
4052
4053 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4054}
4055
4056static void gen9_enable_rc6(struct drm_device *dev)
4057{
4058 struct drm_i915_private *dev_priv = dev->dev_private;
4031 struct intel_engine_cs *ring; 4059 struct intel_engine_cs *ring;
4032 uint32_t rc6_mask = 0; 4060 uint32_t rc6_mask = 0;
4033 int unused; 4061 int unused;
@@ -4037,7 +4065,7 @@ static void gen9_enable_rps(struct drm_device *dev)
4037 4065
4038 /* 1b: Get forcewake during program sequence. Although the driver 4066 /* 1b: Get forcewake during program sequence. Although the driver
4039 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ 4067 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4040 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); 4068 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4041 4069
4042 /* 2a: Disable RC states. */ 4070 /* 2a: Disable RC states. */
4043 I915_WRITE(GEN6_RC_CONTROL, 0); 4071 I915_WRITE(GEN6_RC_CONTROL, 0);
@@ -4051,6 +4079,10 @@ static void gen9_enable_rps(struct drm_device *dev)
4051 I915_WRITE(GEN6_RC_SLEEP, 0); 4079 I915_WRITE(GEN6_RC_SLEEP, 0);
4052 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ 4080 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4053 4081
4082 /* 2c: Program Coarse Power Gating Policies. */
4083 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4084 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4085
4054 /* 3a: Enable RC6 */ 4086 /* 3a: Enable RC6 */
4055 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 4087 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4056 rc6_mask = GEN6_RC_CTL_RC6_ENABLE; 4088 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
@@ -4060,7 +4092,10 @@ static void gen9_enable_rps(struct drm_device *dev)
4060 GEN6_RC_CTL_EI_MODE(1) | 4092 GEN6_RC_CTL_EI_MODE(1) |
4061 rc6_mask); 4093 rc6_mask);
4062 4094
4063 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); 4095 /* 3b: Enable Coarse Power Gating only when RC6 is enabled */
4096 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 3 : 0);
4097
4098 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4064 4099
4065} 4100}
4066 4101
@@ -4076,7 +4111,7 @@ static void gen8_enable_rps(struct drm_device *dev)
4076 4111
4077 /* 1c & 1d: Get forcewake during program sequence. Although the driver 4112 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4078 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ 4113 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4079 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); 4114 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4080 4115
4081 /* 2a: Disable RC states. */ 4116 /* 2a: Disable RC states. */
4082 I915_WRITE(GEN6_RC_CONTROL, 0); 4117 I915_WRITE(GEN6_RC_CONTROL, 0);
@@ -4143,7 +4178,7 @@ static void gen8_enable_rps(struct drm_device *dev)
4143 dev_priv->rps.power = HIGH_POWER; /* force a reset */ 4178 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4144 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); 4179 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4145 4180
4146 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); 4181 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4147} 4182}
4148 4183
4149static void gen6_enable_rps(struct drm_device *dev) 4184static void gen6_enable_rps(struct drm_device *dev)
@@ -4171,7 +4206,7 @@ static void gen6_enable_rps(struct drm_device *dev)
4171 I915_WRITE(GTFIFODBG, gtfifodbg); 4206 I915_WRITE(GTFIFODBG, gtfifodbg);
4172 } 4207 }
4173 4208
4174 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); 4209 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4175 4210
4176 /* Initialize rps frequencies */ 4211 /* Initialize rps frequencies */
4177 gen6_init_rps_frequencies(dev); 4212 gen6_init_rps_frequencies(dev);
@@ -4251,7 +4286,7 @@ static void gen6_enable_rps(struct drm_device *dev)
4251 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); 4286 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4252 } 4287 }
4253 4288
4254 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); 4289 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4255} 4290}
4256 4291
4257static void __gen6_update_ring_freq(struct drm_device *dev) 4292static void __gen6_update_ring_freq(struct drm_device *dev)
@@ -4338,11 +4373,35 @@ void gen6_update_ring_freq(struct drm_device *dev)
4338 4373
4339static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) 4374static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
4340{ 4375{
4376 struct drm_device *dev = dev_priv->dev;
4341 u32 val, rp0; 4377 u32 val, rp0;
4342 4378
4343 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); 4379 if (dev->pdev->revision >= 0x20) {
4344 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK; 4380 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
4345 4381
4382 switch (INTEL_INFO(dev)->eu_total) {
4383 case 8:
4384 /* (2 * 4) config */
4385 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
4386 break;
4387 case 12:
4388 /* (2 * 6) config */
4389 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
4390 break;
4391 case 16:
4392 /* (2 * 8) config */
4393 default:
4394 /* Setting (2 * 8) Min RP0 for any other combination */
4395 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
4396 break;
4397 }
4398 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
4399 } else {
4400 /* For pre-production hardware */
4401 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4402 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4403 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4404 }
4346 return rp0; 4405 return rp0;
4347} 4406}
4348 4407
@@ -4358,20 +4417,36 @@ static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4358 4417
4359static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) 4418static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4360{ 4419{
4420 struct drm_device *dev = dev_priv->dev;
4361 u32 val, rp1; 4421 u32 val, rp1;
4362 4422
4363 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 4423 if (dev->pdev->revision >= 0x20) {
4364 rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK; 4424 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
4365 4425 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
4426 } else {
4427 /* For pre-production hardware */
4428 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4429 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4430 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
4431 }
4366 return rp1; 4432 return rp1;
4367} 4433}
4368 4434
4369static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv) 4435static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
4370{ 4436{
4437 struct drm_device *dev = dev_priv->dev;
4371 u32 val, rpn; 4438 u32 val, rpn;
4372 4439
4373 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); 4440 if (dev->pdev->revision >= 0x20) {
4374 rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK; 4441 val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
4442 rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
4443 FB_GFX_FREQ_FUSE_MASK);
4444 } else { /* For pre-production hardware */
4445 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4446 rpn = ((val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) &
4447 PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK);
4448 }
4449
4375 return rpn; 4450 return rpn;
4376} 4451}
4377 4452
@@ -4542,22 +4617,22 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
4542 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); 4617 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4543 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; 4618 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4544 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", 4619 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4545 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq), 4620 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4546 dev_priv->rps.max_freq); 4621 dev_priv->rps.max_freq);
4547 4622
4548 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); 4623 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4549 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", 4624 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4550 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 4625 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4551 dev_priv->rps.efficient_freq); 4626 dev_priv->rps.efficient_freq);
4552 4627
4553 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); 4628 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4554 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", 4629 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
4555 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), 4630 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4556 dev_priv->rps.rp1_freq); 4631 dev_priv->rps.rp1_freq);
4557 4632
4558 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); 4633 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4559 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", 4634 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4560 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq), 4635 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4561 dev_priv->rps.min_freq); 4636 dev_priv->rps.min_freq);
4562 4637
4563 /* Preserve min/max settings in case of re-init */ 4638 /* Preserve min/max settings in case of re-init */
@@ -4611,22 +4686,22 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
4611 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); 4686 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4612 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; 4687 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4613 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", 4688 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4614 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq), 4689 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4615 dev_priv->rps.max_freq); 4690 dev_priv->rps.max_freq);
4616 4691
4617 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); 4692 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
4618 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", 4693 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4619 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 4694 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4620 dev_priv->rps.efficient_freq); 4695 dev_priv->rps.efficient_freq);
4621 4696
4622 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); 4697 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
4623 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", 4698 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
4624 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), 4699 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
4625 dev_priv->rps.rp1_freq); 4700 dev_priv->rps.rp1_freq);
4626 4701
4627 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv); 4702 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
4628 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", 4703 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4629 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq), 4704 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4630 dev_priv->rps.min_freq); 4705 dev_priv->rps.min_freq);
4631 4706
4632 WARN_ONCE((dev_priv->rps.max_freq | 4707 WARN_ONCE((dev_priv->rps.max_freq |
@@ -4670,7 +4745,10 @@ static void cherryview_enable_rps(struct drm_device *dev)
4670 4745
4671 /* 1a & 1b: Get forcewake during program sequence. Although the driver 4746 /* 1a & 1b: Get forcewake during program sequence. Although the driver
4672 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ 4747 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4673 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); 4748 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4749
4750 /* Disable RC states. */
4751 I915_WRITE(GEN6_RC_CONTROL, 0);
4674 4752
4675 /* 2a: Program RC6 thresholds.*/ 4753 /* 2a: Program RC6 thresholds.*/
4676 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 4754 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
@@ -4681,7 +4759,8 @@ static void cherryview_enable_rps(struct drm_device *dev)
4681 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 4759 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4682 I915_WRITE(GEN6_RC_SLEEP, 0); 4760 I915_WRITE(GEN6_RC_SLEEP, 0);
4683 4761
4684 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ 4762 /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */
4763 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
4685 4764
4686 /* allows RC6 residency counter to work */ 4765 /* allows RC6 residency counter to work */
4687 I915_WRITE(VLV_COUNTER_CONTROL, 4766 I915_WRITE(VLV_COUNTER_CONTROL,
@@ -4695,11 +4774,12 @@ static void cherryview_enable_rps(struct drm_device *dev)
4695 /* 3: Enable RC6 */ 4774 /* 3: Enable RC6 */
4696 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && 4775 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
4697 (pcbr >> VLV_PCBR_ADDR_SHIFT)) 4776 (pcbr >> VLV_PCBR_ADDR_SHIFT))
4698 rc6_mode = GEN6_RC_CTL_EI_MODE(1); 4777 rc6_mode = GEN7_RC_CTL_TO_MODE;
4699 4778
4700 I915_WRITE(GEN6_RC_CONTROL, rc6_mode); 4779 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4701 4780
4702 /* 4 Program defaults and thresholds for RPS*/ 4781 /* 4 Program defaults and thresholds for RPS*/
4782 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
4703 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); 4783 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4704 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); 4784 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4705 I915_WRITE(GEN6_RP_UP_EI, 66000); 4785 I915_WRITE(GEN6_RP_UP_EI, 66000);
@@ -4707,14 +4787,10 @@ static void cherryview_enable_rps(struct drm_device *dev)
4707 4787
4708 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 4788 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4709 4789
4710 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4711 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4712 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4713
4714 /* 5: Enable RPS */ 4790 /* 5: Enable RPS */
4715 I915_WRITE(GEN6_RP_CONTROL, 4791 I915_WRITE(GEN6_RP_CONTROL,
4716 GEN6_RP_MEDIA_HW_NORMAL_MODE | 4792 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4717 GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */ 4793 GEN6_RP_MEDIA_IS_GFX |
4718 GEN6_RP_ENABLE | 4794 GEN6_RP_ENABLE |
4719 GEN6_RP_UP_BUSY_AVG | 4795 GEN6_RP_UP_BUSY_AVG |
4720 GEN6_RP_DOWN_IDLE_AVG); 4796 GEN6_RP_DOWN_IDLE_AVG);
@@ -4729,16 +4805,16 @@ static void cherryview_enable_rps(struct drm_device *dev)
4729 4805
4730 dev_priv->rps.cur_freq = (val >> 8) & 0xff; 4806 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4731 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", 4807 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4732 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), 4808 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4733 dev_priv->rps.cur_freq); 4809 dev_priv->rps.cur_freq);
4734 4810
4735 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", 4811 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4736 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 4812 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4737 dev_priv->rps.efficient_freq); 4813 dev_priv->rps.efficient_freq);
4738 4814
4739 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); 4815 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4740 4816
4741 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); 4817 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4742} 4818}
4743 4819
4744static void valleyview_enable_rps(struct drm_device *dev) 4820static void valleyview_enable_rps(struct drm_device *dev)
@@ -4759,15 +4835,18 @@ static void valleyview_enable_rps(struct drm_device *dev)
4759 } 4835 }
4760 4836
4761 /* If VLV, Forcewake all wells, else re-direct to regular path */ 4837 /* If VLV, Forcewake all wells, else re-direct to regular path */
4762 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); 4838 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4763 4839
4840 /* Disable RC states. */
4841 I915_WRITE(GEN6_RC_CONTROL, 0);
4842
4843 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
4764 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); 4844 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4765 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); 4845 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4766 I915_WRITE(GEN6_RP_UP_EI, 66000); 4846 I915_WRITE(GEN6_RP_UP_EI, 66000);
4767 I915_WRITE(GEN6_RP_DOWN_EI, 350000); 4847 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4768 4848
4769 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 4849 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4770 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240);
4771 4850
4772 I915_WRITE(GEN6_RP_CONTROL, 4851 I915_WRITE(GEN6_RP_CONTROL,
4773 GEN6_RP_MEDIA_TURBO | 4852 GEN6_RP_MEDIA_TURBO |
@@ -4810,16 +4889,16 @@ static void valleyview_enable_rps(struct drm_device *dev)
4810 4889
4811 dev_priv->rps.cur_freq = (val >> 8) & 0xff; 4890 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
4812 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", 4891 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4813 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), 4892 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
4814 dev_priv->rps.cur_freq); 4893 dev_priv->rps.cur_freq);
4815 4894
4816 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", 4895 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4817 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 4896 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4818 dev_priv->rps.efficient_freq); 4897 dev_priv->rps.efficient_freq);
4819 4898
4820 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); 4899 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
4821 4900
4822 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); 4901 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4823} 4902}
4824 4903
4825void ironlake_teardown_rc6(struct drm_device *dev) 4904void ironlake_teardown_rc6(struct drm_device *dev)
@@ -5527,7 +5606,9 @@ static void intel_gen6_powersave_work(struct work_struct *work)
5527 } else if (IS_VALLEYVIEW(dev)) { 5606 } else if (IS_VALLEYVIEW(dev)) {
5528 valleyview_enable_rps(dev); 5607 valleyview_enable_rps(dev);
5529 } else if (INTEL_INFO(dev)->gen >= 9) { 5608 } else if (INTEL_INFO(dev)->gen >= 9) {
5609 gen9_enable_rc6(dev);
5530 gen9_enable_rps(dev); 5610 gen9_enable_rps(dev);
5611 __gen6_update_ring_freq(dev);
5531 } else if (IS_BROADWELL(dev)) { 5612 } else if (IS_BROADWELL(dev)) {
5532 gen8_enable_rps(dev); 5613 gen8_enable_rps(dev);
5533 __gen6_update_ring_freq(dev); 5614 __gen6_update_ring_freq(dev);
@@ -6147,6 +6228,17 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
6147 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 6228 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6148 6229
6149 /* 6230 /*
6231 * BSpec recommends 8x4 when MSAA is used,
6232 * however in practice 16x4 seems fastest.
6233 *
6234 * Note that PS/WM thread counts depend on the WIZ hashing
6235 * disable bit, which we don't touch here, but it's good
6236 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6237 */
6238 I915_WRITE(GEN7_GT_MODE,
6239 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6240
6241 /*
6150 * WaIncreaseL3CreditsForVLVB0:vlv 6242 * WaIncreaseL3CreditsForVLVB0:vlv
6151 * This is the hardware default actually. 6243 * This is the hardware default actually.
6152 */ 6244 */
@@ -6521,28 +6613,24 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6521 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; 6613 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
6522} 6614}
6523 6615
6524int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) 6616int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
6525{ 6617{
6526 int ret = -1;
6527
6528 if (IS_CHERRYVIEW(dev_priv->dev)) 6618 if (IS_CHERRYVIEW(dev_priv->dev))
6529 ret = chv_gpu_freq(dev_priv, val); 6619 return chv_gpu_freq(dev_priv, val);
6530 else if (IS_VALLEYVIEW(dev_priv->dev)) 6620 else if (IS_VALLEYVIEW(dev_priv->dev))
6531 ret = byt_gpu_freq(dev_priv, val); 6621 return byt_gpu_freq(dev_priv, val);
6532 6622 else
6533 return ret; 6623 return val * GT_FREQUENCY_MULTIPLIER;
6534} 6624}
6535 6625
6536int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val) 6626int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
6537{ 6627{
6538 int ret = -1;
6539
6540 if (IS_CHERRYVIEW(dev_priv->dev)) 6628 if (IS_CHERRYVIEW(dev_priv->dev))
6541 ret = chv_freq_opcode(dev_priv, val); 6629 return chv_freq_opcode(dev_priv, val);
6542 else if (IS_VALLEYVIEW(dev_priv->dev)) 6630 else if (IS_VALLEYVIEW(dev_priv->dev))
6543 ret = byt_freq_opcode(dev_priv, val); 6631 return byt_freq_opcode(dev_priv, val);
6544 6632 else
6545 return ret; 6633 return val / GT_FREQUENCY_MULTIPLIER;
6546} 6634}
6547 6635
6548void intel_pm_setup(struct drm_device *dev) 6636void intel_pm_setup(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 5ae193ec464a..b9f40c2e0af7 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -79,8 +79,8 @@ static void intel_psr_write_vsc(struct intel_dp *intel_dp,
79 struct drm_device *dev = dig_port->base.base.dev; 79 struct drm_device *dev = dig_port->base.base.dev;
80 struct drm_i915_private *dev_priv = dev->dev_private; 80 struct drm_i915_private *dev_priv = dev->dev_private;
81 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 81 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
82 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); 82 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config->cpu_transcoder);
83 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); 83 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config->cpu_transcoder);
84 uint32_t *data = (uint32_t *) vsc_psr; 84 uint32_t *data = (uint32_t *) vsc_psr;
85 unsigned int i; 85 unsigned int i;
86 86
@@ -142,6 +142,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
142 struct drm_device *dev = dig_port->base.base.dev; 142 struct drm_device *dev = dig_port->base.base.dev;
143 struct drm_i915_private *dev_priv = dev->dev_private; 143 struct drm_i915_private *dev_priv = dev->dev_private;
144 uint32_t aux_clock_divider; 144 uint32_t aux_clock_divider;
145 uint32_t aux_data_reg, aux_ctl_reg;
145 int precharge = 0x3; 146 int precharge = 0x3;
146 static const uint8_t aux_msg[] = { 147 static const uint8_t aux_msg[] = {
147 [0] = DP_AUX_NATIVE_WRITE << 4, 148 [0] = DP_AUX_NATIVE_WRITE << 4,
@@ -164,16 +165,34 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
164 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 165 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
165 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); 166 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
166 167
168 aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
169 DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev);
170 aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
171 DPA_AUX_CH_CTL : EDP_PSR_AUX_CTL(dev);
172
167 /* Setup AUX registers */ 173 /* Setup AUX registers */
168 for (i = 0; i < sizeof(aux_msg); i += 4) 174 for (i = 0; i < sizeof(aux_msg); i += 4)
169 I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i, 175 I915_WRITE(aux_data_reg + i,
170 intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); 176 intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
171 177
172 I915_WRITE(EDP_PSR_AUX_CTL(dev), 178 if (INTEL_INFO(dev)->gen >= 9) {
179 uint32_t val;
180
181 val = I915_READ(aux_ctl_reg);
182 val &= ~DP_AUX_CH_CTL_TIME_OUT_MASK;
183 val |= DP_AUX_CH_CTL_TIME_OUT_1600us;
184 val &= ~DP_AUX_CH_CTL_MESSAGE_SIZE_MASK;
185 val |= (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
186 /* Use hardcoded data values for PSR */
187 val &= ~DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL;
188 I915_WRITE(aux_ctl_reg, val);
189 } else {
190 I915_WRITE(aux_ctl_reg,
173 DP_AUX_CH_CTL_TIME_OUT_400us | 191 DP_AUX_CH_CTL_TIME_OUT_400us |
174 (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 192 (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
175 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 193 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
176 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); 194 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
195 }
177} 196}
178 197
179static void vlv_psr_enable_source(struct intel_dp *intel_dp) 198static void vlv_psr_enable_source(struct intel_dp *intel_dp)
@@ -263,14 +282,14 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
263 } 282 }
264 283
265 if (IS_HASWELL(dev) && 284 if (IS_HASWELL(dev) &&
266 I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & 285 I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
267 S3D_ENABLE) { 286 S3D_ENABLE) {
268 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); 287 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
269 return false; 288 return false;
270 } 289 }
271 290
272 if (IS_HASWELL(dev) && 291 if (IS_HASWELL(dev) &&
273 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 292 intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
274 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); 293 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
275 return false; 294 return false;
276 } 295 }
@@ -351,6 +370,9 @@ void intel_psr_enable(struct intel_dp *intel_dp)
351 370
352 /* Enable PSR on the panel */ 371 /* Enable PSR on the panel */
353 hsw_psr_enable_sink(intel_dp); 372 hsw_psr_enable_sink(intel_dp);
373
374 if (INTEL_INFO(dev)->gen >= 9)
375 intel_psr_activate(intel_dp);
354 } else { 376 } else {
355 vlv_psr_setup_vsc(intel_dp); 377 vlv_psr_setup_vsc(intel_dp);
356 378
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 23020d67329b..0bd3976d88e1 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -539,7 +539,7 @@ static int init_ring_common(struct intel_engine_cs *ring)
539 struct drm_i915_gem_object *obj = ringbuf->obj; 539 struct drm_i915_gem_object *obj = ringbuf->obj;
540 int ret = 0; 540 int ret = 0;
541 541
542 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); 542 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
543 543
544 if (!stop_ring(ring)) { 544 if (!stop_ring(ring)) {
545 /* G45 ring initialization often fails to reset head to zero */ 545 /* G45 ring initialization often fails to reset head to zero */
@@ -611,7 +611,7 @@ static int init_ring_common(struct intel_engine_cs *ring)
611 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); 611 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
612 612
613out: 613out:
614 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); 614 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
615 615
616 return ret; 616 return ret;
617} 617}
@@ -851,9 +851,25 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
851 */ 851 */
852 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 852 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
853 853
854 /* Wa4x4STCOptimizationDisable:chv */
855 WA_SET_BIT_MASKED(CACHE_MODE_1,
856 GEN8_4x4_STC_OPTIMIZATION_DISABLE);
857
854 /* Improve HiZ throughput on CHV. */ 858 /* Improve HiZ throughput on CHV. */
855 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 859 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
856 860
861 /*
862 * BSpec recommends 8x4 when MSAA is used,
863 * however in practice 16x4 seems fastest.
864 *
865 * Note that PS/WM thread counts depend on the WIZ hashing
866 * disable bit, which we don't touch here, but it's good
867 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
868 */
869 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
870 GEN6_WIZ_HASHING_MASK,
871 GEN6_WIZ_HASHING_16x4);
872
857 return 0; 873 return 0;
858} 874}
859 875
@@ -1949,7 +1965,7 @@ static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
1949 return 0; 1965 return 0;
1950 1966
1951 list_for_each_entry(request, &ring->request_list, list) { 1967 list_for_each_entry(request, &ring->request_list, list) {
1952 if (__intel_ring_space(request->tail, ringbuf->tail, 1968 if (__intel_ring_space(request->postfix, ringbuf->tail,
1953 ringbuf->size) >= n) { 1969 ringbuf->size) >= n) {
1954 break; 1970 break;
1955 } 1971 }
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 6dbb6f462007..714f3fdd57d2 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -99,13 +99,6 @@ struct intel_ringbuffer {
99 99
100 struct intel_engine_cs *ring; 100 struct intel_engine_cs *ring;
101 101
102 /*
103 * FIXME: This backpointer is an artifact of the history of how the
104 * execlist patches came into being. It will get removed once the basic
105 * code has landed.
106 */
107 struct intel_context *FIXME_lrc_ctx;
108
109 u32 head; 102 u32 head;
110 u32 tail; 103 u32 tail;
111 int space; 104 int space;
@@ -123,6 +116,8 @@ struct intel_ringbuffer {
123 u32 last_retired_head; 116 u32 last_retired_head;
124}; 117};
125 118
119struct intel_context;
120
126struct intel_engine_cs { 121struct intel_engine_cs {
127 const char *name; 122 const char *name;
128 enum intel_ring_id { 123 enum intel_ring_id {
@@ -239,11 +234,14 @@ struct intel_engine_cs {
239 struct list_head execlist_retired_req_list; 234 struct list_head execlist_retired_req_list;
240 u8 next_context_status_buffer; 235 u8 next_context_status_buffer;
241 u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */ 236 u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */
242 int (*emit_request)(struct intel_ringbuffer *ringbuf); 237 int (*emit_request)(struct intel_ringbuffer *ringbuf,
238 struct drm_i915_gem_request *request);
243 int (*emit_flush)(struct intel_ringbuffer *ringbuf, 239 int (*emit_flush)(struct intel_ringbuffer *ringbuf,
240 struct intel_context *ctx,
244 u32 invalidate_domains, 241 u32 invalidate_domains,
245 u32 flush_domains); 242 u32 flush_domains);
246 int (*emit_bb_start)(struct intel_ringbuffer *ringbuf, 243 int (*emit_bb_start)(struct intel_ringbuffer *ringbuf,
244 struct intel_context *ctx,
247 u64 offset, unsigned flags); 245 u64 offset, unsigned flags);
248 246
249 /** 247 /**
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 8bf7bb4a12bc..49695d7d51e3 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -703,6 +703,10 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
703 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 703 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
704 BIT(POWER_DOMAIN_PORT_CRT) | \ 704 BIT(POWER_DOMAIN_PORT_CRT) | \
705 BIT(POWER_DOMAIN_PLLS) | \ 705 BIT(POWER_DOMAIN_PLLS) | \
706 BIT(POWER_DOMAIN_AUX_A) | \
707 BIT(POWER_DOMAIN_AUX_B) | \
708 BIT(POWER_DOMAIN_AUX_C) | \
709 BIT(POWER_DOMAIN_AUX_D) | \
706 BIT(POWER_DOMAIN_INIT)) 710 BIT(POWER_DOMAIN_INIT))
707#define HSW_DISPLAY_POWER_DOMAINS ( \ 711#define HSW_DISPLAY_POWER_DOMAINS ( \
708 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ 712 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
@@ -724,24 +728,30 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
724 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 728 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
725 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 729 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
726 BIT(POWER_DOMAIN_PORT_CRT) | \ 730 BIT(POWER_DOMAIN_PORT_CRT) | \
731 BIT(POWER_DOMAIN_AUX_B) | \
732 BIT(POWER_DOMAIN_AUX_C) | \
727 BIT(POWER_DOMAIN_INIT)) 733 BIT(POWER_DOMAIN_INIT))
728 734
729#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ 735#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
730 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ 736 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
731 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 737 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
738 BIT(POWER_DOMAIN_AUX_B) | \
732 BIT(POWER_DOMAIN_INIT)) 739 BIT(POWER_DOMAIN_INIT))
733 740
734#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ 741#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
735 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 742 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
743 BIT(POWER_DOMAIN_AUX_B) | \
736 BIT(POWER_DOMAIN_INIT)) 744 BIT(POWER_DOMAIN_INIT))
737 745
738#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ 746#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
739 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 747 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
740 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 748 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
749 BIT(POWER_DOMAIN_AUX_C) | \
741 BIT(POWER_DOMAIN_INIT)) 750 BIT(POWER_DOMAIN_INIT))
742 751
743#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ 752#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
744 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 753 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
754 BIT(POWER_DOMAIN_AUX_C) | \
745 BIT(POWER_DOMAIN_INIT)) 755 BIT(POWER_DOMAIN_INIT))
746 756
747#define CHV_PIPE_A_POWER_DOMAINS ( \ 757#define CHV_PIPE_A_POWER_DOMAINS ( \
@@ -761,20 +771,25 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
761 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ 771 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
762 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ 772 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
763 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ 773 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
774 BIT(POWER_DOMAIN_AUX_B) | \
775 BIT(POWER_DOMAIN_AUX_C) | \
764 BIT(POWER_DOMAIN_INIT)) 776 BIT(POWER_DOMAIN_INIT))
765 777
766#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ 778#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
767 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ 779 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
768 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 780 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
781 BIT(POWER_DOMAIN_AUX_D) | \
769 BIT(POWER_DOMAIN_INIT)) 782 BIT(POWER_DOMAIN_INIT))
770 783
771#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \ 784#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
772 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ 785 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
773 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 786 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
787 BIT(POWER_DOMAIN_AUX_D) | \
774 BIT(POWER_DOMAIN_INIT)) 788 BIT(POWER_DOMAIN_INIT))
775 789
776#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \ 790#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
777 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ 791 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
792 BIT(POWER_DOMAIN_AUX_D) | \
778 BIT(POWER_DOMAIN_INIT)) 793 BIT(POWER_DOMAIN_INIT))
779 794
780static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 795static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 4e3d362931e9..64ad2b40179f 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -30,6 +30,7 @@
30#include <linux/delay.h> 30#include <linux/delay.h>
31#include <linux/export.h> 31#include <linux/export.h>
32#include <drm/drmP.h> 32#include <drm/drmP.h>
33#include <drm/drm_atomic_helper.h>
33#include <drm/drm_crtc.h> 34#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h> 35#include <drm/drm_edid.h>
35#include "intel_drv.h" 36#include "intel_drv.h"
@@ -1007,7 +1008,7 @@ static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
1007 } 1008 }
1008 1009
1009 if (intel_sdvo->rgb_quant_range_selectable) { 1010 if (intel_sdvo->rgb_quant_range_selectable) {
1010 if (intel_crtc->config.limited_color_range) 1011 if (intel_crtc->config->limited_color_range)
1011 frame.avi.quantization_range = 1012 frame.avi.quantization_range =
1012 HDMI_QUANTIZATION_RANGE_LIMITED; 1013 HDMI_QUANTIZATION_RANGE_LIMITED;
1013 else 1014 else
@@ -1085,7 +1086,7 @@ intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
1085 return true; 1086 return true;
1086} 1087}
1087 1088
1088static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config) 1089static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
1089{ 1090{
1090 unsigned dotclock = pipe_config->port_clock; 1091 unsigned dotclock = pipe_config->port_clock;
1091 struct dpll *clock = &pipe_config->dpll; 1092 struct dpll *clock = &pipe_config->dpll;
@@ -1112,11 +1113,11 @@ static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config)
1112} 1113}
1113 1114
1114static bool intel_sdvo_compute_config(struct intel_encoder *encoder, 1115static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
1115 struct intel_crtc_config *pipe_config) 1116 struct intel_crtc_state *pipe_config)
1116{ 1117{
1117 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1118 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1118 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 1119 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1119 struct drm_display_mode *mode = &pipe_config->requested_mode; 1120 struct drm_display_mode *mode = &pipe_config->base.mode;
1120 1121
1121 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); 1122 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1122 pipe_config->pipe_bpp = 8*3; 1123 pipe_config->pipe_bpp = 8*3;
@@ -1181,8 +1182,8 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
1181 struct drm_i915_private *dev_priv = dev->dev_private; 1182 struct drm_i915_private *dev_priv = dev->dev_private;
1182 struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc); 1183 struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc);
1183 struct drm_display_mode *adjusted_mode = 1184 struct drm_display_mode *adjusted_mode =
1184 &crtc->config.adjusted_mode; 1185 &crtc->config->base.adjusted_mode;
1185 struct drm_display_mode *mode = &crtc->config.requested_mode; 1186 struct drm_display_mode *mode = &crtc->config->base.mode;
1186 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); 1187 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
1187 u32 sdvox; 1188 u32 sdvox;
1188 struct intel_sdvo_in_out_map in_out; 1189 struct intel_sdvo_in_out_map in_out;
@@ -1224,7 +1225,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
1224 if (!intel_sdvo_set_target_input(intel_sdvo)) 1225 if (!intel_sdvo_set_target_input(intel_sdvo))
1225 return; 1226 return;
1226 1227
1227 if (crtc->config.has_hdmi_sink) { 1228 if (crtc->config->has_hdmi_sink) {
1228 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); 1229 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1229 intel_sdvo_set_colorimetry(intel_sdvo, 1230 intel_sdvo_set_colorimetry(intel_sdvo,
1230 SDVO_COLORIMETRY_RGB256); 1231 SDVO_COLORIMETRY_RGB256);
@@ -1244,7 +1245,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
1244 DRM_INFO("Setting input timings on %s failed\n", 1245 DRM_INFO("Setting input timings on %s failed\n",
1245 SDVO_NAME(intel_sdvo)); 1246 SDVO_NAME(intel_sdvo));
1246 1247
1247 switch (crtc->config.pixel_multiplier) { 1248 switch (crtc->config->pixel_multiplier) {
1248 default: 1249 default:
1249 WARN(1, "unknown pixel mutlipler specified\n"); 1250 WARN(1, "unknown pixel mutlipler specified\n");
1250 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1251 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
@@ -1259,7 +1260,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
1259 /* The real mode polarity is set by the SDVO commands, using 1260 /* The real mode polarity is set by the SDVO commands, using
1260 * struct intel_sdvo_dtd. */ 1261 * struct intel_sdvo_dtd. */
1261 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; 1262 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
1262 if (!HAS_PCH_SPLIT(dev) && crtc->config.limited_color_range) 1263 if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
1263 sdvox |= HDMI_COLOR_RANGE_16_235; 1264 sdvox |= HDMI_COLOR_RANGE_16_235;
1264 if (INTEL_INFO(dev)->gen < 5) 1265 if (INTEL_INFO(dev)->gen < 5)
1265 sdvox |= SDVO_BORDER_ENABLE; 1266 sdvox |= SDVO_BORDER_ENABLE;
@@ -1289,7 +1290,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
1289 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { 1290 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1290 /* done in crtc_mode_set as it lives inside the dpll register */ 1291 /* done in crtc_mode_set as it lives inside the dpll register */
1291 } else { 1292 } else {
1292 sdvox |= (crtc->config.pixel_multiplier - 1) 1293 sdvox |= (crtc->config->pixel_multiplier - 1)
1293 << SDVO_PORT_MULTIPLY_SHIFT; 1294 << SDVO_PORT_MULTIPLY_SHIFT;
1294 } 1295 }
1295 1296
@@ -1338,7 +1339,7 @@ static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1338} 1339}
1339 1340
1340static void intel_sdvo_get_config(struct intel_encoder *encoder, 1341static void intel_sdvo_get_config(struct intel_encoder *encoder,
1341 struct intel_crtc_config *pipe_config) 1342 struct intel_crtc_state *pipe_config)
1342{ 1343{
1343 struct drm_device *dev = encoder->base.dev; 1344 struct drm_device *dev = encoder->base.dev;
1344 struct drm_i915_private *dev_priv = dev->dev_private; 1345 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1370,7 +1371,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
1370 flags |= DRM_MODE_FLAG_NVSYNC; 1371 flags |= DRM_MODE_FLAG_NVSYNC;
1371 } 1372 }
1372 1373
1373 pipe_config->adjusted_mode.flags |= flags; 1374 pipe_config->base.adjusted_mode.flags |= flags;
1374 1375
1375 /* 1376 /*
1376 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in 1377 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
@@ -1392,7 +1393,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
1392 if (HAS_PCH_SPLIT(dev)) 1393 if (HAS_PCH_SPLIT(dev))
1393 ironlake_check_encoder_dotclock(pipe_config, dotclock); 1394 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1394 1395
1395 pipe_config->adjusted_mode.crtc_clock = dotclock; 1396 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1396 1397
1397 /* Cross check the port pixel multiplier with the sdvo encoder state. */ 1398 /* Cross check the port pixel multiplier with the sdvo encoder state. */
1398 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, 1399 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
@@ -2190,7 +2191,9 @@ static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
2190 .detect = intel_sdvo_detect, 2191 .detect = intel_sdvo_detect,
2191 .fill_modes = drm_helper_probe_single_connector_modes, 2192 .fill_modes = drm_helper_probe_single_connector_modes,
2192 .set_property = intel_sdvo_set_property, 2193 .set_property = intel_sdvo_set_property,
2194 .atomic_get_property = intel_connector_atomic_get_property,
2193 .destroy = intel_sdvo_destroy, 2195 .destroy = intel_sdvo_destroy,
2196 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2194}; 2197};
2195 2198
2196static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { 2199static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 01d841ea3140..3c42eeffa3cb 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -75,7 +75,7 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
75 return 0; 75 return 0;
76} 76}
77 77
78u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr) 78u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr)
79{ 79{
80 u32 val = 0; 80 u32 val = 0;
81 81
@@ -89,7 +89,7 @@ u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr)
89 return val; 89 return val;
90} 90}
91 91
92void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val) 92void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val)
93{ 93{
94 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 94 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
95 95
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index dca3f70ef1ba..0a52c44ad03d 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -80,7 +80,7 @@ static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs)
80bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count) 80bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count)
81{ 81{
82 struct drm_device *dev = crtc->base.dev; 82 struct drm_device *dev = crtc->base.dev;
83 const struct drm_display_mode *mode = &crtc->config.adjusted_mode; 83 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
84 enum pipe pipe = crtc->pipe; 84 enum pipe pipe = crtc->pipe;
85 long timeout = msecs_to_jiffies_timeout(1); 85 long timeout = msecs_to_jiffies_timeout(1);
86 int scanline, min, max, vblank_start; 86 int scanline, min, max, vblank_start;
@@ -256,7 +256,7 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
256 default: 256 default:
257 BUG(); 257 BUG();
258 } 258 }
259 if (intel_plane->rotation == BIT(DRM_ROTATE_180)) 259 if (drm_plane->state->rotation == BIT(DRM_ROTATE_180))
260 plane_ctl |= PLANE_CTL_ROTATE_180; 260 plane_ctl |= PLANE_CTL_ROTATE_180;
261 261
262 plane_ctl |= PLANE_CTL_ENABLE; 262 plane_ctl |= PLANE_CTL_ENABLE;
@@ -493,7 +493,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
493 fb->pitches[0]); 493 fb->pitches[0]);
494 linear_offset -= sprsurf_offset; 494 linear_offset -= sprsurf_offset;
495 495
496 if (intel_plane->rotation == BIT(DRM_ROTATE_180)) { 496 if (dplane->state->rotation == BIT(DRM_ROTATE_180)) {
497 sprctl |= SP_ROTATE_180; 497 sprctl |= SP_ROTATE_180;
498 498
499 x += src_w; 499 x += src_w;
@@ -684,7 +684,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
684 pixel_size, fb->pitches[0]); 684 pixel_size, fb->pitches[0]);
685 linear_offset -= sprsurf_offset; 685 linear_offset -= sprsurf_offset;
686 686
687 if (intel_plane->rotation == BIT(DRM_ROTATE_180)) { 687 if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
688 sprctl |= SPRITE_ROTATE_180; 688 sprctl |= SPRITE_ROTATE_180;
689 689
690 /* HSW and BDW does this automagically in hardware */ 690 /* HSW and BDW does this automagically in hardware */
@@ -884,7 +884,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
884 pixel_size, fb->pitches[0]); 884 pixel_size, fb->pitches[0]);
885 linear_offset -= dvssurf_offset; 885 linear_offset -= dvssurf_offset;
886 886
887 if (intel_plane->rotation == BIT(DRM_ROTATE_180)) { 887 if (plane->state->rotation == BIT(DRM_ROTATE_180)) {
888 dvscntr |= DVS_ROTATE_180; 888 dvscntr |= DVS_ROTATE_180;
889 889
890 x += src_w; 890 x += src_w;
@@ -1125,7 +1125,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
1125 min_scale = intel_plane->can_scale ? 1 : (1 << 16); 1125 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
1126 1126
1127 drm_rect_rotate(src, fb->width << 16, fb->height << 16, 1127 drm_rect_rotate(src, fb->width << 16, fb->height << 16,
1128 intel_plane->rotation); 1128 state->base.rotation);
1129 1129
1130 hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale); 1130 hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
1131 BUG_ON(hscale < 0); 1131 BUG_ON(hscale < 0);
@@ -1166,7 +1166,7 @@ intel_check_sprite_plane(struct drm_plane *plane,
1166 drm_rect_height(dst) * vscale - drm_rect_height(src)); 1166 drm_rect_height(dst) * vscale - drm_rect_height(src));
1167 1167
1168 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, 1168 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
1169 intel_plane->rotation); 1169 state->base.rotation);
1170 1170
1171 /* sanity check to make sure the src viewport wasn't enlarged */ 1171 /* sanity check to make sure the src viewport wasn't enlarged */
1172 WARN_ON(src->x1 < (int) state->base.src_x || 1172 WARN_ON(src->x1 < (int) state->base.src_x ||
@@ -1362,33 +1362,6 @@ out_unlock:
1362 return ret; 1362 return ret;
1363} 1363}
1364 1364
1365int intel_plane_set_property(struct drm_plane *plane,
1366 struct drm_property *prop,
1367 uint64_t val)
1368{
1369 struct drm_device *dev = plane->dev;
1370 struct intel_plane *intel_plane = to_intel_plane(plane);
1371 uint64_t old_val;
1372 int ret = -ENOENT;
1373
1374 if (prop == dev->mode_config.rotation_property) {
1375 /* exactly one rotation angle please */
1376 if (hweight32(val & 0xf) != 1)
1377 return -EINVAL;
1378
1379 if (intel_plane->rotation == val)
1380 return 0;
1381
1382 old_val = intel_plane->rotation;
1383 intel_plane->rotation = val;
1384 ret = intel_plane_restore(plane);
1385 if (ret)
1386 intel_plane->rotation = old_val;
1387 }
1388
1389 return ret;
1390}
1391
1392int intel_plane_restore(struct drm_plane *plane) 1365int intel_plane_restore(struct drm_plane *plane)
1393{ 1366{
1394 if (!plane->crtc || !plane->fb) 1367 if (!plane->crtc || !plane->fb)
@@ -1401,15 +1374,6 @@ int intel_plane_restore(struct drm_plane *plane)
1401 plane->state->src_w, plane->state->src_h); 1374 plane->state->src_w, plane->state->src_h);
1402} 1375}
1403 1376
1404static const struct drm_plane_funcs intel_sprite_plane_funcs = {
1405 .update_plane = drm_plane_helper_update,
1406 .disable_plane = drm_plane_helper_disable,
1407 .destroy = intel_plane_destroy,
1408 .set_property = intel_plane_set_property,
1409 .atomic_duplicate_state = intel_plane_duplicate_state,
1410 .atomic_destroy_state = intel_plane_destroy_state,
1411};
1412
1413static uint32_t ilk_plane_formats[] = { 1377static uint32_t ilk_plane_formats[] = {
1414 DRM_FORMAT_XRGB8888, 1378 DRM_FORMAT_XRGB8888,
1415 DRM_FORMAT_YUYV, 1379 DRM_FORMAT_YUYV,
@@ -1457,6 +1421,7 @@ int
1457intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) 1421intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1458{ 1422{
1459 struct intel_plane *intel_plane; 1423 struct intel_plane *intel_plane;
1424 struct intel_plane_state *state;
1460 unsigned long possible_crtcs; 1425 unsigned long possible_crtcs;
1461 const uint32_t *plane_formats; 1426 const uint32_t *plane_formats;
1462 int num_plane_formats; 1427 int num_plane_formats;
@@ -1469,12 +1434,12 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1469 if (!intel_plane) 1434 if (!intel_plane)
1470 return -ENOMEM; 1435 return -ENOMEM;
1471 1436
1472 intel_plane->base.state = 1437 state = intel_create_plane_state(&intel_plane->base);
1473 intel_plane_duplicate_state(&intel_plane->base); 1438 if (!state) {
1474 if (intel_plane->base.state == NULL) {
1475 kfree(intel_plane); 1439 kfree(intel_plane);
1476 return -ENOMEM; 1440 return -ENOMEM;
1477 } 1441 }
1442 intel_plane->base.state = &state->base;
1478 1443
1479 switch (INTEL_INFO(dev)->gen) { 1444 switch (INTEL_INFO(dev)->gen) {
1480 case 5: 1445 case 5:
@@ -1545,12 +1510,11 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1545 1510
1546 intel_plane->pipe = pipe; 1511 intel_plane->pipe = pipe;
1547 intel_plane->plane = plane; 1512 intel_plane->plane = plane;
1548 intel_plane->rotation = BIT(DRM_ROTATE_0);
1549 intel_plane->check_plane = intel_check_sprite_plane; 1513 intel_plane->check_plane = intel_check_sprite_plane;
1550 intel_plane->commit_plane = intel_commit_sprite_plane; 1514 intel_plane->commit_plane = intel_commit_sprite_plane;
1551 possible_crtcs = (1 << pipe); 1515 possible_crtcs = (1 << pipe);
1552 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs, 1516 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1553 &intel_sprite_plane_funcs, 1517 &intel_plane_funcs,
1554 plane_formats, num_plane_formats, 1518 plane_formats, num_plane_formats,
1555 DRM_PLANE_TYPE_OVERLAY); 1519 DRM_PLANE_TYPE_OVERLAY);
1556 if (ret) { 1520 if (ret) {
@@ -1567,7 +1531,7 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
1567 if (dev->mode_config.rotation_property) 1531 if (dev->mode_config.rotation_property)
1568 drm_object_attach_property(&intel_plane->base.base, 1532 drm_object_attach_property(&intel_plane->base.base,
1569 dev->mode_config.rotation_property, 1533 dev->mode_config.rotation_property,
1570 intel_plane->rotation); 1534 state->base.rotation);
1571 1535
1572 drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs); 1536 drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1573 1537
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 6f5f59b880f5..892d23c8479d 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -31,6 +31,7 @@
31 */ 31 */
32 32
33#include <drm/drmP.h> 33#include <drm/drmP.h>
34#include <drm/drm_atomic_helper.h>
34#include <drm/drm_crtc.h> 35#include <drm/drm_crtc.h>
35#include <drm/drm_edid.h> 36#include <drm/drm_edid.h>
36#include "intel_drv.h" 37#include "intel_drv.h"
@@ -908,14 +909,14 @@ intel_tv_mode_valid(struct drm_connector *connector,
908 909
909static void 910static void
910intel_tv_get_config(struct intel_encoder *encoder, 911intel_tv_get_config(struct intel_encoder *encoder,
911 struct intel_crtc_config *pipe_config) 912 struct intel_crtc_state *pipe_config)
912{ 913{
913 pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock; 914 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
914} 915}
915 916
916static bool 917static bool
917intel_tv_compute_config(struct intel_encoder *encoder, 918intel_tv_compute_config(struct intel_encoder *encoder,
918 struct intel_crtc_config *pipe_config) 919 struct intel_crtc_state *pipe_config)
919{ 920{
920 struct intel_tv *intel_tv = enc_to_tv(encoder); 921 struct intel_tv *intel_tv = enc_to_tv(encoder);
921 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv); 922 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
@@ -923,12 +924,12 @@ intel_tv_compute_config(struct intel_encoder *encoder,
923 if (!tv_mode) 924 if (!tv_mode)
924 return false; 925 return false;
925 926
926 pipe_config->adjusted_mode.crtc_clock = tv_mode->clock; 927 pipe_config->base.adjusted_mode.crtc_clock = tv_mode->clock;
927 DRM_DEBUG_KMS("forcing bpc to 8 for TV\n"); 928 DRM_DEBUG_KMS("forcing bpc to 8 for TV\n");
928 pipe_config->pipe_bpp = 8*3; 929 pipe_config->pipe_bpp = 8*3;
929 930
930 /* TV has it's own notion of sync and other mode flags, so clear them. */ 931 /* TV has it's own notion of sync and other mode flags, so clear them. */
931 pipe_config->adjusted_mode.flags = 0; 932 pipe_config->base.adjusted_mode.flags = 0;
932 933
933 /* 934 /*
934 * FIXME: We don't check whether the input mode is actually what we want 935 * FIXME: We don't check whether the input mode is actually what we want
@@ -1512,7 +1513,9 @@ static const struct drm_connector_funcs intel_tv_connector_funcs = {
1512 .detect = intel_tv_detect, 1513 .detect = intel_tv_detect,
1513 .destroy = intel_tv_destroy, 1514 .destroy = intel_tv_destroy,
1514 .set_property = intel_tv_set_property, 1515 .set_property = intel_tv_set_property,
1516 .atomic_get_property = intel_connector_atomic_get_property,
1515 .fill_modes = drm_helper_probe_single_connector_modes, 1517 .fill_modes = drm_helper_probe_single_connector_modes,
1518 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1516}; 1519};
1517 1520
1518static const struct drm_connector_helper_funcs intel_tv_connector_helper_funcs = { 1521static const struct drm_connector_helper_funcs intel_tv_connector_helper_funcs = {
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index e9561de382aa..76b60a3538b2 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -24,6 +24,8 @@
24#include "i915_drv.h" 24#include "i915_drv.h"
25#include "intel_drv.h" 25#include "intel_drv.h"
26 26
27#include <linux/pm_runtime.h>
28
27#define FORCEWAKE_ACK_TIMEOUT_MS 2 29#define FORCEWAKE_ACK_TIMEOUT_MS 2
28 30
29#define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__)) 31#define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
@@ -40,6 +42,26 @@
40 42
41#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__) 43#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
42 44
45static const char * const forcewake_domain_names[] = {
46 "render",
47 "blitter",
48 "media",
49};
50
51const char *
52intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
53{
54 BUILD_BUG_ON((sizeof(forcewake_domain_names)/sizeof(const char *)) !=
55 FW_DOMAIN_ID_COUNT);
56
57 if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
58 return forcewake_domain_names[id];
59
60 WARN_ON(id);
61
62 return "unknown";
63}
64
43static void 65static void
44assert_device_not_suspended(struct drm_i915_private *dev_priv) 66assert_device_not_suspended(struct drm_i915_private *dev_priv)
45{ 67{
@@ -47,73 +69,127 @@ assert_device_not_suspended(struct drm_i915_private *dev_priv)
47 "Device suspended\n"); 69 "Device suspended\n");
48} 70}
49 71
50static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) 72static inline void
73fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
51{ 74{
52 /* w/a for a sporadic read returning 0 by waiting for the GT 75 WARN_ON(d->reg_set == 0);
53 * thread to wake up. 76 __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
54 */
55 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
56 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
57 DRM_ERROR("GT thread status wait timed out\n");
58} 77}
59 78
60static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) 79static inline void
80fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
61{ 81{
62 __raw_i915_write32(dev_priv, FORCEWAKE, 0); 82 mod_timer_pinned(&d->timer, jiffies + 1);
63 /* something from same cacheline, but !FORCEWAKE */
64 __raw_posting_read(dev_priv, ECOBUS);
65} 83}
66 84
67static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, 85static inline void
68 int fw_engine) 86fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
69{ 87{
70 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0, 88 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
89 FORCEWAKE_KERNEL) == 0,
71 FORCEWAKE_ACK_TIMEOUT_MS)) 90 FORCEWAKE_ACK_TIMEOUT_MS))
72 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); 91 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
92 intel_uncore_forcewake_domain_to_str(d->id));
93}
73 94
74 __raw_i915_write32(dev_priv, FORCEWAKE, 1); 95static inline void
75 /* something from same cacheline, but !FORCEWAKE */ 96fw_domain_get(const struct intel_uncore_forcewake_domain *d)
76 __raw_posting_read(dev_priv, ECOBUS); 97{
98 __raw_i915_write32(d->i915, d->reg_set, d->val_set);
99}
77 100
78 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1), 101static inline void
102fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
103{
104 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
105 FORCEWAKE_KERNEL),
79 FORCEWAKE_ACK_TIMEOUT_MS)) 106 FORCEWAKE_ACK_TIMEOUT_MS))
80 DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); 107 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
108 intel_uncore_forcewake_domain_to_str(d->id));
109}
81 110
82 /* WaRsForcewakeWaitTC0:snb */ 111static inline void
83 __gen6_gt_wait_for_thread_c0(dev_priv); 112fw_domain_put(const struct intel_uncore_forcewake_domain *d)
113{
114 __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
84} 115}
85 116
86static void __gen7_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) 117static inline void
118fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
87{ 119{
88 __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); 120 /* something from same cacheline, but not from the set register */
89 /* something from same cacheline, but !FORCEWAKE_MT */ 121 if (d->reg_post)
90 __raw_posting_read(dev_priv, ECOBUS); 122 __raw_posting_read(d->i915, d->reg_post);
91} 123}
92 124
93static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv, 125static void
94 int fw_engine) 126fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
95{ 127{
96 u32 forcewake_ack; 128 struct intel_uncore_forcewake_domain *d;
129 enum forcewake_domain_id id;
97 130
98 if (IS_HASWELL(dev_priv->dev) || IS_BROADWELL(dev_priv->dev)) 131 for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
99 forcewake_ack = FORCEWAKE_ACK_HSW; 132 fw_domain_wait_ack_clear(d);
100 else 133 fw_domain_get(d);
101 forcewake_ack = FORCEWAKE_MT_ACK; 134 fw_domain_wait_ack(d);
135 }
136}
102 137
103 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0, 138static void
104 FORCEWAKE_ACK_TIMEOUT_MS)) 139fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
105 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); 140{
141 struct intel_uncore_forcewake_domain *d;
142 enum forcewake_domain_id id;
106 143
107 __raw_i915_write32(dev_priv, FORCEWAKE_MT, 144 for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
108 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); 145 fw_domain_put(d);
109 /* something from same cacheline, but !FORCEWAKE_MT */ 146 fw_domain_posting_read(d);
110 __raw_posting_read(dev_priv, ECOBUS); 147 }
148}
111 149
112 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL), 150static void
113 FORCEWAKE_ACK_TIMEOUT_MS)) 151fw_domains_posting_read(struct drm_i915_private *dev_priv)
114 DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); 152{
153 struct intel_uncore_forcewake_domain *d;
154 enum forcewake_domain_id id;
155
156 /* No need to do for all, just do for first found */
157 for_each_fw_domain(d, dev_priv, id) {
158 fw_domain_posting_read(d);
159 break;
160 }
161}
115 162
116 /* WaRsForcewakeWaitTC0:ivb,hsw */ 163static void
164fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
165{
166 struct intel_uncore_forcewake_domain *d;
167 enum forcewake_domain_id id;
168
169 WARN_ON(dev_priv->uncore.fw_domains == 0);
170
171 for_each_fw_domain_mask(d, fw_domains, dev_priv, id)
172 fw_domain_reset(d);
173
174 fw_domains_posting_read(dev_priv);
175}
176
177static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
178{
179 /* w/a for a sporadic read returning 0 by waiting for the GT
180 * thread to wake up.
181 */
182 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
183 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
184 DRM_ERROR("GT thread status wait timed out\n");
185}
186
187static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
188 enum forcewake_domains fw_domains)
189{
190 fw_domains_get(dev_priv, fw_domains);
191
192 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
117 __gen6_gt_wait_for_thread_c0(dev_priv); 193 __gen6_gt_wait_for_thread_c0(dev_priv);
118} 194}
119 195
@@ -126,27 +202,13 @@ static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
126 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg); 202 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
127} 203}
128 204
129static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, 205static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
130 int fw_engine) 206 enum forcewake_domains fw_domains)
131{ 207{
132 __raw_i915_write32(dev_priv, FORCEWAKE, 0); 208 fw_domains_put(dev_priv, fw_domains);
133 /* something from same cacheline, but !FORCEWAKE */
134 __raw_posting_read(dev_priv, ECOBUS);
135 gen6_gt_check_fifodbg(dev_priv); 209 gen6_gt_check_fifodbg(dev_priv);
136} 210}
137 211
138static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv,
139 int fw_engine)
140{
141 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
142 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
143 /* something from same cacheline, but !FORCEWAKE_MT */
144 __raw_posting_read(dev_priv, ECOBUS);
145
146 if (IS_GEN7(dev_priv->dev))
147 gen6_gt_check_fifodbg(dev_priv);
148}
149
150static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) 212static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
151{ 213{
152 int ret = 0; 214 int ret = 0;
@@ -174,332 +236,78 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
174 return ret; 236 return ret;
175} 237}
176 238
177static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) 239static void intel_uncore_fw_release_timer(unsigned long arg)
178{
179 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
180 _MASKED_BIT_DISABLE(0xffff));
181 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
182 _MASKED_BIT_DISABLE(0xffff));
183 /* something from same cacheline, but !FORCEWAKE_VLV */
184 __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
185}
186
187static void __vlv_force_wake_get(struct drm_i915_private *dev_priv,
188 int fw_engine)
189{
190 /* Check for Render Engine */
191 if (FORCEWAKE_RENDER & fw_engine) {
192 if (wait_for_atomic((__raw_i915_read32(dev_priv,
193 FORCEWAKE_ACK_VLV) &
194 FORCEWAKE_KERNEL) == 0,
195 FORCEWAKE_ACK_TIMEOUT_MS))
196 DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
197
198 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
199 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
200
201 if (wait_for_atomic((__raw_i915_read32(dev_priv,
202 FORCEWAKE_ACK_VLV) &
203 FORCEWAKE_KERNEL),
204 FORCEWAKE_ACK_TIMEOUT_MS))
205 DRM_ERROR("Timed out: waiting for Render to ack.\n");
206 }
207
208 /* Check for Media Engine */
209 if (FORCEWAKE_MEDIA & fw_engine) {
210 if (wait_for_atomic((__raw_i915_read32(dev_priv,
211 FORCEWAKE_ACK_MEDIA_VLV) &
212 FORCEWAKE_KERNEL) == 0,
213 FORCEWAKE_ACK_TIMEOUT_MS))
214 DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
215
216 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
217 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
218
219 if (wait_for_atomic((__raw_i915_read32(dev_priv,
220 FORCEWAKE_ACK_MEDIA_VLV) &
221 FORCEWAKE_KERNEL),
222 FORCEWAKE_ACK_TIMEOUT_MS))
223 DRM_ERROR("Timed out: waiting for media to ack.\n");
224 }
225}
226
227static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
228 int fw_engine)
229{
230
231 /* Check for Render Engine */
232 if (FORCEWAKE_RENDER & fw_engine)
233 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
234 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
235
236
237 /* Check for Media Engine */
238 if (FORCEWAKE_MEDIA & fw_engine)
239 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
240 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
241
242 /* something from same cacheline, but !FORCEWAKE_VLV */
243 __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
244 if (!IS_CHERRYVIEW(dev_priv->dev))
245 gen6_gt_check_fifodbg(dev_priv);
246}
247
248static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
249{
250 unsigned long irqflags;
251
252 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
253
254 if (fw_engine & FORCEWAKE_RENDER &&
255 dev_priv->uncore.fw_rendercount++ != 0)
256 fw_engine &= ~FORCEWAKE_RENDER;
257 if (fw_engine & FORCEWAKE_MEDIA &&
258 dev_priv->uncore.fw_mediacount++ != 0)
259 fw_engine &= ~FORCEWAKE_MEDIA;
260
261 if (fw_engine)
262 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_engine);
263
264 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
265}
266
267static void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
268{ 240{
241 struct intel_uncore_forcewake_domain *domain = (void *)arg;
269 unsigned long irqflags; 242 unsigned long irqflags;
270 243
271 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 244 assert_device_not_suspended(domain->i915);
272 245
273 if (fw_engine & FORCEWAKE_RENDER) { 246 spin_lock_irqsave(&domain->i915->uncore.lock, irqflags);
274 WARN_ON(!dev_priv->uncore.fw_rendercount); 247 if (WARN_ON(domain->wake_count == 0))
275 if (--dev_priv->uncore.fw_rendercount != 0) 248 domain->wake_count++;
276 fw_engine &= ~FORCEWAKE_RENDER;
277 }
278
279 if (fw_engine & FORCEWAKE_MEDIA) {
280 WARN_ON(!dev_priv->uncore.fw_mediacount);
281 if (--dev_priv->uncore.fw_mediacount != 0)
282 fw_engine &= ~FORCEWAKE_MEDIA;
283 }
284 249
285 if (fw_engine) 250 if (--domain->wake_count == 0)
286 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw_engine); 251 domain->i915->uncore.funcs.force_wake_put(domain->i915,
252 1 << domain->id);
287 253
288 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 254 spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags);
289} 255}
290 256
291static void __gen9_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) 257void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
292{
293 __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
294 _MASKED_BIT_DISABLE(0xffff));
295
296 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
297 _MASKED_BIT_DISABLE(0xffff));
298
299 __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
300 _MASKED_BIT_DISABLE(0xffff));
301}
302
303static void
304__gen9_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
305{
306 /* Check for Render Engine */
307 if (FORCEWAKE_RENDER & fw_engine) {
308 if (wait_for_atomic((__raw_i915_read32(dev_priv,
309 FORCEWAKE_ACK_RENDER_GEN9) &
310 FORCEWAKE_KERNEL) == 0,
311 FORCEWAKE_ACK_TIMEOUT_MS))
312 DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
313
314 __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
315 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
316
317 if (wait_for_atomic((__raw_i915_read32(dev_priv,
318 FORCEWAKE_ACK_RENDER_GEN9) &
319 FORCEWAKE_KERNEL),
320 FORCEWAKE_ACK_TIMEOUT_MS))
321 DRM_ERROR("Timed out: waiting for Render to ack.\n");
322 }
323
324 /* Check for Media Engine */
325 if (FORCEWAKE_MEDIA & fw_engine) {
326 if (wait_for_atomic((__raw_i915_read32(dev_priv,
327 FORCEWAKE_ACK_MEDIA_GEN9) &
328 FORCEWAKE_KERNEL) == 0,
329 FORCEWAKE_ACK_TIMEOUT_MS))
330 DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
331
332 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
333 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
334
335 if (wait_for_atomic((__raw_i915_read32(dev_priv,
336 FORCEWAKE_ACK_MEDIA_GEN9) &
337 FORCEWAKE_KERNEL),
338 FORCEWAKE_ACK_TIMEOUT_MS))
339 DRM_ERROR("Timed out: waiting for Media to ack.\n");
340 }
341
342 /* Check for Blitter Engine */
343 if (FORCEWAKE_BLITTER & fw_engine) {
344 if (wait_for_atomic((__raw_i915_read32(dev_priv,
345 FORCEWAKE_ACK_BLITTER_GEN9) &
346 FORCEWAKE_KERNEL) == 0,
347 FORCEWAKE_ACK_TIMEOUT_MS))
348 DRM_ERROR("Timed out: Blitter forcewake old ack to clear.\n");
349
350 __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
351 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
352
353 if (wait_for_atomic((__raw_i915_read32(dev_priv,
354 FORCEWAKE_ACK_BLITTER_GEN9) &
355 FORCEWAKE_KERNEL),
356 FORCEWAKE_ACK_TIMEOUT_MS))
357 DRM_ERROR("Timed out: waiting for Blitter to ack.\n");
358 }
359}
360
361static void
362__gen9_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
363{
364 /* Check for Render Engine */
365 if (FORCEWAKE_RENDER & fw_engine)
366 __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
367 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
368
369 /* Check for Media Engine */
370 if (FORCEWAKE_MEDIA & fw_engine)
371 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
372 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
373
374 /* Check for Blitter Engine */
375 if (FORCEWAKE_BLITTER & fw_engine)
376 __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
377 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
378}
379
380static void
381gen9_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
382{ 258{
259 struct drm_i915_private *dev_priv = dev->dev_private;
383 unsigned long irqflags; 260 unsigned long irqflags;
261 struct intel_uncore_forcewake_domain *domain;
262 int retry_count = 100;
263 enum forcewake_domain_id id;
264 enum forcewake_domains fw = 0, active_domains;
384 265
385 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 266 /* Hold uncore.lock across reset to prevent any register access
386 267 * with forcewake not set correctly. Wait until all pending
387 if (FORCEWAKE_RENDER & fw_engine) { 268 * timers are run before holding.
388 if (dev_priv->uncore.fw_rendercount++ == 0) 269 */
389 dev_priv->uncore.funcs.force_wake_get(dev_priv, 270 while (1) {
390 FORCEWAKE_RENDER); 271 active_domains = 0;
391 }
392 272
393 if (FORCEWAKE_MEDIA & fw_engine) { 273 for_each_fw_domain(domain, dev_priv, id) {
394 if (dev_priv->uncore.fw_mediacount++ == 0) 274 if (del_timer_sync(&domain->timer) == 0)
395 dev_priv->uncore.funcs.force_wake_get(dev_priv, 275 continue;
396 FORCEWAKE_MEDIA);
397 }
398 276
399 if (FORCEWAKE_BLITTER & fw_engine) { 277 intel_uncore_fw_release_timer((unsigned long)domain);
400 if (dev_priv->uncore.fw_blittercount++ == 0) 278 }
401 dev_priv->uncore.funcs.force_wake_get(dev_priv,
402 FORCEWAKE_BLITTER);
403 }
404 279
405 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 280 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
406}
407 281
408static void 282 for_each_fw_domain(domain, dev_priv, id) {
409gen9_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) 283 if (timer_pending(&domain->timer))
410{ 284 active_domains |= (1 << id);
411 unsigned long irqflags; 285 }
412
413 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
414 286
415 if (FORCEWAKE_RENDER & fw_engine) { 287 if (active_domains == 0)
416 WARN_ON(dev_priv->uncore.fw_rendercount == 0); 288 break;
417 if (--dev_priv->uncore.fw_rendercount == 0)
418 dev_priv->uncore.funcs.force_wake_put(dev_priv,
419 FORCEWAKE_RENDER);
420 }
421 289
422 if (FORCEWAKE_MEDIA & fw_engine) { 290 if (--retry_count == 0) {
423 WARN_ON(dev_priv->uncore.fw_mediacount == 0); 291 DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
424 if (--dev_priv->uncore.fw_mediacount == 0) 292 break;
425 dev_priv->uncore.funcs.force_wake_put(dev_priv, 293 }
426 FORCEWAKE_MEDIA);
427 }
428 294
429 if (FORCEWAKE_BLITTER & fw_engine) { 295 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
430 WARN_ON(dev_priv->uncore.fw_blittercount == 0); 296 cond_resched();
431 if (--dev_priv->uncore.fw_blittercount == 0)
432 dev_priv->uncore.funcs.force_wake_put(dev_priv,
433 FORCEWAKE_BLITTER);
434 } 297 }
435 298
436 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 299 WARN_ON(active_domains);
437}
438
439static void gen6_force_wake_timer(unsigned long arg)
440{
441 struct drm_i915_private *dev_priv = (void *)arg;
442 unsigned long irqflags;
443
444 assert_device_not_suspended(dev_priv);
445
446 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
447 WARN_ON(!dev_priv->uncore.forcewake_count);
448
449 if (--dev_priv->uncore.forcewake_count == 0)
450 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
451 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
452
453 intel_runtime_pm_put(dev_priv);
454}
455
456void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
457{
458 struct drm_i915_private *dev_priv = dev->dev_private;
459 unsigned long irqflags;
460
461 if (del_timer_sync(&dev_priv->uncore.force_wake_timer))
462 gen6_force_wake_timer((unsigned long)dev_priv);
463
464 /* Hold uncore.lock across reset to prevent any register access
465 * with forcewake not set correctly
466 */
467 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
468 300
469 if (IS_VALLEYVIEW(dev)) 301 for_each_fw_domain(domain, dev_priv, id)
470 vlv_force_wake_reset(dev_priv); 302 if (domain->wake_count)
471 else if (IS_GEN6(dev) || IS_GEN7(dev)) 303 fw |= 1 << id;
472 __gen6_gt_force_wake_reset(dev_priv);
473 304
474 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) 305 if (fw)
475 __gen7_gt_force_wake_mt_reset(dev_priv); 306 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
476 307
477 if (IS_GEN9(dev)) 308 fw_domains_reset(dev_priv, FORCEWAKE_ALL);
478 __gen9_gt_force_wake_mt_reset(dev_priv);
479 309
480 if (restore) { /* If reset with a user forcewake, try to restore */ 310 if (restore) { /* If reset with a user forcewake, try to restore */
481 unsigned fw = 0;
482
483 if (IS_VALLEYVIEW(dev)) {
484 if (dev_priv->uncore.fw_rendercount)
485 fw |= FORCEWAKE_RENDER;
486
487 if (dev_priv->uncore.fw_mediacount)
488 fw |= FORCEWAKE_MEDIA;
489 } else if (IS_GEN9(dev)) {
490 if (dev_priv->uncore.fw_rendercount)
491 fw |= FORCEWAKE_RENDER;
492
493 if (dev_priv->uncore.fw_mediacount)
494 fw |= FORCEWAKE_MEDIA;
495
496 if (dev_priv->uncore.fw_blittercount)
497 fw |= FORCEWAKE_BLITTER;
498 } else {
499 if (dev_priv->uncore.forcewake_count)
500 fw = FORCEWAKE_ALL;
501 }
502
503 if (fw) 311 if (fw)
504 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw); 312 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
505 313
@@ -509,17 +317,16 @@ void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
509 GT_FIFO_FREE_ENTRIES_MASK; 317 GT_FIFO_FREE_ENTRIES_MASK;
510 } 318 }
511 319
320 if (!restore)
321 assert_forcewakes_inactive(dev_priv);
322
512 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 323 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
513} 324}
514 325
515static void __intel_uncore_early_sanitize(struct drm_device *dev, 326static void intel_uncore_ellc_detect(struct drm_device *dev)
516 bool restore_forcewake)
517{ 327{
518 struct drm_i915_private *dev_priv = dev->dev_private; 328 struct drm_i915_private *dev_priv = dev->dev_private;
519 329
520 if (HAS_FPGA_DBG_UNCLAIMED(dev))
521 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
522
523 if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && 330 if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
524 (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) { 331 (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
525 /* The docs do not explain exactly how the calculation can be 332 /* The docs do not explain exactly how the calculation can be
@@ -530,6 +337,15 @@ static void __intel_uncore_early_sanitize(struct drm_device *dev,
530 dev_priv->ellc_size = 128; 337 dev_priv->ellc_size = 128;
531 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size); 338 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
532 } 339 }
340}
341
342static void __intel_uncore_early_sanitize(struct drm_device *dev,
343 bool restore_forcewake)
344{
345 struct drm_i915_private *dev_priv = dev->dev_private;
346
347 if (HAS_FPGA_DBG_UNCLAIMED(dev))
348 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
533 349
534 /* clear out old GT FIFO errors */ 350 /* clear out old GT FIFO errors */
535 if (IS_GEN6(dev) || IS_GEN7(dev)) 351 if (IS_GEN6(dev) || IS_GEN7(dev))
@@ -551,81 +367,92 @@ void intel_uncore_sanitize(struct drm_device *dev)
551 intel_disable_gt_powersave(dev); 367 intel_disable_gt_powersave(dev);
552} 368}
553 369
554/* 370/**
555 * Generally this is called implicitly by the register read function. However, 371 * intel_uncore_forcewake_get - grab forcewake domain references
556 * if some sequence requires the GT to not power down then this function should 372 * @dev_priv: i915 device instance
557 * be called at the beginning of the sequence followed by a call to 373 * @fw_domains: forcewake domains to get reference on
558 * gen6_gt_force_wake_put() at the end of the sequence. 374 *
375 * This function can be used get GT's forcewake domain references.
376 * Normal register access will handle the forcewake domains automatically.
377 * However if some sequence requires the GT to not power down a particular
378 * forcewake domains this function should be called at the beginning of the
379 * sequence. And subsequently the reference should be dropped by symmetric
380 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
381 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
559 */ 382 */
560void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) 383void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
384 enum forcewake_domains fw_domains)
561{ 385{
562 unsigned long irqflags; 386 unsigned long irqflags;
387 struct intel_uncore_forcewake_domain *domain;
388 enum forcewake_domain_id id;
563 389
564 if (!dev_priv->uncore.funcs.force_wake_get) 390 if (!dev_priv->uncore.funcs.force_wake_get)
565 return; 391 return;
566 392
567 intel_runtime_pm_get(dev_priv); 393 WARN_ON(dev_priv->pm.suspended);
568
569 /* Redirect to Gen9 specific routine */
570 if (IS_GEN9(dev_priv->dev))
571 return gen9_force_wake_get(dev_priv, fw_engine);
572 394
573 /* Redirect to VLV specific routine */ 395 fw_domains &= dev_priv->uncore.fw_domains;
574 if (IS_VALLEYVIEW(dev_priv->dev))
575 return vlv_force_wake_get(dev_priv, fw_engine);
576 396
577 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 397 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
578 if (dev_priv->uncore.forcewake_count++ == 0) 398
579 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); 399 for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
400 if (domain->wake_count++)
401 fw_domains &= ~(1 << id);
402 }
403
404 if (fw_domains)
405 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
406
580 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 407 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
581} 408}
582 409
583/* 410/**
584 * see gen6_gt_force_wake_get() 411 * intel_uncore_forcewake_put - release a forcewake domain reference
412 * @dev_priv: i915 device instance
413 * @fw_domains: forcewake domains to put references
414 *
415 * This function drops the device-level forcewakes for specified
416 * domains obtained by intel_uncore_forcewake_get().
585 */ 417 */
586void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) 418void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
419 enum forcewake_domains fw_domains)
587{ 420{
588 unsigned long irqflags; 421 unsigned long irqflags;
589 bool delayed = false; 422 struct intel_uncore_forcewake_domain *domain;
423 enum forcewake_domain_id id;
590 424
591 if (!dev_priv->uncore.funcs.force_wake_put) 425 if (!dev_priv->uncore.funcs.force_wake_put)
592 return; 426 return;
593 427
594 /* Redirect to Gen9 specific routine */ 428 fw_domains &= dev_priv->uncore.fw_domains;
595 if (IS_GEN9(dev_priv->dev)) {
596 gen9_force_wake_put(dev_priv, fw_engine);
597 goto out;
598 }
599 429
600 /* Redirect to VLV specific routine */ 430 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
601 if (IS_VALLEYVIEW(dev_priv->dev)) {
602 vlv_force_wake_put(dev_priv, fw_engine);
603 goto out;
604 }
605 431
432 for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
433 if (WARN_ON(domain->wake_count == 0))
434 continue;
606 435
607 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 436 if (--domain->wake_count)
608 WARN_ON(!dev_priv->uncore.forcewake_count); 437 continue;
609 438
610 if (--dev_priv->uncore.forcewake_count == 0) { 439 domain->wake_count++;
611 dev_priv->uncore.forcewake_count++; 440 fw_domain_arm_timer(domain);
612 delayed = true;
613 mod_timer_pinned(&dev_priv->uncore.force_wake_timer,
614 jiffies + 1);
615 } 441 }
616 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
617 442
618out: 443 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
619 if (!delayed)
620 intel_runtime_pm_put(dev_priv);
621} 444}
622 445
623void assert_force_wake_inactive(struct drm_i915_private *dev_priv) 446void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
624{ 447{
448 struct intel_uncore_forcewake_domain *domain;
449 enum forcewake_domain_id id;
450
625 if (!dev_priv->uncore.funcs.force_wake_get) 451 if (!dev_priv->uncore.funcs.force_wake_get)
626 return; 452 return;
627 453
628 WARN_ON(dev_priv->uncore.forcewake_count > 0); 454 for_each_fw_domain(domain, dev_priv, id)
455 WARN_ON(domain->wake_count);
629} 456}
630 457
631/* We give fast paths for the really cool registers */ 458/* We give fast paths for the really cool registers */
@@ -737,96 +564,118 @@ hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
737 } 564 }
738} 565}
739 566
740#define REG_READ_HEADER(x) \ 567#define GEN2_READ_HEADER(x) \
741 unsigned long irqflags; \
742 u##x val = 0; \ 568 u##x val = 0; \
743 assert_device_not_suspended(dev_priv); \ 569 assert_device_not_suspended(dev_priv);
744 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
745 570
746#define REG_READ_FOOTER \ 571#define GEN2_READ_FOOTER \
747 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
748 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 572 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
749 return val 573 return val
750 574
751#define __gen4_read(x) \ 575#define __gen2_read(x) \
752static u##x \ 576static u##x \
753gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ 577gen2_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
754 REG_READ_HEADER(x); \ 578 GEN2_READ_HEADER(x); \
755 val = __raw_i915_read##x(dev_priv, reg); \ 579 val = __raw_i915_read##x(dev_priv, reg); \
756 REG_READ_FOOTER; \ 580 GEN2_READ_FOOTER; \
757} 581}
758 582
759#define __gen5_read(x) \ 583#define __gen5_read(x) \
760static u##x \ 584static u##x \
761gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ 585gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
762 REG_READ_HEADER(x); \ 586 GEN2_READ_HEADER(x); \
763 ilk_dummy_write(dev_priv); \ 587 ilk_dummy_write(dev_priv); \
764 val = __raw_i915_read##x(dev_priv, reg); \ 588 val = __raw_i915_read##x(dev_priv, reg); \
765 REG_READ_FOOTER; \ 589 GEN2_READ_FOOTER; \
590}
591
592__gen5_read(8)
593__gen5_read(16)
594__gen5_read(32)
595__gen5_read(64)
596__gen2_read(8)
597__gen2_read(16)
598__gen2_read(32)
599__gen2_read(64)
600
601#undef __gen5_read
602#undef __gen2_read
603
604#undef GEN2_READ_FOOTER
605#undef GEN2_READ_HEADER
606
607#define GEN6_READ_HEADER(x) \
608 unsigned long irqflags; \
609 u##x val = 0; \
610 assert_device_not_suspended(dev_priv); \
611 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
612
613#define GEN6_READ_FOOTER \
614 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
615 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
616 return val
617
618static inline void __force_wake_get(struct drm_i915_private *dev_priv,
619 enum forcewake_domains fw_domains)
620{
621 struct intel_uncore_forcewake_domain *domain;
622 enum forcewake_domain_id id;
623
624 if (WARN_ON(!fw_domains))
625 return;
626
627 /* Ideally GCC would be constant-fold and eliminate this loop */
628 for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
629 if (domain->wake_count) {
630 fw_domains &= ~(1 << id);
631 continue;
632 }
633
634 domain->wake_count++;
635 fw_domain_arm_timer(domain);
636 }
637
638 if (fw_domains)
639 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
766} 640}
767 641
768#define __gen6_read(x) \ 642#define __gen6_read(x) \
769static u##x \ 643static u##x \
770gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ 644gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
771 REG_READ_HEADER(x); \ 645 GEN6_READ_HEADER(x); \
772 hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \ 646 hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
773 if (dev_priv->uncore.forcewake_count == 0 && \ 647 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) \
774 NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ 648 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
775 dev_priv->uncore.funcs.force_wake_get(dev_priv, \ 649 val = __raw_i915_read##x(dev_priv, reg); \
776 FORCEWAKE_ALL); \
777 val = __raw_i915_read##x(dev_priv, reg); \
778 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
779 FORCEWAKE_ALL); \
780 } else { \
781 val = __raw_i915_read##x(dev_priv, reg); \
782 } \
783 hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \ 650 hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
784 REG_READ_FOOTER; \ 651 GEN6_READ_FOOTER; \
785} 652}
786 653
787#define __vlv_read(x) \ 654#define __vlv_read(x) \
788static u##x \ 655static u##x \
789vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ 656vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
790 unsigned fwengine = 0; \ 657 GEN6_READ_HEADER(x); \
791 REG_READ_HEADER(x); \ 658 if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) \
792 if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \ 659 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
793 if (dev_priv->uncore.fw_rendercount == 0) \ 660 else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) \
794 fwengine = FORCEWAKE_RENDER; \ 661 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
795 } else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \
796 if (dev_priv->uncore.fw_mediacount == 0) \
797 fwengine = FORCEWAKE_MEDIA; \
798 } \
799 if (fwengine) \
800 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
801 val = __raw_i915_read##x(dev_priv, reg); \ 662 val = __raw_i915_read##x(dev_priv, reg); \
802 if (fwengine) \ 663 GEN6_READ_FOOTER; \
803 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
804 REG_READ_FOOTER; \
805} 664}
806 665
807#define __chv_read(x) \ 666#define __chv_read(x) \
808static u##x \ 667static u##x \
809chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ 668chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
810 unsigned fwengine = 0; \ 669 GEN6_READ_HEADER(x); \
811 REG_READ_HEADER(x); \ 670 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
812 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \ 671 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
813 if (dev_priv->uncore.fw_rendercount == 0) \ 672 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
814 fwengine = FORCEWAKE_RENDER; \ 673 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
815 } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ 674 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
816 if (dev_priv->uncore.fw_mediacount == 0) \ 675 __force_wake_get(dev_priv, \
817 fwengine = FORCEWAKE_MEDIA; \ 676 FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \
818 } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
819 if (dev_priv->uncore.fw_rendercount == 0) \
820 fwengine |= FORCEWAKE_RENDER; \
821 if (dev_priv->uncore.fw_mediacount == 0) \
822 fwengine |= FORCEWAKE_MEDIA; \
823 } \
824 if (fwengine) \
825 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
826 val = __raw_i915_read##x(dev_priv, reg); \ 677 val = __raw_i915_read##x(dev_priv, reg); \
827 if (fwengine) \ 678 GEN6_READ_FOOTER; \
828 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
829 REG_READ_FOOTER; \
830} 679}
831 680
832#define SKL_NEEDS_FORCE_WAKE(dev_priv, reg) \ 681#define SKL_NEEDS_FORCE_WAKE(dev_priv, reg) \
@@ -835,33 +684,22 @@ chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
835#define __gen9_read(x) \ 684#define __gen9_read(x) \
836static u##x \ 685static u##x \
837gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ 686gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
838 REG_READ_HEADER(x); \ 687 enum forcewake_domains fw_engine; \
839 if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ 688 GEN6_READ_HEADER(x); \
840 val = __raw_i915_read##x(dev_priv, reg); \ 689 if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg))) \
841 } else { \ 690 fw_engine = 0; \
842 unsigned fwengine = 0; \ 691 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
843 if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) { \ 692 fw_engine = FORCEWAKE_RENDER; \
844 if (dev_priv->uncore.fw_rendercount == 0) \ 693 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
845 fwengine = FORCEWAKE_RENDER; \ 694 fw_engine = FORCEWAKE_MEDIA; \
846 } else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) { \ 695 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
847 if (dev_priv->uncore.fw_mediacount == 0) \ 696 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
848 fwengine = FORCEWAKE_MEDIA; \ 697 else \
849 } else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) { \ 698 fw_engine = FORCEWAKE_BLITTER; \
850 if (dev_priv->uncore.fw_rendercount == 0) \ 699 if (fw_engine) \
851 fwengine |= FORCEWAKE_RENDER; \ 700 __force_wake_get(dev_priv, fw_engine); \
852 if (dev_priv->uncore.fw_mediacount == 0) \ 701 val = __raw_i915_read##x(dev_priv, reg); \
853 fwengine |= FORCEWAKE_MEDIA; \ 702 GEN6_READ_FOOTER; \
854 } else { \
855 if (dev_priv->uncore.fw_blittercount == 0) \
856 fwengine = FORCEWAKE_BLITTER; \
857 } \
858 if (fwengine) \
859 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
860 val = __raw_i915_read##x(dev_priv, reg); \
861 if (fwengine) \
862 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
863 } \
864 REG_READ_FOOTER; \
865} 703}
866 704
867__gen9_read(8) 705__gen9_read(8)
@@ -880,55 +718,66 @@ __gen6_read(8)
880__gen6_read(16) 718__gen6_read(16)
881__gen6_read(32) 719__gen6_read(32)
882__gen6_read(64) 720__gen6_read(64)
883__gen5_read(8)
884__gen5_read(16)
885__gen5_read(32)
886__gen5_read(64)
887__gen4_read(8)
888__gen4_read(16)
889__gen4_read(32)
890__gen4_read(64)
891 721
892#undef __gen9_read 722#undef __gen9_read
893#undef __chv_read 723#undef __chv_read
894#undef __vlv_read 724#undef __vlv_read
895#undef __gen6_read 725#undef __gen6_read
896#undef __gen5_read 726#undef GEN6_READ_FOOTER
897#undef __gen4_read 727#undef GEN6_READ_HEADER
898#undef REG_READ_FOOTER
899#undef REG_READ_HEADER
900 728
901#define REG_WRITE_HEADER \ 729#define GEN2_WRITE_HEADER \
902 unsigned long irqflags; \
903 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 730 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
904 assert_device_not_suspended(dev_priv); \ 731 assert_device_not_suspended(dev_priv); \
905 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
906 732
907#define REG_WRITE_FOOTER \ 733#define GEN2_WRITE_FOOTER
908 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
909 734
910#define __gen4_write(x) \ 735#define __gen2_write(x) \
911static void \ 736static void \
912gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ 737gen2_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
913 REG_WRITE_HEADER; \ 738 GEN2_WRITE_HEADER; \
914 __raw_i915_write##x(dev_priv, reg, val); \ 739 __raw_i915_write##x(dev_priv, reg, val); \
915 REG_WRITE_FOOTER; \ 740 GEN2_WRITE_FOOTER; \
916} 741}
917 742
918#define __gen5_write(x) \ 743#define __gen5_write(x) \
919static void \ 744static void \
920gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ 745gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
921 REG_WRITE_HEADER; \ 746 GEN2_WRITE_HEADER; \
922 ilk_dummy_write(dev_priv); \ 747 ilk_dummy_write(dev_priv); \
923 __raw_i915_write##x(dev_priv, reg, val); \ 748 __raw_i915_write##x(dev_priv, reg, val); \
924 REG_WRITE_FOOTER; \ 749 GEN2_WRITE_FOOTER; \
925} 750}
926 751
752__gen5_write(8)
753__gen5_write(16)
754__gen5_write(32)
755__gen5_write(64)
756__gen2_write(8)
757__gen2_write(16)
758__gen2_write(32)
759__gen2_write(64)
760
761#undef __gen5_write
762#undef __gen2_write
763
764#undef GEN2_WRITE_FOOTER
765#undef GEN2_WRITE_HEADER
766
767#define GEN6_WRITE_HEADER \
768 unsigned long irqflags; \
769 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
770 assert_device_not_suspended(dev_priv); \
771 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
772
773#define GEN6_WRITE_FOOTER \
774 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
775
927#define __gen6_write(x) \ 776#define __gen6_write(x) \
928static void \ 777static void \
929gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ 778gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
930 u32 __fifo_ret = 0; \ 779 u32 __fifo_ret = 0; \
931 REG_WRITE_HEADER; \ 780 GEN6_WRITE_HEADER; \
932 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ 781 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
933 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ 782 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
934 } \ 783 } \
@@ -936,14 +785,14 @@ gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
936 if (unlikely(__fifo_ret)) { \ 785 if (unlikely(__fifo_ret)) { \
937 gen6_gt_check_fifodbg(dev_priv); \ 786 gen6_gt_check_fifodbg(dev_priv); \
938 } \ 787 } \
939 REG_WRITE_FOOTER; \ 788 GEN6_WRITE_FOOTER; \
940} 789}
941 790
942#define __hsw_write(x) \ 791#define __hsw_write(x) \
943static void \ 792static void \
944hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ 793hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
945 u32 __fifo_ret = 0; \ 794 u32 __fifo_ret = 0; \
946 REG_WRITE_HEADER; \ 795 GEN6_WRITE_HEADER; \
947 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ 796 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
948 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ 797 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
949 } \ 798 } \
@@ -954,7 +803,7 @@ hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace)
954 } \ 803 } \
955 hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \ 804 hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
956 hsw_unclaimed_reg_detect(dev_priv); \ 805 hsw_unclaimed_reg_detect(dev_priv); \
957 REG_WRITE_FOOTER; \ 806 GEN6_WRITE_FOOTER; \
958} 807}
959 808
960static const u32 gen8_shadowed_regs[] = { 809static const u32 gen8_shadowed_regs[] = {
@@ -981,50 +830,31 @@ static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
981#define __gen8_write(x) \ 830#define __gen8_write(x) \
982static void \ 831static void \
983gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ 832gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
984 REG_WRITE_HEADER; \ 833 GEN6_WRITE_HEADER; \
985 hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \ 834 hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
986 if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \ 835 if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) \
987 if (dev_priv->uncore.forcewake_count == 0) \ 836 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
988 dev_priv->uncore.funcs.force_wake_get(dev_priv, \ 837 __raw_i915_write##x(dev_priv, reg, val); \
989 FORCEWAKE_ALL); \
990 __raw_i915_write##x(dev_priv, reg, val); \
991 if (dev_priv->uncore.forcewake_count == 0) \
992 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
993 FORCEWAKE_ALL); \
994 } else { \
995 __raw_i915_write##x(dev_priv, reg, val); \
996 } \
997 hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \ 838 hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
998 hsw_unclaimed_reg_detect(dev_priv); \ 839 hsw_unclaimed_reg_detect(dev_priv); \
999 REG_WRITE_FOOTER; \ 840 GEN6_WRITE_FOOTER; \
1000} 841}
1001 842
1002#define __chv_write(x) \ 843#define __chv_write(x) \
1003static void \ 844static void \
1004chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ 845chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
1005 unsigned fwengine = 0; \
1006 bool shadowed = is_gen8_shadowed(dev_priv, reg); \ 846 bool shadowed = is_gen8_shadowed(dev_priv, reg); \
1007 REG_WRITE_HEADER; \ 847 GEN6_WRITE_HEADER; \
1008 if (!shadowed) { \ 848 if (!shadowed) { \
1009 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \ 849 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
1010 if (dev_priv->uncore.fw_rendercount == 0) \ 850 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
1011 fwengine = FORCEWAKE_RENDER; \ 851 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
1012 } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ 852 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
1013 if (dev_priv->uncore.fw_mediacount == 0) \ 853 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
1014 fwengine = FORCEWAKE_MEDIA; \ 854 __force_wake_get(dev_priv, FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \
1015 } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
1016 if (dev_priv->uncore.fw_rendercount == 0) \
1017 fwengine |= FORCEWAKE_RENDER; \
1018 if (dev_priv->uncore.fw_mediacount == 0) \
1019 fwengine |= FORCEWAKE_MEDIA; \
1020 } \
1021 } \ 855 } \
1022 if (fwengine) \
1023 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
1024 __raw_i915_write##x(dev_priv, reg, val); \ 856 __raw_i915_write##x(dev_priv, reg, val); \
1025 if (fwengine) \ 857 GEN6_WRITE_FOOTER; \
1026 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
1027 REG_WRITE_FOOTER; \
1028} 858}
1029 859
1030static const u32 gen9_shadowed_regs[] = { 860static const u32 gen9_shadowed_regs[] = {
@@ -1054,36 +884,23 @@ static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg)
1054static void \ 884static void \
1055gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \ 885gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
1056 bool trace) { \ 886 bool trace) { \
1057 REG_WRITE_HEADER; \ 887 enum forcewake_domains fw_engine; \
1058 if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \ 888 GEN6_WRITE_HEADER; \
1059 is_gen9_shadowed(dev_priv, reg)) { \ 889 if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \
1060 __raw_i915_write##x(dev_priv, reg, val); \ 890 is_gen9_shadowed(dev_priv, reg)) \
1061 } else { \ 891 fw_engine = 0; \
1062 unsigned fwengine = 0; \ 892 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
1063 if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) { \ 893 fw_engine = FORCEWAKE_RENDER; \
1064 if (dev_priv->uncore.fw_rendercount == 0) \ 894 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
1065 fwengine = FORCEWAKE_RENDER; \ 895 fw_engine = FORCEWAKE_MEDIA; \
1066 } else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) { \ 896 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
1067 if (dev_priv->uncore.fw_mediacount == 0) \ 897 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
1068 fwengine = FORCEWAKE_MEDIA; \ 898 else \
1069 } else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) { \ 899 fw_engine = FORCEWAKE_BLITTER; \
1070 if (dev_priv->uncore.fw_rendercount == 0) \ 900 if (fw_engine) \
1071 fwengine |= FORCEWAKE_RENDER; \ 901 __force_wake_get(dev_priv, fw_engine); \
1072 if (dev_priv->uncore.fw_mediacount == 0) \ 902 __raw_i915_write##x(dev_priv, reg, val); \
1073 fwengine |= FORCEWAKE_MEDIA; \ 903 GEN6_WRITE_FOOTER; \
1074 } else { \
1075 if (dev_priv->uncore.fw_blittercount == 0) \
1076 fwengine = FORCEWAKE_BLITTER; \
1077 } \
1078 if (fwengine) \
1079 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
1080 fwengine); \
1081 __raw_i915_write##x(dev_priv, reg, val); \
1082 if (fwengine) \
1083 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
1084 fwengine); \
1085 } \
1086 REG_WRITE_FOOTER; \
1087} 904}
1088 905
1089__gen9_write(8) 906__gen9_write(8)
@@ -1106,24 +923,14 @@ __gen6_write(8)
1106__gen6_write(16) 923__gen6_write(16)
1107__gen6_write(32) 924__gen6_write(32)
1108__gen6_write(64) 925__gen6_write(64)
1109__gen5_write(8)
1110__gen5_write(16)
1111__gen5_write(32)
1112__gen5_write(64)
1113__gen4_write(8)
1114__gen4_write(16)
1115__gen4_write(32)
1116__gen4_write(64)
1117 926
1118#undef __gen9_write 927#undef __gen9_write
1119#undef __chv_write 928#undef __chv_write
1120#undef __gen8_write 929#undef __gen8_write
1121#undef __hsw_write 930#undef __hsw_write
1122#undef __gen6_write 931#undef __gen6_write
1123#undef __gen5_write 932#undef GEN6_WRITE_FOOTER
1124#undef __gen4_write 933#undef GEN6_WRITE_HEADER
1125#undef REG_WRITE_FOOTER
1126#undef REG_WRITE_HEADER
1127 934
1128#define ASSIGN_WRITE_MMIO_VFUNCS(x) \ 935#define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1129do { \ 936do { \
@@ -1141,24 +948,83 @@ do { \
1141 dev_priv->uncore.funcs.mmio_readq = x##_read64; \ 948 dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1142} while (0) 949} while (0)
1143 950
1144void intel_uncore_init(struct drm_device *dev) 951
952static void fw_domain_init(struct drm_i915_private *dev_priv,
953 enum forcewake_domain_id domain_id,
954 u32 reg_set, u32 reg_ack)
1145{ 955{
1146 struct drm_i915_private *dev_priv = dev->dev_private; 956 struct intel_uncore_forcewake_domain *d;
1147 957
1148 setup_timer(&dev_priv->uncore.force_wake_timer, 958 if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1149 gen6_force_wake_timer, (unsigned long)dev_priv); 959 return;
1150 960
1151 __intel_uncore_early_sanitize(dev, false); 961 d = &dev_priv->uncore.fw_domain[domain_id];
962
963 WARN_ON(d->wake_count);
964
965 d->wake_count = 0;
966 d->reg_set = reg_set;
967 d->reg_ack = reg_ack;
968
969 if (IS_GEN6(dev_priv)) {
970 d->val_reset = 0;
971 d->val_set = FORCEWAKE_KERNEL;
972 d->val_clear = 0;
973 } else {
974 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
975 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
976 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
977 }
978
979 if (IS_VALLEYVIEW(dev_priv))
980 d->reg_post = FORCEWAKE_ACK_VLV;
981 else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
982 d->reg_post = ECOBUS;
983 else
984 d->reg_post = 0;
985
986 d->i915 = dev_priv;
987 d->id = domain_id;
988
989 setup_timer(&d->timer, intel_uncore_fw_release_timer, (unsigned long)d);
990
991 dev_priv->uncore.fw_domains |= (1 << domain_id);
992
993 fw_domain_reset(d);
994}
995
996static void intel_uncore_fw_domains_init(struct drm_device *dev)
997{
998 struct drm_i915_private *dev_priv = dev->dev_private;
1152 999
1153 if (IS_GEN9(dev)) { 1000 if (IS_GEN9(dev)) {
1154 dev_priv->uncore.funcs.force_wake_get = __gen9_force_wake_get; 1001 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1155 dev_priv->uncore.funcs.force_wake_put = __gen9_force_wake_put; 1002 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1003 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1004 FORCEWAKE_RENDER_GEN9,
1005 FORCEWAKE_ACK_RENDER_GEN9);
1006 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1007 FORCEWAKE_BLITTER_GEN9,
1008 FORCEWAKE_ACK_BLITTER_GEN9);
1009 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1010 FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1156 } else if (IS_VALLEYVIEW(dev)) { 1011 } else if (IS_VALLEYVIEW(dev)) {
1157 dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get; 1012 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1158 dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put; 1013 if (!IS_CHERRYVIEW(dev))
1014 dev_priv->uncore.funcs.force_wake_put =
1015 fw_domains_put_with_fifo;
1016 else
1017 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1018 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1019 FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1020 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1021 FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1159 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 1022 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1160 dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get; 1023 dev_priv->uncore.funcs.force_wake_get =
1161 dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put; 1024 fw_domains_get_with_thread_status;
1025 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1026 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1027 FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1162 } else if (IS_IVYBRIDGE(dev)) { 1028 } else if (IS_IVYBRIDGE(dev)) {
1163 u32 ecobus; 1029 u32 ecobus;
1164 1030
@@ -1171,31 +1037,47 @@ void intel_uncore_init(struct drm_device *dev)
1171 * (correctly) interpreted by the test below as MT 1037 * (correctly) interpreted by the test below as MT
1172 * forcewake being disabled. 1038 * forcewake being disabled.
1173 */ 1039 */
1040 dev_priv->uncore.funcs.force_wake_get =
1041 fw_domains_get_with_thread_status;
1042 dev_priv->uncore.funcs.force_wake_put =
1043 fw_domains_put_with_fifo;
1044
1045 /* We need to init first for ECOBUS access and then
1046 * determine later if we want to reinit, in case of MT access is
1047 * not working
1048 */
1049 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1050 FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1051
1174 mutex_lock(&dev->struct_mutex); 1052 mutex_lock(&dev->struct_mutex);
1175 __gen7_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL); 1053 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1176 ecobus = __raw_i915_read32(dev_priv, ECOBUS); 1054 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1177 __gen7_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL); 1055 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1178 mutex_unlock(&dev->struct_mutex); 1056 mutex_unlock(&dev->struct_mutex);
1179 1057
1180 if (ecobus & FORCEWAKE_MT_ENABLE) { 1058 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1181 dev_priv->uncore.funcs.force_wake_get =
1182 __gen7_gt_force_wake_mt_get;
1183 dev_priv->uncore.funcs.force_wake_put =
1184 __gen7_gt_force_wake_mt_put;
1185 } else {
1186 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); 1059 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1187 DRM_INFO("when using vblank-synced partial screen updates.\n"); 1060 DRM_INFO("when using vblank-synced partial screen updates.\n");
1188 dev_priv->uncore.funcs.force_wake_get = 1061 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1189 __gen6_gt_force_wake_get; 1062 FORCEWAKE, FORCEWAKE_ACK);
1190 dev_priv->uncore.funcs.force_wake_put =
1191 __gen6_gt_force_wake_put;
1192 } 1063 }
1193 } else if (IS_GEN6(dev)) { 1064 } else if (IS_GEN6(dev)) {
1194 dev_priv->uncore.funcs.force_wake_get = 1065 dev_priv->uncore.funcs.force_wake_get =
1195 __gen6_gt_force_wake_get; 1066 fw_domains_get_with_thread_status;
1196 dev_priv->uncore.funcs.force_wake_put = 1067 dev_priv->uncore.funcs.force_wake_put =
1197 __gen6_gt_force_wake_put; 1068 fw_domains_put_with_fifo;
1069 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1070 FORCEWAKE, FORCEWAKE_ACK);
1198 } 1071 }
1072}
1073
1074void intel_uncore_init(struct drm_device *dev)
1075{
1076 struct drm_i915_private *dev_priv = dev->dev_private;
1077
1078 intel_uncore_ellc_detect(dev);
1079 intel_uncore_fw_domains_init(dev);
1080 __intel_uncore_early_sanitize(dev, false);
1199 1081
1200 switch (INTEL_INFO(dev)->gen) { 1082 switch (INTEL_INFO(dev)->gen) {
1201 default: 1083 default:
@@ -1236,8 +1118,8 @@ void intel_uncore_init(struct drm_device *dev)
1236 case 4: 1118 case 4:
1237 case 3: 1119 case 3:
1238 case 2: 1120 case 2:
1239 ASSIGN_WRITE_MMIO_VFUNCS(gen4); 1121 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1240 ASSIGN_READ_MMIO_VFUNCS(gen4); 1122 ASSIGN_READ_MMIO_VFUNCS(gen2);
1241 break; 1123 break;
1242 } 1124 }
1243 1125