drm/radeon: properly program gart on rv740, juniper, cypress, barts, hemlock

Need to program an additional VM register.  This doesn't not currently
cause any problems, but allows us to program the proper backend
map in a subsequent patch which should improve performance on these
asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Dave Airlie <airlied@redhat.com>

4 files changed, 9 insertions, 0 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 5d9c2c64a8e2..0408ac27a863 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1029,6 +1029,11 @@ int evergreen_pcie_gart_enable(struct radeon_device *rdev)
                 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
                 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
                 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
+                if ((rdev->family == CHIP_JUNIPER) ||
+                    (rdev->family == CHIP_CYPRESS) ||
+                    (rdev->family == CHIP_HEMLOCK) ||
+                    (rdev->family == CHIP_BARTS))
+                        WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
         }
         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 79130bfd1d6f..3dd43e760362 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -452,6 +452,7 @@
 #define MC_VM_MD_L1_TLB0_CNTL                           0x2654
 #define MC_VM_MD_L1_TLB1_CNTL                           0x2658
 #define MC_VM_MD_L1_TLB2_CNTL                           0x265C
+#define MC_VM_MD_L1_TLB3_CNTL                           0x2698
 
 #define FUS_MC_VM_MD_L1_TLB0_CNTL                       0x265C
 #define FUS_MC_VM_MD_L1_TLB1_CNTL                       0x2660
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index c824d49305a4..c12349dba3a2 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -151,6 +151,8 @@ int rv770_pcie_gart_enable(struct radeon_device *rdev)
         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
+        if (rdev->family == CHIP_RV740)
+                WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index 9c549f702f2f..7addbef54b42 100644
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -174,6 +174,7 @@
 #define MC_VM_MD_L1_TLB0_CNTL                           0x2654
 #define MC_VM_MD_L1_TLB1_CNTL                           0x2658
 #define MC_VM_MD_L1_TLB2_CNTL                           0x265C
+#define MC_VM_MD_L1_TLB3_CNTL                           0x2698
 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR              0x203C
 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR                 0x2038
 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR                  0x2034