drm/radeon: cleanup VM id handling a bit

Store a reference to the VM into the IB structure, that
makes calculating the IBs address a bit less complicated.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>

7 files changed, 25 insertions, 26 deletions

diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 853800e8582f..fb6aa9dbd3a2 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -879,12 +879,13 @@ void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
 #endif
                           (ib->gpu_addr & 0xFFFFFFFC));
         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
-        radeon_ring_write(ring, ib->length_dw | (ib->vm_id << 24));
+        radeon_ring_write(ring, ib->length_dw | 
+                          (ib->vm ? (ib->vm->id << 24) : 0));
 
         /* flush read cache over gart for this vmid */
         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
         radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
-        radeon_ring_write(ring, ib->vm_id);
+        radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
         radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
         radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
         radeon_ring_write(ring, 0xFFFFFFFF);
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index ff3a444836d4..bf3d7902f5a0 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -3800,7 +3800,7 @@ int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
                 return r;
         }
         WREG32(scratch, 0xCAFEDEAD);
-        r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, 256);
+        r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
         if (r) {
                 return r;
         }
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 459c251991c1..fd4289bb78d9 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2635,7 +2635,7 @@ int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
                 return r;
         }
         WREG32(scratch, 0xCAFEDEAD);
-        r = radeon_ib_get(rdev, ring->idx, &ib, 256);
+        r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
         if (r) {
                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
                 return r;
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index a1c4d4dac7df..a5470e793043 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -592,7 +592,7 @@ struct radeon_ib {
         uint32_t                        *ptr;
         int                             ring;
         struct radeon_fence             *fence;
-        unsigned                        vm_id;
+        struct radeon_vm                *vm;
         bool                            is_const_ib;
         struct radeon_fence             *sync_to[RADEON_NUM_RINGS];
         struct radeon_semaphore         *semaphore;
@@ -734,7 +734,8 @@ struct si_rlc {
 };
 
 int radeon_ib_get(struct radeon_device *rdev, int ring,
-                  struct radeon_ib *ib, unsigned size);
+                  struct radeon_ib *ib, struct radeon_vm *vm,
+                  unsigned size);
 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
                        struct radeon_ib *const_ib);
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index b4a0db24f4dd..0a9d1eb719cf 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -363,7 +363,7 @@ static int radeon_cs_ib_chunk(struct radeon_device *rdev,
          * uncached).
          */
         r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
-                           ib_chunk->length_dw * 4);
+                           NULL, ib_chunk->length_dw * 4);
         if (r) {
                 DRM_ERROR("Failed to get ib !\n");
                 return r;
@@ -380,7 +380,6 @@ static int radeon_cs_ib_chunk(struct radeon_device *rdev,
                 return r;
         }
         radeon_cs_sync_rings(parser);
-        parser->ib.vm_id = 0;
         r = radeon_ib_schedule(rdev, &parser->ib, NULL);
         if (r) {
                 DRM_ERROR("Failed to schedule IB !\n");
@@ -426,7 +425,7 @@ static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
                         return -EINVAL;
                 }
                 r =  radeon_ib_get(rdev, parser->ring, &parser->const_ib,
-                                   ib_chunk->length_dw * 4);
+                                   vm, ib_chunk->length_dw * 4);
                 if (r) {
                         DRM_ERROR("Failed to get const ib !\n");
                         return r;
@@ -450,7 +449,7 @@ static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
                 return -EINVAL;
         }
         r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
-                           ib_chunk->length_dw * 4);
+                           vm, ib_chunk->length_dw * 4);
         if (r) {
                 DRM_ERROR("Failed to get ib !\n");
                 return r;
@@ -478,19 +477,8 @@ static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
         }
         radeon_cs_sync_rings(parser);
 
-        parser->ib.vm_id = vm->id;
-        /* ib pool is bind at 0 in virtual address space,
-         * so gpu_addr is the offset inside the pool bo
-         */
-        parser->ib.gpu_addr = parser->ib.sa_bo->soffset;
-
         if ((rdev->family >= CHIP_TAHITI) &&
             (parser->chunk_const_ib_idx != -1)) {
-                parser->const_ib.vm_id = vm->id;
-                /* ib pool is bind at 0 in virtual address space,
-                 * so gpu_addr is the offset inside the pool bo
-                 */
-                parser->const_ib.gpu_addr = parser->const_ib.sa_bo->soffset;
                 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib);
         } else {
                 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index 43c431a2686d..b9b1eddcd097 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -58,7 +58,8 @@ int radeon_debugfs_sa_init(struct radeon_device *rdev);
  * Returns 0 on success, error on failure.
  */
 int radeon_ib_get(struct radeon_device *rdev, int ring,
-                  struct radeon_ib *ib, unsigned size)
+                  struct radeon_ib *ib, struct radeon_vm *vm,
+                  unsigned size)
 {
         int i, r;
 
@@ -76,8 +77,15 @@ int radeon_ib_get(struct radeon_device *rdev, int ring,
         ib->ring = ring;
         ib->fence = NULL;
         ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo);
-        ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo);
-        ib->vm_id = 0;
+        ib->vm = vm;
+        if (vm) {
+                /* ib pool is bind at 0 in virtual address space,
+                 * so gpu_addr is the offset inside the pool bo
+                 */
+                ib->gpu_addr = ib->sa_bo->soffset;
+        } else {
+                ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo);
+        }
         ib->is_const_ib = false;
         for (i = 0; i < RADEON_NUM_RINGS; ++i)
                 ib->sync_to[i] = NULL;
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 3feff33e9d7f..e0846ce65f65 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1806,13 +1806,14 @@ void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
 #endif
                           (ib->gpu_addr & 0xFFFFFFFC));
         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
-        radeon_ring_write(ring, ib->length_dw | (ib->vm_id << 24));
+        radeon_ring_write(ring, ib->length_dw |
+                          (ib->vm ? (ib->vm->id << 24) : 0));
 
         if (!ib->is_const_ib) {
                 /* flush read cache over gart for this vmid */
                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
                 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
-                radeon_ring_write(ring, ib->vm_id);
+                radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
                 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
                                   PACKET3_TC_ACTION_ENA |