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authorAlex Deucher <alexander.deucher@amd.com>2014-01-20 18:20:29 -0500
committerAlex Deucher <alexander.deucher@amd.com>2014-01-20 18:20:29 -0500
commitf5f1f897c892cbff6135cd743df9989ca7bc29e4 (patch)
tree18197d06c797c03e13d91e0e0519cf4428fedf1a /drivers/gpu/drm/radeon
parentd30df55b3ec069283408b6d3b013bcba52dd03dc (diff)
drm/radeon: add query to fetch the max engine clock (v2)
This is needed for reporting the max GPU engine clock in OpenCL. This just reports the max possible engine clock, it does not take into account current conditions that may limit that clock. v2: fix query number for merge with 3.13 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon')
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c7
-rw-r--r--drivers/gpu/drm/radeon/rv770_dpm.c14
2 files changed, 13 insertions, 8 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index 5bf50cec017e..9e3af24e1b05 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -470,6 +470,13 @@ static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file
470 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n"); 470 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
471 } 471 }
472 break; 472 break;
473 case RADEON_INFO_MAX_SCLK:
474 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
475 rdev->pm.dpm_enabled)
476 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
477 else
478 *value = rdev->pm.default_sclk * 10;
479 break;
473 default: 480 default:
474 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 481 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
475 return -EINVAL; 482 return -EINVAL;
diff --git a/drivers/gpu/drm/radeon/rv770_dpm.c b/drivers/gpu/drm/radeon/rv770_dpm.c
index b95267846ff2..cb730cddfb9a 100644
--- a/drivers/gpu/drm/radeon/rv770_dpm.c
+++ b/drivers/gpu/drm/radeon/rv770_dpm.c
@@ -2251,14 +2251,12 @@ static void rv7xx_parse_pplib_clock_info(struct radeon_device *rdev,
2251 pl->vddci = vddci; 2251 pl->vddci = vddci;
2252 } 2252 }
2253 2253
2254 if (rdev->family >= CHIP_BARTS) { 2254 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
2255 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 2255 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
2256 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 2256 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
2257 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 2257 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
2258 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 2258 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
2259 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 2259 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
2260 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
2261 }
2262 } 2260 }
2263} 2261}
2264 2262