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authorChristian König <christian.koenig@amd.com>2014-02-18 08:52:33 -0500
committerChristian König <christian.koenig@amd.com>2014-02-18 11:49:19 -0500
commitff212f25feb44a915ce9c0144faef7fae27a6e61 (patch)
tree4cfdebae7d47c5504d087ef8950e068a426f1270 /drivers/gpu/drm/radeon/si.c
parenta1d6f97c8cfa7c3554d0391c0b16505d1d97f380 (diff)
drm/radeon: drop drivers copy of the rptr
In all cases where it really matters we are using the read functions anyway. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/si.c')
-rw-r--r--drivers/gpu/drm/radeon/si.c8
1 files changed, 1 insertions, 7 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 83578324e5d1..b406a48ef202 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -3434,8 +3434,6 @@ static int si_cp_resume(struct radeon_device *rdev)
3434 3434
3435 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8); 3435 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
3436 3436
3437 ring->rptr = RREG32(CP_RB0_RPTR);
3438
3439 /* ring1 - compute only */ 3437 /* ring1 - compute only */
3440 /* Set ring buffer size */ 3438 /* Set ring buffer size */
3441 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; 3439 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
@@ -3460,8 +3458,6 @@ static int si_cp_resume(struct radeon_device *rdev)
3460 3458
3461 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8); 3459 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
3462 3460
3463 ring->rptr = RREG32(CP_RB1_RPTR);
3464
3465 /* ring2 - compute only */ 3461 /* ring2 - compute only */
3466 /* Set ring buffer size */ 3462 /* Set ring buffer size */
3467 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; 3463 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
@@ -3486,8 +3482,6 @@ static int si_cp_resume(struct radeon_device *rdev)
3486 3482
3487 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8); 3483 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
3488 3484
3489 ring->rptr = RREG32(CP_RB2_RPTR);
3490
3491 /* start the rings */ 3485 /* start the rings */
3492 si_cp_start(rdev); 3486 si_cp_start(rdev);
3493 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; 3487 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
@@ -3872,7 +3866,7 @@ bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
3872 if (!(reset_mask & (RADEON_RESET_GFX | 3866 if (!(reset_mask & (RADEON_RESET_GFX |
3873 RADEON_RESET_COMPUTE | 3867 RADEON_RESET_COMPUTE |
3874 RADEON_RESET_CP))) { 3868 RADEON_RESET_CP))) {
3875 radeon_ring_lockup_update(ring); 3869 radeon_ring_lockup_update(rdev, ring);
3876 return false; 3870 return false;
3877 } 3871 }
3878 /* force CP activities */ 3872 /* force CP activities */