drm/radeon: drop drivers copy of the rptr

In all cases where it really matters we are using the read functions anyway.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

15 files changed, 32 insertions, 53 deletions

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 2b31c3233a5e..835dcfb78916 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -4031,8 +4031,6 @@ static int cik_cp_gfx_resume(struct radeon_device *rdev)
         WREG32(CP_RB0_BASE, rb_addr);
         WREG32(CP_RB0_BASE_HI, upper_32_bits(rb_addr));
 
-        ring->rptr = RREG32(CP_RB0_RPTR);
-
         /* start the ring */
         cik_cp_gfx_start(rdev);
         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
@@ -4587,8 +4585,7 @@ static int cik_cp_compute_resume(struct radeon_device *rdev)
                 rdev->ring[idx].wptr = 0;
                 mqd->queue_state.cp_hqd_pq_wptr = rdev->ring[idx].wptr;
                 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
-                rdev->ring[idx].rptr = RREG32(CP_HQD_PQ_RPTR);
-                mqd->queue_state.cp_hqd_pq_rptr = rdev->ring[idx].rptr;
+                mqd->queue_state.cp_hqd_pq_rptr = RREG32(CP_HQD_PQ_RPTR);
 
                 /* set the vmid for the queue */
                 mqd->queue_state.cp_hqd_vmid = 0;
@@ -5118,7 +5115,7 @@ bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
         if (!(reset_mask & (RADEON_RESET_GFX |
                             RADEON_RESET_COMPUTE |
                             RADEON_RESET_CP))) {
-                radeon_ring_lockup_update(ring);
+                radeon_ring_lockup_update(rdev, ring);
                 return false;
         }
         /* force CP activities */
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
index 1ecb3f1070e3..e474760d714c 100644
--- a/drivers/gpu/drm/radeon/cik_sdma.c
+++ b/drivers/gpu/drm/radeon/cik_sdma.c
@@ -362,8 +362,6 @@ static int cik_sdma_gfx_resume(struct radeon_device *rdev)
                 ring->wptr = 0;
                 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2);
 
-                ring->rptr = RREG32(SDMA0_GFX_RB_RPTR + reg_offset) >> 2;
-
                 /* enable DMA RB */
                 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE);
 
@@ -713,7 +711,7 @@ bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
                 mask = RADEON_RESET_DMA1;
 
         if (!(reset_mask & mask)) {
-                radeon_ring_lockup_update(ring);
+                radeon_ring_lockup_update(rdev, ring);
                 return false;
         }
         /* force ring activities */
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index f2b9e21ce4da..d9156be5b9a6 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2990,8 +2990,6 @@ static int evergreen_cp_resume(struct radeon_device *rdev)
         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
 
-        ring->rptr = RREG32(CP_RB_RPTR);
-
         evergreen_cp_start(rdev);
         ring->ready = true;
         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
@@ -3952,7 +3950,7 @@ bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *rin
         if (!(reset_mask & (RADEON_RESET_GFX |
                             RADEON_RESET_COMPUTE |
                             RADEON_RESET_CP))) {
-                radeon_ring_lockup_update(ring);
+                radeon_ring_lockup_update(rdev, ring);
                 return false;
         }
         /* force CP activities */
diff --git a/drivers/gpu/drm/radeon/evergreen_dma.c b/drivers/gpu/drm/radeon/evergreen_dma.c
index a37b54436382..d448961e9ab2 100644
--- a/drivers/gpu/drm/radeon/evergreen_dma.c
+++ b/drivers/gpu/drm/radeon/evergreen_dma.c
@@ -174,7 +174,7 @@ bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *rin
         u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);
 
         if (!(reset_mask & RADEON_RESET_DMA)) {
-                radeon_ring_lockup_update(ring);
+                radeon_ring_lockup_update(rdev, ring);
                 return false;
         }
         /* force ring activities */
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index ea932ac66fc6..7601532b7372 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1642,8 +1642,8 @@ static int cayman_cp_resume(struct radeon_device *rdev)
                 ring = &rdev->ring[ridx[i]];
                 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
 
-                ring->rptr = ring->wptr = 0;
-                WREG32(cp_rb_rptr[i], ring->rptr);
+                ring->wptr = 0;
+                WREG32(cp_rb_rptr[i], 0);
                 WREG32(cp_rb_wptr[i], ring->wptr);
 
                 mdelay(1);
@@ -1917,7 +1917,7 @@ bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
         if (!(reset_mask & (RADEON_RESET_GFX |
                             RADEON_RESET_COMPUTE |
                             RADEON_RESET_CP))) {
-                radeon_ring_lockup_update(ring);
+                radeon_ring_lockup_update(rdev, ring);
                 return false;
         }
         /* force CP activities */
diff --git a/drivers/gpu/drm/radeon/ni_dma.c b/drivers/gpu/drm/radeon/ni_dma.c
index 7cf96b15377f..95e533c61f83 100644
--- a/drivers/gpu/drm/radeon/ni_dma.c
+++ b/drivers/gpu/drm/radeon/ni_dma.c
@@ -248,8 +248,6 @@ int cayman_dma_resume(struct radeon_device *rdev)
                 ring->wptr = 0;
                 WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2);
 
-                ring->rptr = RREG32(DMA_RB_RPTR + reg_offset) >> 2;
-
                 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE);
 
                 ring->ready = true;
@@ -302,7 +300,7 @@ bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
                 mask = RADEON_RESET_DMA1;
 
         if (!(reset_mask & mask)) {
-                radeon_ring_lockup_update(ring);
+                radeon_ring_lockup_update(rdev, ring);
                 return false;
         }
         /* force ring activities */
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index ef024ce3f7cc..3a7438163d06 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1193,7 +1193,6 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 
         WREG32(RADEON_CP_RB_CNTL, tmp);
         udelay(10);
-        ring->rptr = RREG32(RADEON_CP_RB_RPTR);
         /* Set cp mode to bus mastering & enable cp*/