diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2014-01-16 10:53:50 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2014-01-20 18:20:54 -0500 |
commit | d526fbdd0fd0e5d78cd2e01a5387ee83431da7fb (patch) | |
tree | 5a57533acc96d00a2c5120bd122bc2910115ec1d /drivers/gpu/drm/radeon/radeon_atombios.c | |
parent | aa34dba8fb9cdcf3f7f8203abce493036b348fdb (diff) |
drm/radeon: fix endian handling in radeon_atom_init_mc_reg_table
Need to swap the data for big endian.
Notcied by sylware in IRC.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_atombios.c')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_atombios.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index 61cff32b4012..00bca1bd5745 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c | |||
@@ -3874,16 +3874,18 @@ int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, | |||
3874 | ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT)); | 3874 | ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT)); |
3875 | } | 3875 | } |
3876 | reg_table->last = i; | 3876 | reg_table->last = i; |
3877 | while ((*(u32 *)reg_data != END_OF_REG_DATA_BLOCK) && | 3877 | while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && |
3878 | (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) { | 3878 | (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) { |
3879 | t_mem_id = (u8)((*(u32 *)reg_data & MEM_ID_MASK) >> MEM_ID_SHIFT); | 3879 | t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) |
3880 | >> MEM_ID_SHIFT); | ||
3880 | if (module_index == t_mem_id) { | 3881 | if (module_index == t_mem_id) { |
3881 | reg_table->mc_reg_table_entry[num_ranges].mclk_max = | 3882 | reg_table->mc_reg_table_entry[num_ranges].mclk_max = |
3882 | (u32)((*(u32 *)reg_data & CLOCK_RANGE_MASK) >> CLOCK_RANGE_SHIFT); | 3883 | (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) |
3884 | >> CLOCK_RANGE_SHIFT); | ||
3883 | for (i = 0, j = 1; i < reg_table->last; i++) { | 3885 | for (i = 0, j = 1; i < reg_table->last; i++) { |
3884 | if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { | 3886 | if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { |
3885 | reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = | 3887 | reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = |
3886 | (u32)*((u32 *)reg_data + j); | 3888 | (u32)le32_to_cpu(*((u32 *)reg_data + j)); |
3887 | j++; | 3889 | j++; |
3888 | } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { | 3890 | } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { |
3889 | reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = | 3891 | reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = |
@@ -3895,7 +3897,7 @@ int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, | |||
3895 | reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) | 3897 | reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) |
3896 | ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); | 3898 | ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); |
3897 | } | 3899 | } |
3898 | if (*(u32 *)reg_data != END_OF_REG_DATA_BLOCK) | 3900 | if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) |
3899 | return -EINVAL; | 3901 | return -EINVAL; |
3900 | reg_table->num_entries = num_ranges; | 3902 | reg_table->num_entries = num_ranges; |
3901 | } else | 3903 | } else |