drm/radeon: fix endian handling in radeon_atom_init_mc_reg_table

Need to swap the data for big endian.
Notcied by sylware in IRC.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 7 insertions, 5 deletions

diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 61cff32b4012..00bca1bd5745 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -3874,16 +3874,18 @@ int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
                                                         ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
                                         }
                                         reg_table->last = i;
-                                        while ((*(u32 *)reg_data != END_OF_REG_DATA_BLOCK) &&
+                                        while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
                                                (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
-                                                t_mem_id = (u8)((*(u32 *)reg_data & MEM_ID_MASK) >> MEM_ID_SHIFT);
+                                                t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
+                                                                >> MEM_ID_SHIFT);
                                                 if (module_index == t_mem_id) {
                                                         reg_table->mc_reg_table_entry[num_ranges].mclk_max =
-                                                                (u32)((*(u32 *)reg_data & CLOCK_RANGE_MASK) >> CLOCK_RANGE_SHIFT);
+                                                                (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
+                                                                      >> CLOCK_RANGE_SHIFT);
                                                         for (i = 0, j = 1; i < reg_table->last; i++) {
                                                                 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
-                                                                                (u32)*((u32 *)reg_data + j);
+                                                                                (u32)le32_to_cpu(*((u32 *)reg_data + j));
                                                                         j++;
                                                                 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
                                                                         reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
@@ -3895,7 +3897,7 @@ int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
                                                 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
                                                         ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
                                         }
-                                        if (*(u32 *)reg_data != END_OF_REG_DATA_BLOCK)
+                                        if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
                                                 return -EINVAL;
                                         reg_table->num_entries = num_ranges;
                                 } else