diff options
author | Christian König <deathsimple@vodafone.de> | 2011-10-13 06:48:45 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2011-12-20 14:49:56 -0500 |
commit | 5596a9db156107b01ceb7db4d50cc091117da627 (patch) | |
tree | 93a485ad83c37f28ba4565292bd13492959d72f8 /drivers/gpu/drm/radeon/radeon_asic.c | |
parent | 7b1f2485db253aaa0081e1c5213533e166130732 (diff) |
drm/radeon: make ring rptr and wptr register offsets variable
Every ring seems to have the concept of read and
write pointers. Make the register offset variable
so we can use the functions for different types of rings.
Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_asic.c')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.c | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 8cfbbc77d70b..1b208ed814a2 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c | |||
@@ -138,7 +138,6 @@ static struct radeon_asic r100_asic = { | |||
138 | .asic_reset = &r100_asic_reset, | 138 | .asic_reset = &r100_asic_reset, |
139 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, | 139 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
140 | .gart_set_page = &r100_pci_gart_set_page, | 140 | .gart_set_page = &r100_pci_gart_set_page, |
141 | .cp_commit = &r100_cp_commit, | ||
142 | .ring_start = &r100_ring_start, | 141 | .ring_start = &r100_ring_start, |
143 | .ring_test = &r100_ring_test, | 142 | .ring_test = &r100_ring_test, |
144 | .ring_ib_execute = &r100_ring_ib_execute, | 143 | .ring_ib_execute = &r100_ring_ib_execute, |
@@ -187,7 +186,6 @@ static struct radeon_asic r200_asic = { | |||
187 | .asic_reset = &r100_asic_reset, | 186 | .asic_reset = &r100_asic_reset, |
188 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, | 187 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
189 | .gart_set_page = &r100_pci_gart_set_page, | 188 | .gart_set_page = &r100_pci_gart_set_page, |
190 | .cp_commit = &r100_cp_commit, | ||
191 | .ring_start = &r100_ring_start, | 189 | .ring_start = &r100_ring_start, |
192 | .ring_test = &r100_ring_test, | 190 | .ring_test = &r100_ring_test, |
193 | .ring_ib_execute = &r100_ring_ib_execute, | 191 | .ring_ib_execute = &r100_ring_ib_execute, |
@@ -235,7 +233,6 @@ static struct radeon_asic r300_asic = { | |||
235 | .asic_reset = &r300_asic_reset, | 233 | .asic_reset = &r300_asic_reset, |
236 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, | 234 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
237 | .gart_set_page = &r100_pci_gart_set_page, | 235 | .gart_set_page = &r100_pci_gart_set_page, |
238 | .cp_commit = &r100_cp_commit, | ||
239 | .ring_start = &r300_ring_start, | 236 | .ring_start = &r300_ring_start, |
240 | .ring_test = &r100_ring_test, | 237 | .ring_test = &r100_ring_test, |
241 | .ring_ib_execute = &r100_ring_ib_execute, | 238 | .ring_ib_execute = &r100_ring_ib_execute, |
@@ -284,7 +281,6 @@ static struct radeon_asic r300_asic_pcie = { | |||
284 | .asic_reset = &r300_asic_reset, | 281 | .asic_reset = &r300_asic_reset, |
285 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, | 282 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
286 | .gart_set_page = &rv370_pcie_gart_set_page, | 283 | .gart_set_page = &rv370_pcie_gart_set_page, |
287 | .cp_commit = &r100_cp_commit, | ||
288 | .ring_start = &r300_ring_start, | 284 | .ring_start = &r300_ring_start, |
289 | .ring_test = &r100_ring_test, | 285 | .ring_test = &r100_ring_test, |
290 | .ring_ib_execute = &r100_ring_ib_execute, | 286 | .ring_ib_execute = &r100_ring_ib_execute, |
@@ -332,7 +328,6 @@ static struct radeon_asic r420_asic = { | |||
332 | .asic_reset = &r300_asic_reset, | 328 | .asic_reset = &r300_asic_reset, |
333 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, | 329 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
334 | .gart_set_page = &rv370_pcie_gart_set_page, | 330 | .gart_set_page = &rv370_pcie_gart_set_page, |
335 | .cp_commit = &r100_cp_commit, | ||
336 | .ring_start = &r300_ring_start, | 331 | .ring_start = &r300_ring_start, |
337 | .ring_test = &r100_ring_test, | 332 | .ring_test = &r100_ring_test, |
338 | .ring_ib_execute = &r100_ring_ib_execute, | 333 | .ring_ib_execute = &r100_ring_ib_execute, |
@@ -381,7 +376,6 @@ static struct radeon_asic rs400_asic = { | |||
381 | .asic_reset = &r300_asic_reset, | 376 | .asic_reset = &r300_asic_reset, |
382 | .gart_tlb_flush = &rs400_gart_tlb_flush, | 377 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
383 | .gart_set_page = &rs400_gart_set_page, | 378 | .gart_set_page = &rs400_gart_set_page, |
384 | .cp_commit = &r100_cp_commit, | ||
385 | .ring_start = &r300_ring_start, | 379 | .ring_start = &r300_ring_start, |
386 | .ring_test = &r100_ring_test, | 380 | .ring_test = &r100_ring_test, |
387 | .ring_ib_execute = &r100_ring_ib_execute, | 381 | .ring_ib_execute = &r100_ring_ib_execute, |
@@ -430,7 +424,6 @@ static struct radeon_asic rs600_asic = { | |||
430 | .asic_reset = &rs600_asic_reset, | 424 | .asic_reset = &rs600_asic_reset, |
431 | .gart_tlb_flush = &rs600_gart_tlb_flush, | 425 | .gart_tlb_flush = &rs600_gart_tlb_flush, |
432 | .gart_set_page = &rs600_gart_set_page, | 426 | .gart_set_page = &rs600_gart_set_page, |
433 | .cp_commit = &r100_cp_commit, | ||
434 | .ring_start = &r300_ring_start, | 427 | .ring_start = &r300_ring_start, |
435 | .ring_test = &r100_ring_test, | 428 | .ring_test = &r100_ring_test, |
436 | .ring_ib_execute = &r100_ring_ib_execute, | 429 | .ring_ib_execute = &r100_ring_ib_execute, |
@@ -479,7 +472,6 @@ static struct radeon_asic rs690_asic = { | |||
479 | .asic_reset = &rs600_asic_reset, | 472 | .asic_reset = &rs600_asic_reset, |
480 | .gart_tlb_flush = &rs400_gart_tlb_flush, | 473 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
481 | .gart_set_page = &rs400_gart_set_page, | 474 | .gart_set_page = &rs400_gart_set_page, |
482 | .cp_commit = &r100_cp_commit, | ||
483 | .ring_start = &r300_ring_start, | 475 | .ring_start = &r300_ring_start, |
484 | .ring_test = &r100_ring_test, | 476 | .ring_test = &r100_ring_test, |
485 | .ring_ib_execute = &r100_ring_ib_execute, | 477 | .ring_ib_execute = &r100_ring_ib_execute, |
@@ -528,7 +520,6 @@ static struct radeon_asic rv515_asic = { | |||
528 | .asic_reset = &rs600_asic_reset, | 520 | .asic_reset = &rs600_asic_reset, |
529 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, | 521 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
530 | .gart_set_page = &rv370_pcie_gart_set_page, | 522 | .gart_set_page = &rv370_pcie_gart_set_page, |
531 | .cp_commit = &r100_cp_commit, | ||
532 | .ring_start = &rv515_ring_start, | 523 | .ring_start = &rv515_ring_start, |
533 | .ring_test = &r100_ring_test, | 524 | .ring_test = &r100_ring_test, |
534 | .ring_ib_execute = &r100_ring_ib_execute, | 525 | .ring_ib_execute = &r100_ring_ib_execute, |
@@ -577,7 +568,6 @@ static struct radeon_asic r520_asic = { | |||
577 | .asic_reset = &rs600_asic_reset, | 568 | .asic_reset = &rs600_asic_reset, |
578 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, | 569 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
579 | .gart_set_page = &rv370_pcie_gart_set_page, | 570 | .gart_set_page = &rv370_pcie_gart_set_page, |
580 | .cp_commit = &r100_cp_commit, | ||
581 | .ring_start = &rv515_ring_start, | 571 | .ring_start = &rv515_ring_start, |
582 | .ring_test = &r100_ring_test, | 572 | .ring_test = &r100_ring_test, |
583 | .ring_ib_execute = &r100_ring_ib_execute, | 573 | .ring_ib_execute = &r100_ring_ib_execute, |
@@ -621,7 +611,6 @@ static struct radeon_asic r600_asic = { | |||
621 | .fini = &r600_fini, | 611 | .fini = &r600_fini, |
622 | .suspend = &r600_suspend, | 612 | .suspend = &r600_suspend, |
623 | .resume = &r600_resume, | 613 | .resume = &r600_resume, |
624 | .cp_commit = &r600_cp_commit, | ||
625 | .vga_set_state = &r600_vga_set_state, | 614 | .vga_set_state = &r600_vga_set_state, |
626 | .gpu_is_lockup = &r600_gpu_is_lockup, | 615 | .gpu_is_lockup = &r600_gpu_is_lockup, |
627 | .asic_reset = &r600_asic_reset, | 616 | .asic_reset = &r600_asic_reset, |
@@ -669,7 +658,6 @@ static struct radeon_asic rs780_asic = { | |||
669 | .fini = &r600_fini, | 658 | .fini = &r600_fini, |
670 | .suspend = &r600_suspend, | 659 | .suspend = &r600_suspend, |
671 | .resume = &r600_resume, | 660 | .resume = &r600_resume, |
672 | .cp_commit = &r600_cp_commit, | ||
673 | .gpu_is_lockup = &r600_gpu_is_lockup, | 661 | .gpu_is_lockup = &r600_gpu_is_lockup, |
674 | .vga_set_state = &r600_vga_set_state, | 662 | .vga_set_state = &r600_vga_set_state, |
675 | .asic_reset = &r600_asic_reset, | 663 | .asic_reset = &r600_asic_reset, |
@@ -717,7 +705,6 @@ static struct radeon_asic rv770_asic = { | |||
717 | .fini = &rv770_fini, | 705 | .fini = &rv770_fini, |
718 | .suspend = &rv770_suspend, | 706 | .suspend = &rv770_suspend, |
719 | .resume = &rv770_resume, | 707 | .resume = &rv770_resume, |
720 | .cp_commit = &r600_cp_commit, | ||
721 | .asic_reset = &r600_asic_reset, | 708 | .asic_reset = &r600_asic_reset, |
722 | .gpu_is_lockup = &r600_gpu_is_lockup, | 709 | .gpu_is_lockup = &r600_gpu_is_lockup, |
723 | .vga_set_state = &r600_vga_set_state, | 710 | .vga_set_state = &r600_vga_set_state, |
@@ -765,7 +752,6 @@ static struct radeon_asic evergreen_asic = { | |||
765 | .fini = &evergreen_fini, | 752 | .fini = &evergreen_fini, |
766 | .suspend = &evergreen_suspend, | 753 | .suspend = &evergreen_suspend, |
767 | .resume = &evergreen_resume, | 754 | .resume = &evergreen_resume, |
768 | .cp_commit = &r600_cp_commit, | ||
769 | .gpu_is_lockup = &evergreen_gpu_is_lockup, | 755 | .gpu_is_lockup = &evergreen_gpu_is_lockup, |
770 | .asic_reset = &evergreen_asic_reset, | 756 | .asic_reset = &evergreen_asic_reset, |
771 | .vga_set_state = &r600_vga_set_state, | 757 | .vga_set_state = &r600_vga_set_state, |
@@ -813,7 +799,6 @@ static struct radeon_asic sumo_asic = { | |||
813 | .fini = &evergreen_fini, | 799 | .fini = &evergreen_fini, |
814 | .suspend = &evergreen_suspend, | 800 | .suspend = &evergreen_suspend, |
815 | .resume = &evergreen_resume, | 801 | .resume = &evergreen_resume, |
816 | .cp_commit = &r600_cp_commit, | ||
817 | .gpu_is_lockup = &evergreen_gpu_is_lockup, | 802 | .gpu_is_lockup = &evergreen_gpu_is_lockup, |
818 | .asic_reset = &evergreen_asic_reset, | 803 | .asic_reset = &evergreen_asic_reset, |
819 | .vga_set_state = &r600_vga_set_state, | 804 | .vga_set_state = &r600_vga_set_state, |
@@ -861,7 +846,6 @@ static struct radeon_asic btc_asic = { | |||
861 | .fini = &evergreen_fini, | 846 | .fini = &evergreen_fini, |
862 | .suspend = &evergreen_suspend, | 847 | .suspend = &evergreen_suspend, |
863 | .resume = &evergreen_resume, | 848 | .resume = &evergreen_resume, |
864 | .cp_commit = &r600_cp_commit, | ||
865 | .gpu_is_lockup = &evergreen_gpu_is_lockup, | 849 | .gpu_is_lockup = &evergreen_gpu_is_lockup, |
866 | .asic_reset = &evergreen_asic_reset, | 850 | .asic_reset = &evergreen_asic_reset, |
867 | .vga_set_state = &r600_vga_set_state, | 851 | .vga_set_state = &r600_vga_set_state, |
@@ -909,7 +893,6 @@ static struct radeon_asic cayman_asic = { | |||
909 | .fini = &cayman_fini, | 893 | .fini = &cayman_fini, |
910 | .suspend = &cayman_suspend, | 894 | .suspend = &cayman_suspend, |
911 | .resume = &cayman_resume, | 895 | .resume = &cayman_resume, |
912 | .cp_commit = &r600_cp_commit, | ||
913 | .gpu_is_lockup = &cayman_gpu_is_lockup, | 896 | .gpu_is_lockup = &cayman_gpu_is_lockup, |
914 | .asic_reset = &cayman_asic_reset, | 897 | .asic_reset = &cayman_asic_reset, |
915 | .vga_set_state = &r600_vga_set_state, | 898 | .vga_set_state = &r600_vga_set_state, |