diff options
author | Jiri Kosina <jkosina@suse.cz> | 2010-08-04 09:14:38 -0400 |
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committer | Jiri Kosina <jkosina@suse.cz> | 2010-08-04 09:14:38 -0400 |
commit | d790d4d583aeaed9fc6f8a9f4d9f8ce6b1c15c7f (patch) | |
tree | 854ab394486288d40fa8179cbfaf66e8bdc44b0f /drivers/gpu/drm/radeon/r600.c | |
parent | 73b2c7165b76b20eb1290e7efebc33cfd21db1ca (diff) | |
parent | 3a09b1be53d23df780a0cd0e4087a05e2ca4a00c (diff) |
Merge branch 'master' into for-next
Diffstat (limited to 'drivers/gpu/drm/radeon/r600.c')
-rw-r--r-- | drivers/gpu/drm/radeon/r600.c | 18 |
1 files changed, 13 insertions, 5 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 0e91871f45be..e100f69faeec 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -130,9 +130,14 @@ void r600_pm_get_dynpm_state(struct radeon_device *rdev) | |||
130 | break; | 130 | break; |
131 | } | 131 | } |
132 | } | 132 | } |
133 | } else | 133 | } else { |
134 | rdev->pm.requested_power_state_index = | 134 | if (rdev->pm.current_power_state_index == 0) |
135 | rdev->pm.current_power_state_index - 1; | 135 | rdev->pm.requested_power_state_index = |
136 | rdev->pm.num_power_states - 1; | ||
137 | else | ||
138 | rdev->pm.requested_power_state_index = | ||
139 | rdev->pm.current_power_state_index - 1; | ||
140 | } | ||
136 | } | 141 | } |
137 | rdev->pm.requested_clock_mode_index = 0; | 142 | rdev->pm.requested_clock_mode_index = 0; |
138 | /* don't use the power state if crtcs are active and no display flag is set */ | 143 | /* don't use the power state if crtcs are active and no display flag is set */ |
@@ -1097,7 +1102,7 @@ static void r600_mc_program(struct radeon_device *rdev) | |||
1097 | WREG32(MC_VM_FB_LOCATION, tmp); | 1102 | WREG32(MC_VM_FB_LOCATION, tmp); |
1098 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); | 1103 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); |
1099 | WREG32(HDP_NONSURFACE_INFO, (2 << 7)); | 1104 | WREG32(HDP_NONSURFACE_INFO, (2 << 7)); |
1100 | WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF); | 1105 | WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); |
1101 | if (rdev->flags & RADEON_IS_AGP) { | 1106 | if (rdev->flags & RADEON_IS_AGP) { |
1102 | WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); | 1107 | WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); |
1103 | WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); | 1108 | WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); |
@@ -1174,6 +1179,7 @@ void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) | |||
1174 | if (rdev->flags & RADEON_IS_IGP) | 1179 | if (rdev->flags & RADEON_IS_IGP) |
1175 | base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24; | 1180 | base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24; |
1176 | radeon_vram_location(rdev, &rdev->mc, base); | 1181 | radeon_vram_location(rdev, &rdev->mc, base); |
1182 | rdev->mc.gtt_base_align = 0; | ||
1177 | radeon_gtt_location(rdev, mc); | 1183 | radeon_gtt_location(rdev, mc); |
1178 | } | 1184 | } |
1179 | } | 1185 | } |
@@ -1219,8 +1225,10 @@ int r600_mc_init(struct radeon_device *rdev) | |||
1219 | rdev->mc.visible_vram_size = rdev->mc.aper_size; | 1225 | rdev->mc.visible_vram_size = rdev->mc.aper_size; |
1220 | r600_vram_gtt_location(rdev, &rdev->mc); | 1226 | r600_vram_gtt_location(rdev, &rdev->mc); |
1221 | 1227 | ||
1222 | if (rdev->flags & RADEON_IS_IGP) | 1228 | if (rdev->flags & RADEON_IS_IGP) { |
1229 | rs690_pm_info(rdev); | ||
1223 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); | 1230 | rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); |
1231 | } | ||
1224 | radeon_update_bandwidth_info(rdev); | 1232 | radeon_update_bandwidth_info(rdev); |
1225 | return 0; | 1233 | return 0; |
1226 | } | 1234 | } |