Merge branch 'master' into for-next

51 files changed, 797 insertions, 296 deletions

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index da06476f2df4..9585e531ac6b 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -864,8 +864,8 @@ drm_mode_std(struct drm_connector *connector, struct edid *edid,
                 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
                                     false);
                 mode->hdisplay = 1366;
-                mode->vsync_start = mode->vsync_start - 1;
-                mode->vsync_end = mode->vsync_end - 1;
+                mode->hsync_start = mode->hsync_start - 1;
+                mode->hsync_end = mode->hsync_end - 1;
                 return mode;
         }
 
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 08c4c926e65f..719662034bbf 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -146,7 +146,7 @@ static bool drm_fb_helper_connector_parse_command_line(struct drm_fb_helper_conn
                                 cvt = 1;
                         break;
                 case 'R':
-                        if (!cvt)
+                        if (cvt)
                                 rb = 1;
                         break;
                 case 'm':
@@ -315,8 +315,9 @@ static void drm_fb_helper_on(struct fb_info *info)
         struct drm_device *dev = fb_helper->dev;
         struct drm_crtc *crtc;
         struct drm_crtc_helper_funcs *crtc_funcs;
+        struct drm_connector *connector;
         struct drm_encoder *encoder;
-        int i;
+        int i, j;
 
         /*
          * For each CRTC in this fb, turn the crtc on then,
@@ -332,7 +333,14 @@ static void drm_fb_helper_on(struct fb_info *info)
 
                 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
 
-
+                /* Walk the connectors & encoders on this fb turning them on */
+                for (j = 0; j < fb_helper->connector_count; j++) {
+                        connector = fb_helper->connector_info[j]->connector;
+                        connector->dpms = DRM_MODE_DPMS_ON;
+                        drm_connector_property_set_value(connector,
+                                                         dev->mode_config.dpms_property,
+                                                         DRM_MODE_DPMS_ON);
+                }
                 /* Found a CRTC on this fb, now find encoders */
                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
                         if (encoder->crtc == crtc) {
@@ -352,8 +360,9 @@ static void drm_fb_helper_off(struct fb_info *info, int dpms_mode)
         struct drm_device *dev = fb_helper->dev;
         struct drm_crtc *crtc;
         struct drm_crtc_helper_funcs *crtc_funcs;
+        struct drm_connector *connector;
         struct drm_encoder *encoder;
-        int i;
+        int i, j;
 
         /*
          * For each CRTC in this fb, find all associated encoders
@@ -367,6 +376,14 @@ static void drm_fb_helper_off(struct fb_info *info, int dpms_mode)
                 if (!crtc->enabled)
                         continue;
 
+                /* Walk the connectors on this fb and mark them off */
+                for (j = 0; j < fb_helper->connector_count; j++) {
+                        connector = fb_helper->connector_info[j]->connector;
+                        connector->dpms = dpms_mode;
+                        drm_connector_property_set_value(connector,
+                                                         dev->mode_config.dpms_property,
+                                                         dpms_mode);
+                }
                 /* Found a CRTC on this fb, now find encoders */
                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
                         if (encoder->crtc == crtc) {
@@ -1024,11 +1041,18 @@ static struct drm_display_mode *drm_pick_cmdline_mode(struct drm_fb_helper_conne
         }
 
 create_mode:
-        mode = drm_cvt_mode(fb_helper_conn->connector->dev, cmdline_mode->xres,
-                            cmdline_mode->yres,
-                            cmdline_mode->refresh_specified ? cmdline_mode->refresh : 60,
-                            cmdline_mode->rb, cmdline_mode->interlace,
-                            cmdline_mode->margins);
+        if (cmdline_mode->cvt)
+                mode = drm_cvt_mode(fb_helper_conn->connector->dev,
+                                    cmdline_mode->xres, cmdline_mode->yres,
+                                    cmdline_mode->refresh_specified ? cmdline_mode->refresh : 60,
+                                    cmdline_mode->rb, cmdline_mode->interlace,
+                                    cmdline_mode->margins);
+        else
+                mode = drm_gtf_mode(fb_helper_conn->connector->dev,
+                                    cmdline_mode->xres, cmdline_mode->yres,
+                                    cmdline_mode->refresh_specified ? cmdline_mode->refresh : 60,
+                                    cmdline_mode->interlace,
+                                    cmdline_mode->margins);
         drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
         list_add(&mode->head, &fb_helper_conn->connector->modes);
         return mode;
diff --git a/drivers/gpu/drm/i915/dvo_tfp410.c b/drivers/gpu/drm/i915/dvo_tfp410.c
index 66c697bc9b22..56f66426207f 100644
--- a/drivers/gpu/drm/i915/dvo_tfp410.c
+++ b/drivers/gpu/drm/i915/dvo_tfp410.c
@@ -208,7 +208,7 @@ static enum drm_connector_status tfp410_detect(struct intel_dvo_device *dvo)
         uint8_t ctl2;
 
         if (tfp410_readb(dvo, TFP410_CTL_2, &ctl2)) {
-                if (ctl2 & TFP410_CTL_2_HTPLG)
+                if (ctl2 & TFP410_CTL_2_RSEN)
                         ret = connector_status_connected;
                 else
                         ret = connector_status_disconnected;
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 52510ad8b25d..9214119c0154 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -605,6 +605,9 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
                 case FBC_NOT_TILED:
                         seq_printf(m, "scanout buffer not tiled");
                         break;
+                case FBC_MULTIPLE_PIPES:
+                        seq_printf(m, "multiple pipes are enabled");
+                        break;
                 default:
                         seq_printf(m, "unknown reason");
                 }
@@ -620,7 +623,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
         drm_i915_private_t *dev_priv = dev->dev_private;
         bool sr_enabled = false;
 
-        if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev))
+        if (IS_I965GM(dev) || IS_I945G(dev) || IS_I945GM(dev))
                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
         else if (IS_I915GM(dev))
                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 59a2bf8592ec..2305a1234f1e 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -128,9 +128,11 @@ static int i915_dma_cleanup(struct drm_device * dev)
         if (dev->irq_enabled)
                 drm_irq_uninstall(dev);
 
+        mutex_lock(&dev->struct_mutex);
         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
         if (HAS_BSD(dev))
                 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
+        mutex_unlock(&dev->struct_mutex);
 
         /* Clear the HWS virtual address at teardown */
         if (I915_NEED_GFX_HWS(dev))
@@ -1229,7 +1231,7 @@ static void i915_warn_stolen(struct drm_device *dev)
 static void i915_setup_compression(struct drm_device *dev, int size)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
-        struct drm_mm_node *compressed_fb, *compressed_llb;
+        struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
         unsigned long cfb_base;
         unsigned long ll_base = 0;
 
@@ -1298,7 +1300,7 @@ static void i915_cleanup_compression(struct drm_device *dev)
         struct drm_i915_private *dev_priv = dev->dev_private;
 
         drm_mm_put_block(dev_priv->compressed_fb);
-        if (!IS_GM45(dev))
+        if (dev_priv->compressed_llb)
                 drm_mm_put_block(dev_priv->compressed_llb);
 }
 
@@ -1410,6 +1412,10 @@ static int i915_load_modeset_init(struct drm_device *dev,
         if (ret)
                 goto cleanup_vga_client;
 
+        /* IIR "flip pending" bit means done if this bit is set */
+        if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
+                dev_priv->flip_pending_is_done = true;
+
         intel_modeset_init(dev);
 
         ret = drm_irq_install(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 276583159847..2e1744d37ad5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -215,6 +215,7 @@ enum no_fbc_reason {
         FBC_MODE_TOO_LARGE, /* mode too large for compression */
         FBC_BAD_PLANE, /* fbc not supported on plane */
         FBC_NOT_TILED, /* buffer not tiled */
+        FBC_MULTIPLE_PIPES, /* more than one pipe active */
 };
 
 enum intel_pch {
@@ -222,6 +223,8 @@ enum intel_pch {
         PCH_CPT,        /* Cougarpoint PCH */
 };
 
+#define QUIRK_PIPEA_FORCE (1<<0)
+
 struct intel_fbdev;
 
 typedef struct drm_i915_private {
@@ -337,6 +340,8 @@ typedef struct drm_i915_private {
         /* PCH chipset type */
         enum intel_pch pch_type;
 
+        unsigned long quirks;
+
         /* Register state */
         bool modeset_on_lid;
         u8 saveLBB;
@@ -596,6 +601,7 @@ typedef struct drm_i915_private {
         struct drm_crtc *plane_to_crtc_mapping[2];
         struct drm_crtc *pipe_to_crtc_mapping[2];
         wait_queue_head_t pending_flip_queue;
+        bool flip_pending_is_done;
 
         /* Reclocking support */
         bool render_reclock_avail;
@@ -1076,7 +1082,7 @@ extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
         drm_i915_private_t *dev_priv = dev->dev_private;                \
         if (I915_VERBOSE)                                               \
                 DRM_DEBUG("   BEGIN_LP_RING %x\n", (int)(n));           \
-        intel_ring_begin(dev, &dev_priv->render_ring, 4*(n));           \
+        intel_ring_begin(dev, &dev_priv->render_ring, (n));             \
 } while (0)
 
 
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 9ded3dae6c87..5aa747fc25a9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2239,8 +2239,9 @@ i915_gem_object_get_pages(struct drm_gem_object *obj,
         mapping = inode->i_mapping;
         for (i = 0; i < page_count; i++) {
                 page = read_cache_page_gfp(mapping, i,
-                                           mapping_gfp_mask (mapping) |
+                                           GFP_HIGHUSER |
                                            __GFP_COLD |
+                                           __GFP_RECLAIMABLE |
                                            gfpmask);
                 if (IS_ERR(page))
                         goto err_pages;
@@ -3646,6 +3647,7 @@ i915_gem_wait_for_pending_flip(struct drm_device *dev,
         return ret;
 }
 
+
 int
 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
                        struct drm_file *file_priv,
@@ -3793,7 +3795,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
                                 unsigned long long total_size = 0;
                                 int num_fences = 0;
                                 for (i = 0; i < args->buffer_count; i++) {
-                                        obj_priv = object_list[i]->driver_private;
+                                        obj_priv = to_intel_bo(object_list[i]);
 
                                         total_size += object_list[i]->size;
                                         num_fences +=
@@ -4741,6 +4743,16 @@ i915_gem_load(struct drm_device *dev)
         list_add(&dev_priv->mm.shrink_list, &shrink_list);
         spin_unlock(&shrink_list_lock);
 
+        /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
+        if (IS_GEN3(dev)) {
+                u32 tmp = I915_READ(MI_ARB_STATE);
+                if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
+                        /* arb state is a masked write, so set bit + bit in mask */
+                        tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
+                        I915_WRITE(MI_ARB_STATE, tmp);
+                }
+        }
+
         /* Old X drivers will take 0-2 for front, back, depth buffers */
         if (!drm_core_check_feature(dev, DRIVER_MODESET))
                 dev_priv->fence_reg_start = 3;
@@ -4977,7 +4989,7 @@ i915_gpu_is_active(struct drm_device *dev)
 }
 
 static int
-i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
+i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
 {
         drm_i915_private_t *dev_priv, *next_dev;
         struct drm_i915_gem_object *obj_priv, *next_obj;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2479be001e40..dba53d4b9fb3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -940,22 +940,30 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
                 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
                         DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
 
-                if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
+                if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
                         intel_prepare_page_flip(dev, 0);
+                        if (dev_priv->flip_pending_is_done)
+                                intel_finish_page_flip_plane(dev, 0);
+                }
 
-                if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
+                if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
                         intel_prepare_page_flip(dev, 1);
+                        if (dev_priv->flip_pending_is_done)
+                                intel_finish_page_flip_plane(dev, 1);
+                }
 
                 if (pipea_stats & vblank_status) {
                         vblank++;
                         drm_handle_vblank(dev, 0);
-                        intel_finish_page_flip(dev, 0);
+                        if (!dev_priv->flip_pending_is_done)
+                                intel_finish_page_flip(dev, 0);
                 }
 
                 if (pipeb_stats & vblank_status) {
                         vblank++;
                         drm_handle_vblank(dev, 1);
-                        intel_finish_page_flip(dev, 1);
+                        if (!dev_priv->flip_pending_is_done)
+                                intel_finish_page_flip(dev, 1);
                 }
 
                 if ((pipea_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
@@ -1387,29 +1395,10 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
         dev_priv->pipestat[1] = 0;
 
         if (I915_HAS_HOTPLUG(dev)) {
-                u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
-
-                /* Note HDMI and DP share bits */
-                if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
-                        hotplug_en |= HDMIB_HOTPLUG_INT_EN;
-                if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
-                        hotplug_en |= HDMIC_HOTPLUG_INT_EN;
-                if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
-                        hotplug_en |= HDMID_HOTPLUG_INT_EN;
-                if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
-                        hotplug_en |= SDVOC_HOTPLUG_INT_EN;
-                if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
-                        hotplug_en |= SDVOB_HOTPLUG_INT_EN;
-                if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)
-                        hotplug_en |= CRT_HOTPLUG_INT_EN;
-                /* Ignore TV since it's buggy */
-
-                I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
-
                 /* Enable in IER... */
                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
                 /* and unmask in IMR */
-                i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
+                dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT;
         }
 
         /*
@@ -1427,16 +1416,41 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
         }
         I915_WRITE(EMR, error_mask);
 
-        /* Disable pipe interrupt enables, clear pending pipe status */
-        I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
-        I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
-        /* Clear pending interrupt status */
-        I915_WRITE(IIR, I915_READ(IIR));
-
-        I915_WRITE(IER, enable_mask);
         I915_WRITE(IMR, dev_priv->irq_mask_reg);
+        I915_WRITE(IER, enable_mask);
         (void) I915_READ(IER);
 
+        if (I915_HAS_HOTPLUG(dev)) {
+                u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
+
+                /* Note HDMI and DP share bits */
+                if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
+                        hotplug_en |= HDMIB_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
+                        hotplug_en |= HDMIC_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
+                        hotplug_en |= HDMID_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
+                        hotplug_en |= SDVOC_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
+                        hotplug_en |= SDVOB_HOTPLUG_INT_EN;
+                if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
+                        hotplug_en |= CRT_HOTPLUG_INT_EN;
+
+                        /* Programming the CRT detection parameters tends
+                           to generate a spurious hotplug event about three
+                           seconds later.  So just do it once.
+                        */
+                        if (IS_G4X(dev))
+                                hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
+                        hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
+                }
+
+                /* Ignore TV since it's buggy */
+
+                I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
+        }
+
         opregion_enable_asle(dev);
 
         return 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 64b0a3afd92b..cf41c672defe 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -178,6 +178,7 @@
 #define   MI_OVERLAY_OFF        (0x2<<21)
 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
 #define MI_DISPLAY_FLIP         MI_INSTR(0x14, 2)
+#define MI_DISPLAY_FLIP_I915    MI_INSTR(0x14, 1)
 #define   MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
 #define MI_STORE_DWORD_IMM      MI_INSTR(0x20, 1)
 #define   MI_MEM_VIRTUAL        (1 << 22) /* 965+ only */
@@ -358,6 +359,70 @@
 #define LM_BURST_LENGTH     0x00000700
 #define LM_FIFO_WATERMARK   0x0000001F
 #define MI_ARB_STATE    0x020e4 /* 915+ only */
+#define   MI_ARB_MASK_SHIFT       16    /* shift for enable bits */
+
+/* Make render/texture TLB fetches lower priorty than associated data
+ *   fetches. This is not turned on by default
+ */
+#define   MI_ARB_RENDER_TLB_LOW_PRIORITY        (1 << 15)
+
+/* Isoch request wait on GTT enable (Display A/B/C streams).
+ * Make isoch requests stall on the TLB update. May cause
+ * display underruns (test mode only)
+ */
+#define   MI_ARB_ISOCH_WAIT_GTT                 (1 << 14)
+
+/* Block grant count for isoch requests when block count is
+ * set to a finite value.
+ */
+#define   MI_ARB_BLOCK_GRANT_MASK               (3 << 12)
+#define   MI_ARB_BLOCK_GRANT_8                  (0 << 12)       /* for 3 display planes */
+#define   MI_ARB_BLOCK_GRANT_4                  (1 << 12)       /* for 2 display planes */
+#define   MI_ARB_BLOCK_GRANT_2                  (2 << 12)       /* for 1 display plane */
+#define   MI_ARB_BLOCK_GRANT_0                  (3 << 12)       /* don't use */
+
+/* Enable render writes to complete in C2/C3/C4 power states.
+ * If this isn't enabled, render writes are prevented in low
+ * power states. That seems bad to me.
+ */
+#define   MI_ARB_C3_LP_WRITE_ENABLE             (1 << 11)
+
+/* This acknowledges an async flip immediately instead
+ * of waiting for 2TLB fetches.
+ */
+#define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE       (1 << 10)
+
+/* Enables non-sequential data reads through arbiter
+ */
+#define   MI_ARB_DUAL_DATA_PHASE_DISABLE        (1 << 9)
+
+/* Disable FSB snooping of cacheable write cycles from binner/render
+ * command stream
+ */
+#define   MI_ARB_CACHE_SNOOP_DISABLE            (1 << 8)
+
+/* Arbiter time slice for non-isoch streams */
+#define   MI_ARB_TIME_SLICE_MASK                (7 << 5)
+#define   MI_ARB_TIME_SLICE_1                   (0 << 5)
+#define   MI_ARB_TIME_SLICE_2                   (1 << 5)
+#define   MI_ARB_TIME_SLICE_4                   (2 << 5)
+#define   MI_ARB_TIME_SLICE_6                   (3 << 5)
+#define   MI_ARB_TIME_SLICE_8                   (4 << 5)
+#define   MI_ARB_TIME_SLICE_10                  (5 << 5)
+#define   MI_ARB_TIME_SLICE_14                  (6 << 5)
+#define   MI_ARB_TIME_SLICE_16                  (7 << 5)
+
+/* Low priority grace period page size */
+#define   MI_ARB_LOW_PRIORITY_GRACE_4KB         (0 << 4)        /* default */
+#define   MI_ARB_LOW_PRIORITY_GRACE_8KB         (1 << 4)
+
+/* Disable display A/B trickle feed */
+#define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE   (1 << 2)
+
+/* Set display plane priority */
+#define   MI_ARB_DISPLAY_PRIORITY_A_B           (0 << 0)        /* display A > display B */
+#define   MI_ARB_DISPLAY_PRIORITY_B_A           (1 << 0)        /* display B > display A */
+
 #define CACHE_MODE_0    0x02120 /* 915+ only */
 #define   CM0_MASK_SHIFT          16
 #define   CM0_IZ_OPT_DISABLE      (1<<6)
@@ -368,6 +433,9 @@
 #define   CM0_RC_OP_FLUSH_DISABLE (1<<0)
 #define BB_ADDR         0x02140 /* 8 bytes */
 #define GFX_FLSH_CNTL   0x02170 /* 915+ only */
+#define ECOSKPD         0x021d0
+#define   ECO_GATING_CX_ONLY    (1<<3)
+#define   ECO_FLIP_DONE         (1<<0)
 
 /* GEN6 interrupt control */
 #define GEN6_RENDER_HWSTAM      0x2098
@@ -1130,7 +1198,6 @@
 #define CRT_HOTPLUG_DETECT_DELAY_2G             (1 << 4)
 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV        (0 << 2)
 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV        (1 << 2)
-#define CRT_HOTPLUG_MASK                        (0x3fc) /* Bits 9-2 */
 
 #define PORT_HOTPLUG_STAT       0x61114
 #define   HDMIB_HOTPLUG_INT_STATUS              (1 << 29)
@@ -2802,6 +2869,7 @@
 
 #define PCH_PP_STATUS           0xc7200
 #define PCH_PP_CONTROL          0xc7204
+#define  PANEL_UNLOCK_REGS      (0xabcd << 16)
 #define  EDP_FORCE_VDD          (1 << 3)
 #define  EDP_BLC_ENABLE         (1 << 2)
 #define  PANEL_POWER_RESET      (1 << 1)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 22ff38455731..ee0732b222a1 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -234,14 +234,8 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
         else
                 tries = 1;
         hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
-        hotplug_en &= CRT_HOTPLUG_MASK;
         hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
 
-        if (IS_G4X(dev))
-                hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
-
-        hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
-
         for (i = 0; i < tries ; i++) {
                 unsigned long timeout;
                 /* turn on the FORCE_DETECT */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cc8131ff319f..5e21b3119824 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -862,8 +862,8 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
         intel_clock_t clock;
         int max_n;
         bool found;
-        /* approximately equals target * 0.00488 */
-        int err_most = (target >> 8) + (target >> 10);
+        /* approximately equals target * 0.00585 */
+        int err_most = (target >> 8) + (target >> 9);
         found = false;
 
         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
@@ -1180,8 +1180,12 @@ static void intel_update_fbc(struct drm_crtc *crtc,
         struct drm_framebuffer *fb = crtc->fb;
         struct intel_framebuffer *intel_fb;
         struct drm_i915_gem_object *obj_priv;
+        struct drm_crtc *tmp_crtc;
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
         int plane = intel_crtc->plane;
+        int crtcs_enabled = 0;
+
+        DRM_DEBUG_KMS("\n");
 
         if (!i915_powersave)
                 return;
@@ -1199,10 +1203,21 @@ static void intel_update_fbc(struct drm_crtc *crtc,
          * If FBC is already on, we just have to verify that we can
          * keep it that way...
          * Need to disable if:
+         *   - more than one pipe is active
          *   - changing FBC params (stride, fence, mode)
          *   - new fb is too large to fit in compressed buffer
          *   - going to an unsupported config (interlace, pixel multiply, etc.)
          */
+        list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
+                if (tmp_crtc->enabled)
+                        crtcs_enabled++;
+        }
+        DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
+        if (crtcs_enabled > 1) {
+                DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
+                dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
+                goto out_disable;
+        }
         if (intel_fb->obj->size > dev_priv->cfb_size) {
                 DRM_DEBUG_KMS("framebuffer too large, disabling "
                                 "compression\n");
@@ -1255,7 +1270,7 @@ out_disable:
         }
 }
 
-static int
+int
 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
 {
         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
@@ -2255,6 +2270,11 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
                         intel_wait_for_vblank(dev);
                 }
 
+                /* Don't disable pipe A or pipe A PLLs if needed */
+                if (pipeconf_reg == PIPEACONF &&
+                    (dev_priv->quirks & QUIRK_PIPEA_FORCE))
+                        goto skip_pipe_off;
+
                 /* Next, disable display pipes */
                 temp = I915_READ(pipeconf_reg);
                 if ((temp & PIPEACONF_ENABLE) != 0) {
@@ -2270,7 +2290,7 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
                         I915_READ(dpll_reg);
                 }
-
+        skip_pipe_off:
                 /* Wait for the clocks to turn off. */
                 udelay(150);
                 break;
@@ -2356,8 +2376,6 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
                 if (mode->clock * 3 > 27000 * 4)
                         return MODE_CLOCK_HIGH;
         }
-
-        drm_mode_set_crtcinfo(adjusted_mode, 0);
         return true;
 }
 
@@ -2970,11 +2988,13 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock,
                 if (srwm < 0)
                         srwm = 1;
                 srwm &= 0x3f;
-                I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
+                if (IS_I965GM(dev))
+                        I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
         } else {
                 /* Turn off self refresh if both pipes are enabled */
-                I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
-                                        & ~FW_BLC_SELF_EN);
+                if (IS_I965GM(dev))
+                        I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
+                                   & ~FW_BLC_SELF_EN);
         }
 
         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
@@ -3734,6 +3754,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                         if (dev_priv->lvds_dither) {
                                 if (HAS_PCH_SPLIT(dev)) {
                                         pipeconf |= PIPE_ENABLE_DITHER;
+                                        pipeconf &= ~PIPE_DITHER_TYPE_MASK;
                                         pipeconf |= PIPE_DITHER_TYPE_ST01;
                                 } else
                                         lvds |= LVDS_ENABLE_DITHER;
@@ -4410,7 +4431,8 @@ static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
 
                 /* Unlock panel regs */
-                I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
+                I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
+                           PANEL_UNLOCK_REGS);
 
                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
                 I915_WRITE(dpll_reg, dpll);
@@ -4453,7 +4475,8 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
 
                 /* Unlock panel regs */
-                I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
+                I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
+                           PANEL_UNLOCK_REGS);
 
                 dpll |= DISPLAY_RATE_SELECT_FPA1;
                 I915_WRITE(dpll_reg, dpll);
@@ -4483,6 +4506,7 @@ static void intel_idle_update(struct work_struct *work)
         struct drm_device *dev = dev_priv->dev;
         struct drm_crtc *crtc;
         struct intel_crtc *intel_crtc;
+        int enabled = 0;
 
         if (!i915_powersave)
                 return;
@@ -4491,21 +4515,22 @@ static void intel_idle_update(struct work_struct *work)
 
         i915_update_gfx_val(dev_priv);
 
-        if (IS_I945G(dev) || IS_I945GM(dev)) {
-                DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
-                I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
-        }
-
         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
                 /* Skip inactive CRTCs */
                 if (!crtc->fb)
                         continue;
 
+                enabled++;
                 intel_crtc = to_intel_crtc(crtc);
                 if (!intel_crtc->busy)
                         intel_decrease_pllclock(crtc);
         }
 
+        if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
+                DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
+                I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
+        }
+
         mutex_unlock(&dev->struct_mutex);
 }
 
@@ -4601,10 +4626,10 @@ static void intel_unpin_work_fn(struct work_struct *__work)
         kfree(work);
 }
 
-void intel_finish_page_flip(struct drm_device *dev, int pipe)
+static void do_intel_finish_page_flip(struct drm_device *dev,
+                                      struct drm_crtc *crtc)
 {
         drm_i915_private_t *dev_priv = dev->dev_private;
-        struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
         struct intel_unpin_work *work;
         struct drm_i915_gem_object *obj_priv;
@@ -4648,6 +4673,22 @@ void intel_finish_page_flip(struct drm_device *dev, int pipe)
         schedule_work(&work->work);
 }
 
+void intel_finish_page_flip(struct drm_device *dev, int pipe)
+{
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+
+        do_intel_finish_page_flip(dev, crtc);
+}
+
+void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
+{
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
+
+        do_intel_finish_page_flip(dev, crtc);
+}
+
 void intel_prepare_page_flip(struct drm_device *dev, int plane)
 {
         drm_i915_private_t *dev_priv = dev->dev_private;
@@ -4675,9 +4716,10 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
         struct drm_gem_object *obj;
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
         struct intel_unpin_work *work;
-        unsigned long flags;
+        unsigned long flags, offset;
         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
         int ret, pipesrc;
+        u32 flip_mask;
 
         work = kzalloc(sizeof *work, GFP_KERNEL);
         if (work == NULL)
@@ -4731,16 +4773,33 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
         atomic_inc(&obj_priv->pending_flip);
         work->pending_flip_obj = obj;
 
+        if (intel_crtc->plane)
+                flip_mask = I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
+        else
+                flip_mask = I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
+
+        /* Wait for any previous flip to finish */
+        if (IS_GEN3(dev))
+                while (I915_READ(ISR) & flip_mask)
+                        ;
+
+        /* Offset into the new buffer for cases of shared fbs between CRTCs */
+        offset = obj_priv->gtt_offset;
+        offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
+
         BEGIN_LP_RING(4);
-        OUT_RING(MI_DISPLAY_FLIP |
-                 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
-        OUT_RING(fb->pitch);
         if (IS_I965G(dev)) {
-                OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
+                OUT_RING(MI_DISPLAY_FLIP |
+                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
+                OUT_RING(fb->pitch);
+                OUT_RING(offset | obj_priv->tiling_mode);
                 pipesrc = I915_READ(pipesrc_reg); 
                 OUT_RING(pipesrc & 0x0fff0fff);
         } else {
-                OUT_RING(obj_priv->gtt_offset);
+                OUT_RING(MI_DISPLAY_FLIP_I915 |
+                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
+                OUT_RING(fb->pitch);
+                OUT_RING(offset);
                 OUT_RING(MI_NOOP);
         }
         ADVANCE_LP_RING();
@@ -5472,6 +5531,66 @@ static void intel_init_display(struct drm_device *dev)
         }
 }
 
+/*
+ * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
+ * resume, or other times.  This quirk makes sure that's the case for
+ * affected systems.
+ */
+static void quirk_pipea_force (struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        dev_priv->quirks |= QUIRK_PIPEA_FORCE;
+        DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
+}
+
+struct intel_quirk {
+        int device;
+        int subsystem_vendor;
+        int subsystem_device;
+        void (*hook)(struct drm_device *dev);
+};
+
+struct intel_quirk intel_quirks[] = {
+        /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
+        { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
+        /* HP Mini needs pipe A force quirk (LP: #322104) */
+        { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
+
+        /* Thinkpad R31 needs pipe A force quirk */
+        { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
+        /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
+        { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
+
+        /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
+        { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
+        /* ThinkPad X40 needs pipe A force quirk */
+
+        /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
+        { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
+
+        /* 855 & before need to leave pipe A & dpll A up */
+        { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
+        { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
+};
+
+static void intel_init_quirks(struct drm_device *dev)
+{
+        struct pci_dev *d = dev->pdev;
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
+                struct intel_quirk *q = &intel_quirks[i];
+
+                if (d->device == q->device &&
+                    (d->subsystem_vendor == q->subsystem_vendor ||
+                     q->subsystem_vendor == PCI_ANY_ID) &&
+                    (d->subsystem_device == q->subsystem_device ||
+                     q->subsystem_device == PCI_ANY_ID))
+                        q->hook(dev);
+        }
+}
+
 void intel_modeset_init(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5484,6 +5603,8 @@ void intel_modeset_init(struct drm_device *dev)
 
         dev->mode_config.funcs = (void *)&intel_mode_funcs;
 
+        intel_init_quirks(dev);
+
         intel_init_display(dev);
 
         if (IS_I965G(dev)) {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 49b54f05d3cf..5dde80f9e652 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -136,6 +136,12 @@ intel_dp_link_required(struct drm_device *dev,
 }
 
 static int
+intel_dp_max_data_rate(int max_link_clock, int max_lanes)
+{
+        return (max_link_clock * max_lanes * 8) / 10;
+}
+
+static int
 intel_dp_mode_valid(struct drm_connector *connector,
                     struct drm_display_mode *mode)
 {
@@ -144,8 +150,11 @@ intel_dp_mode_valid(struct drm_connector *connector,
         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder));
         int max_lanes = intel_dp_max_lane_count(intel_encoder);
 
-        if (intel_dp_link_required(connector->dev, intel_encoder, mode->clock)
-                        > max_link_clock * max_lanes)
+        /* only refuse the mode on non eDP since we have seen some wierd eDP panels
+           which are outside spec tolerances but somehow work by magic */
+        if (!IS_eDP(intel_encoder) &&
+            (intel_dp_link_required(connector->dev, intel_encoder, mode->clock)
+             > intel_dp_max_data_rate(max_link_clock, max_lanes)))
                 return MODE_CLOCK_HIGH;
 
         if (mode->clock < 10000)
@@ -506,7 +515,7 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 
         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
                 for (clock = 0; clock <= max_clock; clock++) {
-                        int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
+                        int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 
                         if (intel_dp_link_required(encoder->dev, intel_encoder, mode->clock)
                                         <= link_avail) {
@@ -521,6 +530,18 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
                         }
                 }
         }
+
+        if (IS_eDP(intel_encoder)) {
+                /* okay we failed just pick the highest */
+                dp_priv->lane_count = max_lane_count;
+                dp_priv->link_bw = bws[max_clock];
+                adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
+                DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
+                              "count %d clock %d\n",
+                              dp_priv->link_bw, dp_priv->lane_count,
+                              adjusted_mode->clock);
+                return true;
+        }
         return false;
 }
 
@@ -696,6 +717,51 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
         }
 }
 
+static void ironlake_edp_panel_on (struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        unsigned long timeout = jiffies + msecs_to_jiffies(5000);
+        u32 pp, pp_status;
+
+        pp_status = I915_READ(PCH_PP_STATUS);
+        if (pp_status & PP_ON)
+                return;
+
+        pp = I915_READ(PCH_PP_CONTROL);
+        pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
+        I915_WRITE(PCH_PP_CONTROL, pp);
+        do {
+                pp_status = I915_READ(PCH_PP_STATUS);
+        } while (((pp_status & PP_ON) == 0) && !time_after(jiffies, timeout));
+
+        if (time_after(jiffies, timeout))
+                DRM_DEBUG_KMS("panel on wait timed out: 0x%08x\n", pp_status);
+
+        pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD);
+        I915_WRITE(PCH_PP_CONTROL, pp);
+}
+
+static void ironlake_edp_panel_off (struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        unsigned long timeout = jiffies + msecs_to_jiffies(5000);
+        u32 pp, pp_status;
+
+        pp = I915_READ(PCH_PP_CONTROL);
+        pp &= ~POWER_TARGET_ON;
+        I915_WRITE(PCH_PP_CONTROL, pp);
+        do {
+                pp_status = I915_READ(PCH_PP_STATUS);
+        } while ((pp_status & PP_ON) && !time_after(jiffies, timeout));
+
+        if (time_after(jiffies, timeout))
+                DRM_DEBUG_KMS("panel off wait timed out\n");
+
+        /* Make sure VDD is enabled so DP AUX will work */
+        pp |= EDP_FORCE_VDD;
+        I915_WRITE(PCH_PP_CONTROL, pp);
+}
+
 static void ironlake_edp_backlight_on (struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -730,14 +796,18 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
         if (mode != DRM_MODE_DPMS_ON) {
                 if (dp_reg & DP_PORT_EN) {
                         intel_dp_link_down(intel_encoder, dp_priv->DP);
-                        if (IS_eDP(intel_encoder))
+                        if (IS_eDP(intel_encoder)) {
                                 ironlake_edp_backlight_off(dev);
+                                ironlake_edp_panel_off(dev);
+                        }
                 }
         } else {
                 if (!(dp_reg & DP_PORT_EN)) {
                         intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
-                        if (IS_eDP(intel_encoder))
+                        if (IS_eDP(intel_encoder)) {
+                                ironlake_edp_panel_on(dev);
                                 ironlake_edp_backlight_on(dev);
+                        }
                 }
         }
         dp_priv->dpms_mode = mode;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index df931f787665..2f7970be9051 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -215,6 +215,9 @@ extern void intel_init_clock_gating(struct drm_device *dev);
 extern void ironlake_enable_drps(struct drm_device *dev);
 extern void ironlake_disable_drps(struct drm_device *dev);
 
+extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
+                                      struct drm_gem_object *obj);
+
 extern int intel_framebuffer_init(struct drm_device *dev,
                                   struct intel_framebuffer *ifb,
                                   struct drm_mode_fb_cmd *mode_cmd,
@@ -224,6 +227,7 @@ extern void intel_fbdev_fini(struct drm_device *dev);
 
 extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
 extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
+extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
 
 extern void intel_setup_overlay(struct drm_device *dev);
 extern void intel_cleanup_overlay(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index c3c505244e07..3e18c9e7729b 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -98,7 +98,7 @@ static int intelfb_create(struct intel_fbdev *ifbdev,
 
         mutex_lock(&dev->struct_mutex);
 
-        ret = i915_gem_object_pin(fbo, 64*1024);
+        ret = intel_pin_and_fence_fb_obj(dev, fbo);
         if (ret) {
                 DRM_ERROR("failed to pin fb: %d\n", ret);
                 goto out_unref;
@@ -236,7 +236,7 @@ int intel_fbdev_destroy(struct drm_device *dev,
 
         drm_framebuffer_cleanup(&ifb->base);
         if (ifb->obj)
-                drm_gem_object_unreference_unlocked(ifb->obj);
+                drm_gem_object_unreference(ifb->obj);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 6a1accd83aec..0eab8df5bf7e 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -599,6 +599,26 @@ static int intel_lvds_get_modes(struct drm_connector *connector)
         return 0;
 }
 
+static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
+{
+        DRM_DEBUG_KMS("Skipping forced modeset for %s\n", id->ident);
+        return 1;
+}
+
+/* The GPU hangs up on these systems if modeset is performed on LID open */
+static const struct dmi_system_id intel_no_modeset_on_lid[] = {
+        {
+                .callback = intel_no_modeset_on_lid_dmi_callback,
+                .ident = "Toshiba Tecra A11",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
+                },
+        },
+
+        { }     /* terminating entry */
+};
+
 /*
  * Lid events. Note the use of 'modeset_on_lid':
  *  - we set it on lid close, and reset it on open
@@ -622,6 +642,9 @@ static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
          */
         if (connector)
                 connector->status = connector->funcs->detect(connector);
+        /* Don't force modeset on machines where it causes a GPU lockup */
+        if (dmi_check_system(intel_no_modeset_on_lid))
+                return NOTIFY_OK;
         if (!acpi_lid_open()) {
                 dev_priv->modeset_on_lid = 1;
                 return NOTIFY_OK;
@@ -983,8 +1006,8 @@ void intel_lvds_init(struct drm_device *dev)
 
         drm_connector_attach_property(&intel_connector->base,
                                       dev->mode_config.scaling_mode_property,
-                                      DRM_MODE_SCALE_FULLSCREEN);
-        lvds_priv->fitting_mode = DRM_MODE_SCALE_FULLSCREEN;
+                                      DRM_MODE_SCALE_ASPECT);
+        lvds_priv->fitting_mode = DRM_MODE_SCALE_ASPECT;
         /*
          * LVDS discovery:
          * 1) check for EDID on DDC
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index cea4f1a8709e..26362f8495a8 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -94,7 +94,7 @@ render_ring_flush(struct drm_device *dev,
 #if WATCH_EXEC
                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
 #endif
-                intel_ring_begin(dev, ring, 8);
+                intel_ring_begin(dev, ring, 2);
                 intel_ring_emit(dev, ring, cmd);
                 intel_ring_emit(dev, ring, MI_NOOP);
                 intel_ring_advance(dev, ring);
@@ -358,7 +358,7 @@ bsd_ring_flush(struct drm_device *dev,
                 u32     invalidate_domains,
                 u32     flush_domains)
 {
-        intel_ring_begin(dev, ring, 8);
+        intel_ring_begin(dev, ring, 2);
         intel_ring_emit(dev, ring, MI_FLUSH);
         intel_ring_emit(dev, ring, MI_NOOP);
         intel_ring_advance(dev, ring);
@@ -687,6 +687,7 @@ int intel_wrap_ring_buffer(struct drm_device *dev,
                 *virt++ = MI_NOOP;
 
         ring->tail = 0;
+        ring->space = ring->head - 8;
 
         return 0;
 }
@@ -721,8 +722,9 @@ int intel_wait_ring_buffer(struct drm_device *dev,
 }
 
 void intel_ring_begin(struct drm_device *dev,
-                struct intel_ring_buffer *ring, int n)
+                struct intel_ring_buffer *ring, int num_dwords)
 {
+        int n = 4*num_dwords;
         if (unlikely(ring->tail + n > ring->size))
                 intel_wrap_ring_buffer(dev, ring);
         if (unlikely(ring->space < n))
@@ -752,7 +754,7 @@ void intel_fill_struct(struct drm_device *dev,
 {
         unsigned int *virt = ring->virtual_start + ring->tail;
         BUG_ON((len&~(4-1)) != 0);
-        intel_ring_begin(dev, ring, len);
+        intel_ring_begin(dev, ring, len/4);
         memcpy(virt, data, len);
         ring->tail += len;
         ring->tail &= ring->size - 1;
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index fc924b649195..e492919faf44 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -203,36 +203,26 @@ struct methods {
         const bool rw;
 };
 
-static struct methods nv04_methods[] = {
-        { "PROM", load_vbios_prom, false },
-        { "PRAMIN", load_vbios_pramin, true },
-        { "PCIROM", load_vbios_pci, true },
-};
-
-static struct methods nv50_methods[] = {
-        { "ACPI", load_vbios_acpi, true },
+static struct methods shadow_methods[] = {
         { "PRAMIN", load_vbios_pramin, true },
         { "PROM", load_vbios_prom, false },
         { "PCIROM", load_vbios_pci, true },
+        { "ACPI", load_vbios_acpi, true },
 };
 
-#define METHODCNT 3
-
 static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
 {
-        struct drm_nouveau_private *dev_priv = dev->dev_private;
-        struct methods *methods;
-        int i;
+        const int nr_methods = ARRAY_SIZE(shadow_methods);
+        struct methods *methods = shadow_methods;
         int testscore = 3;
-        int scores[METHODCNT];
+        int scores[nr_methods], i;
 
         if (nouveau_vbios) {
-                methods = nv04_methods;
-                for (i = 0; i < METHODCNT; i++)
+                for (i = 0; i < nr_methods; i++)
                         if (!strcasecmp(nouveau_vbios, methods[i].desc))
                                 break;
 
-                if (i < METHODCNT) {
+                if (i < nr_methods) {
                         NV_INFO(dev, "Attempting to use BIOS image from %s\n",
                                 methods[i].desc);
 
@@ -244,12 +234,7 @@ static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
                 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
         }
 
-        if (dev_priv->card_type < NV_50)
-                methods = nv04_methods;
-        else
-                methods = nv50_methods;
-
-        for (i = 0; i < METHODCNT; i++) {
+        for (i = 0; i < nr_methods; i++) {
                 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
                          methods[i].desc);
                 data[0] = data[1] = 0;  /* avoid reuse of previous image */
@@ -260,7 +245,7 @@ static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
         }
 
         while (--testscore > 0) {
-                for (i = 0; i < METHODCNT; i++) {
+                for (i = 0; i < nr_methods; i++) {
                         if (scores[i] == testscore) {
                                 NV_TRACE(dev, "Using BIOS image from %s\n",
                                          methods[i].desc);
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index c9a4a0d2a115..257ea130ae13 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -387,7 +387,8 @@ int nouveau_fbcon_init(struct drm_device *dev)
         dev_priv->nfbdev = nfbdev;
         nfbdev->helper.funcs = &nouveau_fbcon_helper_funcs;
 
-        ret = drm_fb_helper_init(dev, &nfbdev->helper, 2, 4);
+        ret = drm_fb_helper_init(dev, &nfbdev->helper,
+                                 nv_two_heads(dev) ? 2 : 1, 4);
         if (ret) {
                 kfree(nfbdev);
                 return ret;
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index f3f2827017ef..8c2d6478a221 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -498,7 +498,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
                 if ((rdev->family == CHIP_RS600) ||
                     (rdev->family == CHIP_RS690) ||
                     (rdev->family == CHIP_RS740))
-                        pll->flags |= (RADEON_PLL_USE_FRAC_FB_DIV |
+                        pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
                                        RADEON_PLL_PREFER_CLOSEST_LOWER);
 
                 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)        /* range limits??? */
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 4b6623df3b96..1caf625e472b 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -607,7 +607,7 @@ static void evergreen_mc_program(struct radeon_device *rdev)
         WREG32(MC_VM_FB_LOCATION, tmp);
         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
-        WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
+        WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
         if (rdev->flags & RADEON_IS_AGP) {
                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
@@ -1222,11 +1222,11 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
                 ps_thread_count = 128;
 
         sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
-        sq_thread_resource_mgmt |= NUM_VS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
-        sq_thread_resource_mgmt |= NUM_GS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
-        sq_thread_resource_mgmt |= NUM_ES_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
-        sq_thread_resource_mgmt_2 = NUM_HS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
-        sq_thread_resource_mgmt_2 |= NUM_LS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
+        sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
+        sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
+        sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
+        sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
+        sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
 
         sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
         sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
@@ -1260,6 +1260,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
         WREG32(VGT_GS_VERTEX_REUSE, 16);
         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
 
+        WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
+        WREG32(VGT_OUT_DEALLOC_CNTL, 16);
+
         WREG32(CB_PERF_CTR0_SEL_0, 0);
         WREG32(CB_PERF_CTR0_SEL_1, 0);
         WREG32(CB_PERF_CTR1_SEL_0, 0);
@@ -1269,6 +1272,26 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
         WREG32(CB_PERF_CTR3_SEL_0, 0);
         WREG32(CB_PERF_CTR3_SEL_1, 0);
 
+        /* clear render buffer base addresses */
+        WREG32(CB_COLOR0_BASE, 0);
+        WREG32(CB_COLOR1_BASE, 0);
+        WREG32(CB_COLOR2_BASE, 0);
+        WREG32(CB_COLOR3_BASE, 0);
+        WREG32(CB_COLOR4_BASE, 0);
+        WREG32(CB_COLOR5_BASE, 0);
+        WREG32(CB_COLOR6_BASE, 0);
+        WREG32(CB_COLOR7_BASE, 0);
+        WREG32(CB_COLOR8_BASE, 0);
+        WREG32(CB_COLOR9_BASE, 0);
+        WREG32(CB_COLOR10_BASE, 0);
+        WREG32(CB_COLOR11_BASE, 0);
+
+        /* set the shader const cache sizes to 0 */
+        for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
+                WREG32(i, 0);
+        for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
+                WREG32(i, 0);
+
         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
 
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 64516b950891..345a75a03c96 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -333,7 +333,6 @@ static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
         header = radeon_get_ib_value(p, h_idx);
         crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
         reg = CP_PACKET0_GET_REG(header);
-        mutex_lock(&p->rdev->ddev->mode_config.mutex);
         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
         if (!obj) {
                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
@@ -368,7 +367,6 @@ static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
                 }
         }
 out:
-        mutex_unlock(&p->rdev->ddev->mode_config.mutex);
         return r;
 }
 
@@ -1197,7 +1195,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                                         DRM_ERROR("bad SET_RESOURCE (tex)\n");
                                         return -EINVAL;
                                 }
-                                ib[idx+1+(i*8)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+                                ib[idx+1+(i*8)+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
                                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
                                         ib[idx+1+(i*8)+1] |= TEX_ARRAY_MODE(ARRAY_2D_TILED_THIN1);
                                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
@@ -1209,7 +1207,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                                         DRM_ERROR("bad SET_RESOURCE (tex)\n");
                                         return -EINVAL;
                                 }
-                                ib[idx+1+(i*8)+4] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+                                ib[idx+1+(i*8)+3] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
                                 mipmap = reloc->robj;
                                 r = evergreen_check_texture_resource(p,  idx+1+(i*8),
                                                 texture, mipmap);
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 79683f6b4452..a1cd621780e2 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -713,6 +713,9 @@
 #define SQ_GSVS_RING_OFFSET_2                           0x28930
 #define SQ_GSVS_RING_OFFSET_3                           0x28934
 
+#define SQ_ALU_CONST_BUFFER_SIZE_PS_0                   0x28140
+#define SQ_ALU_CONST_BUFFER_SIZE_HS_0                   0x28f80
+
 #define SQ_ALU_CONST_CACHE_PS_0                         0x28940
 #define SQ_ALU_CONST_CACHE_PS_1                         0x28944
 #define SQ_ALU_CONST_CACHE_PS_2                         0x28948
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index cf89aa2eb28c..a89a15ab524d 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1230,7 +1230,6 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
         header = radeon_get_ib_value(p, h_idx);
         crtc_id = radeon_get_ib_value(p, h_idx + 5);
         reg = CP_PACKET0_GET_REG(header);
-        mutex_lock(&p->rdev->ddev->mode_config.mutex);
         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
         if (!obj) {
                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
@@ -1264,7 +1263,6 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
         }
 out:
-        mutex_unlock(&p->rdev->ddev->mode_config.mutex);
         return r;
 }
 
@@ -1628,6 +1626,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                 case RADEON_TXFORMAT_RGB332:
                 case RADEON_TXFORMAT_Y8:
                         track->textures[i].cpp = 1;
+                        track->textures[i].compress_format = R100_TRACK_COMP_NONE;
                         break;
                 case RADEON_TXFORMAT_AI88:
                 case RADEON_TXFORMAT_ARGB1555:
@@ -1639,12 +1638,14 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                 case RADEON_TXFORMAT_LDUDV655:
                 case RADEON_TXFORMAT_DUDV88:
                         track->textures[i].cpp = 2;
+                        track->textures[i].compress_format = R100_TRACK_COMP_NONE;
                         break;
                 case RADEON_TXFORMAT_ARGB8888:
                 case RADEON_TXFORMAT_RGBA8888:
                 case RADEON_TXFORMAT_SHADOW32:
                 case RADEON_TXFORMAT_LDUDUV8888:
                         track->textures[i].cpp = 4;
+                        track->textures[i].compress_format = R100_TRACK_COMP_NONE;
                         break;
                 case RADEON_TXFORMAT_DXT1:
                         track->textures[i].cpp = 1;
@@ -2351,6 +2352,7 @@ void r100_mc_init(struct radeon_device *rdev)
         if (rdev->flags & RADEON_IS_IGP)
                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
         radeon_vram_location(rdev, &rdev->mc, base);
+        rdev->mc.gtt_base_align = 0;
         if (!(rdev->flags & RADEON_IS_AGP))
                 radeon_gtt_location(rdev, &rdev->mc);
         radeon_update_bandwidth_info(rdev);
@@ -2604,12 +2606,6 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg,
         int surf_index = reg * 16;
         int flags = 0;
 
-        /* r100/r200 divide by 16 */
-        if (rdev->family < CHIP_R300)
-                flags = pitch / 16;
-        else
-                flags = pitch / 8;
-
         if (rdev->family <= CHIP_RS200) {
                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
@@ -2633,6 +2629,20 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg,
         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
 
+        /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
+        if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
+                if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
+                        if (ASIC_IS_RN50(rdev))
+                                pitch /= 16;
+        }
+
+        /* r100/r200 divide by 16 */
+        if (rdev->family < CHIP_R300)
+                flags |= pitch / 16;
+        else
+                flags |= pitch / 8;
+
+
         DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
@@ -3147,33 +3157,6 @@ static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
         DRM_ERROR("compress format            %d\n", t->compress_format);
 }
 
-static int r100_cs_track_cube(struct radeon_device *rdev,
-                              struct r100_cs_track *track, unsigned idx)
-{
-        unsigned face, w, h;
-        struct radeon_bo *cube_robj;
-        unsigned long size;
-
-        for (face = 0; face < 5; face++) {
-                cube_robj = track->textures[idx].cube_info[face].robj;
-                w = track->textures[idx].cube_info[face].width;
-                h = track->textures[idx].cube_info[face].height;
-
-                size = w * h;
-                size *= track->textures[idx].cpp;
-
-                size += track->textures[idx].cube_info[face].offset;
-
-                if (size > radeon_bo_size(cube_robj)) {
-                        DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
-                                  size, radeon_bo_size(cube_robj));
-                        r100_cs_track_texture_print(&track->textures[idx]);
-                        return -1;
-                }
-        }
-        return 0;
-}
-
 static int r100_track_compress_size(int compress_format, int w, int h)
 {
         int block_width, block_height, block_bytes;
@@ -3204,6 +3187,37 @@ static int r100_track_compress_size(int compress_format, int w, int h)
         return sz;
 }
 
+static int r100_cs_track_cube(struct radeon_device *rdev,
+                              struct r100_cs_track *track, unsigned idx)
+{
+        unsigned face, w, h;
+        struct radeon_bo *cube_robj;
+        unsigned long size;
+        unsigned compress_format = track->textures[idx].compress_format;
+
+        for (face = 0; face < 5; face++) {
+                cube_robj = track->textures[idx].cube_info[face].robj;
+                w = track->textures[idx].cube_info[face].width;
+                h = track->textures[idx].cube_info[face].height;
+
+                if (compress_format) {
+                        size = r100_track_compress_size(compress_format, w, h);
+                } else
+                        size = w * h;
+                size *= track->textures[idx].cpp;
+
+                size += track->textures[idx].cube_info[face].offset;
+
+                if (size > radeon_bo_size(cube_robj)) {
+                        DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
+                                  size, radeon_bo_size(cube_robj));
+                        r100_cs_track_texture_print(&track->textures[idx]);
+                        return -1;
+                }
+        }
+        return 0;
+}
+
 static int r100_cs_track_texture_check(struct radeon_device *rdev,
                                        struct r100_cs_track *track)
 {
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c
index 85617c311212..0266d72e0a4c 100644
--- a/drivers/gpu/drm/radeon/r200.c
+++ b/drivers/gpu/drm/radeon/r200.c
@@ -415,6 +415,8 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                 /* 2D, 3D, CUBE */
                 switch (tmp) {
                 case 0:
+                case 3:
+                case 4:
                 case 5:
                 case 6:
                 case 7:
@@ -450,6 +452,7 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                 case R200_TXFORMAT_RGB332:
                 case R200_TXFORMAT_Y8:
                         track->textures[i].cpp = 1;
+                        track->textures[i].compress_format = R100_TRACK_COMP_NONE;
                         break;
                 case R200_TXFORMAT_AI88:
                 case R200_TXFORMAT_ARGB1555:
@@ -461,6 +464,7 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                 case R200_TXFORMAT_DVDU88:
                 case R200_TXFORMAT_AVYU4444:
                         track->textures[i].cpp = 2;
+                        track->textures[i].compress_format = R100_TRACK_COMP_NONE;
                         break;
                 case R200_TXFORMAT_ARGB8888:
                 case R200_TXFORMAT_RGBA8888:
@@ -468,6 +472,7 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                 case R200_TXFORMAT_BGR111110:
                 case R200_TXFORMAT_LDVDU8888:
                         track->textures[i].cpp = 4;
+                        track->textures[i].compress_format = R100_TRACK_COMP_NONE;
                         break;
                 case R200_TXFORMAT_DXT1:
                         track->textures[i].cpp = 1;
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index b2f9efe2897c..19a7ef7ee344 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -481,6 +481,7 @@ void r300_mc_init(struct radeon_device *rdev)
         if (rdev->flags & RADEON_IS_IGP)
                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
         radeon_vram_location(rdev, &rdev->mc, base);
+        rdev->mc.gtt_base_align = 0;
         if (!(rdev->flags & RADEON_IS_AGP))
                 radeon_gtt_location(rdev, &rdev->mc);
         radeon_update_bandwidth_info(rdev);
@@ -881,6 +882,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                 case R300_TX_FORMAT_Y4X4:
                 case R300_TX_FORMAT_Z3Y3X2:
                         track->textures[i].cpp = 1;
+                        track->textures[i].compress_format = R100_TRACK_COMP_NONE;
                         break;
                 case R300_TX_FORMAT_X16:
                 case R300_TX_FORMAT_Y8X8:
@@ -892,6 +894,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                 case R300_TX_FORMAT_B8G8_B8G8:
                 case R300_TX_FORMAT_G8R8_G8B8:
                         track->textures[i].cpp = 2;
+                        track->textures[i].compress_format = R100_TRACK_COMP_NONE;
                         break;
                 case R300_TX_FORMAT_Y16X16:
                 case R300_TX_FORMAT_Z11Y11X10:
@@ -902,14 +905,17 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
                 case R300_TX_FORMAT_FL_I32:
                 case 0x1e:
                         track->textures[i].cpp = 4;
+                        track->textures[i].compress_format = R100_TRACK_COMP_NONE;
                         break;
                 case R300_TX_FORMAT_W16Z16Y16X16:
                 case R300_TX_FORMAT_FL_R16G16B16A16:
                 case R300_TX_FORMAT_FL_I32A32:
                         track->textures[i].cpp = 8;
+                        track->textures[i].compress_format = R100_TRACK_COMP_NONE;
                         break;
                 case R300_TX_FORMAT_FL_R32G32B32A32:
                         track->textures[i].cpp = 16;
+                        track->textures[i].compress_format = R100_TRACK_COMP_NONE;
                         break;
                 case R300_TX_FORMAT_DXT1:
                         track->textures[i].cpp = 1;
@@ -1171,6 +1177,8 @@ int r300_cs_parse(struct radeon_cs_parser *p)
         int r;
 
         track = kzalloc(sizeof(*track), GFP_KERNEL);
+        if (track == NULL)
+                return -ENOMEM;
         r100_cs_track_clear(p->rdev, track);
         p->track = track;
         do {
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index 34330df28483..694af7cc23ac 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -125,6 +125,7 @@ void r520_mc_init(struct radeon_device *rdev)
         r520_vram_get_type(rdev);
         r100_vram_init_sizes(rdev);
         radeon_vram_location(rdev, &rdev->mc, 0);
+        rdev->mc.gtt_base_align = 0;
         if (!(rdev->flags & RADEON_IS_AGP))
                 radeon_gtt_location(rdev, &rdev->mc);
         radeon_update_bandwidth_info(rdev);
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 0e91871f45be..e100f69faeec 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -130,9 +130,14 @@ void r600_pm_get_dynpm_state(struct radeon_device *rdev)
                                                         break;
                                                 }
                                         }
-                                } else
-                                        rdev->pm.requested_power_state_index =
-                                                rdev->pm.current_power_state_index - 1;
+                                } else {
+                                        if (rdev->pm.current_power_state_index == 0)
+                                                rdev->pm.requested_power_state_index =
+                                                        rdev->pm.num_power_states - 1;
+                                        else
+                                                rdev->pm.requested_power_state_index =
+                                                        rdev->pm.current_power_state_index - 1;
+                                }
                         }
                         rdev->pm.requested_clock_mode_index = 0;
                         /* don't use the power state if crtcs are active and no display flag is set */
@@ -1097,7 +1102,7 @@ static void r600_mc_program(struct radeon_device *rdev)
         WREG32(MC_VM_FB_LOCATION, tmp);
         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
-        WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
+        WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
         if (rdev->flags & RADEON_IS_AGP) {
                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
@@ -1174,6 +1179,7 @@ void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
                 if (rdev->flags & RADEON_IS_IGP)
                         base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
                 radeon_vram_location(rdev, &rdev->mc, base);
+                rdev->mc.gtt_base_align = 0;
                 radeon_gtt_location(rdev, mc);
         }
 }
@@ -1219,8 +1225,10 @@ int r600_mc_init(struct radeon_device *rdev)
         rdev->mc.visible_vram_size = rdev->mc.aper_size;
         r600_vram_gtt_location(rdev, &rdev->mc);
 
-        if (rdev->flags & RADEON_IS_IGP)
+        if (rdev->flags & RADEON_IS_IGP) {
+                rs690_pm_info(rdev);
                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
+        }
         radeon_update_bandwidth_info(rdev);
         return 0;
 }
diff --git a/drivers/gpu/drm/radeon/r600_blit.c b/drivers/gpu/drm/radeon/r600_blit.c
index f4fb88ece2bb..ca5c29f70779 100644
--- a/drivers/gpu/drm/radeon/r600_blit.c
+++ b/drivers/gpu/drm/radeon/r600_blit.c
@@ -538,9 +538,12 @@ int
 r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv)
 {
         drm_radeon_private_t *dev_priv = dev->dev_private;
+        int ret;
         DRM_DEBUG("\n");
 
-        r600_nomm_get_vb(dev);
+        ret = r600_nomm_get_vb(dev);
+        if (ret)
+                return ret;
 
         dev_priv->blit_vb->file_priv = file_priv;
 
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index c39c1bc13016..144c32d37136 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -585,7 +585,7 @@ static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
         header = radeon_get_ib_value(p, h_idx);
         crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
         reg = CP_PACKET0_GET_REG(header);
-        mutex_lock(&p->rdev->ddev->mode_config.mutex);
+
         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
         if (!obj) {
                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
@@ -620,7 +620,6 @@ static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
                 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
         }
 out:
-        mutex_unlock(&p->rdev->ddev->mode_config.mutex);
         return r;
 }
 
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 8e1d44ca26ec..2f94dc66c183 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -177,6 +177,7 @@ void radeon_pm_resume(struct radeon_device *rdev);
 void radeon_combios_get_power_modes(struct radeon_device *rdev);
 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level);
+void rs690_pm_info(struct radeon_device *rdev);
 
 /*
  * Fences.
@@ -350,6 +351,7 @@ struct radeon_mc {
         int                     vram_mtrr;
         bool                    vram_is_ddr;
         bool                    igp_sideport_enabled;
+        u64                     gtt_base_align;
 };
 
 bool radeon_combios_sideport_present(struct radeon_device *rdev);
@@ -619,7 +621,8 @@ enum radeon_dynpm_state {
         DYNPM_STATE_DISABLED,
         DYNPM_STATE_MINIMUM,
         DYNPM_STATE_PAUSED,
-        DYNPM_STATE_ACTIVE
+        DYNPM_STATE_ACTIVE,
+        DYNPM_STATE_SUSPENDED,
 };
 enum radeon_dynpm_action {
         DYNPM_ACTION_NONE,
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 87f7e2cc52d4..646f96f97c77 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -780,6 +780,13 @@ int radeon_asic_init(struct radeon_device *rdev)
         case CHIP_R423:
         case CHIP_RV410:
                 rdev->asic = &r420_asic;
+                /* handle macs */
+                if (rdev->bios == NULL) {
+                        rdev->asic->get_engine_clock = &radeon_legacy_get_engine_clock;
+                        rdev->asic->set_engine_clock = &radeon_legacy_set_engine_clock;
+                        rdev->asic->get_memory_clock = &radeon_legacy_get_memory_clock;
+                        rdev->asic->set_memory_clock = NULL;
+                }
                 break;
         case CHIP_RS400:
         case CHIP_RS480:
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 99bd8a9c56b3..10673ae59cfa 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -280,6 +280,15 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
                 }
         }
 
+        /* ASUS HD 3600 board lists the DVI port as HDMI */
+        if ((dev->pdev->device == 0x9598) &&
+            (dev->pdev->subsystem_vendor == 0x1043) &&
+            (dev->pdev->subsystem_device == 0x01e4)) {
+                if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
+                        *connector_type = DRM_MODE_CONNECTOR_DVII;
+                }
+        }
+
         /* ASUS HD 3450 board lists the DVI port as HDMI */
         if ((dev->pdev->device == 0x95C5) &&
             (dev->pdev->subsystem_vendor == 0x1043) &&
@@ -1029,8 +1038,15 @@ bool radeon_atombios_sideport_present(struct radeon_device *rdev)
                                       data_offset);
                 switch (crev) {
                 case 1:
-                        if (igp_info->info.ucMemoryType & 0xf0)
-                                return true;
+                        /* AMD IGPS */
+                        if ((rdev->family == CHIP_RS690) ||
+                            (rdev->family == CHIP_RS740)) {
+                                if (igp_info->info.ulBootUpMemoryClock)
+                                        return true;
+                        } else {
+                                if (igp_info->info.ucMemoryType & 0xf0)
+                                        return true;
+                        }
                         break;
                 case 2:
                         if (igp_info->info_2.ucMemoryType & 0x0f)
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index fbba938f8048..2c9213739999 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -48,6 +48,10 @@ static bool igp_read_bios_from_vram(struct radeon_device *rdev)
         resource_size_t vram_base;
         resource_size_t size = 256 * 1024; /* ??? */
 
+        if (!(rdev->flags & RADEON_IS_IGP))
+                if (!radeon_card_posted(rdev))
+                        return false;
+
         rdev->bios = NULL;
         vram_base = drm_get_resource_start(rdev->ddev, 0);
         bios = ioremap(vram_base, size);
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 1bee2f9e24a5..2417d7b06fdb 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -1411,6 +1411,11 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
                 } else
 #endif /* CONFIG_PPC_PMAC */
+#ifdef CONFIG_PPC64
+                if (ASIC_IS_RN50(rdev))
+                        rdev->mode_info.connector_table = CT_RN50_POWER;
+                else
+#endif
                         rdev->mode_info.connector_table = CT_GENERIC;
         }
 
@@ -1853,6 +1858,33 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                             CONNECTOR_OBJECT_ID_SVIDEO,
                                             &hpd);
                 break;
+        case CT_RN50_POWER:
+                DRM_INFO("Connector Table: %d (rn50-power)\n",
+                         rdev->mode_info.connector_table);
+                /* VGA - primary dac */
+                ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
+                hpd.hpd = RADEON_HPD_NONE;
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_CRT1_SUPPORT,
+                                                                1),
+                                          ATOM_DEVICE_CRT1_SUPPORT);
+                radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
+                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_VGA,
+                                            &hpd);
+                ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
+                hpd.hpd = RADEON_HPD_NONE;
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_CRT2_SUPPORT,
+                                                                2),
+                                          ATOM_DEVICE_CRT2_SUPPORT);
+                radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
+                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_VGA,
+                                            &hpd);
+                break;
         default:
                 DRM_INFO("Connector table: %d (invalid)\n",
                          rdev->mode_info.connector_table);
@@ -1906,15 +1938,6 @@ static bool radeon_apply_legacy_quirks(struct drm_device *dev,
                         return false;
         }
 
-        /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
-        if (dev->pdev->device == 0x5159 &&
-            dev->pdev->subsystem_vendor == 0x1002 &&
-            dev->pdev->subsystem_device == 0x013a) {
-                if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
-                        *legacy_connector = CONNECTOR_CRT_LEGACY;
-
-        }
-
         /* X300 card with extra non-existent DVI port */
         if (dev->pdev->device == 0x5B60 &&
             dev->pdev->subsystem_vendor == 0x17af &&
@@ -3019,6 +3042,22 @@ void radeon_combios_asic_init(struct drm_device *dev)
                 combios_write_ram_size(dev);
         }
 
+        /* quirk for rs4xx HP nx6125 laptop to make it resume
+         * - it hangs on resume inside the dynclk 1 table.
+         */
+        if (rdev->family == CHIP_RS480 &&
+            rdev->pdev->subsystem_vendor == 0x103c &&
+            rdev->pdev->subsystem_device == 0x308b)
+                return;
+
+        /* quirk for rs4xx HP dv5000 laptop to make it resume
+         * - it hangs on resume inside the dynclk 1 table.
+         */
+        if (rdev->family == CHIP_RS480 &&
+            rdev->pdev->subsystem_vendor == 0x103c &&
+            rdev->pdev->subsystem_device == 0x30a4)
+                return;
+
         /* DYN CLK 1 */
         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
         if (table)
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 0c7ccc6961a3..adccbc2c202c 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -771,30 +771,27 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
                         } else
                                 ret = connector_status_connected;
 
-                        /* multiple connectors on the same encoder with the same ddc line
-                         * This tends to be HDMI and DVI on the same encoder with the
-                         * same ddc line.  If the edid says HDMI, consider the HDMI port
-                         * connected and the DVI port disconnected.  If the edid doesn't
-                         * say HDMI, vice versa.
+                        /* This gets complicated.  We have boards with VGA + HDMI with a
+                         * shared DDC line and we have boards with DVI-D + HDMI with a shared
+                         * DDC line.  The latter is more complex because with DVI<->HDMI adapters
+                         * you don't really know what's connected to which port as both are digital.
                          */
                         if (radeon_connector->shared_ddc && (ret == connector_status_connected)) {
                                 struct drm_device *dev = connector->dev;
+                                struct radeon_device *rdev = dev->dev_private;
                                 struct drm_connector *list_connector;
                                 struct radeon_connector *list_radeon_connector;
                                 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) {
                                         if (connector == list_connector)
                                                 continue;
                                         list_radeon_connector = to_radeon_connector(list_connector);
-                                        if (radeon_connector->devices == list_radeon_connector->devices) {
-                                                if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
-                                                        if (connector->connector_type == DRM_MODE_CONNECTOR_DVID) {
-                                                                kfree(radeon_connector->edid);
-                                                                radeon_connector->edid = NULL;
-                                                                ret = connector_status_disconnected;
-                                                        }
-                                                } else {
-                                                        if ((connector->connector_type == DRM_MODE_CONNECTOR_HDMIA) ||
-                                                            (connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)) {
+                                        if (list_radeon_connector->shared_ddc &&
+                                            (list_radeon_connector->ddc_bus->rec.i2c_id ==
+                                             radeon_connector->ddc_bus->rec.i2c_id)) {
+                                                /* cases where both connectors are digital */
+                                                if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
+                                                        /* hpd is our only option in this case */
+                                                        if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) {
                                                                 kfree(radeon_connector->edid);
                                                                 radeon_connector->edid = NULL;
                                                                 ret = connector_status_disconnected;
diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c
index b7023fff89eb..4eb67c0e0996 100644
--- a/drivers/gpu/drm/radeon/radeon_cursor.c
+++ b/drivers/gpu/drm/radeon/radeon_cursor.c
@@ -194,7 +194,7 @@ unpin:
 fail:
         drm_gem_object_unreference_unlocked(obj);
 
-        return 0;
+        return ret;
 }
 
 int radeon_crtc_cursor_move(struct drm_crtc *crtc,
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index f10faed21567..dd279da90546 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -226,20 +226,20 @@ void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 {
         u64 size_af, size_bf;
 
-        size_af = 0xFFFFFFFF - mc->vram_end;
-        size_bf = mc->vram_start;
+        size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
+        size_bf = mc->vram_start & ~mc->gtt_base_align;
         if (size_bf > size_af) {
                 if (mc->gtt_size > size_bf) {
                         dev_warn(rdev->dev, "limiting GTT\n");
                         mc->gtt_size = size_bf;
                 }
-                mc->gtt_start = mc->vram_start - mc->gtt_size;
+                mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
         } else {
                 if (mc->gtt_size > size_af) {
                         dev_warn(rdev->dev, "limiting GTT\n");
                         mc->gtt_size = size_af;
                 }
-                mc->gtt_start = mc->vram_end + 1;
+                mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
         }
         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
         dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n",
@@ -779,6 +779,7 @@ int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
 
 int radeon_resume_kms(struct drm_device *dev)
 {
+        struct drm_connector *connector;
         struct radeon_device *rdev = dev->dev_private;
 
         if (rdev->powered_down)
@@ -797,6 +798,12 @@ int radeon_resume_kms(struct drm_device *dev)
         radeon_resume(rdev);
         radeon_pm_resume(rdev);
         radeon_restore_bios_scratch_regs(rdev);
+
+        /* turn on display hw */
+        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+                drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
+        }
+
         radeon_fbdev_set_suspend(rdev, 0);
         release_console_sem();
 
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 1ebb100015b7..e0b30b264c28 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -1072,6 +1072,8 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
         if (is_dig) {
                 switch (mode) {
                 case DRM_MODE_DPMS_ON:
+                        if (!ASIC_IS_DCE4(rdev))
+                                atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
                         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 
@@ -1079,8 +1081,6 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
                                 if (ASIC_IS_DCE4(rdev))
                                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
                         }
-                        if (!ASIC_IS_DCE4(rdev))
-                                atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
                         break;
                 case DRM_MODE_DPMS_STANDBY:
                 case DRM_MODE_DPMS_SUSPEND:
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index 6a70c0dc7f92..ab389f89fa8d 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -128,7 +128,8 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
                 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
                         crtc = (struct drm_crtc *)minfo->crtcs[i];
                         if (crtc && crtc->base.id == value) {
-                                value = i;
+                                struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+                                value = radeon_crtc->crtc_id;
                                 found = 1;
                                 break;
                         }
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index 5b07b8848e09..5688a0cf6bbe 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -108,6 +108,7 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
                 udelay(panel_pwr_delay * 1000);
                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
+                udelay(panel_pwr_delay * 1000);
                 break;
         }
 
@@ -928,16 +929,14 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
         if (ASIC_IS_R300(rdev)) {
                 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
                 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
-        }
-
-        if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev))
-                disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
-        else
+        } else if (rdev->family != CHIP_R200)
                 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
-
-        if (rdev->family == CHIP_R200)
+        else if (rdev->family == CHIP_R200)
                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 
+        if (rdev->family >= CHIP_R200)
+                disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
+
         if (is_tv) {
                 uint32_t dac_cntl;
 
@@ -1002,15 +1001,13 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
         if (ASIC_IS_R300(rdev)) {
                 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
                 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
-        }
+        } else if (rdev->family != CHIP_R200)
+                WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
+        else if (rdev->family == CHIP_R200)
+                WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 
         if (rdev->family >= CHIP_R200)
                 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
-        else
-                WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
-
-        if (rdev->family == CHIP_R200)
-                WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 
         if (is_tv)
                 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_tv.c b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
index f2ed27c8055b..032040397743 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_tv.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
@@ -642,8 +642,8 @@ void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
         }
         flicker_removal = (tmp + 500) / 1000;
 
-        if (flicker_removal < 2)
-                flicker_removal = 2;
+        if (flicker_removal < 3)
+                flicker_removal = 3;
         for (i = 0; i < ARRAY_SIZE(SLOPE_limit); ++i) {
                 if (flicker_removal == SLOPE_limit[i])
                         break;
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 67358baf28b2..95696aa57ac8 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -206,6 +206,7 @@ enum radeon_connector_table {
         CT_MINI_INTERNAL,
         CT_IMAC_G5_ISIGHT,
         CT_EMAC,
+        CT_RN50_POWER,
 };
 
 enum radeon_dvo_chip {
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 63f679a04b25..3fa6984d9896 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -333,6 +333,7 @@ static ssize_t radeon_get_pm_profile(struct device *dev,
         return snprintf(buf, PAGE_SIZE, "%s\n",
                         (cp == PM_PROFILE_AUTO) ? "auto" :
                         (cp == PM_PROFILE_LOW) ? "low" :
+                        (cp == PM_PROFILE_MID) ? "mid" :
                         (cp == PM_PROFILE_HIGH) ? "high" : "default");
 }
 
@@ -397,13 +398,20 @@ static ssize_t radeon_set_pm_method(struct device *dev,
                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
                 mutex_unlock(&rdev->pm.mutex);
         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
+                bool flush_wq = false;
+
                 mutex_lock(&rdev->pm.mutex);
-                rdev->pm.pm_method = PM_METHOD_PROFILE;
+                if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
+                        cancel_delayed_work(&rdev->pm.dynpm_idle_work);
+                        flush_wq = true;
+                }
                 /* disable dynpm */
                 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
-                cancel_delayed_work(&rdev->pm.dynpm_idle_work);
+                rdev->pm.pm_method = PM_METHOD_PROFILE;
                 mutex_unlock(&rdev->pm.mutex);
+                if (flush_wq)
+                        flush_workqueue(rdev->wq);
         } else {
                 DRM_ERROR("invalid power method!\n");
                 goto fail;
@@ -418,9 +426,18 @@ static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon
 
 void radeon_pm_suspend(struct radeon_device *rdev)
 {
+        bool flush_wq = false;
+
         mutex_lock(&rdev->pm.mutex);
-        cancel_delayed_work(&rdev->pm.dynpm_idle_work);
+        if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
+                cancel_delayed_work(&rdev->pm.dynpm_idle_work);
+                if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
+                        rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
+                flush_wq = true;
+        }
         mutex_unlock(&rdev->pm.mutex);
+        if (flush_wq)
+                flush_workqueue(rdev->wq);
 }
 
 void radeon_pm_resume(struct radeon_device *rdev)
@@ -432,6 +449,12 @@ void radeon_pm_resume(struct radeon_device *rdev)
         rdev->pm.current_sclk = rdev->clock.default_sclk;
         rdev->pm.current_mclk = rdev->clock.default_mclk;
         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
+        if (rdev->pm.pm_method == PM_METHOD_DYNPM
+            && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
+                rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
+                queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
+                                        msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
+        }
         mutex_unlock(&rdev->pm.mutex);
         radeon_pm_compute_clocks(rdev);
 }
@@ -486,6 +509,8 @@ int radeon_pm_init(struct radeon_device *rdev)
 void radeon_pm_fini(struct radeon_device *rdev)
 {
         if (rdev->pm.num_power_states > 1) {
+                bool flush_wq = false;
+
                 mutex_lock(&rdev->pm.mutex);
                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
                         rdev->pm.profile = PM_PROFILE_DEFAULT;
@@ -493,13 +518,16 @@ void radeon_pm_fini(struct radeon_device *rdev)
                         radeon_pm_set_clocks(rdev);
                 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
                         /* cancel work */
-                        cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
+                        cancel_delayed_work(&rdev->pm.dynpm_idle_work);
+                        flush_wq = true;
                         /* reset default clocks */
                         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
                         radeon_pm_set_clocks(rdev);
                 }
                 mutex_unlock(&rdev->pm.mutex);
+                if (flush_wq)
+                        flush_workqueue(rdev->wq);
 
                 device_remove_file(rdev->dev, &dev_attr_power_profile);
                 device_remove_file(rdev->dev, &dev_attr_power_method);
@@ -720,12 +748,12 @@ static void radeon_dynpm_idle_work_handler(struct work_struct *work)
                         radeon_pm_get_dynpm_state(rdev);
                         radeon_pm_set_clocks(rdev);
                 }
+
+                queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
+                                        msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
         }
         mutex_unlock(&rdev->pm.mutex);
         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
-
-        queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
-                                        msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 }
 
 /*
diff --git a/drivers/gpu/drm/radeon/reg_srcs/evergreen b/drivers/gpu/drm/radeon/reg_srcs/evergreen
index b5c757f68d3c..f78fd592544d 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/evergreen
+++ b/drivers/gpu/drm/radeon/reg_srcs/evergreen
@@ -80,8 +80,8 @@ evergreen 0x9400
 0x00028010 DB_RENDER_OVERRIDE2
 0x00028028 DB_STENCIL_CLEAR
 0x0002802C DB_DEPTH_CLEAR
-0x00028034 PA_SC_SCREEN_SCISSOR_BR
 0x00028030 PA_SC_SCREEN_SCISSOR_TL
+0x00028034 PA_SC_SCREEN_SCISSOR_BR
 0x0002805C DB_DEPTH_SLICE
 0x00028140 SQ_ALU_CONST_BUFFER_SIZE_PS_0
 0x00028144 SQ_ALU_CONST_BUFFER_SIZE_PS_1
@@ -460,8 +460,8 @@ evergreen 0x9400
 0x00028844 SQ_PGM_RESOURCES_PS
 0x00028848 SQ_PGM_RESOURCES_2_PS
 0x0002884C SQ_PGM_EXPORTS_PS
-0x0002885C SQ_PGM_RESOURCES_VS
-0x00028860 SQ_PGM_RESOURCES_2_VS
+0x00028860 SQ_PGM_RESOURCES_VS
+0x00028864 SQ_PGM_RESOURCES_2_VS
 0x00028878 SQ_PGM_RESOURCES_GS
 0x0002887C SQ_PGM_RESOURCES_2_GS
 0x00028890 SQ_PGM_RESOURCES_ES
@@ -469,8 +469,8 @@ evergreen 0x9400
 0x000288A8 SQ_PGM_RESOURCES_FS
 0x000288BC SQ_PGM_RESOURCES_HS
 0x000288C0 SQ_PGM_RESOURCES_2_HS
-0x000288D0 SQ_PGM_RESOURCES_LS
-0x000288D4 SQ_PGM_RESOURCES_2_LS
+0x000288D4 SQ_PGM_RESOURCES_LS
+0x000288D8 SQ_PGM_RESOURCES_2_LS
 0x000288E8 SQ_LDS_ALLOC
 0x000288EC SQ_LDS_ALLOC_PS
 0x000288F0 SQ_VTX_SEMANTIC_CLEAR
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index 9e4240b3bf0b..f454c9a5e7f2 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -57,7 +57,9 @@ void rs400_gart_adjust_size(struct radeon_device *rdev)
         }
         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
                 /* FIXME: RS400 & RS480 seems to have issue with GART size
-                 * if 4G of system memory (needs more testing) */
+                 * if 4G of system memory (needs more testing)
+                 */
+                /* XXX is this still an issue with proper alignment? */
                 rdev->mc.gtt_size = 32 * 1024 * 1024;
                 DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n");
         }
@@ -263,6 +265,7 @@ void rs400_mc_init(struct radeon_device *rdev)
         r100_vram_init_sizes(rdev);
         base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
         radeon_vram_location(rdev, &rdev->mc, base);
+        rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
         radeon_gtt_location(rdev, &rdev->mc);
         radeon_update_bandwidth_info(rdev);
 }
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 7bb4c3e52f3b..6dc15ea8ba33 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -698,6 +698,7 @@ void rs600_mc_init(struct radeon_device *rdev)
         base = G_000004_MC_FB_START(base) << 16;
         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
         radeon_vram_location(rdev, &rdev->mc, base);
+        rdev->mc.gtt_base_align = 0;
         radeon_gtt_location(rdev, &rdev->mc);
         radeon_update_bandwidth_info(rdev);
 }
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index bcc33195ebc2..ce4ecbe10816 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -79,7 +79,13 @@ void rs690_pm_info(struct radeon_device *rdev)
                         tmp.full = dfixed_const(100);
                         rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info.ulBootUpMemoryClock);
                         rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
-                        rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
+                        if (info->info.usK8MemoryClock)
+                                rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
+                        else if (rdev->clock.default_mclk) {
+                                rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
+                                rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
+                        } else
+                                rdev->pm.igp_system_mclk.full = dfixed_const(400);
                         rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
                         rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
                         break;
@@ -87,34 +93,31 @@ void rs690_pm_info(struct radeon_device *rdev)
                         tmp.full = dfixed_const(100);
                         rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info_v2.ulBootUpSidePortClock);
                         rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
-                        rdev->pm.igp_system_mclk.full = dfixed_const(info->info_v2.ulBootUpUMAClock);
+                        if (info->info_v2.ulBootUpUMAClock)
+                                rdev->pm.igp_system_mclk.full = dfixed_const(info->info_v2.ulBootUpUMAClock);
+                        else if (rdev->clock.default_mclk)
+                                rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
+                        else
+                                rdev->pm.igp_system_mclk.full = dfixed_const(66700);
                         rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
                         rdev->pm.igp_ht_link_clk.full = dfixed_const(info->info_v2.ulHTLinkFreq);
                         rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
                         rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
                         break;
                 default:
-                        tmp.full = dfixed_const(100);
                         /* We assume the slower possible clock ie worst case */
-                        /* DDR 333Mhz */
-                        rdev->pm.igp_sideport_mclk.full = dfixed_const(333);
-                        /* FIXME: system clock ? */
-                        rdev->pm.igp_system_mclk.full = dfixed_const(100);
-                        rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
-                        rdev->pm.igp_ht_link_clk.full = dfixed_const(200);
+                        rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
+                        rdev->pm.igp_system_mclk.full = dfixed_const(200);
+                        rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
                         rdev->pm.igp_ht_link_width.full = dfixed_const(8);
                         DRM_ERROR("No integrated system info for your GPU, using safe default\n");
                         break;
                 }
         } else {
-                tmp.full = dfixed_const(100);
                 /* We assume the slower possible clock ie worst case */
-                /* DDR 333Mhz */
-                rdev->pm.igp_sideport_mclk.full = dfixed_const(333);
-                /* FIXME: system clock ? */
-                rdev->pm.igp_system_mclk.full = dfixed_const(100);
-                rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
-                rdev->pm.igp_ht_link_clk.full = dfixed_const(200);
+                rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
+                rdev->pm.igp_system_mclk.full = dfixed_const(200);
+                rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
                 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
                 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
         }
@@ -159,6 +162,7 @@ void rs690_mc_init(struct radeon_device *rdev)
         rs690_pm_info(rdev);
         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
         radeon_vram_location(rdev, &rdev->mc, base);
+        rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
         radeon_gtt_location(rdev, &rdev->mc);
         radeon_update_bandwidth_info(rdev);
 }
@@ -228,10 +232,6 @@ void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
         fixed20_12 a, b, c;
         fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
         fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
-        /* FIXME: detect IGP with sideport memory, i don't think there is any
-         * such product available
-         */
-        bool sideport = false;
 
         if (!crtc->base.enabled) {
                 /* FIXME: wouldn't it better to set priority mark to maximum */
@@ -300,7 +300,7 @@ void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
 
         /* Maximun bandwidth is the minimun bandwidth of all component */
         rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
-        if (sideport) {
+        if (rdev->mc.igp_sideport_enabled) {
                 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
                         rdev->pm.sideport_bandwidth.full)
                         rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 7d9a7b0a180a..0c9c169a6852 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -195,6 +195,7 @@ void rv515_mc_init(struct radeon_device *rdev)
         rv515_vram_get_type(rdev);
         r100_vram_init_sizes(rdev);
         radeon_vram_location(rdev, &rdev->mc, 0);
+        rdev->mc.gtt_base_align = 0;
         if (!(rdev->flags & RADEON_IS_AGP))
                 radeon_gtt_location(rdev, &rdev->mc);
         radeon_update_bandwidth_info(rdev);
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index cec536c222c5..b7fd82064922 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -224,7 +224,7 @@ static void rv770_mc_program(struct radeon_device *rdev)
         WREG32(MC_VM_FB_LOCATION, tmp);
         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
-        WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
+        WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
         if (rdev->flags & RADEON_IS_AGP) {
                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index ef910694bd63..ca904799f018 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -40,11 +40,13 @@
 #include <linux/slab.h>
 
 #include <asm/atomic.h>
-#include <asm/agp.h>
 
 #include "ttm/ttm_bo_driver.h"
 #include "ttm/ttm_page_alloc.h"
 
+#ifdef TTM_HAS_AGP
+#include <asm/agp.h>
+#endif
 
 #define NUM_PAGES_TO_ALLOC              (PAGE_SIZE/sizeof(struct page *))
 #define SMALL_ALLOCATION                16
@@ -104,7 +106,6 @@ struct ttm_pool_opts {
 struct ttm_pool_manager {
         struct kobject          kobj;
         struct shrinker         mm_shrink;
-        atomic_t                page_alloc_inited;
         struct ttm_pool_opts    options;
 
         union {
@@ -142,7 +143,7 @@ static void ttm_pool_kobj_release(struct kobject *kobj)
 {
         struct ttm_pool_manager *m =
                 container_of(kobj, struct ttm_pool_manager, kobj);
-        (void)m;
+        kfree(m);
 }
 
 static ssize_t ttm_pool_store(struct kobject *kobj,
@@ -214,9 +215,7 @@ static struct kobj_type ttm_pool_kobj_type = {
         .default_attrs = ttm_pool_attrs,
 };
 
-static struct ttm_pool_manager _manager = {
-        .page_alloc_inited      = ATOMIC_INIT(0)
-};
+static struct ttm_pool_manager *_manager;
 
 #ifndef CONFIG_X86
 static int set_pages_array_wb(struct page **pages, int addrinarray)
@@ -271,7 +270,7 @@ static struct ttm_page_pool *ttm_get_pool(int flags,
         if (flags & TTM_PAGE_FLAG_DMA32)
                 pool_index |= 0x2;
 
-        return &_manager.pools[pool_index];
+        return &_manager->pools[pool_index];
 }
 
 /* set memory back to wb and free the pages. */
@@ -387,7 +386,7 @@ static int ttm_pool_get_num_unused_pages(void)
         unsigned i;
         int total = 0;
         for (i = 0; i < NUM_POOLS; ++i)
-                total += _manager.pools[i].npages;
+                total += _manager->pools[i].npages;
 
         return total;
 }
@@ -395,7 +394,7 @@ static int ttm_pool_get_num_unused_pages(void)
 /**
  * Callback for mm to request pool to reduce number of page held.
  */
-static int ttm_pool_mm_shrink(int shrink_pages, gfp_t gfp_mask)
+static int ttm_pool_mm_shrink(struct shrinker *shrink, int shrink_pages, gfp_t gfp_mask)
 {
         static atomic_t start_pool = ATOMIC_INIT(0);
         unsigned i;
@@ -408,7 +407,7 @@ static int ttm_pool_mm_shrink(int shrink_pages, gfp_t gfp_mask)
                 unsigned nr_free = shrink_pages;
                 if (shrink_pages == 0)
                         break;
-                pool = &_manager.pools[(i + pool_offset)%NUM_POOLS];
+                pool = &_manager->pools[(i + pool_offset)%NUM_POOLS];
                 shrink_pages = ttm_page_pool_free(pool, nr_free);
         }
         /* return estimated number of unused pages in pool */
@@ -576,10 +575,10 @@ static void ttm_page_pool_fill_locked(struct ttm_page_pool *pool,
 
         /* If allocation request is small and there is not enough
          * pages in pool we fill the pool first */
-        if (count < _manager.options.small
+        if (count < _manager->options.small
                 && count > pool->npages) {
                 struct list_head new_pages;
-                unsigned alloc_size = _manager.options.alloc_size;
+                unsigned alloc_size = _manager->options.alloc_size;
 
                 /**
                  * Can't change page caching if in irqsave context. We have to
@@ -667,7 +666,7 @@ int ttm_get_pages(struct list_head *pages, int flags,
 {
         struct ttm_page_pool *pool = ttm_get_pool(flags, cstate);
         struct page *p = NULL;
-        int gfp_flags = 0;
+        int gfp_flags = GFP_USER;
         int r;
 
         /* set zero flag for page allocation if required */
@@ -759,8 +758,8 @@ void ttm_put_pages(struct list_head *pages, unsigned page_count, int flags,
         pool->npages += page_count;
         /* Check that we don't go over the pool limit */
         page_count = 0;
-        if (pool->npages > _manager.options.max_size) {
-                page_count = pool->npages - _manager.options.max_size;
+        if (pool->npages > _manager->options.max_size) {
+                page_count = pool->npages - _manager->options.max_size;
                 /* free at least NUM_PAGES_TO_ALLOC number of pages
                  * to reduce calls to set_memory_wb */
                 if (page_count < NUM_PAGES_TO_ALLOC)
@@ -785,33 +784,36 @@ static void ttm_page_pool_init_locked(struct ttm_page_pool *pool, int flags,
 int ttm_page_alloc_init(struct ttm_mem_global *glob, unsigned max_pages)
 {
         int ret;
-        if (atomic_add_return(1, &_manager.page_alloc_inited) > 1)
-                return 0;
+
+        WARN_ON(_manager);
 
         printk(KERN_INFO TTM_PFX "Initializing pool allocator.\n");
 
-        ttm_page_pool_init_locked(&_manager.wc_pool, GFP_HIGHUSER, "wc");
+        _manager = kzalloc(sizeof(*_manager), GFP_KERNEL);
+
+        ttm_page_pool_init_locked(&_manager->wc_pool, GFP_HIGHUSER, "wc");
 
-        ttm_page_pool_init_locked(&_manager.uc_pool, GFP_HIGHUSER, "uc");
+        ttm_page_pool_init_locked(&_manager->uc_pool, GFP_HIGHUSER, "uc");
 
-        ttm_page_pool_init_locked(&_manager.wc_pool_dma32, GFP_USER | GFP_DMA32,
-                        "wc dma");
+        ttm_page_pool_init_locked(&_manager->wc_pool_dma32,
+                                  GFP_USER | GFP_DMA32, "wc dma");
 
-        ttm_page_pool_init_locked(&_manager.uc_pool_dma32, GFP_USER | GFP_DMA32,
-                        "uc dma");
+        ttm_page_pool_init_locked(&_manager->uc_pool_dma32,
+                                  GFP_USER | GFP_DMA32, "uc dma");
 
-        _manager.options.max_size = max_pages;
-        _manager.options.small = SMALL_ALLOCATION;
-        _manager.options.alloc_size = NUM_PAGES_TO_ALLOC;
+        _manager->options.max_size = max_pages;
+        _manager->options.small = SMALL_ALLOCATION;
+        _manager->options.alloc_size = NUM_PAGES_TO_ALLOC;
 
-        kobject_init(&_manager.kobj, &ttm_pool_kobj_type);
-        ret = kobject_add(&_manager.kobj, &glob->kobj, "pool");
+        ret = kobject_init_and_add(&_manager->kobj, &ttm_pool_kobj_type,
+                                   &glob->kobj, "pool");
         if (unlikely(ret != 0)) {
-                kobject_put(&_manager.kobj);
+                kobject_put(&_manager->kobj);
+                _manager = NULL;
                 return ret;
         }
 
-        ttm_pool_mm_shrink_init(&_manager);
+        ttm_pool_mm_shrink_init(_manager);
 
         return 0;
 }
@@ -820,16 +822,14 @@ void ttm_page_alloc_fini()
 {
         int i;
 
-        if (atomic_sub_return(1, &_manager.page_alloc_inited) > 0)
-                return;
-
         printk(KERN_INFO TTM_PFX "Finalizing pool allocator.\n");
-        ttm_pool_mm_shrink_fini(&_manager);
+        ttm_pool_mm_shrink_fini(_manager);
 
         for (i = 0; i < NUM_POOLS; ++i)
-                ttm_page_pool_free(&_manager.pools[i], FREE_ALL_PAGES);
+                ttm_page_pool_free(&_manager->pools[i], FREE_ALL_PAGES);
 
-        kobject_put(&_manager.kobj);
+        kobject_put(&_manager->kobj);
+        _manager = NULL;
 }
 
 int ttm_page_alloc_debugfs(struct seq_file *m, void *data)
@@ -837,14 +837,14 @@ int ttm_page_alloc_debugfs(struct seq_file *m, void *data)
         struct ttm_page_pool *p;
         unsigned i;
         char *h[] = {"pool", "refills", "pages freed", "size"};
-        if (atomic_read(&_manager.page_alloc_inited) == 0) {
+        if (!_manager) {
                 seq_printf(m, "No pool allocator running.\n");
                 return 0;
         }
         seq_printf(m, "%6s %12s %13s %8s\n",
                         h[0], h[1], h[2], h[3]);
         for (i = 0; i < NUM_POOLS; ++i) {
-                p = &_manager.pools[i];
+                p = &_manager->pools[i];
 
                 seq_printf(m, "%6s %12ld %13ld %8d\n",
                                 p->name, p->nrefills,
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index f1d626112415..437ac786277a 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -972,6 +972,7 @@ int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data,
         ret = copy_from_user(rects, user_rects, rects_size);
         if (unlikely(ret != 0)) {
                 DRM_ERROR("Failed to get rects.\n");
+                ret = -EFAULT;
                 goto out_free;
         }