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authorAlex Deucher <alexdeucher@gmail.com>2010-08-27 18:25:25 -0400
committerDave Airlie <airlied@redhat.com>2010-10-05 21:38:08 -0400
commit724c80e1d630296d1324859e964d80d35007d83c (patch)
tree954e86447e1c259160d09c732ac0eb0289b2ec8b /drivers/gpu/drm/radeon/r420.c
parentb70d6bb3f67b2e2964abafb0117f1733f062cba5 (diff)
drm/radeon/kms: enable writeback (v2)
When writeback is enabled, the GPU shadows writes to certain registers into a buffer in memory. The driver can then read the values from the shadow rather than reading back from the register across the bus. Writeback can be disabled by setting the no_wb module param to 1. On r6xx/r7xx/evergreen, the following registers are shadowed: - CP scratch registers - CP read pointer - IH write pointer On r1xx-rr5xx, the following registers are shadowed: - CP scratch registers - CP read pointer v2: - Combine wb patches for r6xx-evergreen and r1xx-r5xx - Writeback is disabled on AGP boards since it tends to be unreliable on AGP using the gart. - Check radeon_wb_init return values properly. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r420.c')
-rw-r--r--drivers/gpu/drm/radeon/r420.c16
1 files changed, 9 insertions, 7 deletions
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 59f7bccc5be0..c387346f93a9 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -248,6 +248,12 @@ static int r420_startup(struct radeon_device *rdev)
248 return r; 248 return r;
249 } 249 }
250 r420_pipes_init(rdev); 250 r420_pipes_init(rdev);
251
252 /* allocate wb buffer */
253 r = radeon_wb_init(rdev);
254 if (r)
255 return r;
256
251 /* Enable IRQ */ 257 /* Enable IRQ */
252 r100_irq_set(rdev); 258 r100_irq_set(rdev);
253 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 259 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
@@ -258,10 +264,6 @@ static int r420_startup(struct radeon_device *rdev)
258 return r; 264 return r;
259 } 265 }
260 r420_cp_errata_init(rdev); 266 r420_cp_errata_init(rdev);
261 r = r100_wb_init(rdev);
262 if (r) {
263 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
264 }
265 r = r100_ib_init(rdev); 267 r = r100_ib_init(rdev);
266 if (r) { 268 if (r) {
267 dev_err(rdev->dev, "failled initializing IB (%d).\n", r); 269 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
@@ -302,7 +304,7 @@ int r420_suspend(struct radeon_device *rdev)
302{ 304{
303 r420_cp_errata_fini(rdev); 305 r420_cp_errata_fini(rdev);
304 r100_cp_disable(rdev); 306 r100_cp_disable(rdev);
305 r100_wb_disable(rdev); 307 radeon_wb_disable(rdev);
306 r100_irq_disable(rdev); 308 r100_irq_disable(rdev);
307 if (rdev->flags & RADEON_IS_PCIE) 309 if (rdev->flags & RADEON_IS_PCIE)
308 rv370_pcie_gart_disable(rdev); 310 rv370_pcie_gart_disable(rdev);
@@ -314,7 +316,7 @@ int r420_suspend(struct radeon_device *rdev)
314void r420_fini(struct radeon_device *rdev) 316void r420_fini(struct radeon_device *rdev)
315{ 317{
316 r100_cp_fini(rdev); 318 r100_cp_fini(rdev);
317 r100_wb_fini(rdev); 319 radeon_wb_fini(rdev);
318 r100_ib_fini(rdev); 320 r100_ib_fini(rdev);
319 radeon_gem_fini(rdev); 321 radeon_gem_fini(rdev);
320 if (rdev->flags & RADEON_IS_PCIE) 322 if (rdev->flags & RADEON_IS_PCIE)
@@ -418,7 +420,7 @@ int r420_init(struct radeon_device *rdev)
418 /* Somethings want wront with the accel init stop accel */ 420 /* Somethings want wront with the accel init stop accel */
419 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 421 dev_err(rdev->dev, "Disabling GPU acceleration\n");
420 r100_cp_fini(rdev); 422 r100_cp_fini(rdev);
421 r100_wb_fini(rdev); 423 radeon_wb_fini(rdev);
422 r100_ib_fini(rdev); 424 r100_ib_fini(rdev);
423 radeon_irq_kms_fini(rdev); 425 radeon_irq_kms_fini(rdev);
424 if (rdev->flags & RADEON_IS_PCIE) 426 if (rdev->flags & RADEON_IS_PCIE)