16 files changed, 258 insertions, 218 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 79082d4398ae..e47d221e24ac 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -731,7 +731,7 @@ int evergreen_cp_resume(struct radeon_device *rdev)
 
         /* Set ring buffer size */
         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
-        tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
+        tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
 #ifdef __BIG_ENDIAN
         tmp |= BUF_SWAP_32BIT;
 #endif
@@ -745,8 +745,19 @@ int evergreen_cp_resume(struct radeon_device *rdev)
         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
         WREG32(CP_RB_RPTR_WR, 0);
         WREG32(CP_RB_WPTR, 0);
-        WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
-        WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
+
+        /* set the wb address wether it's enabled or not */
+        WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
+        WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
+        WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
+
+        if (rdev->wb.enabled)
+                WREG32(SCRATCH_UMSK, 0xff);
+        else {
+                tmp |= RB_NO_UPDATE;
+                WREG32(SCRATCH_UMSK, 0);
+        }
+
         mdelay(1);
         WREG32(CP_RB_CNTL, tmp);
 
@@ -1759,8 +1770,10 @@ static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
 {
         u32 wptr, tmp;
 
-        /* XXX use writeback */
-        wptr = RREG32(IH_RB_WPTR);
+        if (rdev->wb.enabled)
+                wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
+        else
+                wptr = RREG32(IH_RB_WPTR);
 
         if (wptr & RB_OVERFLOW) {
                 /* When a ring buffer overflow happen start parsing interrupt
@@ -2068,6 +2081,11 @@ static int evergreen_startup(struct radeon_device *rdev)
         }
 #endif
 
+        /* allocate wb buffer */
+        r = radeon_wb_init(rdev);
+        if (r)
+                return r;
+
         /* Enable IRQ */
         r = r600_irq_init(rdev);
         if (r) {
@@ -2086,8 +2104,6 @@ static int evergreen_startup(struct radeon_device *rdev)
         r = evergreen_cp_resume(rdev);
         if (r)
                 return r;
-        /* write back buffer are not vital so don't worry about failure */
-        r600_wb_enable(rdev);
 
         return 0;
 }
@@ -2128,7 +2144,7 @@ int evergreen_suspend(struct radeon_device *rdev)
         r700_cp_stop(rdev);
         rdev->cp.ready = false;
         evergreen_irq_suspend(rdev);
-        r600_wb_disable(rdev);
+        radeon_wb_disable(rdev);
         evergreen_pcie_gart_disable(rdev);
 #if 0
         /* unpin shaders bo */
@@ -2245,8 +2261,8 @@ int evergreen_init(struct radeon_device *rdev)
         if (r) {
                 dev_err(rdev->dev, "disabling GPU acceleration\n");
                 r700_cp_fini(rdev);
-                r600_wb_fini(rdev);
                 r600_irq_fini(rdev);
+                radeon_wb_fini(rdev);
                 radeon_irq_kms_fini(rdev);
                 evergreen_pcie_gart_fini(rdev);
                 rdev->accel_working = false;
@@ -2270,8 +2286,8 @@ void evergreen_fini(struct radeon_device *rdev)
 {
         /*r600_blit_fini(rdev);*/
         r700_cp_fini(rdev);
-        r600_wb_fini(rdev);
         r600_irq_fini(rdev);
+        radeon_wb_fini(rdev);
         radeon_irq_kms_fini(rdev);
         evergreen_pcie_gart_fini(rdev);
         radeon_gem_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index e151f16a8f86..7712c055b3e8 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -675,67 +675,6 @@ void r100_fence_ring_emit(struct radeon_device *rdev,
         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 }
 
-int r100_wb_init(struct radeon_device *rdev)
-{
-        int r;
-
-        if (rdev->wb.wb_obj == NULL) {
-                r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
-                                        RADEON_GEM_DOMAIN_GTT,
-                                        &rdev->wb.wb_obj);
-                if (r) {
-                        dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
-                        return r;
-                }
-                r = radeon_bo_reserve(rdev->wb.wb_obj, false);
-                if (unlikely(r != 0))
-                        return r;
-                r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
-                                        &rdev->wb.gpu_addr);
-                if (r) {
-                        dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
-                        radeon_bo_unreserve(rdev->wb.wb_obj);
-                        return r;
-                }
-                r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
-                radeon_bo_unreserve(rdev->wb.wb_obj);
-                if (r) {
-                        dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
-                        return r;
-                }
-        }
-        WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
-        WREG32(R_00070C_CP_RB_RPTR_ADDR,
-                S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
-        WREG32(R_000770_SCRATCH_UMSK, 0xff);
-        return 0;
-}
-
-void r100_wb_disable(struct radeon_device *rdev)
-{
-        WREG32(R_000770_SCRATCH_UMSK, 0);
-}
-
-void r100_wb_fini(struct radeon_device *rdev)
-{
-        int r;
-
-        r100_wb_disable(rdev);
-        if (rdev->wb.wb_obj) {
-                r = radeon_bo_reserve(rdev->wb.wb_obj, false);
-                if (unlikely(r != 0)) {
-                        dev_err(rdev->dev, "(%d) can't finish WB\n", r);
-                        return;
-                }
-                radeon_bo_kunmap(rdev->wb.wb_obj);
-                radeon_bo_unpin(rdev->wb.wb_obj);
-                radeon_bo_unreserve(rdev->wb.wb_obj);
-                radeon_bo_unref(&rdev->wb.wb_obj);
-                rdev->wb.wb = NULL;
-                rdev->wb.wb_obj = NULL;
-        }
-}
-
 int r100_copy_blit(struct radeon_device *rdev,
                    uint64_t src_offset,
                    uint64_t dst_offset,
@@ -996,20 +935,32 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
-               REG_SET(RADEON_MAX_FETCH, max_fetch) |
-               RADEON_RB_NO_UPDATE);
+               REG_SET(RADEON_MAX_FETCH, max_fetch));
 #ifdef __BIG_ENDIAN
         tmp |= RADEON_BUF_SWAP_32BIT;
 #endif
-        WREG32(RADEON_CP_RB_CNTL, tmp);
+        WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
 
         /* Set ring address */
         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
         /* Force read & write ptr to 0 */
-        WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
+        WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
         WREG32(RADEON_CP_RB_RPTR_WR, 0);
         WREG32(RADEON_CP_RB_WPTR, 0);
+
+        /* set the wb address whether it's enabled or not */
+        WREG32(R_00070C_CP_RB_RPTR_ADDR,
+                S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
+        WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
+
+        if (rdev->wb.enabled)
+                WREG32(R_000770_SCRATCH_UMSK, 0xff);
+        else {
+                tmp |= RADEON_RB_NO_UPDATE;
+                WREG32(R_000770_SCRATCH_UMSK, 0);
+        }
+
         WREG32(RADEON_CP_RB_CNTL, tmp);
         udelay(10);
         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
@@ -1050,6 +1001,7 @@ void r100_cp_disable(struct radeon_device *rdev)
         rdev->cp.ready = false;
         WREG32(RADEON_CP_CSQ_MODE, 0);
         WREG32(RADEON_CP_CSQ_CNTL, 0);
+        WREG32(R_000770_SCRATCH_UMSK, 0);
         if (r100_gui_wait_for_idle(rdev)) {
                 printk(KERN_WARNING "Failed to wait GUI idle while "
                        "programming pipes. Bad things might happen.\n");
@@ -3734,6 +3686,12 @@ static int r100_startup(struct radeon_device *rdev)
                 if (r)
                         return r;
         }
+
+        /* allocate wb buffer */
+        r = radeon_wb_init(rdev);
+        if (r)
+                return r;
+
         /* Enable IRQ */
         r100_irq_set(rdev);
         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
@@ -3743,9 +3701,6 @@ static int r100_startup(struct radeon_device *rdev)
                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
                 return r;
         }
-        r = r100_wb_init(rdev);
-        if (r)
-                dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
         r = r100_ib_init(rdev);
         if (r) {
                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
@@ -3779,7 +3734,7 @@ int r100_resume(struct radeon_device *rdev)
 int r100_suspend(struct radeon_device *rdev)
 {
         r100_cp_disable(rdev);
-        r100_wb_disable(rdev);
+        radeon_wb_disable(rdev);
         r100_irq_disable(rdev);
         if (rdev->flags & RADEON_IS_PCI)
                 r100_pci_gart_disable(rdev);
@@ -3789,7 +3744,7 @@ int r100_suspend(struct radeon_device *rdev)
 void r100_fini(struct radeon_device *rdev)
 {
         r100_cp_fini(rdev);
-        r100_wb_fini(rdev);
+        radeon_wb_fini(rdev);
         r100_ib_fini(rdev);
         radeon_gem_fini(rdev);
         if (rdev->flags & RADEON_IS_PCI)
@@ -3902,7 +3857,7 @@ int r100_init(struct radeon_device *rdev)
                 /* Somethings want wront with the accel init stop accel */
                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
                 r100_cp_fini(rdev);
-                r100_wb_fini(rdev);
+                radeon_wb_fini(rdev);
                 r100_ib_fini(rdev);
                 radeon_irq_kms_fini(rdev);
                 if (rdev->flags & RADEON_IS_PCI)
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index c827738ad7dd..34527e600fe9 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -1332,6 +1332,12 @@ static int r300_startup(struct radeon_device *rdev)
                 if (r)
                         return r;
         }
+
+        /* allocate wb buffer */
+        r = radeon_wb_init(rdev);
+        if (r)
+                return r;
+
         /* Enable IRQ */
         r100_irq_set(rdev);
         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
@@ -1341,9 +1347,6 @@ static int r300_startup(struct radeon_device *rdev)
                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
                 return r;
         }
-        r = r100_wb_init(rdev);
-        if (r)
-                dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
         r = r100_ib_init(rdev);
         if (r) {
                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
@@ -1379,7 +1382,7 @@ int r300_resume(struct radeon_device *rdev)
 int r300_suspend(struct radeon_device *rdev)
 {
         r100_cp_disable(rdev);
-        r100_wb_disable(rdev);
+        radeon_wb_disable(rdev);
         r100_irq_disable(rdev);
         if (rdev->flags & RADEON_IS_PCIE)
                 rv370_pcie_gart_disable(rdev);
@@ -1391,7 +1394,7 @@ int r300_suspend(struct radeon_device *rdev)
 void r300_fini(struct radeon_device *rdev)
 {
         r100_cp_fini(rdev);
-        r100_wb_fini(rdev);
+        radeon_wb_fini(rdev);
         r100_ib_fini(rdev);
         radeon_gem_fini(rdev);
         if (rdev->flags & RADEON_IS_PCIE)
@@ -1484,7 +1487,7 @@ int r300_init(struct radeon_device *rdev)
                 /* Somethings want wront with the accel init stop accel */
                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
                 r100_cp_fini(rdev);
-                r100_wb_fini(rdev);
+                radeon_wb_fini(rdev);
                 r100_ib_fini(rdev);
                 radeon_irq_kms_fini(rdev);
                 if (rdev->flags & RADEON_IS_PCIE)
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 59f7bccc5be0..c387346f93a9 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -248,6 +248,12 @@ static int r420_startup(struct radeon_device *rdev)
                         return r;
         }
         r420_pipes_init(rdev);
+
+        /* allocate wb buffer */
+        r = radeon_wb_init(rdev);
+        if (r)
+                return r;
+
         /* Enable IRQ */
         r100_irq_set(rdev);
         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
@@ -258,10 +264,6 @@ static int r420_startup(struct radeon_device *rdev)
                 return r;
         }
         r420_cp_errata_init(rdev);
-        r = r100_wb_init(rdev);
-        if (r) {
-                dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
-        }
         r = r100_ib_init(rdev);
         if (r) {
                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
@@ -302,7 +304,7 @@ int r420_suspend(struct radeon_device *rdev)
 {
         r420_cp_errata_fini(rdev);
         r100_cp_disable(rdev);
-        r100_wb_disable(rdev);
+        radeon_wb_disable(rdev);
         r100_irq_disable(rdev);
         if (rdev->flags & RADEON_IS_PCIE)
                 rv370_pcie_gart_disable(rdev);
@@ -314,7 +316,7 @@ int r420_suspend(struct radeon_device *rdev)
 void r420_fini(struct radeon_device *rdev)
 {
         r100_cp_fini(rdev);
-        r100_wb_fini(rdev);
+        radeon_wb_fini(rdev);
         r100_ib_fini(rdev);
         radeon_gem_fini(rdev);
         if (rdev->flags & RADEON_IS_PCIE)
@@ -418,7 +420,7 @@ int r420_init(struct radeon_device *rdev)
                 /* Somethings want wront with the accel init stop accel */
                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
                 r100_cp_fini(rdev);
-                r100_wb_fini(rdev);
+                radeon_wb_fini(rdev);
                 r100_ib_fini(rdev);
                 radeon_irq_kms_fini(rdev);
                 if (rdev->flags & RADEON_IS_PCIE)
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index 1458dee902dd..3c8677f9e385 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -181,6 +181,12 @@ static int r520_startup(struct radeon_device *rdev)
                 if (r)
                         return r;
         }
+
+        /* allocate wb buffer */
+        r = radeon_wb_init(rdev);
+        if (r)
+                return r;
+
         /* Enable IRQ */
         rs600_irq_set(rdev);
         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
@@ -190,9 +196,6 @@ static int r520_startup(struct radeon_device *rdev)
                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
                 return r;
         }
-        r = r100_wb_init(rdev);
-        if (r)
-                dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
         r = r100_ib_init(rdev);
         if (r) {
                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
@@ -295,7 +298,7 @@ int r520_init(struct radeon_device *rdev)
                 /* Somethings want wront with the accel init stop accel */
                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
                 r100_cp_fini(rdev);
-                r100_wb_fini(rdev);
+                radeon_wb_fini(rdev);
                 r100_ib_fini(rdev);
                 radeon_irq_kms_fini(rdev);
                 rv370_pcie_gart_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 927509ff349a..fbce58b2cd04 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1918,6 +1918,7 @@ void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 void r600_cp_stop(struct radeon_device *rdev)
 {
         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
+        WREG32(SCRATCH_UMSK, 0);
 }
 
 int r600_init_microcode(struct radeon_device *rdev)
@@ -2150,7 +2151,7 @@ int r600_cp_resume(struct radeon_device *rdev)
 
         /* Set ring buffer size */
         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
-        tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
+        tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
 #ifdef __BIG_ENDIAN
         tmp |= BUF_SWAP_32BIT;
 #endif
@@ -2164,8 +2165,19 @@ int r600_cp_resume(struct radeon_device *rdev)
         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
         WREG32(CP_RB_RPTR_WR, 0);
         WREG32(CP_RB_WPTR, 0);
-        WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
-        WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
+
+        /* set the wb address whether it's enabled or not */
+        WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
+        WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
+        WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
+
+        if (rdev->wb.enabled)
+                WREG32(SCRATCH_UMSK, 0xff);
+        else {
+                tmp |= RB_NO_UPDATE;
+                WREG32(SCRATCH_UMSK, 0);
+        }
+
         mdelay(1);
         WREG32(CP_RB_CNTL, tmp);
 
@@ -2217,9 +2229,10 @@ void r600_scratch_init(struct radeon_device *rdev)
         int i;
 
         rdev->scratch.num_reg = 7;
+        rdev->scratch.reg_base = SCRATCH_REG0;
         for (i = 0; i < rdev->scratch.num_reg; i++) {
                 rdev->scratch.free[i] = true;
-                rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
+                rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
         }
 }
 
@@ -2263,70 +2276,6 @@ int r600_ring_test(struct radeon_device *rdev)
         return r;
 }
 
-void r600_wb_disable(struct radeon_device *rdev)
-{
-        int r;
-
-        WREG32(SCRATCH_UMSK, 0);
-        if (rdev->wb.wb_obj) {
-                r = radeon_bo_reserve(rdev->wb.wb_obj, false);
-                if (unlikely(r != 0))
-                        return;
-                radeon_bo_kunmap(rdev->wb.wb_obj);
-                radeon_bo_unpin(rdev->wb.wb_obj);
-                radeon_bo_unreserve(rdev->wb.wb_obj);
-        }
-}
-
-void r600_wb_fini(struct radeon_device *rdev)
-{
-        r600_wb_disable(rdev);
-        if (rdev->wb.wb_obj) {
-                radeon_bo_unref(&rdev->wb.wb_obj);
-                rdev->wb.wb = NULL;
-                rdev->wb.wb_obj = NULL;
-        }
-}
-
-int r600_wb_enable(struct radeon_device *rdev)
-{
-        int r;
-
-        if (rdev->wb.wb_obj == NULL) {
-                r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
-                                RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
-                if (r) {
-                        dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
-                        return r;
-                }
-                r = radeon_bo_reserve(rdev->wb.wb_obj, false);
-                if (unlikely(r != 0)) {
-                        r600_wb_fini(rdev);
-                        return r;
-                }
-                r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
-                                &rdev->wb.gpu_addr);
-                if (r) {
-                        radeon_bo_unreserve(rdev->wb.wb_obj);
-                        dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
-                        r600_wb_fini(rdev);
-                        return r;
-                }
-                r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
-                radeon_bo_unreserve(rdev->wb.wb_obj);
-                if (r) {
-                        dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
-                        r600_wb_fini(rdev);
-                        return r;
-                }
-        }
-        WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
-        WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
-        WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
-        WREG32(SCRATCH_UMSK, 0xff);
-        return 0;
-}
-
 void r600_fence_ring_emit(struct radeon_device *rdev,
                           struct radeon_fence *fence)
 {
@@ -2427,6 +2376,11 @@ int r600_startup(struct radeon_device *rdev)
                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
         }
 
+        /* allocate wb buffer */
+        r = radeon_wb_init(rdev);
+        if (r)
+                return r;
+
         /* Enable IRQ */
         r = r600_irq_init(rdev);
         if (r) {
@@ -2445,8 +2399,7 @@ int r600_startup(struct radeon_device *rdev)
         r = r600_cp_resume(rdev);
         if (r)
                 return r;
-        /* write back buffer are not vital so don't worry about failure */
-        r600_wb_enable(rdev);
+
         return 0;
 }
 
@@ -2505,7 +2458,7 @@ int r600_suspend(struct radeon_device *rdev)
         r600_cp_stop(rdev);
         rdev->cp.ready = false;
         r600_irq_suspend(rdev);
-        r600_wb_disable(rdev);
+        radeon_wb_disable(rdev);
         r600_pcie_gart_disable(rdev);
         /* unpin shaders bo */
         if (rdev->r600_blit.shader_obj) {
@@ -2602,8 +2555,8 @@ int r600_init(struct radeon_device *rdev)
         if (r) {
                 dev_err(rdev->dev, "disabling GPU acceleration\n");
                 r600_cp_fini(rdev);
-                r600_wb_fini(rdev);
                 r600_irq_fini(rdev);
+                radeon_wb_fini(rdev);
                 radeon_irq_kms_fini(rdev);
                 r600_pcie_gart_fini(rdev);
                 rdev->accel_working = false;
@@ -2633,8 +2586,8 @@ void r600_fini(struct radeon_device *rdev)
         r600_audio_fini(rdev);
         r600_blit_fini(rdev);
         r600_cp_fini(rdev);
-        r600_wb_fini(rdev);
         r600_irq_fini(rdev);
+        radeon_wb_fini(rdev);
         radeon_irq_kms_fini(rdev);
         r600_pcie_gart_fini(rdev);
         radeon_agp_fini(rdev);
@@ -2969,10 +2922,13 @@ int r600_irq_init(struct radeon_device *rdev)
         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
                       IH_WPTR_OVERFLOW_CLEAR |
                       (rb_bufsz << 1));
-        /* WPTR writeback, not yet */
-        /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
-        WREG32(IH_RB_WPTR_ADDR_LO, 0);
-        WREG32(IH_RB_WPTR_ADDR_HI, 0);
+
+        if (rdev->wb.enabled)
+                ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
+
+        /* set the writeback address whether it's enabled or not */
+        WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
+        WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
 
         WREG32(IH_RB_CNTL, ih_rb_cntl);
 
@@ -3230,8 +3186,10 @@ static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
 {
         u32 wptr, tmp;
 
-        /* XXX use writeback */
-        wptr = RREG32(IH_RB_WPTR);
+        if (rdev->wb.enabled)
+                wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
+        else
+                wptr = RREG32(IH_RB_WPTR);
 
         if (wptr & RB_OVERFLOW) {
                 /* When a ring buffer overflow happen start parsing interrupt
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index a168d644bf9e..4e10938d8dd1 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -365,6 +365,7 @@ bool radeon_atombios_sideport_present(struct radeon_device *rdev);
  */
 struct radeon_scratch {
         unsigned                num_reg;
+        uint32_t                reg_base;
         bool                    free[32];
         uint32_t                reg[32];
 };
@@ -593,8 +594,13 @@ struct radeon_wb {
         struct radeon_bo        *wb_obj;
         volatile uint32_t       *wb;
         uint64_t                gpu_addr;
+        bool                    enabled;
 };
 
+#define RADEON_WB_SCRATCH_OFFSET 0
+#define RADEON_WB_CP_RPTR_OFFSET 1024
+#define R600_WB_IH_WPTR_OFFSET   2048
+
 /**
  * struct radeon_pm - power management datas
  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
@@ -1340,6 +1346,9 @@ extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
 extern void radeon_update_display_priority(struct radeon_device *rdev);
 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
 extern void radeon_scratch_init(struct radeon_device *rdev);
+extern void radeon_wb_fini(struct radeon_device *rdev);
+extern int radeon_wb_init(struct radeon_device *rdev);
+extern void radeon_wb_disable(struct radeon_device *rdev);
 extern void radeon_surface_init(struct radeon_device *rdev);
 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
@@ -1424,9 +1433,6 @@ extern int r600_pcie_gart_init(struct radeon_device *rdev);
 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
 extern int r600_ib_test(struct radeon_device *rdev);
 extern int r600_ring_test(struct radeon_device *rdev);
-extern void r600_wb_fini(struct radeon_device *rdev);
-extern int r600_wb_enable(struct radeon_device *rdev);
-extern void r600_wb_disable(struct radeon_device *rdev);
 extern void r600_scratch_init(struct radeon_device *rdev);
 extern int r600_blit_init(struct radeon_device *rdev);
 extern void r600_blit_fini(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index a5aff755f0d2..6d3b055c02fd 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -108,9 +108,6 @@ void r100_irq_disable(struct radeon_device *rdev);
 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
 void r100_vram_init_sizes(struct radeon_device *rdev);
-void r100_wb_disable(struct radeon_device *rdev);
-void r100_wb_fini(struct radeon_device *rdev);
-int r100_wb_init(struct radeon_device *rdev);
 int r100_cp_reset(struct radeon_device *rdev);
 void r100_vga_render_disable(struct radeon_device *rdev);
 void r100_restore_sanity(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 256d204a6d24..cfc162d05010 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -117,9 +117,10 @@ void radeon_scratch_init(struct radeon_device *rdev)
         } else {
                 rdev->scratch.num_reg = 7;
         }
+        rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
         for (i = 0; i < rdev->scratch.num_reg; i++) {
                 rdev->scratch.free[i] = true;
-                rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
+                rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
         }
 }
 
@@ -149,6 +150,80 @@ void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
         }
 }
 
+void radeon_wb_disable(struct radeon_device *rdev)
+{
+        int r;
+
+        if (rdev->wb.wb_obj) {
+                r = radeon_bo_reserve(rdev->wb.wb_obj, false);
+                if (unlikely(r != 0))
+                        return;
+                radeon_bo_kunmap(rdev->wb.wb_obj);
+                radeon_bo_unpin(rdev->wb.wb_obj);
+                radeon_bo_unreserve(rdev->wb.wb_obj);
+        }
+        rdev->wb.enabled = false;
+}
+
+void radeon_wb_fini(struct radeon_device *rdev)
+{
+        radeon_wb_disable(rdev);
+        if (rdev->wb.wb_obj) {
+                radeon_bo_unref(&rdev->wb.wb_obj);
+                rdev->wb.wb = NULL;
+                rdev->wb.wb_obj = NULL;
+        }
+}
+
+int radeon_wb_init(struct radeon_device *rdev)
+{
+        int r;
+
+        if (rdev->wb.wb_obj == NULL) {
+                r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
+                                RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
+                if (r) {
+                        dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
+                        return r;
+                }
+        }
+        r = radeon_bo_reserve(rdev->wb.wb_obj, false);
+        if (unlikely(r != 0)) {
+                radeon_wb_fini(rdev);
+                return r;
+        }
+        r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
+                          &rdev->wb.gpu_addr);
+        if (r) {
+                radeon_bo_unreserve(rdev->wb.wb_obj);
+                dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
+                radeon_wb_fini(rdev);
+                return r;
+        }
+        r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
+        radeon_bo_unreserve(rdev->wb.wb_obj);
+        if (r) {
+                dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
+                radeon_wb_fini(rdev);
+                return r;
+        }
+
+        /* disabled via module param */
+        if (radeon_no_wb == 1)
+                rdev->wb.enabled = false;
+        else {
+                /* often unreliable on AGP */
+                if (rdev->flags & RADEON_IS_AGP) {
+                        rdev->wb.enabled = false;
+                } else
+                        rdev->wb.enabled = true;
+        }
+
+        dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
+
+        return 0;
+}
+
 /**
  * radeon_vram_location - try to find VRAM location
  * @rdev: radeon device structure holding all necessary informations
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index b1f9a81b5d1d..698a7ed3a6a1 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -72,7 +72,11 @@ static bool radeon_fence_poll_locked(struct radeon_device *rdev)
         bool wake = false;
         unsigned long cjiffies;
 
-        seq = RREG32(rdev->fence_drv.scratch_reg);
+        if (rdev->wb.enabled) {
+                u32 scratch_index = RADEON_WB_SCRATCH_OFFSET + rdev->fence_drv.scratch_reg - rdev->scratch.reg_base;
+                seq = rdev->wb.wb[scratch_index/4];
+        } else
+                seq = RREG32(rdev->fence_drv.scratch_reg);
         if (seq != rdev->fence_drv.last_seq) {
                 rdev->fence_drv.last_seq = seq;
                 rdev->fence_drv.last_jiffies = jiffies;
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index 261e98a276db..6ea798ce8218 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -247,10 +247,14 @@ void radeon_ib_pool_fini(struct radeon_device *rdev)
  */
 void radeon_ring_free_size(struct radeon_device *rdev)
 {
-        if (rdev->family >= CHIP_R600)
-                rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
-        else
-                rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
+        if (rdev->wb.enabled)
+                rdev->cp.rptr = rdev->wb.wb[RADEON_WB_CP_RPTR_OFFSET/4];
+        else {
+                if (rdev->family >= CHIP_R600)
+                        rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
+                else
+                        rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
+        }
         /* This works because ring_size is a power of 2 */
         rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4));
         rdev->cp.ring_free_dw -= rdev->cp.wptr;
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index ae2b76b9a388..f683e51a2a06 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -397,6 +397,12 @@ static int rs400_startup(struct radeon_device *rdev)
         r = rs400_gart_enable(rdev);
         if (r)
                 return r;
+
+        /* allocate wb buffer */
+        r = radeon_wb_init(rdev);
+        if (r)
+                return r;
+
         /* Enable IRQ */
         r100_irq_set(rdev);
         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
@@ -406,9 +412,6 @@ static int rs400_startup(struct radeon_device *rdev)
                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
                 return r;
         }
-        r = r100_wb_init(rdev);
-        if (r)
-                dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
         r = r100_ib_init(rdev);
         if (r) {
                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
@@ -443,7 +446,7 @@ int rs400_resume(struct radeon_device *rdev)
 int rs400_suspend(struct radeon_device *rdev)
 {
         r100_cp_disable(rdev);
-        r100_wb_disable(rdev);
+        radeon_wb_disable(rdev);
         r100_irq_disable(rdev);
         rs400_gart_disable(rdev);
         return 0;
@@ -452,7 +455,7 @@ int rs400_suspend(struct radeon_device *rdev)
 void rs400_fini(struct radeon_device *rdev)
 {
         r100_cp_fini(rdev);
-        r100_wb_fini(rdev);
+        radeon_wb_fini(rdev);
         r100_ib_fini(rdev);
         radeon_gem_fini(rdev);
         rs400_gart_fini(rdev);
@@ -526,7 +529,7 @@ int rs400_init(struct radeon_device *rdev)
                 /* Somethings want wront with the accel init stop accel */
                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
                 r100_cp_fini(rdev);
-                r100_wb_fini(rdev);
+                radeon_wb_fini(rdev);
                 r100_ib_fini(rdev);
                 rs400_gart_fini(rdev);
                 radeon_irq_kms_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index cc05b230d7ef..8d8359a5d459 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -795,6 +795,12 @@ static int rs600_startup(struct radeon_device *rdev)
         r = rs600_gart_enable(rdev);
         if (r)
                 return r;
+
+        /* allocate wb buffer */
+        r = radeon_wb_init(rdev);
+        if (r)
+                return r;
+
         /* Enable IRQ */
         rs600_irq_set(rdev);
         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
@@ -804,9 +810,6 @@ static int rs600_startup(struct radeon_device *rdev)
                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
                 return r;
         }
-        r = r100_wb_init(rdev);
-        if (r)
-                dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
         r = r100_ib_init(rdev);
         if (r) {
                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
@@ -847,7 +850,7 @@ int rs600_suspend(struct radeon_device *rdev)
 {
         r600_audio_fini(rdev);
         r100_cp_disable(rdev);
-        r100_wb_disable(rdev);
+        radeon_wb_disable(rdev);
         rs600_irq_disable(rdev);
         rs600_gart_disable(rdev);
         return 0;
@@ -857,7 +860,7 @@ void rs600_fini(struct radeon_device *rdev)
 {
         r600_audio_fini(rdev);
         r100_cp_fini(rdev);
-        r100_wb_fini(rdev);
+        radeon_wb_fini(rdev);
         r100_ib_fini(rdev);
         radeon_gem_fini(rdev);
         rs600_gart_fini(rdev);
@@ -931,7 +934,7 @@ int rs600_init(struct radeon_device *rdev)
                 /* Somethings want wront with the accel init stop accel */
                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
                 r100_cp_fini(rdev);
-                r100_wb_fini(rdev);
+                radeon_wb_fini(rdev);
                 r100_ib_fini(rdev);
                 rs600_gart_fini(rdev);
                 radeon_irq_kms_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 3e3f75718be3..70ed66ef1ca8 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -615,6 +615,12 @@ static int rs690_startup(struct radeon_device *rdev)
         r = rs400_gart_enable(rdev);
         if (r)
                 return r;
+
+        /* allocate wb buffer */
+        r = radeon_wb_init(rdev);
+        if (r)
+                return r;
+
         /* Enable IRQ */
         rs600_irq_set(rdev);
         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
@@ -624,9 +630,6 @@ static int rs690_startup(struct radeon_device *rdev)
                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
                 return r;
         }
-        r = r100_wb_init(rdev);
-        if (r)
-                dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
         r = r100_ib_init(rdev);
         if (r) {
                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
@@ -667,7 +670,7 @@ int rs690_suspend(struct radeon_device *rdev)
 {
         r600_audio_fini(rdev);
         r100_cp_disable(rdev);
-        r100_wb_disable(rdev);
+        radeon_wb_disable(rdev);
         rs600_irq_disable(rdev);
         rs400_gart_disable(rdev);
         return 0;
@@ -677,7 +680,7 @@ void rs690_fini(struct radeon_device *rdev)
 {
         r600_audio_fini(rdev);
         r100_cp_fini(rdev);
-        r100_wb_fini(rdev);
+        radeon_wb_fini(rdev);
         r100_ib_fini(rdev);
         radeon_gem_fini(rdev);
         rs400_gart_fini(rdev);
@@ -752,7 +755,7 @@ int rs690_init(struct radeon_device *rdev)
                 /* Somethings want wront with the accel init stop accel */
                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
                 r100_cp_fini(rdev);
-                r100_wb_fini(rdev);
+                radeon_wb_fini(rdev);
                 r100_ib_fini(rdev);
                 rs400_gart_fini(rdev);
                 radeon_irq_kms_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 4d6e86041a9f..5d569f41f4ae 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -386,6 +386,12 @@ static int rv515_startup(struct radeon_device *rdev)
                 if (r)
                         return r;
         }
+
+        /* allocate wb buffer */
+        r = radeon_wb_init(rdev);
+        if (r)
+                return r;
+
         /* Enable IRQ */
         rs600_irq_set(rdev);
         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
@@ -395,9 +401,6 @@ static int rv515_startup(struct radeon_device *rdev)
                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
                 return r;
         }
-        r = r100_wb_init(rdev);
-        if (r)
-                dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
         r = r100_ib_init(rdev);
         if (r) {
                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
@@ -431,7 +434,7 @@ int rv515_resume(struct radeon_device *rdev)
 int rv515_suspend(struct radeon_device *rdev)
 {
         r100_cp_disable(rdev);
-        r100_wb_disable(rdev);
+        radeon_wb_disable(rdev);
         rs600_irq_disable(rdev);
         if (rdev->flags & RADEON_IS_PCIE)
                 rv370_pcie_gart_disable(rdev);
@@ -447,7 +450,7 @@ void rv515_set_safe_registers(struct radeon_device *rdev)
 void rv515_fini(struct radeon_device *rdev)
 {
         r100_cp_fini(rdev);
-        r100_wb_fini(rdev);
+        radeon_wb_fini(rdev);
         r100_ib_fini(rdev);
         radeon_gem_fini(rdev);
         rv370_pcie_gart_fini(rdev);
@@ -527,7 +530,7 @@ int rv515_init(struct radeon_device *rdev)
                 /* Somethings want wront with the accel init stop accel */
                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
                 r100_cp_fini(rdev);
-                r100_wb_fini(rdev);
+                radeon_wb_fini(rdev);
                 r100_ib_fini(rdev);
                 radeon_irq_kms_fini(rdev);
                 rv370_pcie_gart_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index bc2beb7d35e9..ff1cc58920c0 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -268,6 +268,7 @@ static void rv770_mc_program(struct radeon_device *rdev)
 void r700_cp_stop(struct radeon_device *rdev)
 {
         WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
+        WREG32(SCRATCH_UMSK, 0);
 }
 
 static int rv770_cp_load_microcode(struct radeon_device *rdev)
@@ -1029,6 +1030,11 @@ static int rv770_startup(struct radeon_device *rdev)
                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
         }
 
+        /* allocate wb buffer */
+        r = radeon_wb_init(rdev);
+        if (r)
+                return r;
+
         /* Enable IRQ */
         r = r600_irq_init(rdev);
         if (r) {
@@ -1047,8 +1053,7 @@ static int rv770_startup(struct radeon_device *rdev)
         r = r600_cp_resume(rdev);
         if (r)
                 return r;
-        /* write back buffer are not vital so don't worry about failure */
-        r600_wb_enable(rdev);
+
         return 0;
 }
 
@@ -1094,7 +1099,7 @@ int rv770_suspend(struct radeon_device *rdev)
         r700_cp_stop(rdev);
         rdev->cp.ready = false;
         r600_irq_suspend(rdev);
-        r600_wb_disable(rdev);
+        radeon_wb_disable(rdev);
         rv770_pcie_gart_disable(rdev);
         /* unpin shaders bo */
         if (rdev->r600_blit.shader_obj) {
@@ -1189,8 +1194,8 @@ int rv770_init(struct radeon_device *rdev)
         if (r) {
                 dev_err(rdev->dev, "disabling GPU acceleration\n");
                 r700_cp_fini(rdev);
-                r600_wb_fini(rdev);
                 r600_irq_fini(rdev);
+                radeon_wb_fini(rdev);
                 radeon_irq_kms_fini(rdev);
                 rv770_pcie_gart_fini(rdev);
                 rdev->accel_working = false;
@@ -1222,8 +1227,8 @@ void rv770_fini(struct radeon_device *rdev)
 {
         r600_blit_fini(rdev);
         r700_cp_fini(rdev);
-        r600_wb_fini(rdev);
         r600_irq_fini(rdev);
+        radeon_wb_fini(rdev);
         radeon_irq_kms_fini(rdev);
         rv770_pcie_gart_fini(rdev);
         rv770_vram_scratch_fini(rdev);