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authorBen Skeggs <bskeggs@redhat.com>2015-01-13 21:34:00 -0500
committerBen Skeggs <bskeggs@redhat.com>2015-01-21 21:17:47 -0500
commit8700287be2b12d091d477fe0568c3858bdedf4e7 (patch)
tree40a4b59a39a0f77f34b31d30db08b2fd51b9af37 /drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
parentfd8666f7db94afc1b63b8439d902783b27a2f27f (diff)
drm/nouveau/sw: rename from software (no binary change)
Shorter device name, make consistent with our engine enums. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c')
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
index f292e7b88628..66d8c338ae98 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
@@ -37,7 +37,7 @@
37#include <engine/device.h> 37#include <engine/device.h>
38#include <engine/dmaobj.h> 38#include <engine/dmaobj.h>
39#include <engine/fifo.h> 39#include <engine/fifo.h>
40#include <engine/software.h> 40#include <engine/sw.h>
41#include <engine/gr.h> 41#include <engine/gr.h>
42#include <engine/disp.h> 42#include <engine/disp.h>
43 43
@@ -77,7 +77,7 @@ nv10_identify(struct nouveau_device *device)
77 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 77 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
78 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 78 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
79 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 79 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
80 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 80 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
81 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 81 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
82 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 82 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
83 break; 83 break;
@@ -96,7 +96,7 @@ nv10_identify(struct nouveau_device *device)
96 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 96 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
97 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 97 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
98 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 98 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
99 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 99 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
100 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 100 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
101 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 101 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
102 break; 102 break;
@@ -115,7 +115,7 @@ nv10_identify(struct nouveau_device *device)
115 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 115 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
116 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 116 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
117 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 117 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
118 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 118 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
119 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 119 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
120 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 120 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
121 break; 121 break;
@@ -134,7 +134,7 @@ nv10_identify(struct nouveau_device *device)
134 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 134 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
135 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 135 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
136 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; 136 device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
137 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 137 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
138 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 138 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
139 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 139 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
140 break; 140 break;
@@ -153,7 +153,7 @@ nv10_identify(struct nouveau_device *device)
153 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 153 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
154 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 154 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
155 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 155 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
156 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 156 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
157 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 157 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
158 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 158 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
159 break; 159 break;
@@ -172,7 +172,7 @@ nv10_identify(struct nouveau_device *device)
172 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 172 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
173 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 173 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
174 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 174 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
175 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 175 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
176 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 176 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
177 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 177 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
178 break; 178 break;
@@ -191,7 +191,7 @@ nv10_identify(struct nouveau_device *device)
191 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; 191 device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
192 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; 192 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
193 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; 193 device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
194 device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; 194 device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass;
195 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; 195 device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
196 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; 196 device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
197 break; 197 break;