drm/nouveau: port remainder of drm code, and rip out compat layer

v2: Ben Skeggs <bskeggs@redhat.com>
- fill in nouveau_pm.dev to prevent oops
- fix ppc issues (build + OF shadow)

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

1 files changed, 194 insertions, 0 deletions

diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.h b/drivers/gpu/drm/nouveau/nouveau_pm.h
index 07cac72c72b4..e2ec9c0ed567 100644
--- a/drivers/gpu/drm/nouveau/nouveau_pm.h
+++ b/drivers/gpu/drm/nouveau/nouveau_pm.h
@@ -25,6 +25,178 @@
 #ifndef __NOUVEAU_PM_H__
 #define __NOUVEAU_PM_H__
 
+#include <subdev/bios/pll.h>
+#include <subdev/clock.h>
+
+struct nouveau_pm_voltage_level {
+        u32 voltage; /* microvolts */
+        u8  vid;
+};
+
+struct nouveau_pm_voltage {
+        bool supported;
+        u8 version;
+        u8 vid_mask;
+
+        struct nouveau_pm_voltage_level *level;
+        int nr_level;
+};
+
+/* Exclusive upper limits */
+#define NV_MEM_CL_DDR2_MAX 8
+#define NV_MEM_WR_DDR2_MAX 9
+#define NV_MEM_CL_DDR3_MAX 17
+#define NV_MEM_WR_DDR3_MAX 17
+#define NV_MEM_CL_GDDR3_MAX 16
+#define NV_MEM_WR_GDDR3_MAX 18
+#define NV_MEM_CL_GDDR5_MAX 21
+#define NV_MEM_WR_GDDR5_MAX 20
+
+struct nouveau_pm_memtiming {
+        int id;
+
+        u32 reg[9];
+        u32 mr[4];
+
+        u8 tCWL;
+
+        u8 odt;
+        u8 drive_strength;
+};
+
+struct nouveau_pm_tbl_header {
+        u8 version;
+        u8 header_len;
+        u8 entry_cnt;
+        u8 entry_len;
+};
+
+struct nouveau_pm_tbl_entry {
+        u8 tWR;
+        u8 tWTR;
+        u8 tCL;
+        u8 tRC;
+        u8 empty_4;
+        u8 tRFC;        /* Byte 5 */
+        u8 empty_6;
+        u8 tRAS;        /* Byte 7 */
+        u8 empty_8;
+        u8 tRP;         /* Byte 9 */
+        u8 tRCDRD;
+        u8 tRCDWR;
+        u8 tRRD;
+        u8 tUNK_13;
+        u8 RAM_FT1;             /* 14, a bitmask of random RAM features */
+        u8 empty_15;
+        u8 tUNK_16;
+        u8 empty_17;
+        u8 tUNK_18;
+        u8 tCWL;
+        u8 tUNK_20, tUNK_21;
+};
+
+struct nouveau_pm_profile;
+struct nouveau_pm_profile_func {
+        void (*destroy)(struct nouveau_pm_profile *);
+        void (*init)(struct nouveau_pm_profile *);
+        void (*fini)(struct nouveau_pm_profile *);
+        struct nouveau_pm_level *(*select)(struct nouveau_pm_profile *);
+};
+
+struct nouveau_pm_profile {
+        const struct nouveau_pm_profile_func *func;
+        struct list_head head;
+        char name[8];
+};
+
+#define NOUVEAU_PM_MAX_LEVEL 8
+struct nouveau_pm_level {
+        struct nouveau_pm_profile profile;
+        struct device_attribute dev_attr;
+        char name[32];
+        int id;
+
+        struct nouveau_pm_memtiming timing;
+        u32 memory;
+        u16 memscript;
+
+        u32 core;
+        u32 shader;
+        u32 rop;
+        u32 copy;
+        u32 daemon;
+        u32 vdec;
+        u32 dom6;
+        u32 unka0;      /* nva3:nvc0 */
+        u32 hub01;      /* nvc0- */
+        u32 hub06;      /* nvc0- */
+        u32 hub07;      /* nvc0- */
+
+        u32 volt_min; /* microvolts */
+        u32 volt_max;
+        u8  fanspeed;
+};
+
+struct nouveau_pm_temp_sensor_constants {
+        u16 offset_constant;
+        s16 offset_mult;
+        s16 offset_div;
+        s16 slope_mult;
+        s16 slope_div;
+};
+
+struct nouveau_pm_threshold_temp {
+        s16 critical;
+        s16 down_clock;
+        s16 fan_boost;
+};
+
+struct nouveau_pm_fan {
+        u32 percent;
+        u32 min_duty;
+        u32 max_duty;
+        u32 pwm_freq;
+        u32 pwm_divisor;
+};
+
+struct nouveau_pm {
+        struct drm_device *dev;
+
+        struct nouveau_pm_voltage voltage;
+        struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
+        int nr_perflvl;
+        struct nouveau_pm_temp_sensor_constants sensor_constants;
+        struct nouveau_pm_threshold_temp threshold_temp;
+        struct nouveau_pm_fan fan;
+
+        struct nouveau_pm_profile *profile_ac;
+        struct nouveau_pm_profile *profile_dc;
+        struct nouveau_pm_profile *profile;
+        struct list_head profiles;
+
+        struct nouveau_pm_level boot;
+        struct nouveau_pm_level *cur;
+
+        struct device *hwmon;
+        struct notifier_block acpi_nb;
+
+        int  (*clocks_get)(struct drm_device *, struct nouveau_pm_level *);
+        void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *);
+        int (*clocks_set)(struct drm_device *, void *);
+
+        int (*voltage_get)(struct drm_device *);
+        int (*voltage_set)(struct drm_device *, int voltage);
+        int (*pwm_get)(struct drm_device *, int line, u32*, u32*);
+        int (*pwm_set)(struct drm_device *, int line, u32, u32);
+        int (*temp_get)(struct drm_device *);
+};
+
+static inline struct nouveau_pm *
+nouveau_pm(struct drm_device *dev)
+{
+        return nouveau_drm(dev)->pm;
+}
+
 struct nouveau_mem_exec_func {
         struct drm_device *dev;
         void (*precharge)(struct nouveau_mem_exec_func *);
@@ -106,4 +278,26 @@ void nouveau_temp_safety_checks(struct drm_device *dev);
 int nv40_temp_get(struct drm_device *dev);
 int nv84_temp_get(struct drm_device *dev);
 
+/* nouveau_mem.c */
+int  nouveau_mem_timing_calc(struct drm_device *, u32 freq,
+                             struct nouveau_pm_memtiming *);
+void nouveau_mem_timing_read(struct drm_device *,
+                             struct nouveau_pm_memtiming *);
+
+static inline int
+nva3_calc_pll(struct drm_device *dev, struct nvbios_pll *pll, u32 freq,
+              int *N, int *fN, int *M, int *P)
+{
+        struct nouveau_device *device = nouveau_dev(dev);
+        struct nouveau_clock *clk = nouveau_clock(device);
+        struct nouveau_pll_vals pv;
+        int ret;
+
+        ret = clk->pll_calc(clk, pll, freq, &pv);
+        *N = pv.N1;
+        *M = pv.M1;
+        *P = pv.log2P;
+        return ret;
+}
+
 #endif