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authorBen Skeggs <bskeggs@redhat.com>2012-07-31 02:16:21 -0400
committerBen Skeggs <bskeggs@redhat.com>2012-10-02 23:12:59 -0400
commit77145f1cbdf8d28b46ff8070ca749bad821e0774 (patch)
treeb496d5d69ce4f5753028b07b09d8cf12025310f2
parent2094dd82eddc468b53ee99d92c38b23a65efac03 (diff)
drm/nouveau: port remainder of drm code, and rip out compat layer
v2: Ben Skeggs <bskeggs@redhat.com> - fill in nouveau_pm.dev to prevent oops - fix ppc issues (build + OF shadow) Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/Makefile47
-rw-r--r--drivers/gpu/drm/nouveau/core/include/subdev/timer.h4
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/bios/base.c30
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_backlight.c16
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.c270
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.h25
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bo.c10
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_calc.c18
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_compat.c609
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_compat.h141
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_connector.c129
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_display.c214
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_display.h94
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_dp.c74
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drm.c227
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drm.h27
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.c353
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h551
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fb.h47
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fbcon.c27
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fbcon.h2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_gem.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_hdmi.c41
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_hw.c150
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_hw.h88
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_irq.c130
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_irq.h11
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_mem.c119
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_perf.c63
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_pm.c254
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_pm.h194
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_prime.c8
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_revcompat.c22
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_revcompat.h12
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_state.c508
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_temp.c56
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_ttm.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_ttm.h4
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_vga.c98
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_vga.h8
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_volt.c48
-rw-r--r--drivers/gpu/drm/nouveau/nv04_crtc.c87
-rw-r--r--drivers/gpu/drm/nouveau/nv04_cursor.c6
-rw-r--r--drivers/gpu/drm/nouveau/nv04_dac.c116
-rw-r--r--drivers/gpu/drm/nouveau/nv04_dfp.c54
-rw-r--r--drivers/gpu/drm/nouveau/nv04_display.c26
-rw-r--r--drivers/gpu/drm/nouveau/nv04_display.h68
-rw-r--r--drivers/gpu/drm/nouveau/nv04_fbcon.c8
-rw-r--r--drivers/gpu/drm/nouveau/nv04_pm.c36
-rw-r--r--drivers/gpu/drm/nouveau/nv04_tv.c25
-rw-r--r--drivers/gpu/drm/nouveau/nv17_tv.c79
-rw-r--r--drivers/gpu/drm/nouveau/nv17_tv.h6
-rw-r--r--drivers/gpu/drm/nouveau/nv17_tv_modes.c2
-rw-r--r--drivers/gpu/drm/nouveau/nv40_pm.c150
-rw-r--r--drivers/gpu/drm/nouveau/nv50_crtc.c72
-rw-r--r--drivers/gpu/drm/nouveau/nv50_cursor.c32
-rw-r--r--drivers/gpu/drm/nouveau/nv50_dac.c83
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c368
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.h24
-rw-r--r--drivers/gpu/drm/nouveau/nv50_evo.c96
-rw-r--r--drivers/gpu/drm/nouveau/nv50_fbcon.c8
-rw-r--r--drivers/gpu/drm/nouveau/nv50_fence.c7
-rw-r--r--drivers/gpu/drm/nouveau/nv50_pm.c201
-rw-r--r--drivers/gpu/drm/nouveau/nv50_sor.c103
-rw-r--r--drivers/gpu/drm/nouveau/nv84_fence.c7
-rw-r--r--drivers/gpu/drm/nouveau/nva3_pm.c272
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_fbcon.c8
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_fence.c10
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_pm.c174
-rw-r--r--drivers/gpu/drm/nouveau/nvd0_display.c408
70 files changed, 3095 insertions, 4174 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index 72f1a1c2e56f..fe14f4bffde1 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -145,47 +145,17 @@ nouveau-y += core/engine/software/nv50.o
145nouveau-y += core/engine/software/nvc0.o 145nouveau-y += core/engine/software/nvc0.o
146nouveau-y += core/engine/vp/nv84.o 146nouveau-y += core/engine/vp/nv84.o
147 147
148# drm/compat - will go away
149nouveau-y += nouveau_compat.o nouveau_revcompat.o
150
151# drm/core 148# drm/core
152nouveau-y += nouveau_drm.o nouveau_chan.o nouveau_dma.o nouveau_fence.o 149nouveau-y += nouveau_drm.o nouveau_chan.o nouveau_dma.o nouveau_fence.o
153nouveau-y += nouveau_agp.o 150nouveau-y += nouveau_irq.o nouveau_vga.o nouveau_agp.o
154nouveau-y += nouveau_ttm.o nouveau_sgdma.o nouveau_bo.o nouveau_gem.o 151nouveau-y += nouveau_ttm.o nouveau_sgdma.o nouveau_bo.o nouveau_gem.o
155 152nouveau-y += nouveau_prime.o nouveau_abi16.o
156nouveau-y += nouveau_abi16.o
157nouveau-y += nv04_fence.o nv10_fence.o nv50_fence.o nv84_fence.o nvc0_fence.o 153nouveau-y += nv04_fence.o nv10_fence.o nv50_fence.o nv84_fence.o nvc0_fence.o
158 154
159# drm/kms/common 155# drm/kms
160nouveau-y += nouveau_fbcon.o 156nouveau-y += nouveau_bios.o nouveau_fbcon.o nouveau_display.o
161 157nouveau-y += nouveau_connector.o nouveau_hdmi.o nouveau_dp.o
162# drm/kms/nv04:nv50 158nouveau-y += nv04_fbcon.o nv50_fbcon.o nvc0_fbcon.o
163nouveau-y += nv04_fbcon.o
164
165# drm/kms/nv50:nvd9
166nouveau-y += nv50_fbcon.o nvc0_fbcon.o
167
168# drm/kms/nvd9-
169
170# other random bits
171nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o
172nouveau-$(CONFIG_ACPI) += nouveau_acpi.o
173nouveau-$(CONFIG_DRM_NOUVEAU_BACKLIGHT) += nouveau_backlight.o
174
175##
176## unported bits below
177##
178
179# drm/core
180nouveau-y += nouveau_drv.o nouveau_state.o nouveau_irq.o
181nouveau-y += nouveau_prime.o
182
183# drm/kms/bios
184nouveau-y += nouveau_bios.o
185
186# drm/kms/common
187nouveau-y += nouveau_display.o nouveau_connector.o
188nouveau-y += nouveau_hdmi.o nouveau_dp.o
189 159
190# drm/kms/nv04:nv50 160# drm/kms/nv04:nv50
191nouveau-y += nouveau_hw.o nouveau_calc.o 161nouveau-y += nouveau_hw.o nouveau_calc.o
@@ -202,4 +172,9 @@ nouveau-y += nouveau_pm.o nouveau_volt.o nouveau_perf.o nouveau_temp.o
202nouveau-y += nv04_pm.o nv40_pm.o nv50_pm.o nva3_pm.o nvc0_pm.o 172nouveau-y += nv04_pm.o nv40_pm.o nv50_pm.o nva3_pm.o nvc0_pm.o
203nouveau-y += nouveau_mem.o 173nouveau-y += nouveau_mem.o
204 174
175# other random bits
176nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o
177nouveau-$(CONFIG_ACPI) += nouveau_acpi.o
178nouveau-$(CONFIG_DRM_NOUVEAU_BACKLIGHT) += nouveau_backlight.o
179
205obj-$(CONFIG_DRM_NOUVEAU)+= nouveau.o 180obj-$(CONFIG_DRM_NOUVEAU)+= nouveau.o
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/timer.h b/drivers/gpu/drm/nouveau/core/include/subdev/timer.h
index d971b83caebe..49bff901544c 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/timer.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/timer.h
@@ -20,8 +20,8 @@ void nouveau_timer_alarm(void *, u32 nsec, struct nouveau_alarm *);
20 nouveau_timer_wait_eq((o), NV_WAIT_DEFAULT, (a), (m), (v)) 20 nouveau_timer_wait_eq((o), NV_WAIT_DEFAULT, (a), (m), (v))
21#define nv_wait_ne(o,a,m,v) \ 21#define nv_wait_ne(o,a,m,v) \
22 nouveau_timer_wait_ne((o), NV_WAIT_DEFAULT, (a), (m), (v)) 22 nouveau_timer_wait_ne((o), NV_WAIT_DEFAULT, (a), (m), (v))
23#define nv_wait_cb(o,a,m,v) \ 23#define nv_wait_cb(o,c,d) \
24 nouveau_timer_wait_cb((o), NV_WAIT_DEFAULT, (a), (m), (v)) 24 nouveau_timer_wait_cb((o), NV_WAIT_DEFAULT, (c), (d))
25 25
26struct nouveau_timer { 26struct nouveau_timer {
27 struct nouveau_subdev base; 27 struct nouveau_subdev base;
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/base.c b/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
index e8e46eca947b..2fbb6df697cd 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/bios/base.c
@@ -56,6 +56,31 @@ nvbios_findstr(const u8 *data, int size, const char *str, int len)
56 return 0; 56 return 0;
57} 57}
58 58
59#if defined(__powerpc__)
60static void
61nouveau_bios_shadow_of(struct nouveau_bios *bios)
62{
63 struct pci_dev *pdev = nv_device(bios)->pdev;
64 struct device_node *dn;
65 const u32 *data;
66 int size, i;
67
68 dn = pci_device_to_OF_node(pdev);
69 if (!dn) {
70 nv_info(bios, "Unable to get the OF node\n");
71 return;
72 }
73
74 data = of_get_property(dn, "NVDA,BMP", &size);
75 if (data) {
76 bios->size = size;
77 bios->data = kmalloc(bios->size, GFP_KERNEL);
78 if (bios->data)
79 memcpy(bios->data, data, size);
80 }
81}
82#endif
83
59static void 84static void
60nouveau_bios_shadow_pramin(struct nouveau_bios *bios) 85nouveau_bios_shadow_pramin(struct nouveau_bios *bios)
61{ 86{
@@ -221,7 +246,7 @@ nouveau_bios_score(struct nouveau_bios *bios, const bool writeable)
221} 246}
222 247
223struct methods { 248struct methods {
224 const char desc[8]; 249 const char desc[16];
225 void (*shadow)(struct nouveau_bios *); 250 void (*shadow)(struct nouveau_bios *);
226 const bool rw; 251 const bool rw;
227 int score; 252 int score;
@@ -233,6 +258,9 @@ static int
233nouveau_bios_shadow(struct nouveau_bios *bios) 258nouveau_bios_shadow(struct nouveau_bios *bios)
234{ 259{
235 struct methods shadow_methods[] = { 260 struct methods shadow_methods[] = {
261#if defined(__powerpc__)
262 { "OpenFirmware", nouveau_bios_shadow_of, true, 0, 0, NULL },
263#endif
236 { "PRAMIN", nouveau_bios_shadow_pramin, true, 0, 0, NULL }, 264 { "PRAMIN", nouveau_bios_shadow_pramin, true, 0, 0, NULL },
237 { "PROM", nouveau_bios_shadow_prom, false, 0, 0, NULL }, 265 { "PROM", nouveau_bios_shadow_prom, false, 0, 0, NULL },
238 { "ACPI", nouveau_bios_shadow_acpi, true, 0, 0, NULL }, 266 { "ACPI", nouveau_bios_shadow_acpi, true, 0, 0, NULL },
diff --git a/drivers/gpu/drm/nouveau/nouveau_backlight.c b/drivers/gpu/drm/nouveau/nouveau_backlight.c
index 5c4cc7a2117a..f65b20a375f6 100644
--- a/drivers/gpu/drm/nouveau/nouveau_backlight.c
+++ b/drivers/gpu/drm/nouveau/nouveau_backlight.c
@@ -71,7 +71,7 @@ static const struct backlight_ops nv40_bl_ops = {
71static int 71static int
72nv40_backlight_init(struct drm_connector *connector) 72nv40_backlight_init(struct drm_connector *connector)
73{ 73{
74 struct nouveau_drm *drm = nouveau_newpriv(connector->dev); 74 struct nouveau_drm *drm = nouveau_drm(connector->dev);
75 struct nouveau_device *device = nv_device(drm->device); 75 struct nouveau_device *device = nv_device(drm->device);
76 struct backlight_properties props; 76 struct backlight_properties props;
77 struct backlight_device *bd; 77 struct backlight_device *bd;
@@ -95,7 +95,7 @@ static int
95nv50_get_intensity(struct backlight_device *bd) 95nv50_get_intensity(struct backlight_device *bd)
96{ 96{
97 struct nouveau_encoder *nv_encoder = bl_get_data(bd); 97 struct nouveau_encoder *nv_encoder = bl_get_data(bd);
98 struct nouveau_drm *drm = nouveau_newpriv(nv_encoder->base.base.dev); 98 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
99 struct nouveau_device *device = nv_device(drm->device); 99 struct nouveau_device *device = nv_device(drm->device);
100 int or = nv_encoder->or; 100 int or = nv_encoder->or;
101 u32 div = 1025; 101 u32 div = 1025;
@@ -110,7 +110,7 @@ static int
110nv50_set_intensity(struct backlight_device *bd) 110nv50_set_intensity(struct backlight_device *bd)
111{ 111{
112 struct nouveau_encoder *nv_encoder = bl_get_data(bd); 112 struct nouveau_encoder *nv_encoder = bl_get_data(bd);
113 struct nouveau_drm *drm = nouveau_newpriv(nv_encoder->base.base.dev); 113 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
114 struct nouveau_device *device = nv_device(drm->device); 114 struct nouveau_device *device = nv_device(drm->device);
115 int or = nv_encoder->or; 115 int or = nv_encoder->or;
116 u32 div = 1025; 116 u32 div = 1025;
@@ -131,7 +131,7 @@ static int
131nva3_get_intensity(struct backlight_device *bd) 131nva3_get_intensity(struct backlight_device *bd)
132{ 132{
133 struct nouveau_encoder *nv_encoder = bl_get_data(bd); 133 struct nouveau_encoder *nv_encoder = bl_get_data(bd);
134 struct nouveau_drm *drm = nouveau_newpriv(nv_encoder->base.base.dev); 134 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
135 struct nouveau_device *device = nv_device(drm->device); 135 struct nouveau_device *device = nv_device(drm->device);
136 int or = nv_encoder->or; 136 int or = nv_encoder->or;
137 u32 div, val; 137 u32 div, val;
@@ -149,7 +149,7 @@ static int
149nva3_set_intensity(struct backlight_device *bd) 149nva3_set_intensity(struct backlight_device *bd)
150{ 150{
151 struct nouveau_encoder *nv_encoder = bl_get_data(bd); 151 struct nouveau_encoder *nv_encoder = bl_get_data(bd);
152 struct nouveau_drm *drm = nouveau_newpriv(nv_encoder->base.base.dev); 152 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
153 struct nouveau_device *device = nv_device(drm->device); 153 struct nouveau_device *device = nv_device(drm->device);
154 int or = nv_encoder->or; 154 int or = nv_encoder->or;
155 u32 div, val; 155 u32 div, val;
@@ -175,7 +175,7 @@ static const struct backlight_ops nva3_bl_ops = {
175static int 175static int
176nv50_backlight_init(struct drm_connector *connector) 176nv50_backlight_init(struct drm_connector *connector)
177{ 177{
178 struct nouveau_drm *drm = nouveau_newpriv(connector->dev); 178 struct nouveau_drm *drm = nouveau_drm(connector->dev);
179 struct nouveau_device *device = nv_device(drm->device); 179 struct nouveau_device *device = nv_device(drm->device);
180 struct nouveau_encoder *nv_encoder; 180 struct nouveau_encoder *nv_encoder;
181 struct backlight_properties props; 181 struct backlight_properties props;
@@ -216,7 +216,7 @@ nv50_backlight_init(struct drm_connector *connector)
216int 216int
217nouveau_backlight_init(struct drm_device *dev) 217nouveau_backlight_init(struct drm_device *dev)
218{ 218{
219 struct nouveau_drm *drm = nouveau_newpriv(dev); 219 struct nouveau_drm *drm = nouveau_drm(dev);
220 struct nouveau_device *device = nv_device(drm->device); 220 struct nouveau_device *device = nv_device(drm->device);
221 struct drm_connector *connector; 221 struct drm_connector *connector;
222 222
@@ -250,7 +250,7 @@ nouveau_backlight_init(struct drm_device *dev)
250void 250void
251nouveau_backlight_exit(struct drm_device *dev) 251nouveau_backlight_exit(struct drm_device *dev)
252{ 252{
253 struct nouveau_drm *drm = nouveau_newpriv(dev); 253 struct nouveau_drm *drm = nouveau_drm(dev);
254 254
255 if (drm->backlight) { 255 if (drm->backlight) {
256 backlight_device_unregister(drm->backlight); 256 backlight_device_unregister(drm->backlight);
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index b83c672a945a..f6b7fa39d312 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -22,9 +22,11 @@
22 * SOFTWARE. 22 * SOFTWARE.
23 */ 23 */
24 24
25#include <subdev/bios.h>
26
25#include "drmP.h" 27#include "drmP.h"
26#define NV_DEBUG_NOTRACE 28#include "nouveau_drm.h"
27#include "nouveau_drv.h" 29#include "nouveau_reg.h"
28#include "nouveau_hw.h" 30#include "nouveau_hw.h"
29#include "nouveau_encoder.h" 31#include "nouveau_encoder.h"
30 32
@@ -94,7 +96,9 @@ static void
94run_digital_op_script(struct drm_device *dev, uint16_t scriptptr, 96run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
95 struct dcb_output *dcbent, int head, bool dl) 97 struct dcb_output *dcbent, int head, bool dl)
96{ 98{
97 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n", 99 struct nouveau_drm *drm = nouveau_drm(dev);
100
101 NV_INFO(drm, "0x%04X: Parsing digital output script table\n",
98 scriptptr); 102 scriptptr);
99 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, head ? NV_CIO_CRE_44_HEADB : 103 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, head ? NV_CIO_CRE_44_HEADB :
100 NV_CIO_CRE_44_HEADA); 104 NV_CIO_CRE_44_HEADA);
@@ -105,8 +109,8 @@ run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
105 109
106static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_output *dcbent, int head, enum LVDS_script script) 110static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_output *dcbent, int head, enum LVDS_script script)
107{ 111{
108 struct drm_nouveau_private *dev_priv = dev->dev_private; 112 struct nouveau_drm *drm = nouveau_drm(dev);
109 struct nvbios *bios = &dev_priv->vbios; 113 struct nvbios *bios = &drm->vbios;
110 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & DCB_OUTPUT_C ? 1 : 0); 114 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & DCB_OUTPUT_C ? 1 : 0);
111 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]); 115 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
112 116
@@ -142,8 +146,8 @@ static int run_lvds_table(struct drm_device *dev, struct dcb_output *dcbent, int
142 * conf byte. These tables are similar to the TMDS tables, consisting 146 * conf byte. These tables are similar to the TMDS tables, consisting
143 * of a list of pxclks and script pointers. 147 * of a list of pxclks and script pointers.
144 */ 148 */
145 struct drm_nouveau_private *dev_priv = dev->dev_private; 149 struct nouveau_drm *drm = nouveau_drm(dev);
146 struct nvbios *bios = &dev_priv->vbios; 150 struct nvbios *bios = &drm->vbios;
147 unsigned int outputset = (dcbent->or == 4) ? 1 : 0; 151 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
148 uint16_t scriptptr = 0, clktable; 152 uint16_t scriptptr = 0, clktable;
149 153
@@ -188,14 +192,14 @@ static int run_lvds_table(struct drm_device *dev, struct dcb_output *dcbent, int
188 192
189 clktable = ROM16(bios->data[clktable]); 193 clktable = ROM16(bios->data[clktable]);
190 if (!clktable) { 194 if (!clktable) {
191 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 195 NV_ERROR(drm, "Pixel clock comparison table not found\n");
192 return -ENOENT; 196 return -ENOENT;
193 } 197 }
194 scriptptr = clkcmptable(bios, clktable, pxclk); 198 scriptptr = clkcmptable(bios, clktable, pxclk);
195 } 199 }
196 200
197 if (!scriptptr) { 201 if (!scriptptr) {
198 NV_ERROR(dev, "LVDS output init script not found\n"); 202 NV_ERROR(drm, "LVDS output init script not found\n");
199 return -ENOENT; 203 return -ENOENT;
200 } 204 }
201 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link); 205 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
@@ -211,8 +215,9 @@ int call_lvds_script(struct drm_device *dev, struct dcb_output *dcbent, int head
211 * This acts as the demux 215 * This acts as the demux
212 */ 216 */
213 217
214 struct drm_nouveau_private *dev_priv = dev->dev_private; 218 struct nouveau_drm *drm = nouveau_drm(dev);
215 struct nvbios *bios = &dev_priv->vbios; 219 struct nouveau_device *device = nv_device(drm->device);
220 struct nvbios *bios = &drm->vbios;
216 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; 221 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
217 uint32_t sel_clk_binding, sel_clk; 222 uint32_t sel_clk_binding, sel_clk;
218 int ret; 223 int ret;
@@ -231,10 +236,10 @@ int call_lvds_script(struct drm_device *dev, struct dcb_output *dcbent, int head
231 if (script == LVDS_RESET && bios->fp.power_off_for_reset) 236 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
232 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk); 237 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
233 238
234 NV_TRACE(dev, "Calling LVDS script %d:\n", script); 239 NV_INFO(drm, "Calling LVDS script %d:\n", script);
235 240
236 /* don't let script change pll->head binding */ 241 /* don't let script change pll->head binding */
237 sel_clk_binding = nv_rd32(dev, NV_PRAMDAC_SEL_CLK) & 0x50000; 242 sel_clk_binding = nv_rd32(device, NV_PRAMDAC_SEL_CLK) & 0x50000;
238 243
239 if (lvds_ver < 0x30) 244 if (lvds_ver < 0x30)
240 ret = call_lvds_manufacturer_script(dev, dcbent, head, script); 245 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
@@ -246,7 +251,7 @@ int call_lvds_script(struct drm_device *dev, struct dcb_output *dcbent, int head
246 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; 251 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
247 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); 252 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
248 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */ 253 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
249 nv_wr32(dev, NV_PBUS_POWERCTRL_2, 0); 254 nv_wr32(device, NV_PBUS_POWERCTRL_2, 0);
250 255
251 return ret; 256 return ret;
252} 257}
@@ -264,12 +269,13 @@ static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct n
264 * the maximum number of records that can be held in the table. 269 * the maximum number of records that can be held in the table.
265 */ 270 */
266 271
272 struct nouveau_drm *drm = nouveau_drm(dev);
267 uint8_t lvds_ver, headerlen, recordlen; 273 uint8_t lvds_ver, headerlen, recordlen;
268 274
269 memset(lth, 0, sizeof(struct lvdstableheader)); 275 memset(lth, 0, sizeof(struct lvdstableheader));
270 276
271 if (bios->fp.lvdsmanufacturerpointer == 0x0) { 277 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
272 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n"); 278 NV_ERROR(drm, "Pointer to LVDS manufacturer table invalid\n");
273 return -EINVAL; 279 return -EINVAL;
274 } 280 }
275 281
@@ -283,7 +289,7 @@ static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct n
283 case 0x30: /* NV4x */ 289 case 0x30: /* NV4x */
284 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 290 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
285 if (headerlen < 0x1f) { 291 if (headerlen < 0x1f) {
286 NV_ERROR(dev, "LVDS table header not understood\n"); 292 NV_ERROR(drm, "LVDS table header not understood\n");
287 return -EINVAL; 293 return -EINVAL;
288 } 294 }
289 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; 295 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
@@ -291,13 +297,13 @@ static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct n
291 case 0x40: /* G80/G90 */ 297 case 0x40: /* G80/G90 */
292 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; 298 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
293 if (headerlen < 0x7) { 299 if (headerlen < 0x7) {
294 NV_ERROR(dev, "LVDS table header not understood\n"); 300 NV_ERROR(drm, "LVDS table header not understood\n");
295 return -EINVAL; 301 return -EINVAL;
296 } 302 }
297 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; 303 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
298 break; 304 break;
299 default: 305 default:
300 NV_ERROR(dev, 306 NV_ERROR(drm,
301 "LVDS table revision %d.%d not currently supported\n", 307 "LVDS table revision %d.%d not currently supported\n",
302 lvds_ver >> 4, lvds_ver & 0xf); 308 lvds_ver >> 4, lvds_ver & 0xf);
303 return -ENOSYS; 309 return -ENOSYS;
@@ -313,7 +319,7 @@ static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct n
313static int 319static int
314get_fp_strap(struct drm_device *dev, struct nvbios *bios) 320get_fp_strap(struct drm_device *dev, struct nvbios *bios)
315{ 321{
316 struct drm_nouveau_private *dev_priv = dev->dev_private; 322 struct nouveau_device *device = nouveau_dev(dev);
317 323
318 /* 324 /*
319 * The fp strap is normally dictated by the "User Strap" in 325 * The fp strap is normally dictated by the "User Strap" in
@@ -327,14 +333,15 @@ get_fp_strap(struct drm_device *dev, struct nvbios *bios)
327 if (bios->major_version < 5 && bios->data[0x48] & 0x4) 333 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
328 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf; 334 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
329 335
330 if (dev_priv->card_type >= NV_50) 336 if (device->card_type >= NV_50)
331 return (nv_rd32(dev, NV_PEXTDEV_BOOT_0) >> 24) & 0xf; 337 return (nv_rd32(device, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
332 else 338 else
333 return (nv_rd32(dev, NV_PEXTDEV_BOOT_0) >> 16) & 0xf; 339 return (nv_rd32(device, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
334} 340}
335 341
336static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios) 342static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
337{ 343{
344 struct nouveau_drm *drm = nouveau_drm(dev);
338 uint8_t *fptable; 345 uint8_t *fptable;
339 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex; 346 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
340 int ret, ofs, fpstrapping; 347 int ret, ofs, fpstrapping;
@@ -344,7 +351,7 @@ static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
344 /* Apple cards don't have the fp table; the laptops use DDC */ 351 /* Apple cards don't have the fp table; the laptops use DDC */
345 /* The table is also missing on some x86 IGPs */ 352 /* The table is also missing on some x86 IGPs */
346#ifndef __powerpc__ 353#ifndef __powerpc__
347 NV_ERROR(dev, "Pointer to flat panel table invalid\n"); 354 NV_ERROR(drm, "Pointer to flat panel table invalid\n");
348#endif 355#endif
349 bios->digital_min_front_porch = 0x4b; 356 bios->digital_min_front_porch = 0x4b;
350 return 0; 357 return 0;
@@ -383,7 +390,7 @@ static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
383 ofs = -7; 390 ofs = -7;
384 break; 391 break;
385 default: 392 default:
386 NV_ERROR(dev, 393 NV_ERROR(drm,
387 "FP table revision %d.%d not currently supported\n", 394 "FP table revision %d.%d not currently supported\n",
388 fptable_ver >> 4, fptable_ver & 0xf); 395 fptable_ver >> 4, fptable_ver & 0xf);
389 return -ENOSYS; 396 return -ENOSYS;
@@ -402,7 +409,7 @@ static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
402 bios->fp.xlatwidth = lth.recordlen; 409 bios->fp.xlatwidth = lth.recordlen;
403 } 410 }
404 if (bios->fp.fpxlatetableptr == 0x0) { 411 if (bios->fp.fpxlatetableptr == 0x0) {
405 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n"); 412 NV_ERROR(drm, "Pointer to flat panel xlat table invalid\n");
406 return -EINVAL; 413 return -EINVAL;
407 } 414 }
408 415
@@ -412,7 +419,7 @@ static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
412 fpstrapping * bios->fp.xlatwidth]; 419 fpstrapping * bios->fp.xlatwidth];
413 420
414 if (fpindex > fpentries) { 421 if (fpindex > fpentries) {
415 NV_ERROR(dev, "Bad flat panel table index\n"); 422 NV_ERROR(drm, "Bad flat panel table index\n");
416 return -ENOENT; 423 return -ENOENT;
417 } 424 }
418 425
@@ -431,7 +438,7 @@ static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
431 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen + 438 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
432 recordlen * fpindex + ofs; 439 recordlen * fpindex + ofs;
433 440
434 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n", 441 NV_INFO(drm, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
435 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1, 442 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
436 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1, 443 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
437 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10); 444 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
@@ -441,8 +448,8 @@ static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
441 448
442bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode) 449bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
443{ 450{
444 struct drm_nouveau_private *dev_priv = dev->dev_private; 451 struct nouveau_drm *drm = nouveau_drm(dev);
445 struct nvbios *bios = &dev_priv->vbios; 452 struct nvbios *bios = &drm->vbios;
446 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr]; 453 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
447 454
448 if (!mode) /* just checking whether we can produce a mode */ 455 if (!mode) /* just checking whether we can produce a mode */
@@ -512,8 +519,8 @@ int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, b
512 * requiring tests against the native-mode pixel clock, cannot be done 519 * requiring tests against the native-mode pixel clock, cannot be done
513 * until later, when this function should be called with non-zero pxclk 520 * until later, when this function should be called with non-zero pxclk
514 */ 521 */
515 struct drm_nouveau_private *dev_priv = dev->dev_private; 522 struct nouveau_drm *drm = nouveau_drm(dev);
516 struct nvbios *bios = &dev_priv->vbios; 523 struct nvbios *bios = &drm->vbios;
517 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0; 524 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
518 struct lvdstableheader lth; 525 struct lvdstableheader lth;
519 uint16_t lvdsofs; 526 uint16_t lvdsofs;
@@ -574,7 +581,7 @@ int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, b
574 lvdsmanufacturerindex = fpstrapping; 581 lvdsmanufacturerindex = fpstrapping;
575 break; 582 break;
576 default: 583 default:
577 NV_ERROR(dev, "LVDS table revision not currently supported\n"); 584 NV_ERROR(drm, "LVDS table revision not currently supported\n");
578 return -ENOSYS; 585 return -ENOSYS;
579 } 586 }
580 587
@@ -671,15 +678,15 @@ nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk,
671 * offset + 5 (16 bits): pointer to first output script table 678 * offset + 5 (16 bits): pointer to first output script table
672 */ 679 */
673 680
674 struct drm_nouveau_private *dev_priv = dev->dev_private; 681 struct nouveau_drm *drm = nouveau_drm(dev);
675 struct nvbios *bios = &dev_priv->vbios; 682 struct nvbios *bios = &drm->vbios;
676 uint8_t *table = &bios->data[bios->display.script_table_ptr]; 683 uint8_t *table = &bios->data[bios->display.script_table_ptr];
677 uint8_t *otable = NULL; 684 uint8_t *otable = NULL;
678 uint16_t script; 685 uint16_t script;
679 int i; 686 int i;
680 687
681 if (!bios->display.script_table_ptr) { 688 if (!bios->display.script_table_ptr) {
682 NV_ERROR(dev, "No pointer to output script table\n"); 689 NV_ERROR(drm, "No pointer to output script table\n");
683 return 1; 690 return 1;
684 } 691 }
685 692
@@ -691,7 +698,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk,
691 return 1; 698 return 1;
692 699
693 if (table[0] != 0x20 && table[0] != 0x21) { 700 if (table[0] != 0x20 && table[0] != 0x21) {
694 NV_ERROR(dev, "Output script table version 0x%02x unknown\n", 701 NV_ERROR(drm, "Output script table version 0x%02x unknown\n",
695 table[0]); 702 table[0]);
696 return 1; 703 return 1;
697 } 704 }
@@ -726,7 +733,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk,
726 * script tables is a pointer to the script to execute. 733 * script tables is a pointer to the script to execute.
727 */ 734 */
728 735
729 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n", 736 NV_DEBUG(drm, "Searching for output entry for %d %d %d\n",
730 dcbent->type, dcbent->location, dcbent->or); 737 dcbent->type, dcbent->location, dcbent->or);
731 for (i = 0; i < table[3]; i++) { 738 for (i = 0; i < table[3]; i++) {
732 otable = ROMPTR(dev, table[table[1] + (i * table[2])]); 739 otable = ROMPTR(dev, table[table[1] + (i * table[2])]);
@@ -735,7 +742,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk,
735 } 742 }
736 743
737 if (!otable) { 744 if (!otable) {
738 NV_DEBUG_KMS(dev, "failed to match any output table\n"); 745 NV_DEBUG(drm, "failed to match any output table\n");
739 return 1; 746 return 1;
740 } 747 }
741 748
@@ -747,7 +754,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk,
747 } 754 }
748 755
749 if (i == otable[5]) { 756 if (i == otable[5]) {
750 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, " 757 NV_ERROR(drm, "Table 0x%04x not found for %d/%d, "
751 "using first\n", 758 "using first\n",
752 type, dcbent->type, dcbent->or); 759 type, dcbent->type, dcbent->or);
753 i = 0; 760 i = 0;
@@ -757,21 +764,21 @@ nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk,
757 if (pclk == 0) { 764 if (pclk == 0) {
758 script = ROM16(otable[6]); 765 script = ROM16(otable[6]);
759 if (!script) { 766 if (!script) {
760 NV_DEBUG_KMS(dev, "output script 0 not found\n"); 767 NV_DEBUG(drm, "output script 0 not found\n");
761 return 1; 768 return 1;
762 } 769 }
763 770
764 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 0\n", script); 771 NV_DEBUG(drm, "0x%04X: parsing output script 0\n", script);
765 nouveau_bios_run_init_table(dev, script, dcbent, crtc); 772 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
766 } else 773 } else
767 if (pclk == -1) { 774 if (pclk == -1) {
768 script = ROM16(otable[8]); 775 script = ROM16(otable[8]);
769 if (!script) { 776 if (!script) {
770 NV_DEBUG_KMS(dev, "output script 1 not found\n"); 777 NV_DEBUG(drm, "output script 1 not found\n");
771 return 1; 778 return 1;
772 } 779 }
773 780
774 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 1\n", script); 781 NV_DEBUG(drm, "0x%04X: parsing output script 1\n", script);
775 nouveau_bios_run_init_table(dev, script, dcbent, crtc); 782 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
776 } else 783 } else
777 if (pclk == -2) { 784 if (pclk == -2) {
@@ -780,11 +787,11 @@ nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk,
780 else 787 else
781 script = 0; 788 script = 0;
782 if (!script) { 789 if (!script) {
783 NV_DEBUG_KMS(dev, "output script 2 not found\n"); 790 NV_DEBUG(drm, "output script 2 not found\n");
784 return 1; 791 return 1;
785 } 792 }
786 793
787 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 2\n", script); 794 NV_DEBUG(drm, "0x%04X: parsing output script 2\n", script);
788 nouveau_bios_run_init_table(dev, script, dcbent, crtc); 795 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
789 } else 796 } else
790 if (pclk > 0) { 797 if (pclk > 0) {
@@ -792,11 +799,11 @@ nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk,
792 if (script) 799 if (script)
793 script = clkcmptable(bios, script, pclk); 800 script = clkcmptable(bios, script, pclk);
794 if (!script) { 801 if (!script) {
795 NV_DEBUG_KMS(dev, "clock script 0 not found\n"); 802 NV_DEBUG(drm, "clock script 0 not found\n");
796 return 1; 803 return 1;
797 } 804 }
798 805
799 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 0\n", script); 806 NV_DEBUG(drm, "0x%04X: parsing clock script 0\n", script);
800 nouveau_bios_run_init_table(dev, script, dcbent, crtc); 807 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
801 } else 808 } else
802 if (pclk < 0) { 809 if (pclk < 0) {
@@ -804,11 +811,11 @@ nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk,
804 if (script) 811 if (script)
805 script = clkcmptable(bios, script, -pclk); 812 script = clkcmptable(bios, script, -pclk);
806 if (!script) { 813 if (!script) {
807 NV_DEBUG_KMS(dev, "clock script 1 not found\n"); 814 NV_DEBUG(drm, "clock script 1 not found\n");
808 return 1; 815 return 1;
809 } 816 }
810 817
811 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 1\n", script); 818 NV_DEBUG(drm, "0x%04X: parsing clock script 1\n", script);
812 nouveau_bios_run_init_table(dev, script, dcbent, crtc); 819 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
813 } 820 }
814 821
@@ -827,8 +834,9 @@ int run_tmds_table(struct drm_device *dev, struct dcb_output *dcbent, int head,
827 * ffs(or) == 3, use the second. 834 * ffs(or) == 3, use the second.
828 */ 835 */
829 836
830 struct drm_nouveau_private *dev_priv = dev->dev_private; 837 struct nouveau_drm *drm = nouveau_drm(dev);
831 struct nvbios *bios = &dev_priv->vbios; 838 struct nouveau_device *device = nv_device(drm->device);
839 struct nvbios *bios = &drm->vbios;
832 int cv = bios->chip_version; 840 int cv = bios->chip_version;
833 uint16_t clktable = 0, scriptptr; 841 uint16_t clktable = 0, scriptptr;
834 uint32_t sel_clk_binding, sel_clk; 842 uint32_t sel_clk_binding, sel_clk;
@@ -849,19 +857,19 @@ int run_tmds_table(struct drm_device *dev, struct dcb_output *dcbent, int head,
849 } 857 }
850 858
851 if (!clktable) { 859 if (!clktable) {
852 NV_ERROR(dev, "Pixel clock comparison table not found\n"); 860 NV_ERROR(drm, "Pixel clock comparison table not found\n");
853 return -EINVAL; 861 return -EINVAL;
854 } 862 }
855 863
856 scriptptr = clkcmptable(bios, clktable, pxclk); 864 scriptptr = clkcmptable(bios, clktable, pxclk);
857 865
858 if (!scriptptr) { 866 if (!scriptptr) {
859 NV_ERROR(dev, "TMDS output init script not found\n"); 867 NV_ERROR(drm, "TMDS output init script not found\n");
860 return -ENOENT; 868 return -ENOENT;
861 } 869 }
862 870
863 /* don't let script change pll->head binding */ 871 /* don't let script change pll->head binding */
864 sel_clk_binding = nv_rd32(dev, NV_PRAMDAC_SEL_CLK) & 0x50000; 872 sel_clk_binding = nv_rd32(device, NV_PRAMDAC_SEL_CLK) & 0x50000;
865 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000); 873 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
866 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; 874 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
867 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); 875 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
@@ -877,10 +885,11 @@ static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint
877 * offset + 2 (8 bits): Chip version 885 * offset + 2 (8 bits): Chip version
878 * offset + 3 (8 bits): Major version 886 * offset + 3 (8 bits): Major version
879 */ 887 */
888 struct nouveau_drm *drm = nouveau_drm(dev);
880 889
881 bios->major_version = bios->data[offset + 3]; 890 bios->major_version = bios->data[offset + 3];
882 bios->chip_version = bios->data[offset + 2]; 891 bios->chip_version = bios->data[offset + 2];
883 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n", 892 NV_INFO(drm, "Bios version %02x.%02x.%02x.%02x\n",
884 bios->data[offset + 3], bios->data[offset + 2], 893 bios->data[offset + 3], bios->data[offset + 2],
885 bios->data[offset + 1], bios->data[offset]); 894 bios->data[offset + 1], bios->data[offset]);
886} 895}
@@ -916,25 +925,26 @@ static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, st
916 * offset + 0 (16 bits): loadval table pointer 925 * offset + 0 (16 bits): loadval table pointer
917 */ 926 */
918 927
928 struct nouveau_drm *drm = nouveau_drm(dev);
919 uint16_t load_table_ptr; 929 uint16_t load_table_ptr;
920 uint8_t version, headerlen, entrylen, num_entries; 930 uint8_t version, headerlen, entrylen, num_entries;
921 931
922 if (bitentry->length != 3) { 932 if (bitentry->length != 3) {
923 NV_ERROR(dev, "Do not understand BIT A table\n"); 933 NV_ERROR(drm, "Do not understand BIT A table\n");
924 return -EINVAL; 934 return -EINVAL;
925 } 935 }
926 936
927 load_table_ptr = ROM16(bios->data[bitentry->offset]); 937 load_table_ptr = ROM16(bios->data[bitentry->offset]);
928 938
929 if (load_table_ptr == 0x0) { 939 if (load_table_ptr == 0x0) {
930 NV_DEBUG(dev, "Pointer to BIT loadval table invalid\n"); 940 NV_DEBUG(drm, "Pointer to BIT loadval table invalid\n");
931 return -EINVAL; 941 return -EINVAL;
932 } 942 }
933 943
934 version = bios->data[load_table_ptr]; 944 version = bios->data[load_table_ptr];
935 945
936 if (version != 0x10) { 946 if (version != 0x10) {
937 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n", 947 NV_ERROR(drm, "BIT loadval table version %d.%d not supported\n",
938 version >> 4, version & 0xF); 948 version >> 4, version & 0xF);
939 return -ENOSYS; 949 return -ENOSYS;
940 } 950 }
@@ -944,7 +954,7 @@ static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, st
944 num_entries = bios->data[load_table_ptr + 3]; 954 num_entries = bios->data[load_table_ptr + 3];
945 955
946 if (headerlen != 4 || entrylen != 4 || num_entries != 2) { 956 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
947 NV_ERROR(dev, "Do not understand BIT loadval table\n"); 957 NV_ERROR(drm, "Do not understand BIT loadval table\n");
948 return -EINVAL; 958 return -EINVAL;
949 } 959 }
950 960
@@ -961,9 +971,10 @@ static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, st
961 * 971 *
962 * There's more in here, but that's unknown. 972 * There's more in here, but that's unknown.
963 */ 973 */
974 struct nouveau_drm *drm = nouveau_drm(dev);
964 975
965 if (bitentry->length < 10) { 976 if (bitentry->length < 10) {
966 NV_ERROR(dev, "Do not understand BIT C table\n"); 977 NV_ERROR(drm, "Do not understand BIT C table\n");
967 return -EINVAL; 978 return -EINVAL;
968 } 979 }
969 980
@@ -982,9 +993,10 @@ static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bi
982 * records beginning with a freq. 993 * records beginning with a freq.
983 * offset + 2 (16 bits): mode table pointer 994 * offset + 2 (16 bits): mode table pointer
984 */ 995 */
996 struct nouveau_drm *drm = nouveau_drm(dev);
985 997
986 if (bitentry->length != 4) { 998 if (bitentry->length != 4) {
987 NV_ERROR(dev, "Do not understand BIT display table\n"); 999 NV_ERROR(drm, "Do not understand BIT display table\n");
988 return -EINVAL; 1000 return -EINVAL;
989 } 1001 }
990 1002
@@ -1000,9 +1012,10 @@ static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios,
1000 * 1012 *
1001 * See parse_script_table_pointers for layout 1013 * See parse_script_table_pointers for layout
1002 */ 1014 */
1015 struct nouveau_drm *drm = nouveau_drm(dev);
1003 1016
1004 if (bitentry->length < 14) { 1017 if (bitentry->length < 14) {
1005 NV_ERROR(dev, "Do not understand init table\n"); 1018 NV_ERROR(drm, "Do not understand init table\n");
1006 return -EINVAL; 1019 return -EINVAL;
1007 } 1020 }
1008 1021
@@ -1029,11 +1042,12 @@ static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, st
1029 * There's other things in the table, purpose unknown 1042 * There's other things in the table, purpose unknown
1030 */ 1043 */
1031 1044
1045 struct nouveau_drm *drm = nouveau_drm(dev);
1032 uint16_t daccmpoffset; 1046 uint16_t daccmpoffset;
1033 uint8_t dacver, dacheaderlen; 1047 uint8_t dacver, dacheaderlen;
1034 1048
1035 if (bitentry->length < 6) { 1049 if (bitentry->length < 6) {
1036 NV_ERROR(dev, "BIT i table too short for needed information\n"); 1050 NV_ERROR(drm, "BIT i table too short for needed information\n");
1037 return -EINVAL; 1051 return -EINVAL;
1038 } 1052 }
1039 1053
@@ -1047,7 +1061,7 @@ static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, st
1047 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE; 1061 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
1048 1062
1049 if (bitentry->length < 15) { 1063 if (bitentry->length < 15) {
1050 NV_WARN(dev, "BIT i table not long enough for DAC load " 1064 NV_WARN(drm, "BIT i table not long enough for DAC load "
1051 "detection comparison table\n"); 1065 "detection comparison table\n");
1052 return -EINVAL; 1066 return -EINVAL;
1053 } 1067 }
@@ -1068,7 +1082,7 @@ static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, st
1068 dacheaderlen = bios->data[daccmpoffset + 1]; 1082 dacheaderlen = bios->data[daccmpoffset + 1];
1069 1083
1070 if (dacver != 0x00 && dacver != 0x10) { 1084 if (dacver != 0x00 && dacver != 0x10) {
1071 NV_WARN(dev, "DAC load detection comparison table version " 1085 NV_WARN(drm, "DAC load detection comparison table version "
1072 "%d.%d not known\n", dacver >> 4, dacver & 0xf); 1086 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
1073 return -ENOSYS; 1087 return -ENOSYS;
1074 } 1088 }
@@ -1088,8 +1102,10 @@ static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios,
1088 * offset + 0 (16 bits): LVDS strap xlate table pointer 1102 * offset + 0 (16 bits): LVDS strap xlate table pointer
1089 */ 1103 */
1090 1104
1105 struct nouveau_drm *drm = nouveau_drm(dev);
1106
1091 if (bitentry->length != 2) { 1107 if (bitentry->length != 2) {
1092 NV_ERROR(dev, "Do not understand BIT LVDS table\n"); 1108 NV_ERROR(drm, "Do not understand BIT LVDS table\n");
1093 return -EINVAL; 1109 return -EINVAL;
1094 } 1110 }
1095 1111
@@ -1159,20 +1175,21 @@ static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios,
1159 * "or" from the DCB. 1175 * "or" from the DCB.
1160 */ 1176 */
1161 1177
1178 struct nouveau_drm *drm = nouveau_drm(dev);
1162 uint16_t tmdstableptr, script1, script2; 1179 uint16_t tmdstableptr, script1, script2;
1163 1180
1164 if (bitentry->length != 2) { 1181 if (bitentry->length != 2) {
1165 NV_ERROR(dev, "Do not understand BIT TMDS table\n"); 1182 NV_ERROR(drm, "Do not understand BIT TMDS table\n");
1166 return -EINVAL; 1183 return -EINVAL;
1167 } 1184 }
1168 1185
1169 tmdstableptr = ROM16(bios->data[bitentry->offset]); 1186 tmdstableptr = ROM16(bios->data[bitentry->offset]);
1170 if (!tmdstableptr) { 1187 if (!tmdstableptr) {
1171 NV_ERROR(dev, "Pointer to TMDS table invalid\n"); 1188 NV_ERROR(drm, "Pointer to TMDS table invalid\n");
1172 return -EINVAL; 1189 return -EINVAL;
1173 } 1190 }
1174 1191
1175 NV_INFO(dev, "TMDS table version %d.%d\n", 1192 NV_INFO(drm, "TMDS table version %d.%d\n",
1176 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf); 1193 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
1177 1194
1178 /* nv50+ has v2.0, but we don't parse it atm */ 1195 /* nv50+ has v2.0, but we don't parse it atm */
@@ -1186,7 +1203,7 @@ static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios,
1186 script1 = ROM16(bios->data[tmdstableptr + 7]); 1203 script1 = ROM16(bios->data[tmdstableptr + 7]);
1187 script2 = ROM16(bios->data[tmdstableptr + 9]); 1204 script2 = ROM16(bios->data[tmdstableptr + 9]);
1188 if (bios->data[script1] != 'q' || bios->data[script2] != 'q') 1205 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
1189 NV_WARN(dev, "TMDS table script pointers not stubbed\n"); 1206 NV_WARN(drm, "TMDS table script pointers not stubbed\n");
1190 1207
1191 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]); 1208 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
1192 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]); 1209 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
@@ -1206,10 +1223,11 @@ parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
1206 * offset + 0 (16 bits): output script table pointer 1223 * offset + 0 (16 bits): output script table pointer
1207 */ 1224 */
1208 1225
1226 struct nouveau_drm *drm = nouveau_drm(dev);
1209 uint16_t outputscripttableptr; 1227 uint16_t outputscripttableptr;
1210 1228
1211 if (bitentry->length != 3) { 1229 if (bitentry->length != 3) {
1212 NV_ERROR(dev, "Do not understand BIT U table\n"); 1230 NV_ERROR(drm, "Do not understand BIT U table\n");
1213 return -EINVAL; 1231 return -EINVAL;
1214 } 1232 }
1215 1233
@@ -1228,8 +1246,8 @@ struct bit_table {
1228int 1246int
1229bit_table(struct drm_device *dev, u8 id, struct bit_entry *bit) 1247bit_table(struct drm_device *dev, u8 id, struct bit_entry *bit)
1230{ 1248{
1231 struct drm_nouveau_private *dev_priv = dev->dev_private; 1249 struct nouveau_drm *drm = nouveau_drm(dev);
1232 struct nvbios *bios = &dev_priv->vbios; 1250 struct nvbios *bios = &drm->vbios;
1233 u8 entries, *entry; 1251 u8 entries, *entry;
1234 1252
1235 if (bios->type != NVBIOS_BIT) 1253 if (bios->type != NVBIOS_BIT)
@@ -1258,12 +1276,13 @@ parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
1258 struct bit_table *table) 1276 struct bit_table *table)
1259{ 1277{
1260 struct drm_device *dev = bios->dev; 1278 struct drm_device *dev = bios->dev;
1279 struct nouveau_drm *drm = nouveau_drm(dev);
1261 struct bit_entry bitentry; 1280 struct bit_entry bitentry;
1262 1281
1263 if (bit_table(dev, table->id, &bitentry) == 0) 1282 if (bit_table(dev, table->id, &bitentry) == 0)
1264 return table->parse_fn(dev, bios, &bitentry); 1283 return table->parse_fn(dev, bios, &bitentry);
1265 1284
1266 NV_INFO(dev, "BIT table '%c' not found\n", table->id); 1285 NV_INFO(drm, "BIT table '%c' not found\n", table->id);
1267 return -ENOSYS; 1286 return -ENOSYS;
1268} 1287}
1269 1288
@@ -1343,6 +1362,7 @@ static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsi
1343 * offset + 156: minimum pixel clock for LVDS dual link 1362 * offset + 156: minimum pixel clock for LVDS dual link
1344 */ 1363 */
1345 1364
1365 struct nouveau_drm *drm = nouveau_drm(dev);
1346 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor; 1366 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
1347 uint16_t bmplength; 1367 uint16_t bmplength;
1348 uint16_t legacy_scripts_offset, legacy_i2c_offset; 1368 uint16_t legacy_scripts_offset, legacy_i2c_offset;
@@ -1356,7 +1376,7 @@ static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsi
1356 bmp_version_major = bmp[5]; 1376 bmp_version_major = bmp[5];
1357 bmp_version_minor = bmp[6]; 1377 bmp_version_minor = bmp[6];
1358 1378
1359 NV_TRACE(dev, "BMP version %d.%d\n", 1379 NV_INFO(drm, "BMP version %d.%d\n",
1360 bmp_version_major, bmp_version_minor); 1380 bmp_version_major, bmp_version_minor);
1361 1381
1362 /* 1382 /*
@@ -1372,7 +1392,7 @@ static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsi
1372 * happened instead. 1392 * happened instead.
1373 */ 1393 */
1374 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) { 1394 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
1375 NV_ERROR(dev, "You have an unsupported BMP version. " 1395 NV_ERROR(drm, "You have an unsupported BMP version. "
1376 "Please send in your bios\n"); 1396 "Please send in your bios\n");
1377 return -ENOSYS; 1397 return -ENOSYS;
1378 } 1398 }
@@ -1421,7 +1441,7 @@ static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsi
1421 1441
1422 /* checksum */ 1442 /* checksum */
1423 if (nv_cksum(bmp, 8)) { 1443 if (nv_cksum(bmp, 8)) {
1424 NV_ERROR(dev, "Bad BMP checksum\n"); 1444 NV_ERROR(drm, "Bad BMP checksum\n");
1425 return -EINVAL; 1445 return -EINVAL;
1426 } 1446 }
1427 1447
@@ -1508,18 +1528,18 @@ static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
1508void * 1528void *
1509olddcb_table(struct drm_device *dev) 1529olddcb_table(struct drm_device *dev)
1510{ 1530{
1511 struct drm_nouveau_private *dev_priv = dev->dev_private; 1531 struct nouveau_drm *drm = nouveau_drm(dev);
1512 u8 *dcb = NULL; 1532 u8 *dcb = NULL;
1513 1533
1514 if (dev_priv->card_type > NV_04) 1534 if (nv_device(drm->device)->card_type > NV_04)
1515 dcb = ROMPTR(dev, dev_priv->vbios.data[0x36]); 1535 dcb = ROMPTR(dev, drm->vbios.data[0x36]);
1516 if (!dcb) { 1536 if (!dcb) {
1517 NV_WARNONCE(dev, "No DCB data found in VBIOS\n"); 1537 NV_WARN(drm, "No DCB data found in VBIOS\n");
1518 return NULL; 1538 return NULL;
1519 } 1539 }
1520 1540
1521 if (dcb[0] >= 0x41) { 1541 if (dcb[0] >= 0x41) {
1522 NV_WARNONCE(dev, "DCB version 0x%02x unknown\n", dcb[0]); 1542 NV_WARN(drm, "DCB version 0x%02x unknown\n", dcb[0]);
1523 return NULL; 1543 return NULL;
1524 } else 1544 } else
1525 if (dcb[0] >= 0x30) { 1545 if (dcb[0] >= 0x30) {
@@ -1551,11 +1571,11 @@ olddcb_table(struct drm_device *dev)
1551 * 1571 *
1552 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful 1572 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
1553 */ 1573 */
1554 NV_WARNONCE(dev, "No useful DCB data in VBIOS\n"); 1574 NV_WARN(drm, "No useful DCB data in VBIOS\n");
1555 return NULL; 1575 return NULL;
1556 } 1576 }
1557 1577
1558 NV_WARNONCE(dev, "DCB header validation failed\n"); 1578 NV_WARN(drm, "DCB header validation failed\n");
1559 return NULL; 1579 return NULL;
1560} 1580}
1561 1581
@@ -1656,6 +1676,8 @@ static bool
1656parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb, 1676parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
1657 uint32_t conn, uint32_t conf, struct dcb_output *entry) 1677 uint32_t conn, uint32_t conf, struct dcb_output *entry)
1658{ 1678{
1679 struct nouveau_drm *drm = nouveau_drm(dev);
1680
1659 entry->type = conn & 0xf; 1681 entry->type = conn & 0xf;
1660 entry->i2c_index = (conn >> 4) & 0xf; 1682 entry->i2c_index = (conn >> 4) & 0xf;
1661 entry->heads = (conn >> 8) & 0xf; 1683 entry->heads = (conn >> 8) & 0xf;
@@ -1709,7 +1731,7 @@ parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
1709 if (dcb->version >= 0x40) 1731 if (dcb->version >= 0x40)
1710 break; 1732 break;
1711 1733
1712 NV_ERROR(dev, "Unknown LVDS configuration bits, " 1734 NV_ERROR(drm, "Unknown LVDS configuration bits, "
1713 "please report\n"); 1735 "please report\n");
1714 } 1736 }
1715 break; 1737 break;
@@ -1783,6 +1805,8 @@ static bool
1783parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb, 1805parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
1784 uint32_t conn, uint32_t conf, struct dcb_output *entry) 1806 uint32_t conn, uint32_t conf, struct dcb_output *entry)
1785{ 1807{
1808 struct nouveau_drm *drm = nouveau_drm(dev);
1809
1786 switch (conn & 0x0000000f) { 1810 switch (conn & 0x0000000f) {
1787 case 0: 1811 case 0:
1788 entry->type = DCB_OUTPUT_ANALOG; 1812 entry->type = DCB_OUTPUT_ANALOG;
@@ -1801,7 +1825,7 @@ parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
1801 entry->type = DCB_OUTPUT_LVDS; 1825 entry->type = DCB_OUTPUT_LVDS;
1802 break; 1826 break;
1803 default: 1827 default:
1804 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f); 1828 NV_ERROR(drm, "Unknown DCB type %d\n", conn & 0x0000000f);
1805 return false; 1829 return false;
1806 } 1830 }
1807 1831
@@ -1840,6 +1864,7 @@ void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
1840 * more options 1864 * more options
1841 */ 1865 */
1842 1866
1867 struct nouveau_drm *drm = nouveau_drm(dev);
1843 int i, newentries = 0; 1868 int i, newentries = 0;
1844 1869
1845 for (i = 0; i < dcb->entries; i++) { 1870 for (i = 0; i < dcb->entries; i++) {
@@ -1857,7 +1882,7 @@ void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
1857 jent->type == ient->type && 1882 jent->type == ient->type &&
1858 jent->location == ient->location && 1883 jent->location == ient->location &&
1859 jent->or == ient->or) { 1884 jent->or == ient->or) {
1860 NV_TRACE(dev, "Merging DCB entries %d and %d\n", 1885 NV_INFO(drm, "Merging DCB entries %d and %d\n",
1861 i, j); 1886 i, j);
1862 ient->heads |= jent->heads; 1887 ient->heads |= jent->heads;
1863 jent->type = 100; /* dummy value */ 1888 jent->type = 100; /* dummy value */
@@ -1883,8 +1908,8 @@ void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
1883static bool 1908static bool
1884apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf) 1909apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
1885{ 1910{
1886 struct drm_nouveau_private *dev_priv = dev->dev_private; 1911 struct nouveau_drm *drm = nouveau_drm(dev);
1887 struct dcb_table *dcb = &dev_priv->vbios.dcb; 1912 struct dcb_table *dcb = &drm->vbios.dcb;
1888 1913
1889 /* Dell Precision M6300 1914 /* Dell Precision M6300
1890 * DCB entry 2: 02025312 00000010 1915 * DCB entry 2: 02025312 00000010
@@ -2021,8 +2046,8 @@ fabricate_dcb_encoder_table(struct drm_device *dev, struct nvbios *bios)
2021static int 2046static int
2022parse_dcb_entry(struct drm_device *dev, void *data, int idx, u8 *outp) 2047parse_dcb_entry(struct drm_device *dev, void *data, int idx, u8 *outp)
2023{ 2048{
2024 struct drm_nouveau_private *dev_priv = dev->dev_private; 2049 struct nouveau_drm *drm = nouveau_drm(dev);
2025 struct dcb_table *dcb = &dev_priv->vbios.dcb; 2050 struct dcb_table *dcb = &drm->vbios.dcb;
2026 u32 conf = (dcb->version >= 0x20) ? ROM32(outp[4]) : ROM32(outp[6]); 2051 u32 conf = (dcb->version >= 0x20) ? ROM32(outp[4]) : ROM32(outp[6]);
2027 u32 conn = ROM32(outp[0]); 2052 u32 conn = ROM32(outp[0]);
2028 bool ret; 2053 bool ret;
@@ -2030,7 +2055,7 @@ parse_dcb_entry(struct drm_device *dev, void *data, int idx, u8 *outp)
2030 if (apply_dcb_encoder_quirks(dev, idx, &conn, &conf)) { 2055 if (apply_dcb_encoder_quirks(dev, idx, &conn, &conf)) {
2031 struct dcb_output *entry = new_dcb_entry(dcb); 2056 struct dcb_output *entry = new_dcb_entry(dcb);
2032 2057
2033 NV_TRACEWARN(dev, "DCB outp %02d: %08x %08x\n", idx, conn, conf); 2058 NV_INFO(drm, "DCB outp %02d: %08x %08x\n", idx, conn, conf);
2034 2059
2035 if (dcb->version >= 0x20) 2060 if (dcb->version >= 0x20)
2036 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry); 2061 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry);
@@ -2100,6 +2125,7 @@ dcb_fake_connectors(struct nvbios *bios)
2100static int 2125static int
2101parse_dcb_table(struct drm_device *dev, struct nvbios *bios) 2126parse_dcb_table(struct drm_device *dev, struct nvbios *bios)
2102{ 2127{
2128 struct nouveau_drm *drm = nouveau_drm(dev);
2103 struct dcb_table *dcb = &bios->dcb; 2129 struct dcb_table *dcb = &bios->dcb;
2104 u8 *dcbt, *conn; 2130 u8 *dcbt, *conn;
2105 int idx; 2131 int idx;
@@ -2115,7 +2141,7 @@ parse_dcb_table(struct drm_device *dev, struct nvbios *bios)
2115 return -EINVAL; 2141 return -EINVAL;
2116 } 2142 }
2117 2143
2118 NV_TRACE(dev, "DCB version %d.%d\n", dcbt[0] >> 4, dcbt[0] & 0xf); 2144 NV_INFO(drm, "DCB version %d.%d\n", dcbt[0] >> 4, dcbt[0] & 0xf);
2119 2145
2120 dcb->version = dcbt[0]; 2146 dcb->version = dcbt[0];
2121 olddcb_outp_foreach(dev, NULL, parse_dcb_entry); 2147 olddcb_outp_foreach(dev, NULL, parse_dcb_entry);
@@ -2134,7 +2160,7 @@ parse_dcb_table(struct drm_device *dev, struct nvbios *bios)
2134 idx = -1; 2160 idx = -1;
2135 while ((conn = olddcb_conn(dev, ++idx))) { 2161 while ((conn = olddcb_conn(dev, ++idx))) {
2136 if (conn[0] != 0xff) { 2162 if (conn[0] != 0xff) {
2137 NV_TRACE(dev, "DCB conn %02d: ", idx); 2163 NV_INFO(drm, "DCB conn %02d: ", idx);
2138 if (olddcb_conntab(dev)[3] < 4) 2164 if (olddcb_conntab(dev)[3] < 4)
2139 printk("%04x\n", ROM16(conn[0])); 2165 printk("%04x\n", ROM16(conn[0]));
2140 else 2166 else
@@ -2156,12 +2182,14 @@ static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bio
2156 * starting at reg 0x00001400 2182 * starting at reg 0x00001400
2157 */ 2183 */
2158 2184
2185 struct nouveau_drm *drm = nouveau_drm(dev);
2186 struct nouveau_device *device = nv_device(drm->device);
2159 uint8_t bytes_to_write; 2187 uint8_t bytes_to_write;
2160 uint16_t hwsq_entry_offset; 2188 uint16_t hwsq_entry_offset;
2161 int i; 2189 int i;
2162 2190
2163 if (bios->data[hwsq_offset] <= entry) { 2191 if (bios->data[hwsq_offset] <= entry) {
2164 NV_ERROR(dev, "Too few entries in HW sequencer table for " 2192 NV_ERROR(drm, "Too few entries in HW sequencer table for "
2165 "requested entry\n"); 2193 "requested entry\n");
2166 return -ENOENT; 2194 return -ENOENT;
2167 } 2195 }
@@ -2169,24 +2197,24 @@ static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bio
2169 bytes_to_write = bios->data[hwsq_offset + 1]; 2197 bytes_to_write = bios->data[hwsq_offset + 1];
2170 2198
2171 if (bytes_to_write != 36) { 2199 if (bytes_to_write != 36) {
2172 NV_ERROR(dev, "Unknown HW sequencer entry size\n"); 2200 NV_ERROR(drm, "Unknown HW sequencer entry size\n");
2173 return -EINVAL; 2201 return -EINVAL;
2174 } 2202 }
2175 2203
2176 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n"); 2204 NV_INFO(drm, "Loading NV17 power sequencing microcode\n");
2177 2205
2178 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write; 2206 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
2179 2207
2180 /* set sequencer control */ 2208 /* set sequencer control */
2181 nv_wr32(dev, 0x00001304, ROM32(bios->data[hwsq_entry_offset])); 2209 nv_wr32(device, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
2182 bytes_to_write -= 4; 2210 bytes_to_write -= 4;
2183 2211
2184 /* write ucode */ 2212 /* write ucode */
2185 for (i = 0; i < bytes_to_write; i += 4) 2213 for (i = 0; i < bytes_to_write; i += 4)
2186 nv_wr32(dev, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4])); 2214 nv_wr32(device, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
2187 2215
2188 /* twiddle NV_PBUS_DEBUG_4 */ 2216 /* twiddle NV_PBUS_DEBUG_4 */
2189 nv_wr32(dev, NV_PBUS_DEBUG_4, nv_rd32(dev, NV_PBUS_DEBUG_4) | 0x18); 2217 nv_wr32(device, NV_PBUS_DEBUG_4, nv_rd32(device, NV_PBUS_DEBUG_4) | 0x18);
2190 2218
2191 return 0; 2219 return 0;
2192} 2220}
@@ -2217,8 +2245,8 @@ static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
2217 2245
2218uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev) 2246uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
2219{ 2247{
2220 struct drm_nouveau_private *dev_priv = dev->dev_private; 2248 struct nouveau_drm *drm = nouveau_drm(dev);
2221 struct nvbios *bios = &dev_priv->vbios; 2249 struct nvbios *bios = &drm->vbios;
2222 const uint8_t edid_sig[] = { 2250 const uint8_t edid_sig[] = {
2223 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; 2251 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
2224 uint16_t offset = 0; 2252 uint16_t offset = 0;
@@ -2241,27 +2269,29 @@ uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
2241 offset++; 2269 offset++;
2242 } 2270 }
2243 2271
2244 NV_TRACE(dev, "Found EDID in BIOS\n"); 2272 NV_INFO(drm, "Found EDID in BIOS\n");
2245 2273
2246 return bios->fp.edid = &bios->data[offset]; 2274 return bios->fp.edid = &bios->data[offset];
2247} 2275}
2248 2276
2249static bool NVInitVBIOS(struct drm_device *dev) 2277static bool NVInitVBIOS(struct drm_device *dev)
2250{ 2278{
2251 struct drm_nouveau_private *dev_priv = dev->dev_private; 2279 struct nouveau_drm *drm = nouveau_drm(dev);
2252 struct nvbios *bios = &dev_priv->vbios; 2280 struct nvbios *bios = &drm->vbios;
2253 2281
2254 memset(bios, 0, sizeof(struct nvbios)); 2282 memset(bios, 0, sizeof(struct nvbios));
2255 spin_lock_init(&bios->lock); 2283 spin_lock_init(&bios->lock);
2256 bios->dev = dev; 2284 bios->dev = dev;
2257 2285
2258 return _nv_bios(dev, &bios->data, &bios->length); 2286 bios->data = nouveau_bios(drm->device)->data;
2287 bios->length = nouveau_bios(drm->device)->size;
2288 return true;
2259} 2289}
2260 2290
2261static int nouveau_parse_vbios_struct(struct drm_device *dev) 2291static int nouveau_parse_vbios_struct(struct drm_device *dev)
2262{ 2292{
2263 struct drm_nouveau_private *dev_priv = dev->dev_private; 2293 struct nouveau_drm *drm = nouveau_drm(dev);
2264 struct nvbios *bios = &dev_priv->vbios; 2294 struct nvbios *bios = &drm->vbios;
2265 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' }; 2295 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
2266 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 }; 2296 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
2267 int offset; 2297 int offset;
@@ -2269,7 +2299,7 @@ static int nouveau_parse_vbios_struct(struct drm_device *dev)
2269 offset = findstr(bios->data, bios->length, 2299 offset = findstr(bios->data, bios->length,
2270 bit_signature, sizeof(bit_signature)); 2300 bit_signature, sizeof(bit_signature));
2271 if (offset) { 2301 if (offset) {
2272 NV_TRACE(dev, "BIT BIOS found\n"); 2302 NV_INFO(drm, "BIT BIOS found\n");
2273 bios->type = NVBIOS_BIT; 2303 bios->type = NVBIOS_BIT;
2274 bios->offset = offset; 2304 bios->offset = offset;
2275 return parse_bit_structure(bios, offset + 6); 2305 return parse_bit_structure(bios, offset + 6);
@@ -2278,21 +2308,21 @@ static int nouveau_parse_vbios_struct(struct drm_device *dev)
2278 offset = findstr(bios->data, bios->length, 2308 offset = findstr(bios->data, bios->length,
2279 bmp_signature, sizeof(bmp_signature)); 2309 bmp_signature, sizeof(bmp_signature));
2280 if (offset) { 2310 if (offset) {
2281 NV_TRACE(dev, "BMP BIOS found\n"); 2311 NV_INFO(drm, "BMP BIOS found\n");
2282 bios->type = NVBIOS_BMP; 2312 bios->type = NVBIOS_BMP;
2283 bios->offset = offset; 2313 bios->offset = offset;
2284 return parse_bmp_structure(dev, bios, offset); 2314 return parse_bmp_structure(dev, bios, offset);
2285 } 2315 }
2286 2316
2287 NV_ERROR(dev, "No known BIOS signature found\n"); 2317 NV_ERROR(drm, "No known BIOS signature found\n");
2288 return -ENODEV; 2318 return -ENODEV;
2289} 2319}
2290 2320
2291int 2321int
2292nouveau_run_vbios_init(struct drm_device *dev) 2322nouveau_run_vbios_init(struct drm_device *dev)
2293{ 2323{
2294 struct drm_nouveau_private *dev_priv = dev->dev_private; 2324 struct nouveau_drm *drm = nouveau_drm(dev);
2295 struct nvbios *bios = &dev_priv->vbios; 2325 struct nvbios *bios = &drm->vbios;
2296 int i, ret = 0; 2326 int i, ret = 0;
2297 2327
2298 /* Reset the BIOS head to 0. */ 2328 /* Reset the BIOS head to 0. */
@@ -2306,7 +2336,7 @@ nouveau_run_vbios_init(struct drm_device *dev)
2306 bios->fp.lvds_init_run = false; 2336 bios->fp.lvds_init_run = false;
2307 } 2337 }
2308 2338
2309 if (dev_priv->card_type >= NV_50) { 2339 if (nv_device(drm->device)->card_type >= NV_50) {
2310 for (i = 0; bios->execute && i < bios->dcb.entries; i++) { 2340 for (i = 0; bios->execute && i < bios->dcb.entries; i++) {
2311 nouveau_bios_run_display_table(dev, 0, 0, 2341 nouveau_bios_run_display_table(dev, 0, 0,
2312 &bios->dcb.entry[i], -1); 2342 &bios->dcb.entry[i], -1);
@@ -2319,10 +2349,10 @@ nouveau_run_vbios_init(struct drm_device *dev)
2319static bool 2349static bool
2320nouveau_bios_posted(struct drm_device *dev) 2350nouveau_bios_posted(struct drm_device *dev)
2321{ 2351{
2322 struct drm_nouveau_private *dev_priv = dev->dev_private; 2352 struct nouveau_drm *drm = nouveau_drm(dev);
2323 unsigned htotal; 2353 unsigned htotal;
2324 2354
2325 if (dev_priv->card_type >= NV_50) { 2355 if (nv_device(drm->device)->card_type >= NV_50) {
2326 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 && 2356 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
2327 NVReadVgaCrtc(dev, 0, 0x1a) == 0) 2357 NVReadVgaCrtc(dev, 0, 0x1a) == 0)
2328 return false; 2358 return false;
@@ -2341,8 +2371,8 @@ nouveau_bios_posted(struct drm_device *dev)
2341int 2371int
2342nouveau_bios_init(struct drm_device *dev) 2372nouveau_bios_init(struct drm_device *dev)
2343{ 2373{
2344 struct drm_nouveau_private *dev_priv = dev->dev_private; 2374 struct nouveau_drm *drm = nouveau_drm(dev);
2345 struct nvbios *bios = &dev_priv->vbios; 2375 struct nvbios *bios = &drm->vbios;
2346 int ret; 2376 int ret;
2347 2377
2348 if (!NVInitVBIOS(dev)) 2378 if (!NVInitVBIOS(dev))
@@ -2364,12 +2394,10 @@ nouveau_bios_init(struct drm_device *dev)
2364 2394
2365 /* ... unless card isn't POSTed already */ 2395 /* ... unless card isn't POSTed already */
2366 if (!nouveau_bios_posted(dev)) { 2396 if (!nouveau_bios_posted(dev)) {
2367 NV_INFO(dev, "Adaptor not initialised, " 2397 NV_INFO(drm, "Adaptor not initialised, "
2368 "running VBIOS init tables.\n"); 2398 "running VBIOS init tables.\n");
2369 bios->execute = true; 2399 bios->execute = true;
2370 } 2400 }
2371 if (nouveau_force_post)
2372 bios->execute = true;
2373 2401
2374 ret = nouveau_run_vbios_init(dev); 2402 ret = nouveau_run_vbios_init(dev);
2375 if (ret) 2403 if (ret)
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h
index 27a64db634d4..3befbb821a56 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.h
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.h
@@ -21,8 +21,8 @@
21 * DEALINGS IN THE SOFTWARE. 21 * DEALINGS IN THE SOFTWARE.
22 */ 22 */
23 23
24#ifndef __NOUVEAU_BIOS_H__ 24#ifndef __NOUVEAU_DISPBIOS_H__
25#define __NOUVEAU_BIOS_H__ 25#define __NOUVEAU_DISPBIOS_H__
26 26
27#include "nvreg.h" 27#include "nvreg.h"
28 28
@@ -38,8 +38,8 @@
38#define ROM48(x) ({ u8 *p = &(x); (u64)ROM16(p[4]) << 32 | ROM32(p[0]); }) 38#define ROM48(x) ({ u8 *p = &(x); (u64)ROM16(p[4]) << 32 | ROM32(p[0]); })
39#define ROM64(x) le64_to_cpu(*(u64 *)&(x)) 39#define ROM64(x) le64_to_cpu(*(u64 *)&(x))
40#define ROMPTR(d,x) ({ \ 40#define ROMPTR(d,x) ({ \
41 struct drm_nouveau_private *dev_priv = (d)->dev_private; \ 41 struct nouveau_drm *drm = nouveau_drm((d)); \
42 ROM16(x) ? &dev_priv->vbios.data[ROM16(x)] : NULL; \ 42 ROM16(x) ? &drm->vbios.data[ROM16(x)] : NULL; \
43}) 43})
44 44
45struct bit_entry { 45struct bit_entry {
@@ -180,4 +180,21 @@ int olddcb_outp_foreach(struct drm_device *, void *data,
180u8 *olddcb_conntab(struct drm_device *); 180u8 *olddcb_conntab(struct drm_device *);
181u8 *olddcb_conn(struct drm_device *, u8 idx); 181u8 *olddcb_conn(struct drm_device *, u8 idx);
182 182
183int nouveau_bios_init(struct drm_device *);
184void nouveau_bios_takedown(struct drm_device *dev);
185int nouveau_run_vbios_init(struct drm_device *);
186struct dcb_connector_table_entry *
187nouveau_bios_connector_entry(struct drm_device *, int index);
188int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk,
189 struct dcb_output *, int crtc);
190bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
191uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
192int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
193 bool *dl, bool *if_is_24bit);
194int run_tmds_table(struct drm_device *, struct dcb_output *,
195 int head, int pxclk);
196int call_lvds_script(struct drm_device *, struct dcb_output *, int head,
197 enum LVDS_script, int pxclk);
198bool bios_encoder_match(struct dcb_output *, u32 hash);
199
183#endif 200#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 3465df327227..ef96bdbb5255 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -49,7 +49,7 @@ static void
49nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, 49nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
50 u32 addr, u32 size, u32 pitch, u32 flags) 50 u32 addr, u32 size, u32 pitch, u32 flags)
51{ 51{
52 struct nouveau_drm *drm = nouveau_newpriv(dev); 52 struct nouveau_drm *drm = nouveau_drm(dev);
53 int i = reg - drm->tile.reg; 53 int i = reg - drm->tile.reg;
54 struct nouveau_fb *pfb = nouveau_fb(drm->device); 54 struct nouveau_fb *pfb = nouveau_fb(drm->device);
55 struct nouveau_fb_tile *tile = &pfb->tile.region[i]; 55 struct nouveau_fb_tile *tile = &pfb->tile.region[i];
@@ -74,7 +74,7 @@ nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
74static struct nouveau_drm_tile * 74static struct nouveau_drm_tile *
75nv10_bo_get_tile_region(struct drm_device *dev, int i) 75nv10_bo_get_tile_region(struct drm_device *dev, int i)
76{ 76{
77 struct nouveau_drm *drm = nouveau_newpriv(dev); 77 struct nouveau_drm *drm = nouveau_drm(dev);
78 struct nouveau_drm_tile *tile = &drm->tile.reg[i]; 78 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
79 79
80 spin_lock(&drm->tile.lock); 80 spin_lock(&drm->tile.lock);
@@ -93,7 +93,7 @@ static void
93nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile, 93nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
94 struct nouveau_fence *fence) 94 struct nouveau_fence *fence)
95{ 95{
96 struct nouveau_drm *drm = nouveau_newpriv(dev); 96 struct nouveau_drm *drm = nouveau_drm(dev);
97 97
98 if (tile) { 98 if (tile) {
99 spin_lock(&drm->tile.lock); 99 spin_lock(&drm->tile.lock);
@@ -112,7 +112,7 @@ static struct nouveau_drm_tile *
112nv10_bo_set_tiling(struct drm_device *dev, u32 addr, 112nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
113 u32 size, u32 pitch, u32 flags) 113 u32 size, u32 pitch, u32 flags)
114{ 114{
115 struct nouveau_drm *drm = nouveau_newpriv(dev); 115 struct nouveau_drm *drm = nouveau_drm(dev);
116 struct nouveau_fb *pfb = nouveau_fb(drm->device); 116 struct nouveau_fb *pfb = nouveau_fb(drm->device);
117 struct nouveau_drm_tile *tile, *found = NULL; 117 struct nouveau_drm_tile *tile, *found = NULL;
118 int i; 118 int i;
@@ -191,7 +191,7 @@ nouveau_bo_new(struct drm_device *dev, int size, int align,
191 struct sg_table *sg, 191 struct sg_table *sg,
192 struct nouveau_bo **pnvbo) 192 struct nouveau_bo **pnvbo)
193{ 193{
194 struct nouveau_drm *drm = nouveau_newpriv(dev); 194 struct nouveau_drm *drm = nouveau_drm(dev);
195 struct nouveau_bo *nvbo; 195 struct nouveau_bo *nvbo;
196 size_t acc_size; 196 size_t acc_size;
197 int ret; 197 int ret;
diff --git a/drivers/gpu/drm/nouveau/nouveau_calc.c b/drivers/gpu/drm/nouveau/nouveau_calc.c
index 5ec677ea1c78..77959526b5f3 100644
--- a/drivers/gpu/drm/nouveau/nouveau_calc.c
+++ b/drivers/gpu/drm/nouveau/nouveau_calc.c
@@ -22,7 +22,8 @@
22 */ 22 */
23 23
24#include "drmP.h" 24#include "drmP.h"
25#include "nouveau_drv.h" 25#include "nouveau_drm.h"
26#include "nouveau_reg.h"
26#include "nouveau_hw.h" 27#include "nouveau_hw.h"
27 28
28/****************************************************************************\ 29/****************************************************************************\
@@ -195,12 +196,13 @@ static void
195nv04_update_arb(struct drm_device *dev, int VClk, int bpp, 196nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
196 int *burst, int *lwm) 197 int *burst, int *lwm)
197{ 198{
198 struct drm_nouveau_private *dev_priv = dev->dev_private; 199 struct nouveau_drm *drm = nouveau_drm(dev);
200 struct nouveau_device *device = nouveau_dev(dev);
199 struct nv_fifo_info fifo_data; 201 struct nv_fifo_info fifo_data;
200 struct nv_sim_state sim_data; 202 struct nv_sim_state sim_data;
201 int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY); 203 int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY);
202 int NVClk = nouveau_hw_get_clock(dev, PLL_CORE); 204 int NVClk = nouveau_hw_get_clock(dev, PLL_CORE);
203 uint32_t cfg1 = nv_rd32(dev, NV04_PFB_CFG1); 205 uint32_t cfg1 = nv_rd32(device, NV04_PFB_CFG1);
204 206
205 sim_data.pclk_khz = VClk; 207 sim_data.pclk_khz = VClk;
206 sim_data.mclk_khz = MClk; 208 sim_data.mclk_khz = MClk;
@@ -218,13 +220,13 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
218 sim_data.mem_latency = 3; 220 sim_data.mem_latency = 3;
219 sim_data.mem_page_miss = 10; 221 sim_data.mem_page_miss = 10;
220 } else { 222 } else {
221 sim_data.memory_type = nv_rd32(dev, NV04_PFB_CFG0) & 0x1; 223 sim_data.memory_type = nv_rd32(device, NV04_PFB_CFG0) & 0x1;
222 sim_data.memory_width = (nv_rd32(dev, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64; 224 sim_data.memory_width = (nv_rd32(device, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64;
223 sim_data.mem_latency = cfg1 & 0xf; 225 sim_data.mem_latency = cfg1 & 0xf;
224 sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1); 226 sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1);
225 } 227 }
226 228
227 if (dev_priv->card_type == NV_04) 229 if (nv_device(drm->device)->card_type == NV_04)
228 nv04_calc_arb(&fifo_data, &sim_data); 230 nv04_calc_arb(&fifo_data, &sim_data);
229 else 231 else
230 nv10_calc_arb(&fifo_data, &sim_data); 232 nv10_calc_arb(&fifo_data, &sim_data);
@@ -249,9 +251,9 @@ nv20_update_arb(int *burst, int *lwm)
249void 251void
250nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm) 252nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm)
251{ 253{
252 struct drm_nouveau_private *dev_priv = dev->dev_private; 254 struct nouveau_drm *drm = nouveau_drm(dev);
253 255
254 if (dev_priv->card_type < NV_20) 256 if (nv_device(drm->device)->card_type < NV_20)
255 nv04_update_arb(dev, vclk, bpp, burst, lwm); 257 nv04_update_arb(dev, vclk, bpp, burst, lwm);
256 else if ((dev->pci_device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ || 258 else if ((dev->pci_device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ ||
257 (dev->pci_device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) { 259 (dev->pci_device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) {
diff --git a/drivers/gpu/drm/nouveau/nouveau_compat.c b/drivers/gpu/drm/nouveau/nouveau_compat.c
deleted file mode 100644
index 3db23496dff6..000000000000
--- a/drivers/gpu/drm/nouveau/nouveau_compat.c
+++ /dev/null
@@ -1,609 +0,0 @@
1#include "nouveau_drm.h"
2#include "nouveau_chan.h"
3#include "nouveau_compat.h"
4
5#include <subdev/bios.h>
6#include <subdev/bios/dcb.h>
7#include <subdev/bios/init.h>
8#include <subdev/bios/pll.h>
9#include <subdev/gpio.h>
10#include <subdev/i2c.h>
11#include <subdev/clock.h>
12#include <subdev/mc.h>
13#include <subdev/timer.h>
14#include <subdev/fb.h>
15#include <subdev/bar.h>
16#include <subdev/vm.h>
17
18int
19nvdrm_gart_init(struct drm_device *dev, u64 *base, u64 *size)
20{
21 struct nouveau_drm *drm = nouveau_newpriv(dev);
22 if (drm->agp.stat == ENABLED) {
23 *base = drm->agp.base;
24 *size = drm->agp.base;
25 return 0;
26 }
27 return -ENODEV;
28}
29
30u8
31_nv_rd08(struct drm_device *dev, u32 reg)
32{
33 struct nouveau_drm *drm = nouveau_newpriv(dev);
34 return nv_ro08(drm->device, reg);
35}
36
37void
38_nv_wr08(struct drm_device *dev, u32 reg, u8 val)
39{
40 struct nouveau_drm *drm = nouveau_newpriv(dev);
41 nv_wo08(drm->device, reg, val);
42}
43
44u32
45_nv_rd32(struct drm_device *dev, u32 reg)
46{
47 struct nouveau_drm *drm = nouveau_newpriv(dev);
48 return nv_ro32(drm->device, reg);
49}
50
51void
52_nv_wr32(struct drm_device *dev, u32 reg, u32 val)
53{
54 struct nouveau_drm *drm = nouveau_newpriv(dev);
55 nv_wo32(drm->device, reg, val);
56}
57
58u32
59_nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
60{
61 u32 tmp = _nv_rd32(dev, reg);
62 _nv_wr32(dev, reg, (tmp & ~mask) | val);
63 return tmp;
64}
65
66bool
67_nv_bios(struct drm_device *dev, u8 **data, u32 *size)
68{
69 struct nouveau_drm *drm = nouveau_newpriv(dev);
70 struct nouveau_bios *bios = nouveau_bios(drm->device);
71 *data = bios->data;
72 *size = bios->size;
73 return true;
74}
75
76void
77nouveau_gpio_reset(struct drm_device *dev)
78{
79 struct nouveau_drm *drm = nouveau_newpriv(dev);
80 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
81 gpio->reset(gpio);
82}
83
84int
85nouveau_gpio_find(struct drm_device *dev, int idx, u8 tag, u8 line,
86 struct dcb_gpio_func *func)
87{
88 struct nouveau_drm *drm = nouveau_newpriv(dev);
89 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
90
91 return gpio->find(gpio, idx, tag, line, func);
92}
93
94bool
95nouveau_gpio_func_valid(struct drm_device *dev, u8 tag)
96{
97 struct nouveau_drm *drm = nouveau_newpriv(dev);
98 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
99 struct dcb_gpio_func func;
100
101 return gpio->find(gpio, 0, tag, 0xff, &func) == 0;
102}
103
104int
105nouveau_gpio_func_set(struct drm_device *dev, u8 tag, int state)
106{
107 struct nouveau_drm *drm = nouveau_newpriv(dev);
108 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
109 if (gpio && gpio->get)
110 return gpio->set(gpio, 0, tag, 0xff, state);
111 return -ENODEV;
112}
113
114int
115nouveau_gpio_func_get(struct drm_device *dev, u8 tag)
116{
117 struct nouveau_drm *drm = nouveau_newpriv(dev);
118 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
119 if (gpio && gpio->get)
120 return gpio->get(gpio, 0, tag, 0xff);
121 return -ENODEV;
122}
123
124int
125nouveau_gpio_irq(struct drm_device *dev, int idx, u8 tag, u8 line, bool on)
126{
127 struct nouveau_drm *drm = nouveau_newpriv(dev);
128 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
129 if (gpio && gpio->irq)
130 return gpio->irq(gpio, idx, tag, line, on);
131 return -ENODEV;
132}
133
134int
135nouveau_gpio_isr_add(struct drm_device *dev, int idx, u8 tag, u8 line,
136 void (*exec)(void *, int state), void *data)
137{
138 struct nouveau_drm *drm = nouveau_newpriv(dev);
139 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
140 if (gpio && gpio->isr_add)
141 return gpio->isr_add(gpio, idx, tag, line, exec, data);
142 return -ENODEV;
143}
144
145void
146nouveau_gpio_isr_del(struct drm_device *dev, int idx, u8 tag, u8 line,
147 void (*exec)(void *, int state), void *data)
148{
149 struct nouveau_drm *drm = nouveau_newpriv(dev);
150 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
151 if (gpio && gpio->isr_del)
152 gpio->isr_del(gpio, idx, tag, line, exec, data);
153}
154
155struct nouveau_i2c_port *
156nouveau_i2c_find(struct drm_device *dev, u8 index)
157{
158 struct nouveau_drm *drm = nouveau_newpriv(dev);
159 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
160
161 return i2c->find(i2c, index);
162}
163
164bool
165nouveau_probe_i2c_addr(struct nouveau_i2c_port *port, int addr)
166{
167 return nv_probe_i2c(port, addr);
168}
169
170struct i2c_adapter *
171nouveau_i2c_adapter(struct nouveau_i2c_port *port)
172{
173 return &port->adapter;
174}
175
176
177int
178nouveau_i2c_identify(struct drm_device *dev, const char *what,
179 struct i2c_board_info *info,
180 bool (*match)(struct nouveau_i2c_port *,
181 struct i2c_board_info *),
182 int index)
183{
184 struct nouveau_drm *drm = nouveau_newpriv(dev);
185 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
186
187 return i2c->identify(i2c, index, what, info, match);
188}
189
190int
191auxch_rd(struct drm_device *dev, struct nouveau_i2c_port *port,
192 u32 addr, u8 *data, u8 size)
193{
194 return nv_rdaux(port, addr, data, size);
195}
196
197int
198auxch_wr(struct drm_device *dev, struct nouveau_i2c_port *port,
199 u32 addr, u8 *data, u8 size)
200{
201 return nv_wraux(port, addr, data, size);
202}
203
204u32
205get_pll_register(struct drm_device *dev, u32 type)
206{
207 struct nouveau_drm *drm = nouveau_newpriv(dev);
208 struct nouveau_bios *bios = nouveau_bios(drm->device);
209 struct nvbios_pll info;
210
211 if (nvbios_pll_parse(bios, type, &info))
212 return 0;
213 return info.reg;
214}
215
216int
217get_pll_limits(struct drm_device *dev, u32 type, struct nvbios_pll *info)
218{
219 struct nouveau_drm *drm = nouveau_newpriv(dev);
220 struct nouveau_bios *bios = nouveau_bios(drm->device);
221
222 return nvbios_pll_parse(bios, type, info);
223}
224
225int
226setPLL(struct drm_device *dev, u32 reg, u32 freq)
227{
228 struct nouveau_drm *drm = nouveau_newpriv(dev);
229 struct nouveau_clock *clk = nouveau_clock(drm->device);
230 int ret = -ENODEV;
231
232 if (clk->pll_set)
233 ret = clk->pll_set(clk, reg, freq);
234 return ret;
235}
236
237
238int
239nouveau_calc_pll_mnp(struct drm_device *dev, struct nvbios_pll *info,
240 int freq, struct nouveau_pll_vals *pv)
241{
242 struct nouveau_drm *drm = nouveau_newpriv(dev);
243 struct nouveau_clock *clk = nouveau_clock(drm->device);
244 int ret = 0;
245
246 if (clk->pll_calc)
247 ret = clk->pll_calc(clk, info, freq, pv);
248 return ret;
249}
250
251int
252nouveau_hw_setpll(struct drm_device *dev, u32 reg1,
253 struct nouveau_pll_vals *pv)
254{
255 struct nouveau_drm *drm = nouveau_newpriv(dev);
256 struct nouveau_clock *clk = nouveau_clock(drm->device);
257 int ret = -ENODEV;
258
259 if (clk->pll_prog)
260 ret = clk->pll_prog(clk, reg1, pv);
261 return ret;
262}
263
264int nva3_pll_calc(struct nouveau_clock *, struct nvbios_pll *, u32 freq,
265 int *N, int *fN, int *M, int *P);
266
267int
268nva3_calc_pll(struct drm_device *dev, struct nvbios_pll *info, u32 freq,
269 int *N, int *fN, int *M, int *P)
270{
271 struct nouveau_drm *drm = nouveau_newpriv(dev);
272 struct nouveau_clock *clk = nouveau_clock(drm->device);
273
274 return nva3_pll_calc(clk, info, freq, N, fN, M, P);
275}
276
277void
278nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
279 struct dcb_output *dcbent, int crtc)
280{
281 struct nouveau_drm *drm = nouveau_newpriv(dev);
282 struct nouveau_bios *bios = nouveau_bios(drm->device);
283 struct nvbios_init init = {
284 .subdev = nv_subdev(bios),
285 .bios = bios,
286 .offset = table,
287 .outp = dcbent,
288 .crtc = crtc,
289 .execute = 1
290 };
291
292 nvbios_exec(&init);
293}
294
295void
296nouveau_bios_init_exec(struct drm_device *dev, uint16_t table)
297{
298 nouveau_bios_run_init_table(dev, table, NULL, 0);
299}
300
301void
302nv_intr(struct drm_device *dev)
303{
304 struct nouveau_drm *drm = nouveau_newpriv(dev);
305 struct nouveau_mc *pmc = nouveau_mc(drm->device);
306 nv_subdev(pmc)->intr(&pmc->base);
307}
308
309bool nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
310 uint32_t reg, uint32_t mask, uint32_t val)
311{
312 struct nouveau_drm *drm = nouveau_newpriv(dev);
313 return nouveau_timer_wait_eq(drm->device, timeout, reg, mask, val);
314}
315
316bool nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
317 uint32_t reg, uint32_t mask, uint32_t val)
318{
319 struct nouveau_drm *drm = nouveau_newpriv(dev);
320 return nouveau_timer_wait_ne(drm->device, timeout, reg, mask, val);
321}
322
323bool nouveau_wait_cb(struct drm_device *dev, u64 timeout,
324 bool (*cond)(void *), void *data)
325{
326 struct nouveau_drm *drm = nouveau_newpriv(dev);
327 return nouveau_timer_wait_cb(drm->device, timeout, cond, data);
328}
329
330u64
331nv_timer_read(struct drm_device *dev)
332{
333 struct nouveau_drm *drm = nouveau_newpriv(dev);
334 struct nouveau_timer *ptimer = nouveau_timer(drm->device);
335 return ptimer->read(ptimer);
336}
337
338int
339nvfb_tile_nr(struct drm_device *dev)
340{
341 struct nouveau_drm *drm = nouveau_newpriv(dev);
342 struct nouveau_fb *pfb = nouveau_fb(drm->device);
343 return pfb->tile.regions;
344}
345
346struct nouveau_fb_tile *
347nvfb_tile(struct drm_device *dev, int i)
348{
349 struct nouveau_drm *drm = nouveau_newpriv(dev);
350 struct nouveau_fb *pfb = nouveau_fb(drm->device);
351 return &pfb->tile.region[i];
352}
353
354void
355nvfb_tile_init(struct drm_device *dev, int i, u32 a, u32 b, u32 c, u32 d)
356{
357 struct nouveau_drm *drm = nouveau_newpriv(dev);
358 struct nouveau_fb *pfb = nouveau_fb(drm->device);
359 pfb->tile.init(pfb, i, a, b, c, d, &pfb->tile.region[i]);
360}
361
362void
363nvfb_tile_fini(struct drm_device *dev, int i)
364{
365 struct nouveau_drm *drm = nouveau_newpriv(dev);
366 struct nouveau_fb *pfb = nouveau_fb(drm->device);
367 pfb->tile.fini(pfb, i, &pfb->tile.region[i]);
368}
369
370void
371nvfb_tile_prog(struct drm_device *dev, int i)
372{
373 struct nouveau_drm *drm = nouveau_newpriv(dev);
374 struct nouveau_fb *pfb = nouveau_fb(drm->device);
375 pfb->tile.prog(pfb, i, &pfb->tile.region[i]);
376}
377
378bool
379nvfb_flags_valid(struct drm_device *dev, u32 flags)
380{
381 struct nouveau_drm *drm = nouveau_newpriv(dev);
382 struct nouveau_fb *pfb = nouveau_fb(drm->device);
383 return pfb->memtype_valid(pfb, flags);
384}
385
386int
387nvfb_vram_get(struct drm_device *dev, u64 size, u32 align, u32 ncmin,
388 u32 memtype, struct nouveau_mem **pmem)
389{
390 struct nouveau_drm *drm = nouveau_newpriv(dev);
391 struct nouveau_fb *pfb = nouveau_fb(drm->device);
392 int ret = pfb->ram.get(pfb, size, align, ncmin, memtype, pmem);
393 if (ret)
394 return ret;
395 (*pmem)->dev = dev;
396 return 0;
397}
398
399void
400nvfb_vram_put(struct drm_device *dev, struct nouveau_mem **pmem)
401{
402 struct nouveau_drm *drm = nouveau_newpriv(dev);
403 struct nouveau_fb *pfb = nouveau_fb(drm->device);
404 pfb->ram.put(pfb, pmem);
405}
406
407
408u64 nvfb_vram_sys_base(struct drm_device *dev)
409{
410 struct nouveau_drm *drm = nouveau_newpriv(dev);
411 struct nouveau_fb *pfb = nouveau_fb(drm->device);
412 return pfb->ram.stolen;
413}
414
415u64 nvfb_vram_size(struct drm_device *dev)
416{
417 struct nouveau_drm *drm = nouveau_newpriv(dev);
418 struct nouveau_fb *pfb = nouveau_fb(drm->device);
419 return pfb->ram.size;
420}
421
422int nvfb_vram_type(struct drm_device *dev)
423{
424 struct nouveau_drm *drm = nouveau_newpriv(dev);
425 struct nouveau_fb *pfb = nouveau_fb(drm->device);
426 return pfb->ram.type;
427}
428
429int nvfb_vram_rank_B(struct drm_device *dev)
430{
431 struct nouveau_drm *drm = nouveau_newpriv(dev);
432 struct nouveau_fb *pfb = nouveau_fb(drm->device);
433 return pfb->ram.ranks > 1;
434}
435
436void
437nv50_fb_vm_trap(struct drm_device *dev, int disp)
438{
439 struct nouveau_drm *drm = nouveau_newpriv(dev);
440 nv50_fb_trap(nouveau_fb(drm->device), disp);
441}
442
443#include <core/subdev/instmem/nv04.h>
444
445struct nouveau_gpuobj *
446nvimem_ramro(struct drm_device *dev)
447{
448 struct nouveau_drm *drm = nouveau_newpriv(dev);
449 struct nv04_instmem_priv *imem = (void *)nouveau_instmem(drm->device);
450 return imem->ramro;
451}
452
453struct nouveau_gpuobj *
454nvimem_ramfc(struct drm_device *dev)
455{
456 struct nouveau_drm *drm = nouveau_newpriv(dev);
457 struct nv04_instmem_priv *imem = (void *)nouveau_instmem(drm->device);
458 return imem->ramfc;
459}
460
461int _nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_gpuobj *par,
462 int size, int align, u32 flags,
463 struct nouveau_gpuobj **pobj)
464{
465 struct nouveau_drm *drm = nouveau_newpriv(dev);
466 int ret;
467
468 if (!par)
469 flags |= NVOBJ_FLAG_HEAP;
470
471 ret = nouveau_gpuobj_new(drm->device, nv_object(par), size, align,
472 flags, pobj);
473 if (ret)
474 return ret;
475
476 (*pobj)->dev = dev;
477 return 0;
478}
479
480u32 nv_ri32(struct drm_device *dev , u32 addr)
481{
482 struct nouveau_drm *drm = nouveau_newpriv(dev);
483 struct nouveau_instmem *imem = nouveau_instmem(drm->device);
484 return nv_ro32(imem, addr);
485}
486
487void nv_wi32(struct drm_device *dev, u32 addr, u32 data)
488{
489 struct nouveau_drm *drm = nouveau_newpriv(dev);
490 struct nouveau_instmem *imem = nouveau_instmem(drm->device);
491 nv_wo32(imem, addr, data);
492}
493
494u32 nvimem_reserved(struct drm_device *dev)
495{
496 struct nouveau_drm *drm = nouveau_newpriv(dev);
497 struct nouveau_instmem *imem = nouveau_instmem(drm->device);
498 return imem->reserved;
499}
500
501int
502nvbar_map(struct drm_device *dev, struct nouveau_mem *mem, u32 flags,
503 struct nouveau_vma *vma)
504{
505 struct nouveau_drm *drm = nouveau_newpriv(dev);
506 struct nouveau_bar *bar = nouveau_bar(drm->device);
507 return bar->umap(bar, mem, flags, vma);
508}
509
510void
511nvbar_unmap(struct drm_device *dev, struct nouveau_vma *vma)
512{
513 struct nouveau_drm *drm = nouveau_newpriv(dev);
514 struct nouveau_bar *bar = nouveau_bar(drm->device);
515 bar->unmap(bar, vma);
516}
517
518int
519nouveau_gpuobj_map_bar(struct nouveau_gpuobj *gpuobj, u32 flags,
520 struct nouveau_vma *vma)
521{
522 struct nouveau_drm *drm = nouveau_newpriv(gpuobj->dev);
523 struct nouveau_bar *bar = nouveau_bar(drm->device);
524 struct nouveau_instobj *iobj = (void *)
525 nv_pclass(nv_object(gpuobj), NV_MEMOBJ_CLASS);
526 struct nouveau_mem **mem = (void *)(iobj + 1);
527 struct nouveau_mem *node = *mem;
528
529 return bar->umap(bar, node, flags, vma);
530}
531
532void
533nvimem_flush(struct drm_device *dev)
534{
535}
536
537void _nv50_vm_flush_engine(struct drm_device *dev, int engine)
538{
539 struct nouveau_drm *drm = nouveau_newpriv(dev);
540 nv50_vm_flush_engine(nv_subdev(drm->device), engine);
541}
542
543int _nouveau_vm_new(struct drm_device *dev, u64 offset, u64 length,
544 u64 mm_offset, struct nouveau_vm **pvm)
545{
546 struct nouveau_drm *drm = nouveau_newpriv(dev);
547 return nouveau_vm_new(nv_device(drm->device), offset, length, mm_offset, pvm);
548}
549
550#include <core/subdev/vm/nv04.h>
551struct nouveau_vm *
552nv04vm_ref(struct drm_device *dev)
553{
554 struct nouveau_drm *drm = nouveau_newpriv(dev);
555 struct nouveau_vmmgr *vmm = nouveau_vmmgr(drm->device);
556 struct nv04_vmmgr_priv *priv = (void *)vmm;
557 return priv->vm;
558}
559
560struct nouveau_gpuobj *
561nv04vm_refdma(struct drm_device *dev)
562{
563 struct nouveau_gpuobj *gpuobj = NULL;
564 nouveau_gpuobj_ref(nv04vm_ref(dev)->pgt[0].obj[0], &gpuobj);
565 return gpuobj;
566}
567
568void
569nvvm_engref(struct nouveau_vm *vm, int eng, int ref)
570{
571 atomic_add(ref, &vm->engref[eng]);
572}
573
574int
575nvvm_spg_shift(struct nouveau_vm *vm)
576{
577 return vm->vmm->spg_shift;
578}
579
580int
581nvvm_lpg_shift(struct nouveau_vm *vm)
582{
583 return vm->vmm->lpg_shift;
584}
585
586u64 nvgpuobj_addr(struct nouveau_object *object)
587{
588 return nv_gpuobj(object)->addr;
589}
590
591struct drm_device *
592nouveau_drv(void *ptr)
593{
594 struct nouveau_drm *drm = ptr;
595 return drm->dev;
596}
597
598struct nouveau_channel *
599nvdrm_channel(struct drm_device *dev)
600{
601 struct nouveau_drm *drm = nouveau_newpriv(dev);
602 return drm->channel;
603}
604
605struct mutex *
606nvchan_mutex(struct nouveau_channel *chan)
607{
608 return &chan->cli->mutex;
609}
diff --git a/drivers/gpu/drm/nouveau/nouveau_compat.h b/drivers/gpu/drm/nouveau/nouveau_compat.h
deleted file mode 100644
index 9f42d1d0f868..000000000000
--- a/drivers/gpu/drm/nouveau/nouveau_compat.h
+++ /dev/null
@@ -1,141 +0,0 @@
1#ifndef __NOUVEAU_COMPAT_H__
2#define __NOUVEAU_COMPAT_H__
3
4int nvdrm_gart_init(struct drm_device *, u64 *, u64 *);
5
6u8 _nv_rd08(struct drm_device *, u32);
7void _nv_wr08(struct drm_device *, u32, u8);
8u32 _nv_rd32(struct drm_device *, u32);
9void _nv_wr32(struct drm_device *, u32, u32);
10u32 _nv_mask(struct drm_device *, u32, u32, u32);
11
12bool _nv_bios(struct drm_device *, u8 **, u32 *);
13
14struct dcb_gpio_func;
15void nouveau_gpio_reset(struct drm_device *);
16int nouveau_gpio_find(struct drm_device *, int, u8, u8, struct dcb_gpio_func *);
17bool nouveau_gpio_func_valid(struct drm_device *, u8 tag);
18int nouveau_gpio_func_set(struct drm_device *, u8 tag, int state);
19int nouveau_gpio_func_get(struct drm_device *, u8 tag);
20int nouveau_gpio_irq(struct drm_device *, int idx, u8 tag, u8 line, bool on);
21int nouveau_gpio_isr_add(struct drm_device *, int idx, u8 tag, u8 line,
22 void (*)(void *, int state), void *data);
23void nouveau_gpio_isr_del(struct drm_device *, int idx, u8 tag, u8 line,
24 void (*)(void *, int state), void *data);
25
26struct nouveau_i2c_port *nouveau_i2c_find(struct drm_device *, u8);
27bool nouveau_probe_i2c_addr(struct nouveau_i2c_port *, int addr);
28struct i2c_adapter *nouveau_i2c_adapter(struct nouveau_i2c_port *);
29int nouveau_i2c_identify(struct drm_device *dev, const char *what,
30 struct i2c_board_info *info,
31 bool (*match)(struct nouveau_i2c_port *,
32 struct i2c_board_info *), int index);
33
34int auxch_rd(struct drm_device *, struct nouveau_i2c_port *, u32, u8 *, u8);
35int auxch_wr(struct drm_device *, struct nouveau_i2c_port *, u32, u8 *, u8);
36
37struct nvbios_pll;
38struct nouveau_pll_vals;
39
40u32 get_pll_register(struct drm_device *dev, u32 type);
41int get_pll_limits(struct drm_device *, u32, struct nvbios_pll *);
42int setPLL(struct drm_device *, u32 reg, u32 clk);
43
44int nouveau_calc_pll_mnp(struct drm_device *, struct nvbios_pll *,
45 int, struct nouveau_pll_vals *);
46int nva3_calc_pll(struct drm_device *dev, struct nvbios_pll *info, u32 freq,
47 int *N, int *fN, int *M, int *P);
48int nouveau_hw_setpll(struct drm_device *, u32, struct nouveau_pll_vals *);
49
50struct dcb_output;
51void nouveau_bios_run_init_table(struct drm_device *, u16, struct dcb_output *, int);
52void nouveau_bios_init_exec(struct drm_device *, u16);
53
54void nv_intr(struct drm_device *);
55
56bool nouveau_wait_eq(struct drm_device *, uint64_t timeout,
57 uint32_t reg, uint32_t mask, uint32_t val);
58bool nouveau_wait_ne(struct drm_device *, uint64_t timeout,
59 uint32_t reg, uint32_t mask, uint32_t val);
60bool nouveau_wait_cb(struct drm_device *, u64 timeout,
61 bool (*cond)(void *), void *);
62
63u64 nv_timer_read(struct drm_device *);
64
65int nvfb_tile_nr(struct drm_device *);
66void nvfb_tile_init(struct drm_device *, int, u32, u32, u32, u32);
67void nvfb_tile_fini(struct drm_device *, int);
68void nvfb_tile_prog(struct drm_device *, int);
69
70struct nouveau_fb_tile *nvfb_tile(struct drm_device *, int);
71
72struct nouveau_mem;
73int nvfb_vram_get(struct drm_device *dev, u64 size, u32 align, u32 ncmin,
74 u32 memtype, struct nouveau_mem **pmem);
75void nvfb_vram_put(struct drm_device *dev, struct nouveau_mem **pmem);
76bool nvfb_flags_valid(struct drm_device *dev, u32);
77
78u64 nvfb_vram_sys_base(struct drm_device *);
79u64 nvfb_vram_size(struct drm_device *);
80int nvfb_vram_type(struct drm_device *);
81int nvfb_vram_rank_B(struct drm_device *);
82
83void nv50_fb_vm_trap(struct drm_device *, int);
84
85struct nouveau_gpuobj *nvimem_ramro(struct drm_device *);
86struct nouveau_gpuobj *nvimem_ramfc(struct drm_device *);
87
88int _nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_gpuobj *par,
89 int size, int align, u32 flags,
90 struct nouveau_gpuobj **pboj);
91
92u32 nv_ri32(struct drm_device *, u32);
93void nv_wi32(struct drm_device *, u32, u32);
94u32 nvimem_reserved(struct drm_device *);
95
96void nvimem_flush(struct drm_device *);
97
98void _nv50_vm_flush_engine(struct drm_device *dev, int engine);
99
100int _nouveau_vm_new(struct drm_device *, u64 offset, u64 length,
101 u64 mm_offset, struct nouveau_vm **);
102
103struct nouveau_vma;
104int nouveau_gpuobj_map_bar(struct nouveau_gpuobj *, u32, struct nouveau_vma *);
105
106int
107nvbar_map(struct drm_device *dev, struct nouveau_mem *mem, u32 flags,
108 struct nouveau_vma *vma);
109void
110nvbar_unmap(struct drm_device *dev, struct nouveau_vma *vma);
111
112struct nouveau_vm *
113nv04vm_ref(struct drm_device *dev);
114
115struct nouveau_gpuobj *
116nv04vm_refdma(struct drm_device *dev);
117
118void
119nvvm_engref(struct nouveau_vm *, int, int);
120
121int
122nvvm_spg_shift(struct nouveau_vm *);
123
124int
125nvvm_lpg_shift(struct nouveau_vm *);
126
127u32
128nv50_display_active_crtcs(struct drm_device *dev);
129
130u64 nvgpuobj_addr(struct nouveau_object *object);
131
132struct drm_device *
133nouveau_drv(void *drm);
134
135struct nouveau_channel *
136nvdrm_channel(struct drm_device *dev);
137
138struct mutex *
139nvchan_mutex(struct nouveau_channel *chan);
140
141#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 5dbf2e45993d..702e2a74d2d1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -31,14 +31,29 @@
31#include "drm_crtc_helper.h" 31#include "drm_crtc_helper.h"
32 32
33#include "nouveau_reg.h" 33#include "nouveau_reg.h"
34#include "nouveau_drv.h" 34#include "nouveau_drm.h"
35#include "nouveau_encoder.h"
36#include "nouveau_crtc.h"
37#include "nouveau_connector.h"
38#include "nouveau_hw.h" 35#include "nouveau_hw.h"
39#include "nouveau_acpi.h" 36#include "nouveau_acpi.h"
40 37
41#include <subdev/bios/gpio.h> 38#include "nouveau_display.h"
39#include "nouveau_connector.h"
40#include "nouveau_encoder.h"
41#include "nouveau_crtc.h"
42
43#include <subdev/i2c.h>
44#include <subdev/gpio.h>
45
46MODULE_PARM_DESC(tv_disable, "Disable TV-out detection");
47static int nouveau_tv_disable = 0;
48module_param_named(tv_disable, nouveau_tv_disable, int, 0400);
49
50MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
51static int nouveau_ignorelid = 0;
52module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
53
54MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (default: enabled)");
55static int nouveau_duallink = 1;
56module_param_named(duallink, nouveau_duallink, int, 0400);
42 57
43static void nouveau_connector_hotplug(void *, int); 58static void nouveau_connector_hotplug(void *, int);
44 59
@@ -85,19 +100,21 @@ static void
85nouveau_connector_destroy(struct drm_connector *connector) 100nouveau_connector_destroy(struct drm_connector *connector)
86{ 101{
87 struct nouveau_connector *nv_connector = nouveau_connector(connector); 102 struct nouveau_connector *nv_connector = nouveau_connector(connector);
88 struct drm_nouveau_private *dev_priv; 103 struct nouveau_gpio *gpio;
104 struct nouveau_drm *drm;
89 struct drm_device *dev; 105 struct drm_device *dev;
90 106
91 if (!nv_connector) 107 if (!nv_connector)
92 return; 108 return;
93 109
94 dev = nv_connector->base.dev; 110 dev = nv_connector->base.dev;
95 dev_priv = dev->dev_private; 111 drm = nouveau_drm(dev);
96 NV_DEBUG_KMS(dev, "\n"); 112 gpio = nouveau_gpio(drm->device);
113 NV_DEBUG(drm, "\n");
97 114
98 if (nv_connector->hpd != DCB_GPIO_UNUSED) { 115 if (gpio && nv_connector->hpd != DCB_GPIO_UNUSED) {
99 nouveau_gpio_isr_del(dev, 0, nv_connector->hpd, 0xff, 116 gpio->isr_del(gpio, 0, nv_connector->hpd, 0xff,
100 nouveau_connector_hotplug, connector); 117 nouveau_connector_hotplug, connector);
101 } 118 }
102 119
103 kfree(nv_connector->edid); 120 kfree(nv_connector->edid);
@@ -111,10 +128,12 @@ nouveau_connector_ddc_detect(struct drm_connector *connector,
111 struct nouveau_encoder **pnv_encoder) 128 struct nouveau_encoder **pnv_encoder)
112{ 129{
113 struct drm_device *dev = connector->dev; 130 struct drm_device *dev = connector->dev;
131 struct nouveau_drm *drm = nouveau_drm(dev);
132 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
114 int i; 133 int i;
115 134
116 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 135 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
117 struct nouveau_i2c_port *i2c = NULL; 136 struct nouveau_i2c_port *port = NULL;
118 struct nouveau_encoder *nv_encoder; 137 struct nouveau_encoder *nv_encoder;
119 struct drm_mode_object *obj; 138 struct drm_mode_object *obj;
120 int id; 139 int id;
@@ -129,11 +148,10 @@ nouveau_connector_ddc_detect(struct drm_connector *connector,
129 nv_encoder = nouveau_encoder(obj_to_encoder(obj)); 148 nv_encoder = nouveau_encoder(obj_to_encoder(obj));
130 149
131 if (nv_encoder->dcb->i2c_index < 0xf) 150 if (nv_encoder->dcb->i2c_index < 0xf)
132 i2c = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index); 151 port = i2c->find(i2c, nv_encoder->dcb->i2c_index);
133 152 if (port && nv_probe_i2c(port, 0x50)) {
134 if (i2c && nouveau_probe_i2c_addr(i2c, 0x50)) {
135 *pnv_encoder = nv_encoder; 153 *pnv_encoder = nv_encoder;
136 return i2c; 154 return port;
137 } 155 }
138 } 156 }
139 157
@@ -175,14 +193,14 @@ nouveau_connector_set_encoder(struct drm_connector *connector,
175 struct nouveau_encoder *nv_encoder) 193 struct nouveau_encoder *nv_encoder)
176{ 194{
177 struct nouveau_connector *nv_connector = nouveau_connector(connector); 195 struct nouveau_connector *nv_connector = nouveau_connector(connector);
178 struct drm_nouveau_private *dev_priv = connector->dev->dev_private; 196 struct nouveau_drm *drm = nouveau_drm(connector->dev);
179 struct drm_device *dev = connector->dev; 197 struct drm_device *dev = connector->dev;
180 198
181 if (nv_connector->detected_encoder == nv_encoder) 199 if (nv_connector->detected_encoder == nv_encoder)
182 return; 200 return;
183 nv_connector->detected_encoder = nv_encoder; 201 nv_connector->detected_encoder = nv_encoder;
184 202
185 if (dev_priv->card_type >= NV_50) { 203 if (nv_device(drm->device)->card_type >= NV_50) {
186 connector->interlace_allowed = true; 204 connector->interlace_allowed = true;
187 connector->doublescan_allowed = true; 205 connector->doublescan_allowed = true;
188 } else 206 } else
@@ -192,8 +210,8 @@ nouveau_connector_set_encoder(struct drm_connector *connector,
192 connector->interlace_allowed = false; 210 connector->interlace_allowed = false;
193 } else { 211 } else {
194 connector->doublescan_allowed = true; 212 connector->doublescan_allowed = true;
195 if (dev_priv->card_type == NV_20 || 213 if (nv_device(drm->device)->card_type == NV_20 ||
196 (dev_priv->card_type == NV_10 && 214 (nv_device(drm->device)->card_type == NV_10 &&
197 (dev->pci_device & 0x0ff0) != 0x0100 && 215 (dev->pci_device & 0x0ff0) != 0x0100 &&
198 (dev->pci_device & 0x0ff0) != 0x0150)) 216 (dev->pci_device & 0x0ff0) != 0x0150))
199 /* HW is broken */ 217 /* HW is broken */
@@ -215,6 +233,7 @@ static enum drm_connector_status
215nouveau_connector_detect(struct drm_connector *connector, bool force) 233nouveau_connector_detect(struct drm_connector *connector, bool force)
216{ 234{
217 struct drm_device *dev = connector->dev; 235 struct drm_device *dev = connector->dev;
236 struct nouveau_drm *drm = nouveau_drm(dev);
218 struct nouveau_connector *nv_connector = nouveau_connector(connector); 237 struct nouveau_connector *nv_connector = nouveau_connector(connector);
219 struct nouveau_encoder *nv_encoder = NULL; 238 struct nouveau_encoder *nv_encoder = NULL;
220 struct nouveau_encoder *nv_partner; 239 struct nouveau_encoder *nv_partner;
@@ -230,18 +249,18 @@ nouveau_connector_detect(struct drm_connector *connector, bool force)
230 249
231 i2c = nouveau_connector_ddc_detect(connector, &nv_encoder); 250 i2c = nouveau_connector_ddc_detect(connector, &nv_encoder);
232 if (i2c) { 251 if (i2c) {
233 nv_connector->edid = drm_get_edid(connector, nouveau_i2c_adapter(i2c)); 252 nv_connector->edid = drm_get_edid(connector, &i2c->adapter);
234 drm_mode_connector_update_edid_property(connector, 253 drm_mode_connector_update_edid_property(connector,
235 nv_connector->edid); 254 nv_connector->edid);
236 if (!nv_connector->edid) { 255 if (!nv_connector->edid) {
237 NV_ERROR(dev, "DDC responded, but no EDID for %s\n", 256 NV_ERROR(drm, "DDC responded, but no EDID for %s\n",
238 drm_get_connector_name(connector)); 257 drm_get_connector_name(connector));
239 goto detect_analog; 258 goto detect_analog;
240 } 259 }
241 260
242 if (nv_encoder->dcb->type == DCB_OUTPUT_DP && 261 if (nv_encoder->dcb->type == DCB_OUTPUT_DP &&
243 !nouveau_dp_detect(to_drm_encoder(nv_encoder))) { 262 !nouveau_dp_detect(to_drm_encoder(nv_encoder))) {
244 NV_ERROR(dev, "Detected %s, but failed init\n", 263 NV_ERROR(drm, "Detected %s, but failed init\n",
245 drm_get_connector_name(connector)); 264 drm_get_connector_name(connector));
246 return connector_status_disconnected; 265 return connector_status_disconnected;
247 } 266 }
@@ -303,7 +322,7 @@ static enum drm_connector_status
303nouveau_connector_detect_lvds(struct drm_connector *connector, bool force) 322nouveau_connector_detect_lvds(struct drm_connector *connector, bool force)
304{ 323{
305 struct drm_device *dev = connector->dev; 324 struct drm_device *dev = connector->dev;
306 struct drm_nouveau_private *dev_priv = dev->dev_private; 325 struct nouveau_drm *drm = nouveau_drm(dev);
307 struct nouveau_connector *nv_connector = nouveau_connector(connector); 326 struct nouveau_connector *nv_connector = nouveau_connector(connector);
308 struct nouveau_encoder *nv_encoder = NULL; 327 struct nouveau_encoder *nv_encoder = NULL;
309 enum drm_connector_status status = connector_status_disconnected; 328 enum drm_connector_status status = connector_status_disconnected;
@@ -320,7 +339,7 @@ nouveau_connector_detect_lvds(struct drm_connector *connector, bool force)
320 return connector_status_disconnected; 339 return connector_status_disconnected;
321 340
322 /* Try retrieving EDID via DDC */ 341 /* Try retrieving EDID via DDC */
323 if (!dev_priv->vbios.fp_no_ddc) { 342 if (!drm->vbios.fp_no_ddc) {
324 status = nouveau_connector_detect(connector, force); 343 status = nouveau_connector_detect(connector, force);
325 if (status == connector_status_connected) 344 if (status == connector_status_connected)
326 goto out; 345 goto out;
@@ -346,7 +365,7 @@ nouveau_connector_detect_lvds(struct drm_connector *connector, bool force)
346 * modeline is avalilable for the panel, set it as the panel's 365 * modeline is avalilable for the panel, set it as the panel's
347 * native mode and exit. 366 * native mode and exit.
348 */ 367 */
349 if (nouveau_bios_fp_mode(dev, NULL) && (dev_priv->vbios.fp_no_ddc || 368 if (nouveau_bios_fp_mode(dev, NULL) && (drm->vbios.fp_no_ddc ||
350 nv_encoder->dcb->lvdsconf.use_straps_for_mode)) { 369 nv_encoder->dcb->lvdsconf.use_straps_for_mode)) {
351 status = connector_status_connected; 370 status = connector_status_connected;
352 goto out; 371 goto out;
@@ -355,7 +374,7 @@ nouveau_connector_detect_lvds(struct drm_connector *connector, bool force)
355 /* Still nothing, some VBIOS images have a hardcoded EDID block 374 /* Still nothing, some VBIOS images have a hardcoded EDID block
356 * stored for the panel stored in them. 375 * stored for the panel stored in them.
357 */ 376 */
358 if (!dev_priv->vbios.fp_no_ddc) { 377 if (!drm->vbios.fp_no_ddc) {
359 struct edid *edid = 378 struct edid *edid =
360 (struct edid *)nouveau_bios_embedded_edid(dev); 379 (struct edid *)nouveau_bios_embedded_edid(dev);
361 if (edid) { 380 if (edid) {
@@ -381,6 +400,7 @@ out:
381static void 400static void
382nouveau_connector_force(struct drm_connector *connector) 401nouveau_connector_force(struct drm_connector *connector)
383{ 402{
403 struct nouveau_drm *drm = nouveau_drm(connector->dev);
384 struct nouveau_connector *nv_connector = nouveau_connector(connector); 404 struct nouveau_connector *nv_connector = nouveau_connector(connector);
385 struct nouveau_encoder *nv_encoder; 405 struct nouveau_encoder *nv_encoder;
386 int type; 406 int type;
@@ -395,7 +415,7 @@ nouveau_connector_force(struct drm_connector *connector)
395 415
396 nv_encoder = find_encoder(connector, type); 416 nv_encoder = find_encoder(connector, type);
397 if (!nv_encoder) { 417 if (!nv_encoder) {
398 NV_ERROR(connector->dev, "can't find encoder to force %s on!\n", 418 NV_ERROR(drm, "can't find encoder to force %s on!\n",
399 drm_get_connector_name(connector)); 419 drm_get_connector_name(connector));
400 connector->status = connector_status_disconnected; 420 connector->status = connector_status_disconnected;
401 return; 421 return;
@@ -408,8 +428,7 @@ static int
408nouveau_connector_set_property(struct drm_connector *connector, 428nouveau_connector_set_property(struct drm_connector *connector,
409 struct drm_property *property, uint64_t value) 429 struct drm_property *property, uint64_t value)
410{ 430{
411 struct drm_nouveau_private *dev_priv = connector->dev->dev_private; 431 struct nouveau_display *disp = nouveau_display(connector->dev);
412 struct nouveau_display_engine *disp = &dev_priv->engine.display;
413 struct nouveau_connector *nv_connector = nouveau_connector(connector); 432 struct nouveau_connector *nv_connector = nouveau_connector(connector);
414 struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder; 433 struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder;
415 struct drm_encoder *encoder = to_drm_encoder(nv_encoder); 434 struct drm_encoder *encoder = to_drm_encoder(nv_encoder);
@@ -545,6 +564,7 @@ static struct drm_display_mode *
545nouveau_connector_native_mode(struct drm_connector *connector) 564nouveau_connector_native_mode(struct drm_connector *connector)
546{ 565{
547 struct drm_connector_helper_funcs *helper = connector->helper_private; 566 struct drm_connector_helper_funcs *helper = connector->helper_private;
567 struct nouveau_drm *drm = nouveau_drm(connector->dev);
548 struct nouveau_connector *nv_connector = nouveau_connector(connector); 568 struct nouveau_connector *nv_connector = nouveau_connector(connector);
549 struct drm_device *dev = connector->dev; 569 struct drm_device *dev = connector->dev;
550 struct drm_display_mode *mode, *largest = NULL; 570 struct drm_display_mode *mode, *largest = NULL;
@@ -558,7 +578,7 @@ nouveau_connector_native_mode(struct drm_connector *connector)
558 578
559 /* Use preferred mode if there is one.. */ 579 /* Use preferred mode if there is one.. */
560 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 580 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
561 NV_DEBUG_KMS(dev, "native mode from preferred\n"); 581 NV_DEBUG(drm, "native mode from preferred\n");
562 return drm_mode_duplicate(dev, mode); 582 return drm_mode_duplicate(dev, mode);
563 } 583 }
564 584
@@ -581,7 +601,7 @@ nouveau_connector_native_mode(struct drm_connector *connector)
581 largest = mode; 601 largest = mode;
582 } 602 }
583 603
584 NV_DEBUG_KMS(dev, "native mode from largest: %dx%d@%d\n", 604 NV_DEBUG(drm, "native mode from largest: %dx%d@%d\n",
585 high_w, high_h, high_v); 605 high_w, high_h, high_v);
586 return largest ? drm_mode_duplicate(dev, largest) : NULL; 606 return largest ? drm_mode_duplicate(dev, largest) : NULL;
587} 607}
@@ -645,10 +665,10 @@ nouveau_connector_scaler_modes_add(struct drm_connector *connector)
645static void 665static void
646nouveau_connector_detect_depth(struct drm_connector *connector) 666nouveau_connector_detect_depth(struct drm_connector *connector)
647{ 667{
648 struct drm_nouveau_private *dev_priv = connector->dev->dev_private; 668 struct nouveau_drm *drm = nouveau_drm(connector->dev);
649 struct nouveau_connector *nv_connector = nouveau_connector(connector); 669 struct nouveau_connector *nv_connector = nouveau_connector(connector);
650 struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder; 670 struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder;
651 struct nvbios *bios = &dev_priv->vbios; 671 struct nvbios *bios = &drm->vbios;
652 struct drm_display_mode *mode = nv_connector->native_mode; 672 struct drm_display_mode *mode = nv_connector->native_mode;
653 bool duallink; 673 bool duallink;
654 674
@@ -695,7 +715,7 @@ static int
695nouveau_connector_get_modes(struct drm_connector *connector) 715nouveau_connector_get_modes(struct drm_connector *connector)
696{ 716{
697 struct drm_device *dev = connector->dev; 717 struct drm_device *dev = connector->dev;
698 struct drm_nouveau_private *dev_priv = dev->dev_private; 718 struct nouveau_drm *drm = nouveau_drm(dev);
699 struct nouveau_connector *nv_connector = nouveau_connector(connector); 719 struct nouveau_connector *nv_connector = nouveau_connector(connector);
700 struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder; 720 struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder;
701 struct drm_encoder *encoder = to_drm_encoder(nv_encoder); 721 struct drm_encoder *encoder = to_drm_encoder(nv_encoder);
@@ -713,7 +733,7 @@ nouveau_connector_get_modes(struct drm_connector *connector)
713 else 733 else
714 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS && 734 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS &&
715 (nv_encoder->dcb->lvdsconf.use_straps_for_mode || 735 (nv_encoder->dcb->lvdsconf.use_straps_for_mode ||
716 dev_priv->vbios.fp_no_ddc) && nouveau_bios_fp_mode(dev, NULL)) { 736 drm->vbios.fp_no_ddc) && nouveau_bios_fp_mode(dev, NULL)) {
717 struct drm_display_mode mode; 737 struct drm_display_mode mode;
718 738
719 nouveau_bios_fp_mode(dev, &mode); 739 nouveau_bios_fp_mode(dev, &mode);
@@ -763,15 +783,15 @@ static unsigned
763get_tmds_link_bandwidth(struct drm_connector *connector) 783get_tmds_link_bandwidth(struct drm_connector *connector)
764{ 784{
765 struct nouveau_connector *nv_connector = nouveau_connector(connector); 785 struct nouveau_connector *nv_connector = nouveau_connector(connector);
766 struct drm_nouveau_private *dev_priv = connector->dev->dev_private; 786 struct nouveau_drm *drm = nouveau_drm(connector->dev);
767 struct dcb_output *dcb = nv_connector->detected_encoder->dcb; 787 struct dcb_output *dcb = nv_connector->detected_encoder->dcb;
768 788
769 if (dcb->location != DCB_LOC_ON_CHIP || 789 if (dcb->location != DCB_LOC_ON_CHIP ||
770 dev_priv->chipset >= 0x46) 790 nv_device(drm->device)->chipset >= 0x46)
771 return 165000; 791 return 165000;
772 else if (dev_priv->chipset >= 0x40) 792 else if (nv_device(drm->device)->chipset >= 0x40)
773 return 155000; 793 return 155000;
774 else if (dev_priv->chipset >= 0x18) 794 else if (nv_device(drm->device)->chipset >= 0x18)
775 return 135000; 795 return 135000;
776 else 796 else
777 return 112000; 797 return 112000;
@@ -901,14 +921,15 @@ struct drm_connector *
901nouveau_connector_create(struct drm_device *dev, int index) 921nouveau_connector_create(struct drm_device *dev, int index)
902{ 922{
903 const struct drm_connector_funcs *funcs = &nouveau_connector_funcs; 923 const struct drm_connector_funcs *funcs = &nouveau_connector_funcs;
904 struct drm_nouveau_private *dev_priv = dev->dev_private; 924 struct nouveau_drm *drm = nouveau_drm(dev);
905 struct nouveau_display_engine *disp = &dev_priv->engine.display; 925 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
926 struct nouveau_display *disp = nouveau_display(dev);
906 struct nouveau_connector *nv_connector = NULL; 927 struct nouveau_connector *nv_connector = NULL;
907 struct drm_connector *connector; 928 struct drm_connector *connector;
908 int type, ret = 0; 929 int type, ret = 0;
909 bool dummy; 930 bool dummy;
910 931
911 NV_DEBUG_KMS(dev, "\n"); 932 NV_DEBUG(drm, "\n");
912 933
913 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 934 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
914 nv_connector = nouveau_connector(connector); 935 nv_connector = nouveau_connector(connector);
@@ -941,7 +962,7 @@ nouveau_connector_create(struct drm_device *dev, int index)
941 nv_connector->type = nv_connector->dcb[0]; 962 nv_connector->type = nv_connector->dcb[0];
942 if (drm_conntype_from_dcb(nv_connector->type) == 963 if (drm_conntype_from_dcb(nv_connector->type) ==
943 DRM_MODE_CONNECTOR_Unknown) { 964 DRM_MODE_CONNECTOR_Unknown) {
944 NV_WARN(dev, "unknown connector type %02x\n", 965 NV_WARN(drm, "unknown connector type %02x\n",
945 nv_connector->type); 966 nv_connector->type);
946 nv_connector->type = DCB_CONNECTOR_NONE; 967 nv_connector->type = DCB_CONNECTOR_NONE;
947 } 968 }
@@ -966,8 +987,8 @@ nouveau_connector_create(struct drm_device *dev, int index)
966 * figure out something suitable ourselves 987 * figure out something suitable ourselves
967 */ 988 */
968 if (nv_connector->type == DCB_CONNECTOR_NONE) { 989 if (nv_connector->type == DCB_CONNECTOR_NONE) {
969 struct drm_nouveau_private *dev_priv = dev->dev_private; 990 struct nouveau_drm *drm = nouveau_drm(dev);
970 struct dcb_table *dcbt = &dev_priv->vbios.dcb; 991 struct dcb_table *dcbt = &drm->vbios.dcb;
971 u32 encoders = 0; 992 u32 encoders = 0;
972 int i; 993 int i;
973 994
@@ -1003,7 +1024,7 @@ nouveau_connector_create(struct drm_device *dev, int index)
1003 if (type == DRM_MODE_CONNECTOR_LVDS) { 1024 if (type == DRM_MODE_CONNECTOR_LVDS) {
1004 ret = nouveau_bios_parse_lvds_table(dev, 0, &dummy, &dummy); 1025 ret = nouveau_bios_parse_lvds_table(dev, 0, &dummy, &dummy);
1005 if (ret) { 1026 if (ret) {
1006 NV_ERROR(dev, "Error parsing LVDS table, disabling\n"); 1027 NV_ERROR(drm, "Error parsing LVDS table, disabling\n");
1007 kfree(nv_connector); 1028 kfree(nv_connector);
1008 return ERR_PTR(ret); 1029 return ERR_PTR(ret);
1009 } 1030 }
@@ -1053,7 +1074,7 @@ nouveau_connector_create(struct drm_device *dev, int index)
1053 1074
1054 switch (nv_connector->type) { 1075 switch (nv_connector->type) {
1055 case DCB_CONNECTOR_VGA: 1076 case DCB_CONNECTOR_VGA:
1056 if (dev_priv->card_type >= NV_50) { 1077 if (nv_device(drm->device)->card_type >= NV_50) {
1057 drm_connector_attach_property(connector, 1078 drm_connector_attach_property(connector,
1058 dev->mode_config.scaling_mode_property, 1079 dev->mode_config.scaling_mode_property,
1059 nv_connector->scaling_mode); 1080 nv_connector->scaling_mode);
@@ -1086,10 +1107,9 @@ nouveau_connector_create(struct drm_device *dev, int index)
1086 } 1107 }
1087 1108
1088 connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1109 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1089 if (nv_connector->hpd != DCB_GPIO_UNUSED) { 1110 if (gpio && nv_connector->hpd != DCB_GPIO_UNUSED) {
1090 ret = nouveau_gpio_isr_add(dev, 0, nv_connector->hpd, 0xff, 1111 ret = gpio->isr_add(gpio, 0, nv_connector->hpd, 0xff,
1091 nouveau_connector_hotplug, 1112 nouveau_connector_hotplug, connector);
1092 connector);
1093 if (ret == 0) 1113 if (ret == 0)
1094 connector->polled = DRM_CONNECTOR_POLL_HPD; 1114 connector->polled = DRM_CONNECTOR_POLL_HPD;
1095 } 1115 }
@@ -1103,8 +1123,9 @@ nouveau_connector_hotplug(void *data, int plugged)
1103{ 1123{
1104 struct drm_connector *connector = data; 1124 struct drm_connector *connector = data;
1105 struct drm_device *dev = connector->dev; 1125 struct drm_device *dev = connector->dev;
1126 struct nouveau_drm *drm = nouveau_drm(dev);
1106 1127
1107 NV_DEBUG(dev, "%splugged %s\n", plugged ? "" : "un", 1128 NV_DEBUG(drm, "%splugged %s\n", plugged ? "" : "un",
1108 drm_get_connector_name(connector)); 1129 drm_get_connector_name(connector));
1109 1130
1110 if (plugged) 1131 if (plugged)
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index a60a9f51e890..61f370d000e9 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -26,18 +26,20 @@
26 26
27#include "drmP.h" 27#include "drmP.h"
28#include "drm_crtc_helper.h" 28#include "drm_crtc_helper.h"
29#include "nouveau_drv.h" 29
30#include "nouveau_fb.h"
31#include "nouveau_fbcon.h" 30#include "nouveau_fbcon.h"
32#include "nouveau_hw.h" 31#include "nouveau_hw.h"
33#include "nouveau_crtc.h" 32#include "nouveau_crtc.h"
34#include "nouveau_dma.h" 33#include "nouveau_dma.h"
34#include "nouveau_gem.h"
35#include "nouveau_connector.h" 35#include "nouveau_connector.h"
36#include "nv50_display.h" 36#include "nv50_display.h"
37 37
38#include "nouveau_fence.h" 38#include "nouveau_fence.h"
39 39
40#include <subdev/bios/gpio.h> 40#include <subdev/bios/gpio.h>
41#include <subdev/gpio.h>
42#include <engine/disp.h>
41 43
42static void 44static void
43nouveau_user_framebuffer_destroy(struct drm_framebuffer *drm_fb) 45nouveau_user_framebuffer_destroy(struct drm_framebuffer *drm_fb)
@@ -72,7 +74,7 @@ nouveau_framebuffer_init(struct drm_device *dev,
72 struct drm_mode_fb_cmd2 *mode_cmd, 74 struct drm_mode_fb_cmd2 *mode_cmd,
73 struct nouveau_bo *nvbo) 75 struct nouveau_bo *nvbo)
74{ 76{
75 struct drm_nouveau_private *dev_priv = dev->dev_private; 77 struct nouveau_drm *drm = nouveau_drm(dev);
76 struct drm_framebuffer *fb = &nv_fb->base; 78 struct drm_framebuffer *fb = &nv_fb->base;
77 int ret; 79 int ret;
78 80
@@ -84,7 +86,7 @@ nouveau_framebuffer_init(struct drm_device *dev,
84 drm_helper_mode_fill_fb_struct(fb, mode_cmd); 86 drm_helper_mode_fill_fb_struct(fb, mode_cmd);
85 nv_fb->nvbo = nvbo; 87 nv_fb->nvbo = nvbo;
86 88
87 if (dev_priv->card_type >= NV_50) { 89 if (nv_device(drm->device)->card_type >= NV_50) {
88 u32 tile_flags = nouveau_bo_tile_layout(nvbo); 90 u32 tile_flags = nouveau_bo_tile_layout(nvbo);
89 if (tile_flags == 0x7a00 || 91 if (tile_flags == 0x7a00 ||
90 tile_flags == 0xfe00) 92 tile_flags == 0xfe00)
@@ -103,21 +105,21 @@ nouveau_framebuffer_init(struct drm_device *dev,
103 case 32: nv_fb->r_format = NV50_EVO_CRTC_FB_DEPTH_24; break; 105 case 32: nv_fb->r_format = NV50_EVO_CRTC_FB_DEPTH_24; break;
104 case 30: nv_fb->r_format = NV50_EVO_CRTC_FB_DEPTH_30; break; 106 case 30: nv_fb->r_format = NV50_EVO_CRTC_FB_DEPTH_30; break;
105 default: 107 default:
106 NV_ERROR(dev, "unknown depth %d\n", fb->depth); 108 NV_ERROR(drm, "unknown depth %d\n", fb->depth);
107 return -EINVAL; 109 return -EINVAL;
108 } 110 }
109 111
110 if (dev_priv->chipset == 0x50) 112 if (nv_device(drm->device)->chipset == 0x50)
111 nv_fb->r_format |= (tile_flags << 8); 113 nv_fb->r_format |= (tile_flags << 8);
112 114
113 if (!tile_flags) { 115 if (!tile_flags) {
114 if (dev_priv->card_type < NV_D0) 116 if (nv_device(drm->device)->card_type < NV_D0)
115 nv_fb->r_pitch = 0x00100000 | fb->pitches[0]; 117 nv_fb->r_pitch = 0x00100000 | fb->pitches[0];
116 else 118 else
117 nv_fb->r_pitch = 0x01000000 | fb->pitches[0]; 119 nv_fb->r_pitch = 0x01000000 | fb->pitches[0];
118 } else { 120 } else {
119 u32 mode = nvbo->tile_mode; 121 u32 mode = nvbo->tile_mode;
120 if (dev_priv->card_type >= NV_C0) 122 if (nv_device(drm->device)->card_type >= NV_C0)
121 mode >>= 4; 123 mode >>= 4;
122 nv_fb->r_pitch = ((fb->pitches[0] / 4) << 4) | mode; 124 nv_fb->r_pitch = ((fb->pitches[0] / 4) << 4) | mode;
123 } 125 }
@@ -213,8 +215,9 @@ static struct nouveau_drm_prop_enum_list dither_depth[] = {
213int 215int
214nouveau_display_init(struct drm_device *dev) 216nouveau_display_init(struct drm_device *dev)
215{ 217{
216 struct drm_nouveau_private *dev_priv = dev->dev_private; 218 struct nouveau_drm *drm = nouveau_drm(dev);
217 struct nouveau_display_engine *disp = &dev_priv->engine.display; 219 struct nouveau_display *disp = nouveau_display(dev);
220 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
218 struct drm_connector *connector; 221 struct drm_connector *connector;
219 int ret; 222 int ret;
220 223
@@ -226,8 +229,8 @@ nouveau_display_init(struct drm_device *dev)
226 * some vbios default this to off for some reason, causing the 229 * some vbios default this to off for some reason, causing the
227 * panel to not work after resume 230 * panel to not work after resume
228 */ 231 */
229 if (nouveau_gpio_func_get(dev, DCB_GPIO_PANEL_POWER) == 0) { 232 if (gpio && gpio->get(gpio, 0, DCB_GPIO_PANEL_POWER, 0xff) == 0) {
230 nouveau_gpio_func_set(dev, DCB_GPIO_PANEL_POWER, true); 233 gpio->set(gpio, 0, DCB_GPIO_PANEL_POWER, 0xff, 1);
231 msleep(300); 234 msleep(300);
232 } 235 }
233 236
@@ -237,7 +240,8 @@ nouveau_display_init(struct drm_device *dev)
237 /* enable hotplug interrupts */ 240 /* enable hotplug interrupts */
238 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 241 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
239 struct nouveau_connector *conn = nouveau_connector(connector); 242 struct nouveau_connector *conn = nouveau_connector(connector);
240 nouveau_gpio_irq(dev, 0, conn->hpd, 0xff, true); 243 if (gpio)
244 gpio->irq(gpio, 0, conn->hpd, 0xff, true);
241 } 245 }
242 246
243 return ret; 247 return ret;
@@ -246,14 +250,16 @@ nouveau_display_init(struct drm_device *dev)
246void 250void
247nouveau_display_fini(struct drm_device *dev) 251nouveau_display_fini(struct drm_device *dev)
248{ 252{
249 struct drm_nouveau_private *dev_priv = dev->dev_private; 253 struct nouveau_drm *drm = nouveau_drm(dev);
250 struct nouveau_display_engine *disp = &dev_priv->engine.display; 254 struct nouveau_display *disp = nouveau_display(dev);
255 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
251 struct drm_connector *connector; 256 struct drm_connector *connector;
252 257
253 /* disable hotplug interrupts */ 258 /* disable hotplug interrupts */
254 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 259 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
255 struct nouveau_connector *conn = nouveau_connector(connector); 260 struct nouveau_connector *conn = nouveau_connector(connector);
256 nouveau_gpio_irq(dev, 0, conn->hpd, 0xff, false); 261 if (gpio)
262 gpio->irq(gpio, 0, conn->hpd, 0xff, false);
257 } 263 }
258 264
259 drm_kms_helper_poll_disable(dev); 265 drm_kms_helper_poll_disable(dev);
@@ -281,18 +287,28 @@ nouveau_display_vblank_put(void *data, int crtc)
281int 287int
282nouveau_display_create(struct drm_device *dev) 288nouveau_display_create(struct drm_device *dev)
283{ 289{
284 struct drm_nouveau_private *dev_priv = dev->dev_private; 290 struct nouveau_drm *drm = nouveau_drm(dev);
285 struct nouveau_display_engine *disp = &dev_priv->engine.display; 291 struct nouveau_disp *pdisp = nouveau_disp(drm->device);
292 struct nouveau_display *disp;
286 int ret, gen; 293 int ret, gen;
287 294
295 disp = drm->display = kzalloc(sizeof(*disp), GFP_KERNEL);
296 if (!disp)
297 return -ENOMEM;
298
299 pdisp->vblank.data = dev;
300 pdisp->vblank.notify = nouveau_display_vblank_notify;
301 pdisp->vblank.get = nouveau_display_vblank_get;
302 pdisp->vblank.put = nouveau_display_vblank_put;
303
288 drm_mode_config_init(dev); 304 drm_mode_config_init(dev);
289 drm_mode_create_scaling_mode_property(dev); 305 drm_mode_create_scaling_mode_property(dev);
290 drm_mode_create_dvi_i_properties(dev); 306 drm_mode_create_dvi_i_properties(dev);
291 307
292 if (dev_priv->card_type < NV_50) 308 if (nv_device(drm->device)->card_type < NV_50)
293 gen = 0; 309 gen = 0;
294 else 310 else
295 if (dev_priv->card_type < NV_D0) 311 if (nv_device(drm->device)->card_type < NV_D0)
296 gen = 1; 312 gen = 1;
297 else 313 else
298 gen = 2; 314 gen = 2;
@@ -326,11 +342,11 @@ nouveau_display_create(struct drm_device *dev)
326 342
327 dev->mode_config.min_width = 0; 343 dev->mode_config.min_width = 0;
328 dev->mode_config.min_height = 0; 344 dev->mode_config.min_height = 0;
329 if (dev_priv->card_type < NV_10) { 345 if (nv_device(drm->device)->card_type < NV_10) {
330 dev->mode_config.max_width = 2048; 346 dev->mode_config.max_width = 2048;
331 dev->mode_config.max_height = 2048; 347 dev->mode_config.max_height = 2048;
332 } else 348 } else
333 if (dev_priv->card_type < NV_50) { 349 if (nv_device(drm->device)->card_type < NV_50) {
334 dev->mode_config.max_width = 4096; 350 dev->mode_config.max_width = 4096;
335 dev->mode_config.max_height = 4096; 351 dev->mode_config.max_height = 4096;
336 } else { 352 } else {
@@ -344,7 +360,13 @@ nouveau_display_create(struct drm_device *dev)
344 drm_kms_helper_poll_init(dev); 360 drm_kms_helper_poll_init(dev);
345 drm_kms_helper_poll_disable(dev); 361 drm_kms_helper_poll_disable(dev);
346 362
347 ret = disp->create(dev); 363 if (nv_device(drm->device)->card_type < NV_50)
364 ret = nv04_display_create(dev);
365 else
366 if (nv_device(drm->device)->card_type < NV_D0)
367 ret = nv50_display_create(dev);
368 else
369 ret = nvd0_display_create(dev);
348 if (ret) 370 if (ret)
349 goto disp_create_err; 371 goto disp_create_err;
350 372
@@ -354,10 +376,11 @@ nouveau_display_create(struct drm_device *dev)
354 goto vblank_err; 376 goto vblank_err;
355 } 377 }
356 378
379 nouveau_backlight_init(dev);
357 return 0; 380 return 0;
358 381
359vblank_err: 382vblank_err:
360 disp->destroy(dev); 383 disp->dtor(dev);
361disp_create_err: 384disp_create_err:
362 drm_kms_helper_poll_fini(dev); 385 drm_kms_helper_poll_fini(dev);
363 drm_mode_config_cleanup(dev); 386 drm_mode_config_cleanup(dev);
@@ -367,28 +390,109 @@ disp_create_err:
367void 390void
368nouveau_display_destroy(struct drm_device *dev) 391nouveau_display_destroy(struct drm_device *dev)
369{ 392{
370 struct drm_nouveau_private *dev_priv = dev->dev_private; 393 struct nouveau_display *disp = nouveau_display(dev);
371 struct nouveau_display_engine *disp = &dev_priv->engine.display;
372 394
395 nouveau_backlight_exit(dev);
373 drm_vblank_cleanup(dev); 396 drm_vblank_cleanup(dev);
374 397
375 disp->destroy(dev); 398 disp->dtor(dev);
376 399
377 drm_kms_helper_poll_fini(dev); 400 drm_kms_helper_poll_fini(dev);
378 drm_mode_config_cleanup(dev); 401 drm_mode_config_cleanup(dev);
402 nouveau_drm(dev)->display = NULL;
403 kfree(disp);
404}
405
406int
407nouveau_display_suspend(struct drm_device *dev)
408{
409 struct nouveau_drm *drm = nouveau_drm(dev);
410 struct drm_crtc *crtc;
411
412 nouveau_display_fini(dev);
413
414 NV_INFO(drm, "unpinning framebuffer(s)...\n");
415 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
416 struct nouveau_framebuffer *nouveau_fb;
417
418 nouveau_fb = nouveau_framebuffer(crtc->fb);
419 if (!nouveau_fb || !nouveau_fb->nvbo)
420 continue;
421
422 nouveau_bo_unpin(nouveau_fb->nvbo);
423 }
424
425 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
426 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
427
428 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
429 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
430 }
431
432 return 0;
433}
434
435void
436nouveau_display_resume(struct drm_device *dev)
437{
438 struct nouveau_drm *drm = nouveau_drm(dev);
439 struct drm_crtc *crtc;
440 int ret;
441
442 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
443 struct nouveau_framebuffer *nouveau_fb;
444
445 nouveau_fb = nouveau_framebuffer(crtc->fb);
446 if (!nouveau_fb || !nouveau_fb->nvbo)
447 continue;
448
449 nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
450 }
451
452 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
453 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
454
455 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
456 if (!ret)
457 ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
458 if (ret)
459 NV_ERROR(drm, "Could not pin/map cursor.\n");
460 }
461
462 nouveau_fbcon_set_suspend(dev, 0);
463 nouveau_fbcon_zfill_all(dev);
464
465 nouveau_display_init(dev);
466
467 /* Force CLUT to get re-loaded during modeset */
468 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
469 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
470
471 nv_crtc->lut.depth = 0;
472 }
473
474 drm_helper_resume_force_mode(dev);
475
476 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
477 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
478 u32 offset = nv_crtc->cursor.nvbo->bo.offset;
479
480 nv_crtc->cursor.set_offset(nv_crtc, offset);
481 nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
482 nv_crtc->cursor_saved_y);
483 }
379} 484}
380 485
381int 486int
382nouveau_vblank_enable(struct drm_device *dev, int crtc) 487nouveau_vblank_enable(struct drm_device *dev, int crtc)
383{ 488{
384 struct drm_nouveau_private *dev_priv = dev->dev_private; 489 struct nouveau_device *device = nouveau_dev(dev);
385 490
386 if (dev_priv->card_type >= NV_D0) 491 if (device->card_type >= NV_D0)
387 nv_mask(dev, 0x6100c0 + (crtc * 0x800), 1, 1); 492 nv_mask(device, 0x6100c0 + (crtc * 0x800), 1, 1);
388 else 493 else
389 494 if (device->card_type >= NV_50)
390 if (dev_priv->card_type >= NV_50) 495 nv_mask(device, NV50_PDISPLAY_INTR_EN_1, 0,
391 nv_mask(dev, NV50_PDISPLAY_INTR_EN_1, 0,
392 NV50_PDISPLAY_INTR_EN_1_VBLANK_CRTC_(crtc)); 496 NV50_PDISPLAY_INTR_EN_1_VBLANK_CRTC_(crtc));
393 else 497 else
394 NVWriteCRTC(dev, crtc, NV_PCRTC_INTR_EN_0, 498 NVWriteCRTC(dev, crtc, NV_PCRTC_INTR_EN_0,
@@ -400,13 +504,13 @@ nouveau_vblank_enable(struct drm_device *dev, int crtc)
400void 504void
401nouveau_vblank_disable(struct drm_device *dev, int crtc) 505nouveau_vblank_disable(struct drm_device *dev, int crtc)
402{ 506{
403 struct drm_nouveau_private *dev_priv = dev->dev_private; 507 struct nouveau_device *device = nouveau_dev(dev);
404 508
405 if (dev_priv->card_type >= NV_D0) 509 if (device->card_type >= NV_D0)
406 nv_mask(dev, 0x6100c0 + (crtc * 0x800), 1, 0); 510 nv_mask(device, 0x6100c0 + (crtc * 0x800), 1, 0);
407 else 511 else
408 if (dev_priv->card_type >= NV_50) 512 if (device->card_type >= NV_50)
409 nv_mask(dev, NV50_PDISPLAY_INTR_EN_1, 513 nv_mask(device, NV50_PDISPLAY_INTR_EN_1,
410 NV50_PDISPLAY_INTR_EN_1_VBLANK_CRTC_(crtc), 0); 514 NV50_PDISPLAY_INTR_EN_1_VBLANK_CRTC_(crtc), 0);
411 else 515 else
412 NVWriteCRTC(dev, crtc, NV_PCRTC_INTR_EN_0, 0); 516 NVWriteCRTC(dev, crtc, NV_PCRTC_INTR_EN_0, 0);
@@ -461,8 +565,8 @@ nouveau_page_flip_emit(struct nouveau_channel *chan,
461 struct nouveau_fence **pfence) 565 struct nouveau_fence **pfence)
462{ 566{
463 struct nouveau_fence_chan *fctx = chan->fence; 567 struct nouveau_fence_chan *fctx = chan->fence;
464 struct drm_device *dev = nouveau_drv(chan->drm); 568 struct nouveau_drm *drm = chan->drm;
465 struct drm_nouveau_private *dev_priv = dev->dev_private; 569 struct drm_device *dev = drm->dev;
466 unsigned long flags; 570 unsigned long flags;
467 int ret; 571 int ret;
468 572
@@ -481,7 +585,7 @@ nouveau_page_flip_emit(struct nouveau_channel *chan,
481 if (ret) 585 if (ret)
482 goto fail; 586 goto fail;
483 587
484 if (dev_priv->card_type < NV_C0) { 588 if (nv_device(drm->device)->card_type < NV_C0) {
485 BEGIN_NV04(chan, NvSubSw, NV_SW_PAGE_FLIP, 1); 589 BEGIN_NV04(chan, NvSubSw, NV_SW_PAGE_FLIP, 1);
486 OUT_RING (chan, 0x00000000); 590 OUT_RING (chan, 0x00000000);
487 OUT_RING (chan, 0x00000000); 591 OUT_RING (chan, 0x00000000);
@@ -509,7 +613,7 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
509 struct drm_pending_vblank_event *event) 613 struct drm_pending_vblank_event *event)
510{ 614{
511 struct drm_device *dev = crtc->dev; 615 struct drm_device *dev = crtc->dev;
512 struct drm_nouveau_private *dev_priv = dev->dev_private; 616 struct nouveau_drm *drm = nouveau_drm(dev);
513 struct nouveau_bo *old_bo = nouveau_framebuffer(crtc->fb)->nvbo; 617 struct nouveau_bo *old_bo = nouveau_framebuffer(crtc->fb)->nvbo;
514 struct nouveau_bo *new_bo = nouveau_framebuffer(fb)->nvbo; 618 struct nouveau_bo *new_bo = nouveau_framebuffer(fb)->nvbo;
515 struct nouveau_page_flip_state *s; 619 struct nouveau_page_flip_state *s;
@@ -517,7 +621,7 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
517 struct nouveau_fence *fence; 621 struct nouveau_fence *fence;
518 int ret; 622 int ret;
519 623
520 if (!nvdrm_channel(dev)) 624 if (!drm->channel)
521 return -ENODEV; 625 return -ENODEV;
522 626
523 s = kzalloc(sizeof(*s), GFP_KERNEL); 627 s = kzalloc(sizeof(*s), GFP_KERNEL);
@@ -540,23 +644,23 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
540 if (fence) 644 if (fence)
541 chan = fence->channel; 645 chan = fence->channel;
542 if (!chan) 646 if (!chan)
543 chan = nvdrm_channel(dev); 647 chan = drm->channel;
544 mutex_lock(nvchan_mutex(chan)); 648 mutex_lock(&chan->cli->mutex);
545 649
546 /* Emit a page flip */ 650 /* Emit a page flip */
547 if (dev_priv->card_type >= NV_50) { 651 if (nv_device(drm->device)->card_type >= NV_50) {
548 if (dev_priv->card_type >= NV_D0) 652 if (nv_device(drm->device)->card_type >= NV_D0)
549 ret = nvd0_display_flip_next(crtc, fb, chan, 0); 653 ret = nvd0_display_flip_next(crtc, fb, chan, 0);
550 else 654 else
551 ret = nv50_display_flip_next(crtc, fb, chan); 655 ret = nv50_display_flip_next(crtc, fb, chan);
552 if (ret) { 656 if (ret) {
553 mutex_unlock(nvchan_mutex(chan)); 657 mutex_unlock(&chan->cli->mutex);
554 goto fail_unreserve; 658 goto fail_unreserve;
555 } 659 }
556 } 660 }
557 661
558 ret = nouveau_page_flip_emit(chan, old_bo, new_bo, s, &fence); 662 ret = nouveau_page_flip_emit(chan, old_bo, new_bo, s, &fence);
559 mutex_unlock(nvchan_mutex(chan)); 663 mutex_unlock(&chan->cli->mutex);
560 if (ret) 664 if (ret)
561 goto fail_unreserve; 665 goto fail_unreserve;
562 666
@@ -579,14 +683,15 @@ nouveau_finish_page_flip(struct nouveau_channel *chan,
579 struct nouveau_page_flip_state *ps) 683 struct nouveau_page_flip_state *ps)
580{ 684{
581 struct nouveau_fence_chan *fctx = chan->fence; 685 struct nouveau_fence_chan *fctx = chan->fence;
582 struct drm_device *dev = nouveau_drv(chan->drm); 686 struct nouveau_drm *drm = chan->drm;
687 struct drm_device *dev = drm->dev;
583 struct nouveau_page_flip_state *s; 688 struct nouveau_page_flip_state *s;
584 unsigned long flags; 689 unsigned long flags;
585 690
586 spin_lock_irqsave(&dev->event_lock, flags); 691 spin_lock_irqsave(&dev->event_lock, flags);
587 692
588 if (list_empty(&fctx->flip)) { 693 if (list_empty(&fctx->flip)) {
589 NV_ERROR(dev, "unexpected pageflip\n"); 694 NV_ERROR(drm, "unexpected pageflip\n");
590 spin_unlock_irqrestore(&dev->event_lock, flags); 695 spin_unlock_irqrestore(&dev->event_lock, flags);
591 return -EINVAL; 696 return -EINVAL;
592 } 697 }
@@ -617,13 +722,12 @@ int
617nouveau_flip_complete(void *data) 722nouveau_flip_complete(void *data)
618{ 723{
619 struct nouveau_channel *chan = data; 724 struct nouveau_channel *chan = data;
620 struct drm_device *dev = nouveau_drv(chan->drm); 725 struct nouveau_drm *drm = chan->drm;
621 struct drm_nouveau_private *dev_priv = dev->dev_private;
622 struct nouveau_page_flip_state state; 726 struct nouveau_page_flip_state state;
623 727
624 if (!nouveau_finish_page_flip(chan, &state)) { 728 if (!nouveau_finish_page_flip(chan, &state)) {
625 if (dev_priv->card_type < NV_50) { 729 if (nv_device(drm->device)->card_type < NV_50) {
626 nv_set_crtc_base(dev, state.crtc, state.offset + 730 nv_set_crtc_base(drm->dev, state.crtc, state.offset +
627 state.y * state.pitch + 731 state.y * state.pitch +
628 state.x * state.bpp / 8); 732 state.x * state.bpp / 8);
629 } 733 }
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.h b/drivers/gpu/drm/nouveau/nouveau_display.h
new file mode 100644
index 000000000000..722548bb3bd3
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_display.h
@@ -0,0 +1,94 @@
1#ifndef __NOUVEAU_DISPLAY_H__
2#define __NOUVEAU_DISPLAY_H__
3
4#include <subdev/vm.h>
5
6#include "nouveau_drm.h"
7
8struct nouveau_framebuffer {
9 struct drm_framebuffer base;
10 struct nouveau_bo *nvbo;
11 struct nouveau_vma vma;
12 u32 r_dma;
13 u32 r_format;
14 u32 r_pitch;
15};
16
17static inline struct nouveau_framebuffer *
18nouveau_framebuffer(struct drm_framebuffer *fb)
19{
20 return container_of(fb, struct nouveau_framebuffer, base);
21}
22
23int nouveau_framebuffer_init(struct drm_device *, struct nouveau_framebuffer *,
24 struct drm_mode_fb_cmd2 *, struct nouveau_bo *);
25
26struct nouveau_page_flip_state {
27 struct list_head head;
28 struct drm_pending_vblank_event *event;
29 int crtc, bpp, pitch, x, y;
30 u64 offset;
31};
32
33struct nouveau_display {
34 void *priv;
35 void (*dtor)(struct drm_device *);
36 int (*init)(struct drm_device *);
37 void (*fini)(struct drm_device *);
38
39 struct drm_property *dithering_mode;
40 struct drm_property *dithering_depth;
41 struct drm_property *underscan_property;
42 struct drm_property *underscan_hborder_property;
43 struct drm_property *underscan_vborder_property;
44 /* not really hue and saturation: */
45 struct drm_property *vibrant_hue_property;
46 struct drm_property *color_vibrance_property;
47};
48
49static inline struct nouveau_display *
50nouveau_display(struct drm_device *dev)
51{
52 return nouveau_drm(dev)->display;
53}
54
55int nouveau_display_create(struct drm_device *dev);
56void nouveau_display_destroy(struct drm_device *dev);
57int nouveau_display_init(struct drm_device *dev);
58void nouveau_display_fini(struct drm_device *dev);
59int nouveau_display_suspend(struct drm_device *dev);
60void nouveau_display_resume(struct drm_device *dev);
61
62int nouveau_vblank_enable(struct drm_device *dev, int crtc);
63void nouveau_vblank_disable(struct drm_device *dev, int crtc);
64
65int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
66 struct drm_pending_vblank_event *event);
67int nouveau_finish_page_flip(struct nouveau_channel *,
68 struct nouveau_page_flip_state *);
69
70int nouveau_display_dumb_create(struct drm_file *, struct drm_device *,
71 struct drm_mode_create_dumb *args);
72int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *,
73 u32 handle, u64 *offset);
74int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *,
75 u32 handle);
76
77void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *);
78
79#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
80extern int nouveau_backlight_init(struct drm_device *);
81extern void nouveau_backlight_exit(struct drm_device *);
82#else
83static inline int
84nouveau_backlight_init(struct drm_device *dev)
85{
86 return 0;
87}
88
89static inline void
90nouveau_backlight_exit(struct drm_device *dev) {
91}
92#endif
93
94#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c
index 6fe11f8c5f6c..78e54cb8dfbe 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dp.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dp.c
@@ -25,31 +25,35 @@
25#include "drmP.h" 25#include "drmP.h"
26#include "drm_dp_helper.h" 26#include "drm_dp_helper.h"
27 27
28#include "nouveau_drv.h" 28#include "nouveau_drm.h"
29#include "nouveau_connector.h" 29#include "nouveau_connector.h"
30#include "nouveau_encoder.h" 30#include "nouveau_encoder.h"
31#include "nouveau_crtc.h" 31#include "nouveau_crtc.h"
32 32
33#include <subdev/gpio.h>
34#include <subdev/i2c.h>
35
33u8 * 36u8 *
34nouveau_dp_bios_data(struct drm_device *dev, struct dcb_output *dcb, u8 **entry) 37nouveau_dp_bios_data(struct drm_device *dev, struct dcb_output *dcb, u8 **entry)
35{ 38{
39 struct nouveau_drm *drm = nouveau_drm(dev);
36 struct bit_entry d; 40 struct bit_entry d;
37 u8 *table; 41 u8 *table;
38 int i; 42 int i;
39 43
40 if (bit_table(dev, 'd', &d)) { 44 if (bit_table(dev, 'd', &d)) {
41 NV_ERROR(dev, "BIT 'd' table not found\n"); 45 NV_ERROR(drm, "BIT 'd' table not found\n");
42 return NULL; 46 return NULL;
43 } 47 }
44 48
45 if (d.version != 1) { 49 if (d.version != 1) {
46 NV_ERROR(dev, "BIT 'd' table version %d unknown\n", d.version); 50 NV_ERROR(drm, "BIT 'd' table version %d unknown\n", d.version);
47 return NULL; 51 return NULL;
48 } 52 }
49 53
50 table = ROMPTR(dev, d.data[0]); 54 table = ROMPTR(dev, d.data[0]);
51 if (!table) { 55 if (!table) {
52 NV_ERROR(dev, "displayport table pointer invalid\n"); 56 NV_ERROR(drm, "displayport table pointer invalid\n");
53 return NULL; 57 return NULL;
54 } 58 }
55 59
@@ -60,7 +64,7 @@ nouveau_dp_bios_data(struct drm_device *dev, struct dcb_output *dcb, u8 **entry)
60 case 0x40: 64 case 0x40:
61 break; 65 break;
62 default: 66 default:
63 NV_ERROR(dev, "displayport table 0x%02x unknown\n", table[0]); 67 NV_ERROR(drm, "displayport table 0x%02x unknown\n", table[0]);
64 return NULL; 68 return NULL;
65 } 69 }
66 70
@@ -70,7 +74,7 @@ nouveau_dp_bios_data(struct drm_device *dev, struct dcb_output *dcb, u8 **entry)
70 return table; 74 return table;
71 } 75 }
72 76
73 NV_ERROR(dev, "displayport encoder table not found\n"); 77 NV_ERROR(drm, "displayport encoder table not found\n");
74 return NULL; 78 return NULL;
75} 79}
76 80
@@ -92,9 +96,10 @@ struct dp_state {
92static void 96static void
93dp_set_link_config(struct drm_device *dev, struct dp_state *dp) 97dp_set_link_config(struct drm_device *dev, struct dp_state *dp)
94{ 98{
99 struct nouveau_drm *drm = nouveau_drm(dev);
95 u8 sink[2]; 100 u8 sink[2];
96 101
97 NV_DEBUG_KMS(dev, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw); 102 NV_DEBUG(drm, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
98 103
99 /* set desired link configuration on the source */ 104 /* set desired link configuration on the source */
100 dp->func->link_set(dev, dp->dcb, dp->crtc, dp->link_nr, dp->link_bw, 105 dp->func->link_set(dev, dp->dcb, dp->crtc, dp->link_nr, dp->link_bw,
@@ -106,27 +111,29 @@ dp_set_link_config(struct drm_device *dev, struct dp_state *dp)
106 if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP) 111 if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)
107 sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 112 sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
108 113
109 auxch_wr(dev, dp->auxch, DP_LINK_BW_SET, sink, 2); 114 nv_wraux(dp->auxch, DP_LINK_BW_SET, sink, 2);
110} 115}
111 116
112static void 117static void
113dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 pattern) 118dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 pattern)
114{ 119{
120 struct nouveau_drm *drm = nouveau_drm(dev);
115 u8 sink_tp; 121 u8 sink_tp;
116 122
117 NV_DEBUG_KMS(dev, "training pattern %d\n", pattern); 123 NV_DEBUG(drm, "training pattern %d\n", pattern);
118 124
119 dp->func->train_set(dev, dp->dcb, pattern); 125 dp->func->train_set(dev, dp->dcb, pattern);
120 126
121 auxch_rd(dev, dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1); 127 nv_rdaux(dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
122 sink_tp &= ~DP_TRAINING_PATTERN_MASK; 128 sink_tp &= ~DP_TRAINING_PATTERN_MASK;
123 sink_tp |= pattern; 129 sink_tp |= pattern;
124 auxch_wr(dev, dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1); 130 nv_wraux(dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
125} 131}
126 132
127static int 133static int
128dp_link_train_commit(struct drm_device *dev, struct dp_state *dp) 134dp_link_train_commit(struct drm_device *dev, struct dp_state *dp)
129{ 135{
136 struct nouveau_drm *drm = nouveau_drm(dev);
130 int i; 137 int i;
131 138
132 for (i = 0; i < dp->link_nr; i++) { 139 for (i = 0; i < dp->link_nr; i++) {
@@ -140,25 +147,26 @@ dp_link_train_commit(struct drm_device *dev, struct dp_state *dp)
140 if ((lpre << 3) == DP_TRAIN_PRE_EMPHASIS_9_5) 147 if ((lpre << 3) == DP_TRAIN_PRE_EMPHASIS_9_5)
141 dp->conf[i] |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 148 dp->conf[i] |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
142 149
143 NV_DEBUG_KMS(dev, "config lane %d %02x\n", i, dp->conf[i]); 150 NV_DEBUG(drm, "config lane %d %02x\n", i, dp->conf[i]);
144 dp->func->train_adj(dev, dp->dcb, i, lvsw, lpre); 151 dp->func->train_adj(dev, dp->dcb, i, lvsw, lpre);
145 } 152 }
146 153
147 return auxch_wr(dev, dp->auxch, DP_TRAINING_LANE0_SET, dp->conf, 4); 154 return nv_wraux(dp->auxch, DP_TRAINING_LANE0_SET, dp->conf, 4);
148} 155}
149 156
150static int 157static int
151dp_link_train_update(struct drm_device *dev, struct dp_state *dp, u32 delay) 158dp_link_train_update(struct drm_device *dev, struct dp_state *dp, u32 delay)
152{ 159{
160 struct nouveau_drm *drm = nouveau_drm(dev);
153 int ret; 161 int ret;
154 162
155 udelay(delay); 163 udelay(delay);
156 164
157 ret = auxch_rd(dev, dp->auxch, DP_LANE0_1_STATUS, dp->stat, 6); 165 ret = nv_rdaux(dp->auxch, DP_LANE0_1_STATUS, dp->stat, 6);
158 if (ret) 166 if (ret)
159 return ret; 167 return ret;
160 168
161 NV_DEBUG_KMS(dev, "status %02x %02x %02x %02x %02x %02x\n", 169 NV_DEBUG(drm, "status %02x %02x %02x %02x %02x %02x\n",
162 dp->stat[0], dp->stat[1], dp->stat[2], dp->stat[3], 170 dp->stat[0], dp->stat[1], dp->stat[2], dp->stat[3],
163 dp->stat[4], dp->stat[5]); 171 dp->stat[4], dp->stat[5]);
164 return 0; 172 return 0;
@@ -287,11 +295,14 @@ nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate,
287 struct nouveau_connector *nv_connector = 295 struct nouveau_connector *nv_connector =
288 nouveau_encoder_connector_get(nv_encoder); 296 nouveau_encoder_connector_get(nv_encoder);
289 struct drm_device *dev = encoder->dev; 297 struct drm_device *dev = encoder->dev;
298 struct nouveau_drm *drm = nouveau_drm(dev);
299 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
300 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
290 const u32 bw_list[] = { 270000, 162000, 0 }; 301 const u32 bw_list[] = { 270000, 162000, 0 };
291 const u32 *link_bw = bw_list; 302 const u32 *link_bw = bw_list;
292 struct dp_state dp; 303 struct dp_state dp;
293 304
294 dp.auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index); 305 dp.auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
295 if (!dp.auxch) 306 if (!dp.auxch)
296 return false; 307 return false;
297 308
@@ -307,7 +318,7 @@ nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate,
307 * we take during link training (DP_SET_POWER is one), we need 318 * we take during link training (DP_SET_POWER is one), we need
308 * to ignore them for the moment to avoid races. 319 * to ignore them for the moment to avoid races.
309 */ 320 */
310 nouveau_gpio_irq(dev, 0, nv_connector->hpd, 0xff, false); 321 gpio->irq(gpio, 0, nv_connector->hpd, 0xff, false);
311 322
312 /* enable down-spreading, if possible */ 323 /* enable down-spreading, if possible */
313 dp_set_downspread(dev, &dp, nv_encoder->dp.dpcd[3] & 1); 324 dp_set_downspread(dev, &dp, nv_encoder->dp.dpcd[3] & 1);
@@ -350,7 +361,7 @@ nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate,
350 dp_link_train_fini(dev, &dp); 361 dp_link_train_fini(dev, &dp);
351 362
352 /* re-enable hotplug detect */ 363 /* re-enable hotplug detect */
353 nouveau_gpio_irq(dev, 0, nv_connector->hpd, 0xff, true); 364 gpio->irq(gpio, 0, nv_connector->hpd, 0xff, true);
354 return true; 365 return true;
355} 366}
356 367
@@ -359,10 +370,12 @@ nouveau_dp_dpms(struct drm_encoder *encoder, int mode, u32 datarate,
359 struct dp_train_func *func) 370 struct dp_train_func *func)
360{ 371{
361 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 372 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
373 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
374 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
362 struct nouveau_i2c_port *auxch; 375 struct nouveau_i2c_port *auxch;
363 u8 status; 376 u8 status;
364 377
365 auxch = nouveau_i2c_find(encoder->dev, nv_encoder->dcb->i2c_index); 378 auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
366 if (!auxch) 379 if (!auxch)
367 return; 380 return;
368 381
@@ -371,7 +384,7 @@ nouveau_dp_dpms(struct drm_encoder *encoder, int mode, u32 datarate,
371 else 384 else
372 status = DP_SET_POWER_D3; 385 status = DP_SET_POWER_D3;
373 386
374 auxch_wr(encoder->dev, auxch, DP_SET_POWER, &status, 1); 387 nv_wraux(auxch, DP_SET_POWER, &status, 1);
375 388
376 if (mode == DRM_MODE_DPMS_ON) 389 if (mode == DRM_MODE_DPMS_ON)
377 nouveau_dp_link_train(encoder, datarate, func); 390 nouveau_dp_link_train(encoder, datarate, func);
@@ -381,17 +394,18 @@ static void
381nouveau_dp_probe_oui(struct drm_device *dev, struct nouveau_i2c_port *auxch, 394nouveau_dp_probe_oui(struct drm_device *dev, struct nouveau_i2c_port *auxch,
382 u8 *dpcd) 395 u8 *dpcd)
383{ 396{
397 struct nouveau_drm *drm = nouveau_drm(dev);
384 u8 buf[3]; 398 u8 buf[3];
385 399
386 if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 400 if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
387 return; 401 return;
388 402
389 if (!auxch_rd(dev, auxch, DP_SINK_OUI, buf, 3)) 403 if (!nv_rdaux(auxch, DP_SINK_OUI, buf, 3))
390 NV_DEBUG_KMS(dev, "Sink OUI: %02hx%02hx%02hx\n", 404 NV_DEBUG(drm, "Sink OUI: %02hx%02hx%02hx\n",
391 buf[0], buf[1], buf[2]); 405 buf[0], buf[1], buf[2]);
392 406
393 if (!auxch_rd(dev, auxch, DP_BRANCH_OUI, buf, 3)) 407 if (!nv_rdaux(auxch, DP_BRANCH_OUI, buf, 3))
394 NV_DEBUG_KMS(dev, "Branch OUI: %02hx%02hx%02hx\n", 408 NV_DEBUG(drm, "Branch OUI: %02hx%02hx%02hx\n",
395 buf[0], buf[1], buf[2]); 409 buf[0], buf[1], buf[2]);
396 410
397} 411}
@@ -401,24 +415,26 @@ nouveau_dp_detect(struct drm_encoder *encoder)
401{ 415{
402 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 416 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
403 struct drm_device *dev = encoder->dev; 417 struct drm_device *dev = encoder->dev;
418 struct nouveau_drm *drm = nouveau_drm(dev);
419 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
404 struct nouveau_i2c_port *auxch; 420 struct nouveau_i2c_port *auxch;
405 u8 *dpcd = nv_encoder->dp.dpcd; 421 u8 *dpcd = nv_encoder->dp.dpcd;
406 int ret; 422 int ret;
407 423
408 auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index); 424 auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
409 if (!auxch) 425 if (!auxch)
410 return false; 426 return false;
411 427
412 ret = auxch_rd(dev, auxch, DP_DPCD_REV, dpcd, 8); 428 ret = nv_rdaux(auxch, DP_DPCD_REV, dpcd, 8);
413 if (ret) 429 if (ret)
414 return false; 430 return false;
415 431
416 nv_encoder->dp.link_bw = 27000 * dpcd[1]; 432 nv_encoder->dp.link_bw = 27000 * dpcd[1];
417 nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK; 433 nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
418 434
419 NV_DEBUG_KMS(dev, "display: %dx%d dpcd 0x%02x\n", 435 NV_DEBUG(drm, "display: %dx%d dpcd 0x%02x\n",
420 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]); 436 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
421 NV_DEBUG_KMS(dev, "encoder: %dx%d\n", 437 NV_DEBUG(drm, "encoder: %dx%d\n",
422 nv_encoder->dcb->dpconf.link_nr, 438 nv_encoder->dcb->dpconf.link_nr,
423 nv_encoder->dcb->dpconf.link_bw); 439 nv_encoder->dcb->dpconf.link_bw);
424 440
@@ -427,7 +443,7 @@ nouveau_dp_detect(struct drm_encoder *encoder)
427 if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw) 443 if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw)
428 nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw; 444 nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw;
429 445
430 NV_DEBUG_KMS(dev, "maximum: %dx%d\n", 446 NV_DEBUG(drm, "maximum: %dx%d\n",
431 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw); 447 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);
432 448
433 nouveau_dp_probe_oui(dev, auxch, dpcd); 449 nouveau_dp_probe_oui(dev, auxch, dpcd);
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index 92ecf50a39d3..8b508cec65a2 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -22,6 +22,7 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24 24
25#include <linux/console.h>
25#include <linux/module.h> 26#include <linux/module.h>
26#include <linux/pci.h> 27#include <linux/pci.h>
27 28
@@ -34,24 +35,22 @@
34#include <subdev/vm.h> 35#include <subdev/vm.h>
35 36
36#include "nouveau_drm.h" 37#include "nouveau_drm.h"
38#include "nouveau_irq.h"
37#include "nouveau_dma.h" 39#include "nouveau_dma.h"
40#include "nouveau_ttm.h"
41#include "nouveau_gem.h"
38#include "nouveau_agp.h" 42#include "nouveau_agp.h"
43#include "nouveau_vga.h"
44#include "nouveau_pm.h"
45#include "nouveau_acpi.h"
46#include "nouveau_bios.h"
47#include "nouveau_ioctl.h"
39#include "nouveau_abi16.h" 48#include "nouveau_abi16.h"
40#include "nouveau_fbcon.h" 49#include "nouveau_fbcon.h"
41#include "nouveau_fence.h" 50#include "nouveau_fence.h"
42 51
43#include "nouveau_ttm.h" 52#include "nouveau_ttm.h"
44 53
45int __devinit nouveau_pci_probe(struct pci_dev *, const struct pci_device_id *);
46void nouveau_pci_remove(struct pci_dev *);
47int nouveau_pci_suspend(struct pci_dev *, pm_message_t);
48int nouveau_pci_resume(struct pci_dev *);
49int __init nouveau_init(struct pci_driver *);
50void __exit nouveau_exit(struct pci_driver *);
51
52int nouveau_load(struct drm_device *, unsigned long);
53int nouveau_unload(struct drm_device *);
54
55MODULE_PARM_DESC(config, "option string to pass to driver core"); 54MODULE_PARM_DESC(config, "option string to pass to driver core");
56static char *nouveau_config; 55static char *nouveau_config;
57module_param_named(config, nouveau_config, charp, 0400); 56module_param_named(config, nouveau_config, charp, 0400);
@@ -64,6 +63,12 @@ MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
64static int nouveau_noaccel = 0; 63static int nouveau_noaccel = 0;
65module_param_named(noaccel, nouveau_noaccel, int, 0400); 64module_param_named(noaccel, nouveau_noaccel, int, 0400);
66 65
66MODULE_PARM_DESC(modeset, "enable driver");
67int nouveau_modeset = -1;
68module_param_named(modeset, nouveau_modeset, int, 0400);
69
70static struct drm_driver driver;
71
67static u64 72static u64
68nouveau_name(struct pci_dev *pdev) 73nouveau_name(struct pci_dev *pdev)
69{ 74{
@@ -206,7 +211,7 @@ nouveau_drm_probe(struct pci_dev *pdev, const struct pci_device_id *pent)
206 211
207 pci_set_master(pdev); 212 pci_set_master(pdev);
208 213
209 ret = nouveau_pci_probe(pdev, pent); 214 ret = drm_get_pci_dev(pdev, pent, &driver);
210 if (ret) { 215 if (ret) {
211 nouveau_object_ref(NULL, (struct nouveau_object **)&device); 216 nouveau_object_ref(NULL, (struct nouveau_object **)&device);
212 return ret; 217 return ret;
@@ -224,13 +229,14 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags)
224 int ret; 229 int ret;
225 230
226 ret = nouveau_cli_create(pdev, 0, sizeof(*drm), (void**)&drm); 231 ret = nouveau_cli_create(pdev, 0, sizeof(*drm), (void**)&drm);
227 dev->dev_private = drm;
228 if (ret) 232 if (ret)
229 return ret; 233 return ret;
230 234
235 dev->dev_private = drm;
236 drm->dev = dev;
237
231 INIT_LIST_HEAD(&drm->clients); 238 INIT_LIST_HEAD(&drm->clients);
232 spin_lock_init(&drm->tile.lock); 239 spin_lock_init(&drm->tile.lock);
233 drm->dev = dev;
234 240
235 /* make sure AGP controller is in a consistent state before we 241 /* make sure AGP controller is in a consistent state before we
236 * (possibly) execute vbios init tables (see nouveau_agp.h) 242 * (possibly) execute vbios init tables (see nouveau_agp.h)
@@ -266,9 +272,15 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags)
266 if (ret) 272 if (ret)
267 goto fail_device; 273 goto fail_device;
268 274
275 /* workaround an odd issue on nvc1 by disabling the device's
276 * nosnoop capability. hopefully won't cause issues until a
277 * better fix is found - assuming there is one...
278 */
269 device = nv_device(drm->device); 279 device = nv_device(drm->device);
280 if (nv_device(drm->device)->chipset == 0xc1)
281 nv_mask(device, 0x00088080, 0x00000800, 0x00000000);
270 282
271 /* initialise AGP */ 283 nouveau_vga_init(drm);
272 nouveau_agp_init(drm); 284 nouveau_agp_init(drm);
273 285
274 if (device->card_type >= NV_50) { 286 if (device->card_type >= NV_50) {
@@ -280,18 +292,43 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags)
280 292
281 ret = nouveau_ttm_init(drm); 293 ret = nouveau_ttm_init(drm);
282 if (ret) 294 if (ret)
283 goto fail_device; 295 goto fail_ttm;
296
297 ret = nouveau_bios_init(dev);
298 if (ret)
299 goto fail_bios;
300
301 ret = nouveau_irq_init(dev);
302 if (ret)
303 goto fail_irq;
284 304
285 ret = nouveau_load(dev, flags); 305 ret = nouveau_display_create(dev);
286 if (ret) 306 if (ret)
287 goto fail_load; 307 goto fail_dispctor;
308
309 if (dev->mode_config.num_crtc) {
310 ret = nouveau_display_init(dev);
311 if (ret)
312 goto fail_dispinit;
313 }
314
315 nouveau_pm_init(dev);
288 316
289 nouveau_accel_init(drm); 317 nouveau_accel_init(drm);
290 nouveau_fbcon_init(dev); 318 nouveau_fbcon_init(dev);
291 return 0; 319 return 0;
292 320
293fail_load: 321fail_dispinit:
322 nouveau_display_destroy(dev);
323fail_dispctor:
324 nouveau_irq_fini(dev);
325fail_irq:
326 nouveau_bios_takedown(dev);
327fail_bios:
294 nouveau_ttm_fini(drm); 328 nouveau_ttm_fini(drm);
329fail_ttm:
330 nouveau_agp_fini(drm);
331 nouveau_vga_fini(drm);
295fail_device: 332fail_device:
296 nouveau_cli_destroy(&drm->client); 333 nouveau_cli_destroy(&drm->client);
297 return ret; 334 return ret;
@@ -300,21 +337,23 @@ fail_device:
300int 337int
301nouveau_drm_unload(struct drm_device *dev) 338nouveau_drm_unload(struct drm_device *dev)
302{ 339{
303 struct nouveau_drm *drm = nouveau_newpriv(dev); 340 struct nouveau_drm *drm = nouveau_drm(dev);
304 struct pci_dev *pdev = dev->pdev;
305 int ret;
306 341
307 nouveau_fbcon_fini(dev); 342 nouveau_fbcon_fini(dev);
308 nouveau_accel_fini(drm); 343 nouveau_accel_fini(drm);
309 344
310 ret = nouveau_unload(dev); 345 nouveau_pm_fini(dev);
311 if (ret) 346
312 return ret; 347 nouveau_display_fini(dev);
348 nouveau_display_destroy(dev);
349
350 nouveau_irq_fini(dev);
351 nouveau_bios_takedown(dev);
313 352
314 nouveau_ttm_fini(drm); 353 nouveau_ttm_fini(drm);
315 nouveau_agp_fini(drm); 354 nouveau_agp_fini(drm);
355 nouveau_vga_fini(drm);
316 356
317 pci_set_drvdata(pdev, drm->client.base.device);
318 nouveau_cli_destroy(&drm->client); 357 nouveau_cli_destroy(&drm->client);
319 return 0; 358 return 0;
320} 359}
@@ -322,9 +361,13 @@ nouveau_drm_unload(struct drm_device *dev)
322static void 361static void
323nouveau_drm_remove(struct pci_dev *pdev) 362nouveau_drm_remove(struct pci_dev *pdev)
324{ 363{
364 struct drm_device *dev = pci_get_drvdata(pdev);
365 struct nouveau_drm *drm = nouveau_drm(dev);
325 struct nouveau_object *device; 366 struct nouveau_object *device;
326 nouveau_pci_remove(pdev); 367
327 device = pci_get_drvdata(pdev); 368 device = drm->client.base.device;
369 drm_put_dev(dev);
370
328 nouveau_object_ref(NULL, &device); 371 nouveau_object_ref(NULL, &device);
329 nouveau_object_debug(); 372 nouveau_object_debug();
330} 373}
@@ -333,7 +376,7 @@ int
333nouveau_drm_suspend(struct pci_dev *pdev, pm_message_t pm_state) 376nouveau_drm_suspend(struct pci_dev *pdev, pm_message_t pm_state)
334{ 377{
335 struct drm_device *dev = pci_get_drvdata(pdev); 378 struct drm_device *dev = pci_get_drvdata(pdev);
336 struct nouveau_drm *drm = nouveau_newpriv(dev); 379 struct nouveau_drm *drm = nouveau_drm(dev);
337 struct nouveau_cli *cli; 380 struct nouveau_cli *cli;
338 int ret; 381 int ret;
339 382
@@ -344,8 +387,8 @@ nouveau_drm_suspend(struct pci_dev *pdev, pm_message_t pm_state)
344 NV_INFO(drm, "suspending fbcon...\n"); 387 NV_INFO(drm, "suspending fbcon...\n");
345 nouveau_fbcon_set_suspend(dev, 1); 388 nouveau_fbcon_set_suspend(dev, 1);
346 389
347 NV_INFO(drm, "suspending drm...\n"); 390 NV_INFO(drm, "suspending display...\n");
348 ret = nouveau_pci_suspend(pdev, pm_state); 391 ret = nouveau_display_suspend(dev);
349 if (ret) 392 if (ret)
350 return ret; 393 return ret;
351 394
@@ -383,7 +426,8 @@ fail_client:
383 nouveau_client_init(&cli->base); 426 nouveau_client_init(&cli->base);
384 } 427 }
385 428
386 nouveau_pci_resume(pdev); 429 NV_INFO(drm, "resuming display...\n");
430 nouveau_display_resume(dev);
387 return ret; 431 return ret;
388} 432}
389 433
@@ -391,7 +435,7 @@ int
391nouveau_drm_resume(struct pci_dev *pdev) 435nouveau_drm_resume(struct pci_dev *pdev)
392{ 436{
393 struct drm_device *dev = pci_get_drvdata(pdev); 437 struct drm_device *dev = pci_get_drvdata(pdev);
394 struct nouveau_drm *drm = nouveau_newpriv(dev); 438 struct nouveau_drm *drm = nouveau_drm(dev);
395 struct nouveau_cli *cli; 439 struct nouveau_cli *cli;
396 int ret; 440 int ret;
397 441
@@ -419,7 +463,13 @@ nouveau_drm_resume(struct pci_dev *pdev)
419 if (drm->fence && nouveau_fence(drm)->resume) 463 if (drm->fence && nouveau_fence(drm)->resume)
420 nouveau_fence(drm)->resume(drm); 464 nouveau_fence(drm)->resume(drm);
421 465
422 return nouveau_pci_resume(pdev); 466 nouveau_run_vbios_init(dev);
467 nouveau_irq_postinstall(dev);
468 nouveau_pm_resume(dev);
469
470 NV_INFO(drm, "resuming display...\n");
471 nouveau_display_resume(dev);
472 return 0;
423} 473}
424 474
425int 475int
@@ -472,6 +522,90 @@ nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
472 nouveau_cli_destroy(cli); 522 nouveau_cli_destroy(cli);
473} 523}
474 524
525static struct drm_ioctl_desc
526nouveau_ioctls[] = {
527 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
528 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
529 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED|DRM_AUTH),
530 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED|DRM_AUTH),
531 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
532 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED|DRM_AUTH),
533 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
534 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
535 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
536 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
537 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
538 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
539};
540
541static const struct file_operations
542nouveau_driver_fops = {
543 .owner = THIS_MODULE,
544 .open = drm_open,
545 .release = drm_release,
546 .unlocked_ioctl = drm_ioctl,
547 .mmap = nouveau_ttm_mmap,
548 .poll = drm_poll,
549 .fasync = drm_fasync,
550 .read = drm_read,
551#if defined(CONFIG_COMPAT)
552 .compat_ioctl = nouveau_compat_ioctl,
553#endif
554 .llseek = noop_llseek,
555};
556
557static struct drm_driver
558driver = {
559 .driver_features =
560 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
561 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
562 DRIVER_MODESET | DRIVER_PRIME,
563
564 .load = nouveau_drm_load,
565 .unload = nouveau_drm_unload,
566 .open = nouveau_drm_open,
567 .preclose = nouveau_drm_preclose,
568 .postclose = nouveau_drm_postclose,
569 .lastclose = nouveau_vga_lastclose,
570
571 .irq_preinstall = nouveau_irq_preinstall,
572 .irq_postinstall = nouveau_irq_postinstall,
573 .irq_uninstall = nouveau_irq_uninstall,
574 .irq_handler = nouveau_irq_handler,
575
576 .get_vblank_counter = drm_vblank_count,
577 .enable_vblank = nouveau_vblank_enable,
578 .disable_vblank = nouveau_vblank_disable,
579
580 .ioctls = nouveau_ioctls,
581 .fops = &nouveau_driver_fops,
582
583 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
584 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
585 .gem_prime_export = nouveau_gem_prime_export,
586 .gem_prime_import = nouveau_gem_prime_import,
587
588 .gem_init_object = nouveau_gem_object_new,
589 .gem_free_object = nouveau_gem_object_del,
590 .gem_open_object = nouveau_gem_object_open,
591 .gem_close_object = nouveau_gem_object_close,
592
593 .dumb_create = nouveau_display_dumb_create,
594 .dumb_map_offset = nouveau_display_dumb_map_offset,
595 .dumb_destroy = nouveau_display_dumb_destroy,
596
597 .name = DRIVER_NAME,
598 .desc = DRIVER_DESC,
599#ifdef GIT_REVISION
600 .date = GIT_REVISION,
601#else
602 .date = DRIVER_DATE,
603#endif
604 .major = DRIVER_MAJOR,
605 .minor = DRIVER_MINOR,
606 .patchlevel = DRIVER_PATCHLEVEL,
607};
608
475static struct pci_device_id 609static struct pci_device_id
476nouveau_drm_pci_table[] = { 610nouveau_drm_pci_table[] = {
477 { 611 {
@@ -500,19 +634,38 @@ nouveau_drm_pci_driver = {
500static int __init 634static int __init
501nouveau_drm_init(void) 635nouveau_drm_init(void)
502{ 636{
503 return nouveau_init(&nouveau_drm_pci_driver); 637 driver.num_ioctls = ARRAY_SIZE(nouveau_ioctls);
638
639 if (nouveau_modeset == -1) {
640#ifdef CONFIG_VGA_CONSOLE
641 if (vgacon_text_force())
642 nouveau_modeset = 0;
643 else
644#endif
645 nouveau_modeset = 1;
646 }
647
648 if (!nouveau_modeset)
649 return 0;
650
651 nouveau_register_dsm_handler();
652 return drm_pci_init(&driver, &nouveau_drm_pci_driver);
504} 653}
505 654
506static void __exit 655static void __exit
507nouveau_drm_exit(void) 656nouveau_drm_exit(void)
508{ 657{
509 nouveau_exit(&nouveau_drm_pci_driver); 658 if (!nouveau_modeset)
659 return;
660
661 drm_pci_exit(&driver, &nouveau_drm_pci_driver);
662 nouveau_unregister_dsm_handler();
510} 663}
511 664
512module_init(nouveau_drm_init); 665module_init(nouveau_drm_init);
513module_exit(nouveau_drm_exit); 666module_exit(nouveau_drm_exit);
514 667
515MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table); 668MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
516MODULE_AUTHOR("Nouveau Project"); 669MODULE_AUTHOR(DRIVER_AUTHOR);
517MODULE_DESCRIPTION("nVidia Riva/TNT/GeForce/Quadro/Tesla"); 670MODULE_DESCRIPTION(DRIVER_DESC);
518MODULE_LICENSE("GPL and additional rights"); 671MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.h b/drivers/gpu/drm/nouveau/nouveau_drm.h
index d50352aa1a16..6abd1a15e742 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.h
@@ -1,6 +1,17 @@
1#ifndef __NOUVEAU_DRMCLI_H__ 1#ifndef __NOUVEAU_DRMCLI_H__
2#define __NOUVEAU_DRMCLI_H__ 2#define __NOUVEAU_DRMCLI_H__
3 3
4#define DRIVER_AUTHOR "Nouveau Project"
5#define DRIVER_EMAIL "nouveau@lists.freedesktop.org"
6
7#define DRIVER_NAME "nouveau"
8#define DRIVER_DESC "nVidia Riva/TNT/GeForce/Quadro/Tesla"
9#define DRIVER_DATE "20120801"
10
11#define DRIVER_MAJOR 1
12#define DRIVER_MINOR 1
13#define DRIVER_PATCHLEVEL 0
14
4#include <core/client.h> 15#include <core/client.h>
5 16
6#include <subdev/vm.h> 17#include <subdev/vm.h>
@@ -19,8 +30,8 @@ struct nouveau_channel;
19 30
20#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 31#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
21 32
22#include "nouveau_revcompat.h"
23#include "nouveau_fence.h" 33#include "nouveau_fence.h"
34#include "nouveau_bios.h"
24 35
25struct nouveau_drm_tile { 36struct nouveau_drm_tile {
26 struct nouveau_fence *fence; 37 struct nouveau_fence *fence;
@@ -96,13 +107,25 @@ struct nouveau_drm {
96 spinlock_t lock; 107 spinlock_t lock;
97 } tile; 108 } tile;
98 109
110 /* modesetting */
111 struct nvbios vbios;
112 struct nouveau_display *display;
99 struct backlight_device *backlight; 113 struct backlight_device *backlight;
114
115 /* power management */
116 struct nouveau_pm *pm;
100}; 117};
101 118
102static inline struct nouveau_drm * 119static inline struct nouveau_drm *
103nouveau_drm(struct drm_device *dev) 120nouveau_drm(struct drm_device *dev)
104{ 121{
105 return nouveau_newpriv(dev); 122 return dev->dev_private;
123}
124
125static inline struct nouveau_device *
126nouveau_dev(struct drm_device *dev)
127{
128 return nv_device(nouveau_drm(dev)->device);
106} 129}
107 130
108int nouveau_drm_suspend(struct pci_dev *, pm_message_t); 131int nouveau_drm_suspend(struct pci_dev *, pm_message_t);
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.c b/drivers/gpu/drm/nouveau/nouveau_drv.c
deleted file mode 100644
index 204772160a4e..000000000000
--- a/drivers/gpu/drm/nouveau/nouveau_drv.c
+++ /dev/null
@@ -1,353 +0,0 @@
1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#include <linux/console.h>
26#include <linux/module.h>
27
28#include "drmP.h"
29#include "drm.h"
30#include "drm_crtc_helper.h"
31#include "nouveau_drv.h"
32#include "nouveau_abi16.h"
33#include "nouveau_hw.h"
34#include "nouveau_fb.h"
35#include "nouveau_fbcon.h"
36#include "nouveau_fence.h"
37#include "nouveau_pm.h"
38#include "nv50_display.h"
39#include "nouveau_acpi.h"
40#include "nouveau_ioctl.h"
41
42#include "drm_pciids.h"
43
44MODULE_PARM_DESC(modeset, "Enable kernel modesetting");
45int nouveau_modeset = -1;
46module_param_named(modeset, nouveau_modeset, int, 0400);
47
48MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM");
49int nouveau_vram_notify = 0;
50module_param_named(vram_notify, nouveau_vram_notify, int, 0400);
51
52MODULE_PARM_DESC(vram_type, "Override detected VRAM type");
53char *nouveau_vram_type;
54module_param_named(vram_type, nouveau_vram_type, charp, 0400);
55
56MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)");
57int nouveau_duallink = 1;
58module_param_named(duallink, nouveau_duallink, int, 0400);
59
60MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)");
61int nouveau_uscript_lvds = -1;
62module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400);
63
64MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
65int nouveau_uscript_tmds = -1;
66module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
67
68MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
69int nouveau_ignorelid = 0;
70module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
71
72MODULE_PARM_DESC(force_post, "Force POST");
73int nouveau_force_post = 0;
74module_param_named(force_post, nouveau_force_post, int, 0400);
75
76MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type");
77int nouveau_override_conntype = 0;
78module_param_named(override_conntype, nouveau_override_conntype, int, 0400);
79
80MODULE_PARM_DESC(tv_disable, "Disable TV-out detection");
81int nouveau_tv_disable = 0;
82module_param_named(tv_disable, nouveau_tv_disable, int, 0400);
83
84MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
85 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
86 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
87 "\t\tDefault: PAL\n"
88 "\t\t*NOTE* Ignored for cards with external TV encoders.");
89char *nouveau_tv_norm;
90module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
91
92MODULE_PARM_DESC(perflvl, "Performance level (default: boot)");
93char *nouveau_perflvl;
94module_param_named(perflvl, nouveau_perflvl, charp, 0400);
95
96MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)");
97int nouveau_perflvl_wr;
98module_param_named(perflvl_wr, nouveau_perflvl_wr, int, 0400);
99
100MODULE_PARM_DESC(msi, "Enable MSI (default: off)");
101int nouveau_msi;
102module_param_named(msi, nouveau_msi, int, 0400);
103
104MODULE_PARM_DESC(ctxfw, "Use external HUB/GPC ucode (fermi)");
105int nouveau_ctxfw;
106module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
107
108MODULE_PARM_DESC(mxmdcb, "Santise DCB table according to MXM-SIS");
109int nouveau_mxmdcb = 1;
110module_param_named(mxmdcb, nouveau_mxmdcb, int, 0400);
111
112int nouveau_fbpercrtc;
113#if 0
114module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400);
115#endif
116
117static struct drm_driver driver;
118
119int __devinit
120nouveau_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
121{
122 return drm_get_pci_dev(pdev, ent, &driver);
123}
124
125void
126nouveau_pci_remove(struct pci_dev *pdev)
127{
128 struct drm_device *dev = pci_get_drvdata(pdev);
129
130 drm_put_dev(dev);
131}
132
133int
134nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
135{
136 struct drm_device *dev = pci_get_drvdata(pdev);
137 struct drm_crtc *crtc;
138
139 NV_INFO(dev, "Disabling display...\n");
140 nouveau_display_fini(dev);
141
142 NV_INFO(dev, "Unpinning framebuffer(s)...\n");
143 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
144 struct nouveau_framebuffer *nouveau_fb;
145
146 nouveau_fb = nouveau_framebuffer(crtc->fb);
147 if (!nouveau_fb || !nouveau_fb->nvbo)
148 continue;
149
150 nouveau_bo_unpin(nouveau_fb->nvbo);
151 }
152
153 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
154 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
155
156 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
157 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
158 }
159
160 return 0;
161}
162
163int
164nouveau_pci_resume(struct pci_dev *pdev)
165{
166 struct drm_device *dev = pci_get_drvdata(pdev);
167 struct drm_crtc *crtc;
168 int ret;
169
170 ret = nouveau_run_vbios_init(dev);
171 if (ret)
172 return ret;
173
174 nouveau_irq_postinstall(dev);
175
176#if 0
177 /* Re-write SKIPS, they'll have been lost over the suspend */
178 if (nouveau_vram_pushbuf) {
179 struct nouveau_channel *chan;
180 int j;
181
182 for (i = 0; i < (pfifo ? pfifo->channels : 0); i++) {
183 chan = dev_priv->channels.ptr[i];
184 if (!chan || !chan->pushbuf_bo)
185 continue;
186
187 for (j = 0; j < NOUVEAU_DMA_SKIPS; j++)
188 nouveau_bo_wr32(chan->pushbuf_bo, i, 0);
189 }
190 }
191#endif
192
193 nouveau_pm_resume(dev);
194
195 NV_INFO(dev, "Restoring mode...\n");
196 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
197 struct nouveau_framebuffer *nouveau_fb;
198
199 nouveau_fb = nouveau_framebuffer(crtc->fb);
200 if (!nouveau_fb || !nouveau_fb->nvbo)
201 continue;
202
203 nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM);
204 }
205
206 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
207 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
208
209 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
210 if (!ret)
211 ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
212 if (ret)
213 NV_ERROR(dev, "Could not pin/map cursor.\n");
214 }
215
216 nouveau_fbcon_set_suspend(dev, 0);
217 nouveau_fbcon_zfill_all(dev);
218
219 nouveau_display_init(dev);
220
221 /* Force CLUT to get re-loaded during modeset */
222 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
223 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
224
225 nv_crtc->lut.depth = 0;
226 }
227
228 drm_helper_resume_force_mode(dev);
229
230 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
231 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
232 u32 offset = nv_crtc->cursor.nvbo->bo.offset;
233
234 nv_crtc->cursor.set_offset(nv_crtc, offset);
235 nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x,
236 nv_crtc->cursor_saved_y);
237 }
238
239 return 0;
240}
241
242static struct drm_ioctl_desc nouveau_ioctls[] = {
243 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
244 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
245 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED|DRM_AUTH),
246 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED|DRM_AUTH),
247 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
248 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED|DRM_AUTH),
249 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
250 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
251 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
252 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
253 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
254 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
255};
256
257static const struct file_operations nouveau_driver_fops = {
258 .owner = THIS_MODULE,
259 .open = drm_open,
260 .release = drm_release,
261 .unlocked_ioctl = drm_ioctl,
262 .mmap = nouveau_ttm_mmap,
263 .poll = drm_poll,
264 .fasync = drm_fasync,
265 .read = drm_read,
266#if defined(CONFIG_COMPAT)
267 .compat_ioctl = nouveau_compat_ioctl,
268#endif
269 .llseek = noop_llseek,
270};
271
272int nouveau_drm_load(struct drm_device *, unsigned long);
273int nouveau_drm_unload(struct drm_device *);
274int nouveau_drm_open(struct drm_device *, struct drm_file *);
275void nouveau_drm_preclose(struct drm_device *dev, struct drm_file *);
276void nouveau_drm_postclose(struct drm_device *, struct drm_file *);
277
278static struct drm_driver driver = {
279 .driver_features =
280 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
281 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
282 DRIVER_MODESET | DRIVER_PRIME,
283 .load = nouveau_drm_load,
284 .firstopen = nouveau_firstopen,
285 .lastclose = nouveau_lastclose,
286 .unload = nouveau_drm_unload,
287 .open = nouveau_drm_open,
288 .preclose = nouveau_drm_preclose,
289 .postclose = nouveau_drm_postclose,
290 .irq_preinstall = nouveau_irq_preinstall,
291 .irq_postinstall = nouveau_irq_postinstall,
292 .irq_uninstall = nouveau_irq_uninstall,
293 .irq_handler = nouveau_irq_handler,
294 .get_vblank_counter = drm_vblank_count,
295 .enable_vblank = nouveau_vblank_enable,
296 .disable_vblank = nouveau_vblank_disable,
297 .ioctls = nouveau_ioctls,
298 .fops = &nouveau_driver_fops,
299
300 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
301 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
302 .gem_prime_export = nouveau_gem_prime_export,
303 .gem_prime_import = nouveau_gem_prime_import,
304
305 .gem_init_object = nouveau_gem_object_new,
306 .gem_free_object = nouveau_gem_object_del,
307 .gem_open_object = nouveau_gem_object_open,
308 .gem_close_object = nouveau_gem_object_close,
309
310 .dumb_create = nouveau_display_dumb_create,
311 .dumb_map_offset = nouveau_display_dumb_map_offset,
312 .dumb_destroy = nouveau_display_dumb_destroy,
313
314 .name = DRIVER_NAME,
315 .desc = DRIVER_DESC,
316#ifdef GIT_REVISION
317 .date = GIT_REVISION,
318#else
319 .date = DRIVER_DATE,
320#endif
321 .major = DRIVER_MAJOR,
322 .minor = DRIVER_MINOR,
323 .patchlevel = DRIVER_PATCHLEVEL,
324};
325
326int __init nouveau_init(struct pci_driver *pdrv)
327{
328 driver.num_ioctls = ARRAY_SIZE(nouveau_ioctls);
329
330 if (nouveau_modeset == -1) {
331#ifdef CONFIG_VGA_CONSOLE
332 if (vgacon_text_force())
333 nouveau_modeset = 0;
334 else
335#endif
336 nouveau_modeset = 1;
337 }
338
339 if (!nouveau_modeset)
340 return 0;
341
342 nouveau_register_dsm_handler();
343 return drm_pci_init(&driver, pdrv);
344}
345
346void __exit nouveau_exit(struct pci_driver *pdrv)
347{
348 if (!nouveau_modeset)
349 return;
350
351 drm_pci_exit(&driver, pdrv);
352 nouveau_unregister_dsm_handler();
353}
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
deleted file mode 100644
index 1228ac45e24c..000000000000
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ /dev/null
@@ -1,551 +0,0 @@
1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
29#define DRIVER_EMAIL "nouveau@lists.freedesktop.org"
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE "20120316"
34
35#define DRIVER_MAJOR 1
36#define DRIVER_MINOR 0
37#define DRIVER_PATCHLEVEL 0
38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48#define XXX_THIS_IS_A_HACK
49#include <subdev/vm.h>
50#include <subdev/fb.h>
51#include <core/gpuobj.h>
52
53enum blah {
54 NV_MEM_TYPE_UNKNOWN = 0,
55 NV_MEM_TYPE_STOLEN,
56 NV_MEM_TYPE_SGRAM,
57 NV_MEM_TYPE_SDRAM,
58 NV_MEM_TYPE_DDR1,
59 NV_MEM_TYPE_DDR2,
60 NV_MEM_TYPE_DDR3,
61 NV_MEM_TYPE_GDDR2,
62 NV_MEM_TYPE_GDDR3,
63 NV_MEM_TYPE_GDDR4,
64 NV_MEM_TYPE_GDDR5
65};
66
67#include <nouveau_drm.h>
68#include "nouveau_reg.h"
69#include <nouveau_bios.h>
70
71#include <subdev/bios/pll.h>
72#include "nouveau_compat.h"
73
74#define nouveau_gpuobj_new(d,c,s,a,f,o) \
75 _nouveau_gpuobj_new((d), NULL, (s), (a), (f), (o))
76
77#define nouveau_vm_new(d,o,l,m,v) \
78 _nouveau_vm_new((d), (o), (l), (m), (v))
79
80#define nv50_vm_flush_engine(d,e) \
81 _nv50_vm_flush_engine((d), (e))
82
83#include "nouveau_bo.h"
84#include "nouveau_gem.h"
85
86struct nouveau_page_flip_state {
87 struct list_head head;
88 struct drm_pending_vblank_event *event;
89 int crtc, bpp, pitch, x, y;
90 uint64_t offset;
91};
92
93struct nouveau_display_engine {
94 void *priv;
95 int (*early_init)(struct drm_device *);
96 void (*late_takedown)(struct drm_device *);
97 int (*create)(struct drm_device *);
98 void (*destroy)(struct drm_device *);
99 int (*init)(struct drm_device *);
100 void (*fini)(struct drm_device *);
101
102 struct drm_property *dithering_mode;
103 struct drm_property *dithering_depth;
104 struct drm_property *underscan_property;
105 struct drm_property *underscan_hborder_property;
106 struct drm_property *underscan_vborder_property;
107 /* not really hue and saturation: */
108 struct drm_property *vibrant_hue_property;
109 struct drm_property *color_vibrance_property;
110};
111
112struct nouveau_pm_voltage_level {
113 u32 voltage; /* microvolts */
114 u8 vid;
115};
116
117struct nouveau_pm_voltage {
118 bool supported;
119 u8 version;
120 u8 vid_mask;
121
122 struct nouveau_pm_voltage_level *level;
123 int nr_level;
124};
125
126/* Exclusive upper limits */
127#define NV_MEM_CL_DDR2_MAX 8
128#define NV_MEM_WR_DDR2_MAX 9
129#define NV_MEM_CL_DDR3_MAX 17
130#define NV_MEM_WR_DDR3_MAX 17
131#define NV_MEM_CL_GDDR3_MAX 16
132#define NV_MEM_WR_GDDR3_MAX 18
133#define NV_MEM_CL_GDDR5_MAX 21
134#define NV_MEM_WR_GDDR5_MAX 20
135
136struct nouveau_pm_memtiming {
137 int id;
138
139 u32 reg[9];
140 u32 mr[4];
141
142 u8 tCWL;
143
144 u8 odt;
145 u8 drive_strength;
146};
147
148struct nouveau_pm_tbl_header {
149 u8 version;
150 u8 header_len;
151 u8 entry_cnt;
152 u8 entry_len;
153};
154
155struct nouveau_pm_tbl_entry {
156 u8 tWR;
157 u8 tWTR;
158 u8 tCL;
159 u8 tRC;
160 u8 empty_4;
161 u8 tRFC; /* Byte 5 */
162 u8 empty_6;
163 u8 tRAS; /* Byte 7 */
164 u8 empty_8;
165 u8 tRP; /* Byte 9 */
166 u8 tRCDRD;
167 u8 tRCDWR;
168 u8 tRRD;
169 u8 tUNK_13;
170 u8 RAM_FT1; /* 14, a bitmask of random RAM features */
171 u8 empty_15;
172 u8 tUNK_16;
173 u8 empty_17;
174 u8 tUNK_18;
175 u8 tCWL;
176 u8 tUNK_20, tUNK_21;
177};
178
179struct nouveau_pm_profile;
180struct nouveau_pm_profile_func {
181 void (*destroy)(struct nouveau_pm_profile *);
182 void (*init)(struct nouveau_pm_profile *);
183 void (*fini)(struct nouveau_pm_profile *);
184 struct nouveau_pm_level *(*select)(struct nouveau_pm_profile *);
185};
186
187struct nouveau_pm_profile {
188 const struct nouveau_pm_profile_func *func;
189 struct list_head head;
190 char name[8];
191};
192
193#define NOUVEAU_PM_MAX_LEVEL 8
194struct nouveau_pm_level {
195 struct nouveau_pm_profile profile;
196 struct device_attribute dev_attr;
197 char name[32];
198 int id;
199
200 struct nouveau_pm_memtiming timing;
201 u32 memory;
202 u16 memscript;
203
204 u32 core;
205 u32 shader;
206 u32 rop;
207 u32 copy;
208 u32 daemon;
209 u32 vdec;
210 u32 dom6;
211 u32 unka0; /* nva3:nvc0 */
212 u32 hub01; /* nvc0- */
213 u32 hub06; /* nvc0- */
214 u32 hub07; /* nvc0- */
215
216 u32 volt_min; /* microvolts */
217 u32 volt_max;
218 u8 fanspeed;
219};
220
221struct nouveau_pm_temp_sensor_constants {
222 u16 offset_constant;
223 s16 offset_mult;
224 s16 offset_div;
225 s16 slope_mult;
226 s16 slope_div;
227};
228
229struct nouveau_pm_threshold_temp {
230 s16 critical;
231 s16 down_clock;
232 s16 fan_boost;
233};
234
235struct nouveau_pm_fan {
236 u32 percent;
237 u32 min_duty;
238 u32 max_duty;
239 u32 pwm_freq;
240 u32 pwm_divisor;
241};
242
243struct nouveau_pm_engine {
244 struct nouveau_pm_voltage voltage;
245 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
246 int nr_perflvl;
247 struct nouveau_pm_temp_sensor_constants sensor_constants;
248 struct nouveau_pm_threshold_temp threshold_temp;
249 struct nouveau_pm_fan fan;
250
251 struct nouveau_pm_profile *profile_ac;
252 struct nouveau_pm_profile *profile_dc;
253 struct nouveau_pm_profile *profile;
254 struct list_head profiles;
255
256 struct nouveau_pm_level boot;
257 struct nouveau_pm_level *cur;
258
259 struct device *hwmon;
260 struct notifier_block acpi_nb;
261
262 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *);
263 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *);
264 int (*clocks_set)(struct drm_device *, void *);
265
266 int (*voltage_get)(struct drm_device *);
267 int (*voltage_set)(struct drm_device *, int voltage);
268 int (*pwm_get)(struct drm_device *, int line, u32*, u32*);
269 int (*pwm_set)(struct drm_device *, int line, u32, u32);
270 int (*temp_get)(struct drm_device *);
271};
272
273struct nouveau_engine {
274 struct nouveau_display_engine display;
275 struct nouveau_pm_engine pm;
276};
277
278enum nouveau_card_type {
279 NV_04 = 0x04,
280 NV_10 = 0x10,
281 NV_20 = 0x20,
282 NV_30 = 0x30,
283 NV_40 = 0x40,
284 NV_50 = 0x50,
285 NV_C0 = 0xc0,
286 NV_D0 = 0xd0,
287 NV_E0 = 0xe0,
288};
289
290struct drm_nouveau_private {
291 struct drm_device *dev;
292
293 void *newpriv;
294
295 /* the card type, takes NV_* as values */
296 enum nouveau_card_type card_type;
297 /* exact chipset, derived from NV_PMC_BOOT_0 */
298 int chipset;
299 u32 crystal;
300
301 /* interrupt handling */
302 void (*irq_handler[32])(struct drm_device *);
303 bool msi_enabled;
304
305 struct nouveau_engine engine;
306
307 /* For PFIFO and PGRAPH. */
308 spinlock_t context_switch_lock;
309
310 struct nvbios vbios;
311};
312
313static inline struct drm_nouveau_private *
314nouveau_private(struct drm_device *dev)
315{
316 return dev->dev_private;
317}
318
319/* nouveau_drv.c */
320extern int nouveau_modeset;
321extern int nouveau_duallink;
322extern int nouveau_uscript_lvds;
323extern int nouveau_uscript_tmds;
324extern int nouveau_vram_pushbuf;
325extern int nouveau_vram_notify;
326extern char *nouveau_vram_type;
327extern int nouveau_fbpercrtc;
328extern int nouveau_tv_disable;
329extern char *nouveau_tv_norm;
330extern int nouveau_ignorelid;
331extern int nouveau_force_post;
332extern int nouveau_override_conntype;
333extern char *nouveau_perflvl;
334extern int nouveau_perflvl_wr;
335extern int nouveau_msi;
336extern int nouveau_ctxfw;
337extern int nouveau_mxmdcb;
338
339extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
340extern int nouveau_pci_resume(struct pci_dev *pdev);
341
342/* nouveau_state.c */
343extern int nouveau_load(struct drm_device *, unsigned long flags);
344extern int nouveau_firstopen(struct drm_device *);
345extern void nouveau_lastclose(struct drm_device *);
346extern int nouveau_unload(struct drm_device *);
347extern int nouveau_card_init(struct drm_device *);
348
349/* nouveau_mem.c */
350extern int nouveau_mem_timing_calc(struct drm_device *, u32 freq,
351 struct nouveau_pm_memtiming *);
352extern void nouveau_mem_timing_read(struct drm_device *,
353 struct nouveau_pm_memtiming *);
354
355/* nouveau_irq.c */
356extern int nouveau_irq_init(struct drm_device *);
357extern void nouveau_irq_fini(struct drm_device *);
358extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
359extern void nouveau_irq_register(struct drm_device *, int status_bit,
360 void (*)(struct drm_device *));
361extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
362extern void nouveau_irq_preinstall(struct drm_device *);
363extern int nouveau_irq_postinstall(struct drm_device *);
364extern void nouveau_irq_uninstall(struct drm_device *);
365
366/* nouveau_backlight.c */
367#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
368extern int nouveau_backlight_init(struct drm_device *);
369extern void nouveau_backlight_exit(struct drm_device *);
370#else
371static inline int nouveau_backlight_init(struct drm_device *dev)
372{
373 return 0;
374}
375
376static inline void nouveau_backlight_exit(struct drm_device *dev) { }
377#endif
378
379/* nouveau_bios.c */
380extern int nouveau_bios_init(struct drm_device *);
381extern void nouveau_bios_takedown(struct drm_device *dev);
382extern int nouveau_run_vbios_init(struct drm_device *);
383extern struct dcb_connector_table_entry *
384nouveau_bios_connector_entry(struct drm_device *, int index);
385extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk,
386 struct dcb_output *, int crtc);
387extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
388extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
389extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
390 bool *dl, bool *if_is_24bit);
391extern int run_tmds_table(struct drm_device *, struct dcb_output *,
392 int head, int pxclk);
393extern int call_lvds_script(struct drm_device *, struct dcb_output *, int head,
394 enum LVDS_script, int pxclk);
395bool bios_encoder_match(struct dcb_output *, u32 hash);
396
397/* nouveau_ttm.c */
398int nouveau_ttm_global_init(struct drm_nouveau_private *);
399void nouveau_ttm_global_release(struct drm_nouveau_private *);
400int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
401
402/* nouveau_hdmi.c */
403void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *);
404
405/* nvd0_display.c */
406extern int nvd0_display_create(struct drm_device *);
407extern void nvd0_display_destroy(struct drm_device *);
408extern int nvd0_display_init(struct drm_device *);
409extern void nvd0_display_fini(struct drm_device *);
410struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc);
411void nvd0_display_flip_stop(struct drm_crtc *);
412int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
413 struct nouveau_channel *, u32 swap_interval);
414
415
416/* nouveau_display.c */
417int nouveau_display_create(struct drm_device *dev);
418void nouveau_display_destroy(struct drm_device *dev);
419int nouveau_display_init(struct drm_device *dev);
420void nouveau_display_fini(struct drm_device *dev);
421int nouveau_vblank_enable(struct drm_device *dev, int crtc);
422void nouveau_vblank_disable(struct drm_device *dev, int crtc);
423int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
424 struct drm_pending_vblank_event *event);
425int nouveau_finish_page_flip(struct nouveau_channel *,
426 struct nouveau_page_flip_state *);
427int nouveau_display_dumb_create(struct drm_file *, struct drm_device *,
428 struct drm_mode_create_dumb *args);
429int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *,
430 uint32_t handle, uint64_t *offset);
431int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *,
432 uint32_t handle);
433
434#ifndef ioread32_native
435#ifdef __BIG_ENDIAN
436#define ioread16_native ioread16be
437#define iowrite16_native iowrite16be
438#define ioread32_native ioread32be
439#define iowrite32_native iowrite32be
440#else /* def __BIG_ENDIAN */
441#define ioread16_native ioread16
442#define iowrite16_native iowrite16
443#define ioread32_native ioread32
444#define iowrite32_native iowrite32
445#endif /* def __BIG_ENDIAN else */
446#endif /* !ioread32_native */
447
448/* register access */
449#define nv_rd08 _nv_rd08
450#define nv_wr08 _nv_wr08
451#define nv_rd32 _nv_rd32
452#define nv_wr32 _nv_wr32
453#define nv_mask _nv_mask
454
455#define nv_wait(dev, reg, mask, val) \
456 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val))
457#define nv_wait_ne(dev, reg, mask, val) \
458 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val))
459#define nv_wait_cb(dev, func, data) \
460 nouveau_wait_cb(dev, 2000000000ULL, (func), (data))
461
462/*
463 * Logging
464 * Argument d is (struct drm_device *).
465 */
466#define NV_PRINTK(level, d, fmt, arg...) \
467 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
468 pci_name(d->pdev), ##arg)
469#ifndef NV_DEBUG_NOTRACE
470#define NV_DEBUG(d, fmt, arg...) do { \
471 if (drm_debug & DRM_UT_DRIVER) { \
472 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
473 __LINE__, ##arg); \
474 } \
475} while (0)
476#define NV_DEBUG_KMS(d, fmt, arg...) do { \
477 if (drm_debug & DRM_UT_KMS) { \
478 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
479 __LINE__, ##arg); \
480 } \
481} while (0)
482#else
483#define NV_DEBUG(d, fmt, arg...) do { \
484 if (drm_debug & DRM_UT_DRIVER) \
485 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
486} while (0)
487#define NV_DEBUG_KMS(d, fmt, arg...) do { \
488 if (drm_debug & DRM_UT_KMS) \
489 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
490} while (0)
491#endif
492#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
493#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
494#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
495#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
496#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
497#define NV_WARNONCE(d, fmt, arg...) do { \
498 static int _warned = 0; \
499 if (!_warned) { \
500 NV_WARN(d, fmt, ##arg); \
501 _warned = 1; \
502 } \
503} while(0)
504
505static inline bool
506nv_two_heads(struct drm_device *dev)
507{
508 struct drm_nouveau_private *dev_priv = dev->dev_private;
509 const int impl = dev->pci_device & 0x0ff0;
510
511 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
512 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
513 return true;
514
515 return false;
516}
517
518static inline bool
519nv_gf4_disp_arch(struct drm_device *dev)
520{
521 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
522}
523
524static inline bool
525nv_two_reg_pll(struct drm_device *dev)
526{
527 struct drm_nouveau_private *dev_priv = dev->dev_private;
528 const int impl = dev->pci_device & 0x0ff0;
529
530 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
531 return true;
532 return false;
533}
534
535static inline bool
536nv_match_device(struct drm_device *dev, unsigned device,
537 unsigned sub_vendor, unsigned sub_device)
538{
539 return dev->pdev->device == device &&
540 dev->pdev->subsystem_vendor == sub_vendor &&
541 dev->pdev->subsystem_device == sub_device;
542}
543
544static inline struct nv04_display *
545nv04_display(struct drm_device *dev)
546{
547 struct drm_nouveau_private *dev_priv = dev->dev_private;
548 return dev_priv->engine.display.priv;
549}
550
551#endif /* __NOUVEAU_DRV_H__ */
diff --git a/drivers/gpu/drm/nouveau/nouveau_fb.h b/drivers/gpu/drm/nouveau/nouveau_fb.h
deleted file mode 100644
index d767567977ee..000000000000
--- a/drivers/gpu/drm/nouveau/nouveau_fb.h
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * Copyright (C) 2008 Maarten Maathuis.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#ifndef __NOUVEAU_FRB_H__
28#define __NOUVEAU_FRB_H__
29
30struct nouveau_framebuffer {
31 struct drm_framebuffer base;
32 struct nouveau_bo *nvbo;
33 struct nouveau_vma vma;
34 u32 r_dma;
35 u32 r_format;
36 u32 r_pitch;
37};
38
39static inline struct nouveau_framebuffer *
40nouveau_framebuffer(struct drm_framebuffer *fb)
41{
42 return container_of(fb, struct nouveau_framebuffer, base);
43}
44
45int nouveau_framebuffer_init(struct drm_device *dev, struct nouveau_framebuffer *nouveau_fb,
46 struct drm_mode_fb_cmd2 *mode_cmd, struct nouveau_bo *nvbo);
47#endif /* __NOUVEAU_FB_H__ */
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index 8b8bc8314d92..e75e071845b7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -47,7 +47,6 @@
47#include "nouveau_drm.h" 47#include "nouveau_drm.h"
48#include "nouveau_gem.h" 48#include "nouveau_gem.h"
49#include "nouveau_bo.h" 49#include "nouveau_bo.h"
50#include "nouveau_fb.h"
51#include "nouveau_fbcon.h" 50#include "nouveau_fbcon.h"
52#include "nouveau_chan.h" 51#include "nouveau_chan.h"
53 52
@@ -66,7 +65,7 @@ static void
66nouveau_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 65nouveau_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
67{ 66{
68 struct nouveau_fbdev *fbcon = info->par; 67 struct nouveau_fbdev *fbcon = info->par;
69 struct nouveau_drm *drm = nouveau_newpriv(fbcon->dev); 68 struct nouveau_drm *drm = nouveau_drm(fbcon->dev);
70 struct nouveau_device *device = nv_device(drm->device); 69 struct nouveau_device *device = nv_device(drm->device);
71 int ret; 70 int ret;
72 71
@@ -98,7 +97,7 @@ static void
98nouveau_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *image) 97nouveau_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *image)
99{ 98{
100 struct nouveau_fbdev *fbcon = info->par; 99 struct nouveau_fbdev *fbcon = info->par;
101 struct nouveau_drm *drm = nouveau_newpriv(fbcon->dev); 100 struct nouveau_drm *drm = nouveau_drm(fbcon->dev);
102 struct nouveau_device *device = nv_device(drm->device); 101 struct nouveau_device *device = nv_device(drm->device);
103 int ret; 102 int ret;
104 103
@@ -130,7 +129,7 @@ static void
130nouveau_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) 129nouveau_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
131{ 130{
132 struct nouveau_fbdev *fbcon = info->par; 131 struct nouveau_fbdev *fbcon = info->par;
133 struct nouveau_drm *drm = nouveau_newpriv(fbcon->dev); 132 struct nouveau_drm *drm = nouveau_drm(fbcon->dev);
134 struct nouveau_device *device = nv_device(drm->device); 133 struct nouveau_device *device = nv_device(drm->device);
135 int ret; 134 int ret;
136 135
@@ -162,7 +161,7 @@ static int
162nouveau_fbcon_sync(struct fb_info *info) 161nouveau_fbcon_sync(struct fb_info *info)
163{ 162{
164 struct nouveau_fbdev *fbcon = info->par; 163 struct nouveau_fbdev *fbcon = info->par;
165 struct nouveau_drm *drm = nouveau_newpriv(fbcon->dev); 164 struct nouveau_drm *drm = nouveau_drm(fbcon->dev);
166 struct nouveau_channel *chan = drm->channel; 165 struct nouveau_channel *chan = drm->channel;
167 int ret; 166 int ret;
168 167
@@ -257,7 +256,7 @@ nouveau_fbcon_create(struct nouveau_fbdev *fbcon,
257 struct drm_fb_helper_surface_size *sizes) 256 struct drm_fb_helper_surface_size *sizes)
258{ 257{
259 struct drm_device *dev = fbcon->dev; 258 struct drm_device *dev = fbcon->dev;
260 struct nouveau_drm *drm = nouveau_newpriv(dev); 259 struct nouveau_drm *drm = nouveau_drm(dev);
261 struct nouveau_device *device = nv_device(drm->device); 260 struct nouveau_device *device = nv_device(drm->device);
262 struct fb_info *info; 261 struct fb_info *info;
263 struct drm_framebuffer *fb; 262 struct drm_framebuffer *fb;
@@ -410,7 +409,7 @@ nouveau_fbcon_find_or_create_single(struct drm_fb_helper *helper,
410void 409void
411nouveau_fbcon_output_poll_changed(struct drm_device *dev) 410nouveau_fbcon_output_poll_changed(struct drm_device *dev)
412{ 411{
413 struct nouveau_drm *drm = nouveau_newpriv(dev); 412 struct nouveau_drm *drm = nouveau_drm(dev);
414 drm_fb_helper_hotplug_event(&drm->fbcon->helper); 413 drm_fb_helper_hotplug_event(&drm->fbcon->helper);
415} 414}
416 415
@@ -442,7 +441,7 @@ nouveau_fbcon_destroy(struct drm_device *dev, struct nouveau_fbdev *fbcon)
442void nouveau_fbcon_gpu_lockup(struct fb_info *info) 441void nouveau_fbcon_gpu_lockup(struct fb_info *info)
443{ 442{
444 struct nouveau_fbdev *fbcon = info->par; 443 struct nouveau_fbdev *fbcon = info->par;
445 struct nouveau_drm *drm = nouveau_newpriv(fbcon->dev); 444 struct nouveau_drm *drm = nouveau_drm(fbcon->dev);
446 445
447 NV_ERROR(drm, "GPU lockup - switching to software fbcon\n"); 446 NV_ERROR(drm, "GPU lockup - switching to software fbcon\n");
448 info->flags |= FBINFO_HWACCEL_DISABLED; 447 info->flags |= FBINFO_HWACCEL_DISABLED;
@@ -458,7 +457,7 @@ static struct drm_fb_helper_funcs nouveau_fbcon_helper_funcs = {
458int 457int
459nouveau_fbcon_init(struct drm_device *dev) 458nouveau_fbcon_init(struct drm_device *dev)
460{ 459{
461 struct nouveau_drm *drm = nouveau_newpriv(dev); 460 struct nouveau_drm *drm = nouveau_drm(dev);
462 struct nouveau_fb *pfb = nouveau_fb(drm->device); 461 struct nouveau_fb *pfb = nouveau_fb(drm->device);
463 struct nouveau_fbdev *fbcon; 462 struct nouveau_fbdev *fbcon;
464 int preferred_bpp; 463 int preferred_bpp;
@@ -499,7 +498,7 @@ nouveau_fbcon_init(struct drm_device *dev)
499void 498void
500nouveau_fbcon_fini(struct drm_device *dev) 499nouveau_fbcon_fini(struct drm_device *dev)
501{ 500{
502 struct nouveau_drm *drm = nouveau_newpriv(dev); 501 struct nouveau_drm *drm = nouveau_drm(dev);
503 502
504 if (!drm->fbcon) 503 if (!drm->fbcon)
505 return; 504 return;
@@ -511,7 +510,7 @@ nouveau_fbcon_fini(struct drm_device *dev)
511 510
512void nouveau_fbcon_save_disable_accel(struct drm_device *dev) 511void nouveau_fbcon_save_disable_accel(struct drm_device *dev)
513{ 512{
514 struct nouveau_drm *drm = nouveau_newpriv(dev); 513 struct nouveau_drm *drm = nouveau_drm(dev);
515 514
516 drm->fbcon->saved_flags = drm->fbcon->helper.fbdev->flags; 515 drm->fbcon->saved_flags = drm->fbcon->helper.fbdev->flags;
517 drm->fbcon->helper.fbdev->flags |= FBINFO_HWACCEL_DISABLED; 516 drm->fbcon->helper.fbdev->flags |= FBINFO_HWACCEL_DISABLED;
@@ -519,13 +518,13 @@ void nouveau_fbcon_save_disable_accel(struct drm_device *dev)
519 518
520void nouveau_fbcon_restore_accel(struct drm_device *dev) 519void nouveau_fbcon_restore_accel(struct drm_device *dev)
521{ 520{
522 struct nouveau_drm *drm = nouveau_newpriv(dev); 521 struct nouveau_drm *drm = nouveau_drm(dev);
523 drm->fbcon->helper.fbdev->flags = drm->fbcon->saved_flags; 522 drm->fbcon->helper.fbdev->flags = drm->fbcon->saved_flags;
524} 523}
525 524
526void nouveau_fbcon_set_suspend(struct drm_device *dev, int state) 525void nouveau_fbcon_set_suspend(struct drm_device *dev, int state)
527{ 526{
528 struct nouveau_drm *drm = nouveau_newpriv(dev); 527 struct nouveau_drm *drm = nouveau_drm(dev);
529 console_lock(); 528 console_lock();
530 if (state == 0) 529 if (state == 0)
531 nouveau_fbcon_save_disable_accel(dev); 530 nouveau_fbcon_save_disable_accel(dev);
@@ -537,6 +536,6 @@ void nouveau_fbcon_set_suspend(struct drm_device *dev, int state)
537 536
538void nouveau_fbcon_zfill_all(struct drm_device *dev) 537void nouveau_fbcon_zfill_all(struct drm_device *dev)
539{ 538{
540 struct nouveau_drm *drm = nouveau_newpriv(dev); 539 struct nouveau_drm *drm = nouveau_drm(dev);
541 nouveau_fbcon_zfill(dev, drm->fbcon); 540 nouveau_fbcon_zfill(dev, drm->fbcon);
542} 541}
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.h b/drivers/gpu/drm/nouveau/nouveau_fbcon.h
index e6404e39eaf1..18e028008225 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.h
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.h
@@ -29,7 +29,7 @@
29 29
30#include "drm_fb_helper.h" 30#include "drm_fb_helper.h"
31 31
32#include "nouveau_fb.h" 32#include "nouveau_display.h"
33 33
34struct nouveau_fbdev { 34struct nouveau_fbdev {
35 struct drm_fb_helper helper; 35 struct drm_fb_helper helper;
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index ba744daeb50e..6454370e78cf 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -550,7 +550,7 @@ nouveau_gem_pushbuf_reloc_apply(struct drm_device *dev,
550 struct drm_nouveau_gem_pushbuf *req, 550 struct drm_nouveau_gem_pushbuf *req,
551 struct drm_nouveau_gem_pushbuf_bo *bo) 551 struct drm_nouveau_gem_pushbuf_bo *bo)
552{ 552{
553 struct nouveau_drm *drm = nouveau_newpriv(dev); 553 struct nouveau_drm *drm = nouveau_drm(dev);
554 struct drm_nouveau_gem_pushbuf_reloc *reloc = NULL; 554 struct drm_nouveau_gem_pushbuf_reloc *reloc = NULL;
555 int ret = 0; 555 int ret = 0;
556 unsigned i; 556 unsigned i;
diff --git a/drivers/gpu/drm/nouveau/nouveau_hdmi.c b/drivers/gpu/drm/nouveau/nouveau_hdmi.c
index c3de36384522..ea712b5762e7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_hdmi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_hdmi.c
@@ -23,7 +23,7 @@
23 */ 23 */
24 24
25#include "drmP.h" 25#include "drmP.h"
26#include "nouveau_drv.h" 26#include "nouveau_drm.h"
27#include "nouveau_connector.h" 27#include "nouveau_connector.h"
28#include "nouveau_encoder.h" 28#include "nouveau_encoder.h"
29#include "nouveau_crtc.h" 29#include "nouveau_crtc.h"
@@ -31,10 +31,10 @@
31static bool 31static bool
32hdmi_sor(struct drm_encoder *encoder) 32hdmi_sor(struct drm_encoder *encoder)
33{ 33{
34 struct drm_nouveau_private *dev_priv = encoder->dev->dev_private; 34 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
35 if (dev_priv->chipset < 0xa3 || 35 if (nv_device(drm->device)->chipset < 0xa3 ||
36 dev_priv->chipset == 0xaa || 36 nv_device(drm->device)->chipset == 0xaa ||
37 dev_priv->chipset == 0xac) 37 nv_device(drm->device)->chipset == 0xac)
38 return false; 38 return false;
39 return true; 39 return true;
40} 40}
@@ -52,13 +52,15 @@ hdmi_base(struct drm_encoder *encoder)
52static void 52static void
53hdmi_wr32(struct drm_encoder *encoder, u32 reg, u32 val) 53hdmi_wr32(struct drm_encoder *encoder, u32 reg, u32 val)
54{ 54{
55 nv_wr32(encoder->dev, hdmi_base(encoder) + reg, val); 55 struct nouveau_device *device = nouveau_dev(encoder->dev);
56 nv_wr32(device, hdmi_base(encoder) + reg, val);
56} 57}
57 58
58static u32 59static u32
59hdmi_rd32(struct drm_encoder *encoder, u32 reg) 60hdmi_rd32(struct drm_encoder *encoder, u32 reg)
60{ 61{
61 return nv_rd32(encoder->dev, hdmi_base(encoder) + reg); 62 struct nouveau_device *device = nouveau_dev(encoder->dev);
63 return nv_rd32(device, hdmi_base(encoder) + reg);
62} 64}
63 65
64static u32 66static u32
@@ -73,12 +75,11 @@ static void
73nouveau_audio_disconnect(struct drm_encoder *encoder) 75nouveau_audio_disconnect(struct drm_encoder *encoder)
74{ 76{
75 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 77 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
76 struct drm_device *dev = encoder->dev; 78 struct nouveau_device *device = nouveau_dev(encoder->dev);
77 u32 or = nv_encoder->or * 0x800; 79 u32 or = nv_encoder->or * 0x800;
78 80
79 if (hdmi_sor(encoder)) { 81 if (hdmi_sor(encoder))
80 nv_mask(dev, 0x61c448 + or, 0x00000003, 0x00000000); 82 nv_mask(device, 0x61c448 + or, 0x00000003, 0x00000000);
81 }
82} 83}
83 84
84static void 85static void
@@ -86,8 +87,8 @@ nouveau_audio_mode_set(struct drm_encoder *encoder,
86 struct drm_display_mode *mode) 87 struct drm_display_mode *mode)
87{ 88{
88 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 89 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
90 struct nouveau_device *device = nouveau_dev(encoder->dev);
89 struct nouveau_connector *nv_connector; 91 struct nouveau_connector *nv_connector;
90 struct drm_device *dev = encoder->dev;
91 u32 or = nv_encoder->or * 0x800; 92 u32 or = nv_encoder->or * 0x800;
92 int i; 93 int i;
93 94
@@ -98,16 +99,16 @@ nouveau_audio_mode_set(struct drm_encoder *encoder,
98 } 99 }
99 100
100 if (hdmi_sor(encoder)) { 101 if (hdmi_sor(encoder)) {
101 nv_mask(dev, 0x61c448 + or, 0x00000001, 0x00000001); 102 nv_mask(device, 0x61c448 + or, 0x00000001, 0x00000001);
102 103
103 drm_edid_to_eld(&nv_connector->base, nv_connector->edid); 104 drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
104 if (nv_connector->base.eld[0]) { 105 if (nv_connector->base.eld[0]) {
105 u8 *eld = nv_connector->base.eld; 106 u8 *eld = nv_connector->base.eld;
106 for (i = 0; i < eld[2] * 4; i++) 107 for (i = 0; i < eld[2] * 4; i++)
107 nv_wr32(dev, 0x61c440 + or, (i << 8) | eld[i]); 108 nv_wr32(device, 0x61c440 + or, (i << 8) | eld[i]);
108 for (i = eld[2] * 4; i < 0x60; i++) 109 for (i = eld[2] * 4; i < 0x60; i++)
109 nv_wr32(dev, 0x61c440 + or, (i << 8) | 0x00); 110 nv_wr32(device, 0x61c440 + or, (i << 8) | 0x00);
110 nv_mask(dev, 0x61c448 + or, 0x00000002, 0x00000002); 111 nv_mask(device, 0x61c448 + or, 0x00000002, 0x00000002);
111 } 112 }
112 } 113 }
113} 114}
@@ -219,9 +220,9 @@ void
219nouveau_hdmi_mode_set(struct drm_encoder *encoder, 220nouveau_hdmi_mode_set(struct drm_encoder *encoder,
220 struct drm_display_mode *mode) 221 struct drm_display_mode *mode)
221{ 222{
223 struct nouveau_device *device = nouveau_dev(encoder->dev);
222 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 224 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
223 struct nouveau_connector *nv_connector; 225 struct nouveau_connector *nv_connector;
224 struct drm_device *dev = encoder->dev;
225 u32 max_ac_packet, rekey; 226 u32 max_ac_packet, rekey;
226 227
227 nv_connector = nouveau_encoder_connector_get(nv_encoder); 228 nv_connector = nouveau_encoder_connector_get(nv_encoder);
@@ -238,9 +239,9 @@ nouveau_hdmi_mode_set(struct drm_encoder *encoder,
238 hdmi_mask(encoder, 0x068, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */ 239 hdmi_mask(encoder, 0x068, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
239 hdmi_mask(encoder, 0x078, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */ 240 hdmi_mask(encoder, 0x078, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
240 241
241 nv_mask(dev, 0x61733c, 0x00100000, 0x00100000); /* RESETF */ 242 nv_mask(device, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
242 nv_mask(dev, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */ 243 nv_mask(device, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
243 nv_mask(dev, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */ 244 nv_mask(device, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */
244 245
245 /* value matches nvidia binary driver, and tegra constant */ 246 /* value matches nvidia binary driver, and tegra constant */
246 rekey = 56; 247 rekey = 56;
diff --git a/drivers/gpu/drm/nouveau/nouveau_hw.c b/drivers/gpu/drm/nouveau/nouveau_hw.c
index dcb65797acbc..a78b24704794 100644
--- a/drivers/gpu/drm/nouveau/nouveau_hw.c
+++ b/drivers/gpu/drm/nouveau/nouveau_hw.c
@@ -23,10 +23,12 @@
23 */ 23 */
24 24
25#include "drmP.h" 25#include "drmP.h"
26#include "nouveau_drv.h" 26#include "nouveau_drm.h"
27#include "nouveau_hw.h" 27#include "nouveau_hw.h"
28 28
29#include <subdev/bios/pll.h> 29#include <subdev/bios/pll.h>
30#include <subdev/clock.h>
31#include <subdev/timer.h>
30 32
31#define CHIPSET_NFORCE 0x01a0 33#define CHIPSET_NFORCE 0x01a0
32#define CHIPSET_NFORCE2 0x01f0 34#define CHIPSET_NFORCE2 0x01f0
@@ -84,12 +86,12 @@ NVReadVgaGr(struct drm_device *dev, int head, uint8_t index)
84void 86void
85NVSetOwner(struct drm_device *dev, int owner) 87NVSetOwner(struct drm_device *dev, int owner)
86{ 88{
87 struct drm_nouveau_private *dev_priv = dev->dev_private; 89 struct nouveau_drm *drm = nouveau_drm(dev);
88 90
89 if (owner == 1) 91 if (owner == 1)
90 owner *= 3; 92 owner *= 3;
91 93
92 if (dev_priv->chipset == 0x11) { 94 if (nv_device(drm->device)->chipset == 0x11) {
93 /* This might seem stupid, but the blob does it and 95 /* This might seem stupid, but the blob does it and
94 * omitting it often locks the system up. 96 * omitting it often locks the system up.
95 */ 97 */
@@ -100,7 +102,7 @@ NVSetOwner(struct drm_device *dev, int owner)
100 /* CR44 is always changed on CRTC0 */ 102 /* CR44 is always changed on CRTC0 */
101 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner); 103 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner);
102 104
103 if (dev_priv->chipset == 0x11) { /* set me harder */ 105 if (nv_device(drm->device)->chipset == 0x11) { /* set me harder */
104 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); 106 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
105 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); 107 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
106 } 108 }
@@ -132,7 +134,7 @@ static void
132nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, 134nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1,
133 uint32_t pll2, struct nouveau_pll_vals *pllvals) 135 uint32_t pll2, struct nouveau_pll_vals *pllvals)
134{ 136{
135 struct drm_nouveau_private *dev_priv = dev->dev_private; 137 struct nouveau_drm *drm = nouveau_drm(dev);
136 138
137 /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */ 139 /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */
138 140
@@ -149,7 +151,7 @@ nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1,
149 pllvals->NM1 = pll1 & 0xffff; 151 pllvals->NM1 = pll1 & 0xffff;
150 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) 152 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2)
151 pllvals->NM2 = pll2 & 0xffff; 153 pllvals->NM2 = pll2 & 0xffff;
152 else if (dev_priv->chipset == 0x30 || dev_priv->chipset == 0x35) { 154 else if (nv_device(drm->device)->chipset == 0x30 || nv_device(drm->device)->chipset == 0x35) {
153 pllvals->M1 &= 0xf; /* only 4 bits */ 155 pllvals->M1 &= 0xf; /* only 4 bits */
154 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { 156 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) {
155 pllvals->M2 = (pll1 >> 4) & 0x7; 157 pllvals->M2 = (pll1 >> 4) & 0x7;
@@ -164,25 +166,27 @@ int
164nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype, 166nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype,
165 struct nouveau_pll_vals *pllvals) 167 struct nouveau_pll_vals *pllvals)
166{ 168{
167 struct drm_nouveau_private *dev_priv = dev->dev_private; 169 struct nouveau_drm *drm = nouveau_drm(dev);
168 uint32_t reg1 = get_pll_register(dev, plltype), pll1, pll2 = 0; 170 struct nouveau_device *device = nv_device(drm->device);
171 struct nouveau_bios *bios = nouveau_bios(device);
172 uint32_t reg1, pll1, pll2 = 0;
169 struct nvbios_pll pll_lim; 173 struct nvbios_pll pll_lim;
170 int ret; 174 int ret;
171 175
172 if (reg1 == 0) 176 ret = nvbios_pll_parse(bios, plltype, &pll_lim);
177 if (ret || !(reg1 = pll_lim.reg))
173 return -ENOENT; 178 return -ENOENT;
174 179
175 pll1 = nv_rd32(dev, reg1); 180 pll1 = nv_rd32(device, reg1);
176
177 if (reg1 <= 0x405c) 181 if (reg1 <= 0x405c)
178 pll2 = nv_rd32(dev, reg1 + 4); 182 pll2 = nv_rd32(device, reg1 + 4);
179 else if (nv_two_reg_pll(dev)) { 183 else if (nv_two_reg_pll(dev)) {
180 uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70); 184 uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70);
181 185
182 pll2 = nv_rd32(dev, reg2); 186 pll2 = nv_rd32(device, reg2);
183 } 187 }
184 188
185 if (dev_priv->card_type == 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) { 189 if (nv_device(drm->device)->card_type == 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) {
186 uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580); 190 uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580);
187 191
188 /* check whether vpll has been forced into single stage mode */ 192 /* check whether vpll has been forced into single stage mode */
@@ -195,13 +199,7 @@ nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype,
195 } 199 }
196 200
197 nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals); 201 nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals);
198
199 ret = get_pll_limits(dev, plltype, &pll_lim);
200 if (ret)
201 return ret;
202
203 pllvals->refclk = pll_lim.refclk; 202 pllvals->refclk = pll_lim.refclk;
204
205 return 0; 203 return 0;
206} 204}
207 205
@@ -255,11 +253,15 @@ nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head)
255 * when such a condition detected. only seen on nv11 to date 253 * when such a condition detected. only seen on nv11 to date
256 */ 254 */
257 255
256 struct nouveau_drm *drm = nouveau_drm(dev);
257 struct nouveau_device *device = nv_device(drm->device);
258 struct nouveau_clock *clk = nouveau_clock(device);
259 struct nouveau_bios *bios = nouveau_bios(device);
258 struct nvbios_pll pll_lim; 260 struct nvbios_pll pll_lim;
259 struct nouveau_pll_vals pv; 261 struct nouveau_pll_vals pv;
260 enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0; 262 enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0;
261 263
262 if (get_pll_limits(dev, pll, &pll_lim)) 264 if (nvbios_pll_parse(bios, pll, &pll_lim))
263 return; 265 return;
264 nouveau_hw_get_pllvals(dev, pll, &pv); 266 nouveau_hw_get_pllvals(dev, pll, &pv);
265 267
@@ -268,13 +270,13 @@ nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head)
268 pv.log2P <= pll_lim.max_p) 270 pv.log2P <= pll_lim.max_p)
269 return; 271 return;
270 272
271 NV_WARN(dev, "VPLL %d outwith limits, attempting to fix\n", head + 1); 273 NV_WARN(drm, "VPLL %d outwith limits, attempting to fix\n", head + 1);
272 274
273 /* set lowest clock within static limits */ 275 /* set lowest clock within static limits */
274 pv.M1 = pll_lim.vco1.max_m; 276 pv.M1 = pll_lim.vco1.max_m;
275 pv.N1 = pll_lim.vco1.min_n; 277 pv.N1 = pll_lim.vco1.min_n;
276 pv.log2P = pll_lim.max_p_usable; 278 pv.log2P = pll_lim.max_p_usable;
277 nouveau_hw_setpll(dev, pll_lim.reg, &pv); 279 clk->pll_prog(clk, pll_lim.reg, &pv);
278} 280}
279 281
280/* 282/*
@@ -303,6 +305,7 @@ static void nouveau_vga_font_io(struct drm_device *dev,
303void 305void
304nouveau_hw_save_vga_fonts(struct drm_device *dev, bool save) 306nouveau_hw_save_vga_fonts(struct drm_device *dev, bool save)
305{ 307{
308 struct nouveau_drm *drm = nouveau_drm(dev);
306 uint8_t misc, gr4, gr5, gr6, seq2, seq4; 309 uint8_t misc, gr4, gr5, gr6, seq2, seq4;
307 bool graphicsmode; 310 bool graphicsmode;
308 unsigned plane; 311 unsigned plane;
@@ -318,12 +321,12 @@ nouveau_hw_save_vga_fonts(struct drm_device *dev, bool save)
318 if (graphicsmode) /* graphics mode => framebuffer => no need to save */ 321 if (graphicsmode) /* graphics mode => framebuffer => no need to save */
319 return; 322 return;
320 323
321 NV_INFO(dev, "%sing VGA fonts\n", save ? "Sav" : "Restor"); 324 NV_INFO(drm, "%sing VGA fonts\n", save ? "Sav" : "Restor");
322 325
323 /* map first 64KiB of VRAM, holds VGA fonts etc */ 326 /* map first 64KiB of VRAM, holds VGA fonts etc */
324 iovram = ioremap(pci_resource_start(dev->pdev, 1), 65536); 327 iovram = ioremap(pci_resource_start(dev->pdev, 1), 65536);
325 if (!iovram) { 328 if (!iovram) {
326 NV_ERROR(dev, "Failed to map VRAM, " 329 NV_ERROR(drm, "Failed to map VRAM, "
327 "cannot save/restore VGA fonts.\n"); 330 "cannot save/restore VGA fonts.\n");
328 return; 331 return;
329 } 332 }
@@ -386,25 +389,25 @@ static void
386nv_save_state_ramdac(struct drm_device *dev, int head, 389nv_save_state_ramdac(struct drm_device *dev, int head,
387 struct nv04_mode_state *state) 390 struct nv04_mode_state *state)
388{ 391{
389 struct drm_nouveau_private *dev_priv = dev->dev_private; 392 struct nouveau_drm *drm = nouveau_drm(dev);
390 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 393 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
391 int i; 394 int i;
392 395
393 if (dev_priv->card_type >= NV_10) 396 if (nv_device(drm->device)->card_type >= NV_10)
394 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC); 397 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC);
395 398
396 nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, &regp->pllvals); 399 nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, &regp->pllvals);
397 state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT); 400 state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT);
398 if (nv_two_heads(dev)) 401 if (nv_two_heads(dev))
399 state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK); 402 state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
400 if (dev_priv->chipset == 0x11) 403 if (nv_device(drm->device)->chipset == 0x11)
401 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11); 404 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11);
402 405
403 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL); 406 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL);
404 407
405 if (nv_gf4_disp_arch(dev)) 408 if (nv_gf4_disp_arch(dev))
406 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630); 409 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630);
407 if (dev_priv->chipset >= 0x30) 410 if (nv_device(drm->device)->chipset >= 0x30)
408 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634); 411 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634);
409 412
410 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP); 413 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP);
@@ -446,7 +449,7 @@ nv_save_state_ramdac(struct drm_device *dev, int head,
446 if (nv_gf4_disp_arch(dev)) 449 if (nv_gf4_disp_arch(dev))
447 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0); 450 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0);
448 451
449 if (dev_priv->card_type == NV_40) { 452 if (nv_device(drm->device)->card_type == NV_40) {
450 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20); 453 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20);
451 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24); 454 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24);
452 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34); 455 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34);
@@ -461,26 +464,27 @@ static void
461nv_load_state_ramdac(struct drm_device *dev, int head, 464nv_load_state_ramdac(struct drm_device *dev, int head,
462 struct nv04_mode_state *state) 465 struct nv04_mode_state *state)
463{ 466{
464 struct drm_nouveau_private *dev_priv = dev->dev_private; 467 struct nouveau_drm *drm = nouveau_drm(dev);
468 struct nouveau_clock *clk = nouveau_clock(drm->device);
465 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 469 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
466 uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF; 470 uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
467 int i; 471 int i;
468 472
469 if (dev_priv->card_type >= NV_10) 473 if (nv_device(drm->device)->card_type >= NV_10)
470 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync); 474 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
471 475
472 nouveau_hw_setpll(dev, pllreg, &regp->pllvals); 476 clk->pll_prog(clk, pllreg, &regp->pllvals);
473 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel); 477 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel);
474 if (nv_two_heads(dev)) 478 if (nv_two_heads(dev))
475 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk); 479 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk);
476 if (dev_priv->chipset == 0x11) 480 if (nv_device(drm->device)->chipset == 0x11)
477 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither); 481 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither);
478 482
479 NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl); 483 NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl);
480 484
481 if (nv_gf4_disp_arch(dev)) 485 if (nv_gf4_disp_arch(dev))
482 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630); 486 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630);
483 if (dev_priv->chipset >= 0x30) 487 if (nv_device(drm->device)->chipset >= 0x30)
484 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634); 488 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634);
485 489
486 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup); 490 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup);
@@ -517,7 +521,7 @@ nv_load_state_ramdac(struct drm_device *dev, int head,
517 if (nv_gf4_disp_arch(dev)) 521 if (nv_gf4_disp_arch(dev))
518 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0); 522 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0);
519 523
520 if (dev_priv->card_type == NV_40) { 524 if (nv_device(drm->device)->card_type == NV_40) {
521 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20); 525 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20);
522 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24); 526 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24);
523 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34); 527 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34);
@@ -582,7 +586,7 @@ static void
582nv_save_state_ext(struct drm_device *dev, int head, 586nv_save_state_ext(struct drm_device *dev, int head,
583 struct nv04_mode_state *state) 587 struct nv04_mode_state *state)
584{ 588{
585 struct drm_nouveau_private *dev_priv = dev->dev_private; 589 struct nouveau_drm *drm = nouveau_drm(dev);
586 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 590 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
587 int i; 591 int i;
588 592
@@ -598,10 +602,10 @@ nv_save_state_ext(struct drm_device *dev, int head,
598 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); 602 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
599 rd_cio_state(dev, head, regp, NV_CIO_CRE_21); 603 rd_cio_state(dev, head, regp, NV_CIO_CRE_21);
600 604
601 if (dev_priv->card_type >= NV_20) 605 if (nv_device(drm->device)->card_type >= NV_20)
602 rd_cio_state(dev, head, regp, NV_CIO_CRE_47); 606 rd_cio_state(dev, head, regp, NV_CIO_CRE_47);
603 607
604 if (dev_priv->card_type >= NV_30) 608 if (nv_device(drm->device)->card_type >= NV_30)
605 rd_cio_state(dev, head, regp, 0x9f); 609 rd_cio_state(dev, head, regp, 0x9f);
606 610
607 rd_cio_state(dev, head, regp, NV_CIO_CRE_49); 611 rd_cio_state(dev, head, regp, NV_CIO_CRE_49);
@@ -610,14 +614,14 @@ nv_save_state_ext(struct drm_device *dev, int head,
610 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); 614 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
611 rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); 615 rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
612 616
613 if (dev_priv->card_type >= NV_10) { 617 if (nv_device(drm->device)->card_type >= NV_10) {
614 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830); 618 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830);
615 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834); 619 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834);
616 620
617 if (dev_priv->card_type >= NV_30) 621 if (nv_device(drm->device)->card_type >= NV_30)
618 regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT); 622 regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT);
619 623
620 if (dev_priv->card_type == NV_40) 624 if (nv_device(drm->device)->card_type == NV_40)
621 regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850); 625 regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850);
622 626
623 if (nv_two_heads(dev)) 627 if (nv_two_heads(dev))
@@ -629,7 +633,7 @@ nv_save_state_ext(struct drm_device *dev, int head,
629 633
630 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); 634 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
631 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); 635 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
632 if (dev_priv->card_type >= NV_10) { 636 if (nv_device(drm->device)->card_type >= NV_10) {
633 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); 637 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
634 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB); 638 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
635 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B); 639 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B);
@@ -657,12 +661,14 @@ static void
657nv_load_state_ext(struct drm_device *dev, int head, 661nv_load_state_ext(struct drm_device *dev, int head,
658 struct nv04_mode_state *state) 662 struct nv04_mode_state *state)
659{ 663{
660 struct drm_nouveau_private *dev_priv = dev->dev_private; 664 struct nouveau_drm *drm = nouveau_drm(dev);
665 struct nouveau_device *device = nv_device(drm->device);
666 struct nouveau_timer *ptimer = nouveau_timer(device);
661 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 667 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
662 uint32_t reg900; 668 uint32_t reg900;
663 int i; 669 int i;
664 670
665 if (dev_priv->card_type >= NV_10) { 671 if (nv_device(drm->device)->card_type >= NV_10) {
666 if (nv_two_heads(dev)) 672 if (nv_two_heads(dev))
667 /* setting ENGINE_CTRL (EC) *must* come before 673 /* setting ENGINE_CTRL (EC) *must* come before
668 * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in 674 * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in
@@ -670,24 +676,24 @@ nv_load_state_ext(struct drm_device *dev, int head,
670 */ 676 */
671 NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl); 677 NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl);
672 678
673 nv_wr32(dev, NV_PVIDEO_STOP, 1); 679 nv_wr32(device, NV_PVIDEO_STOP, 1);
674 nv_wr32(dev, NV_PVIDEO_INTR_EN, 0); 680 nv_wr32(device, NV_PVIDEO_INTR_EN, 0);
675 nv_wr32(dev, NV_PVIDEO_OFFSET_BUFF(0), 0); 681 nv_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0);
676 nv_wr32(dev, NV_PVIDEO_OFFSET_BUFF(1), 0); 682 nv_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0);
677 nv_wr32(dev, NV_PVIDEO_LIMIT(0), 0); //dev_priv->fb_available_size - 1); 683 nv_wr32(device, NV_PVIDEO_LIMIT(0), 0); //drm->fb_available_size - 1);
678 nv_wr32(dev, NV_PVIDEO_LIMIT(1), 0); //dev_priv->fb_available_size - 1); 684 nv_wr32(device, NV_PVIDEO_LIMIT(1), 0); //drm->fb_available_size - 1);
679 nv_wr32(dev, NV_PVIDEO_UVPLANE_LIMIT(0), 0); //dev_priv->fb_available_size - 1); 685 nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), 0); //drm->fb_available_size - 1);
680 nv_wr32(dev, NV_PVIDEO_UVPLANE_LIMIT(1), 0); //dev_priv->fb_available_size - 1); 686 nv_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), 0); //drm->fb_available_size - 1);
681 nv_wr32(dev, NV_PBUS_POWERCTRL_2, 0); 687 nv_wr32(device, NV_PBUS_POWERCTRL_2, 0);
682 688
683 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg); 689 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);
684 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830); 690 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830);
685 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834); 691 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834);
686 692
687 if (dev_priv->card_type >= NV_30) 693 if (nv_device(drm->device)->card_type >= NV_30)
688 NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext); 694 NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
689 695
690 if (dev_priv->card_type == NV_40) { 696 if (nv_device(drm->device)->card_type == NV_40) {
691 NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850); 697 NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850);
692 698
693 reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900); 699 reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900);
@@ -710,23 +716,23 @@ nv_load_state_ext(struct drm_device *dev, int head,
710 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); 716 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
711 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); 717 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
712 718
713 if (dev_priv->card_type >= NV_20) 719 if (nv_device(drm->device)->card_type >= NV_20)
714 wr_cio_state(dev, head, regp, NV_CIO_CRE_47); 720 wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
715 721
716 if (dev_priv->card_type >= NV_30) 722 if (nv_device(drm->device)->card_type >= NV_30)
717 wr_cio_state(dev, head, regp, 0x9f); 723 wr_cio_state(dev, head, regp, 0x9f);
718 724
719 wr_cio_state(dev, head, regp, NV_CIO_CRE_49); 725 wr_cio_state(dev, head, regp, NV_CIO_CRE_49);
720 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); 726 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
721 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); 727 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
722 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); 728 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
723 if (dev_priv->card_type == NV_40) 729 if (nv_device(drm->device)->card_type == NV_40)
724 nv_fix_nv40_hw_cursor(dev, head); 730 nv_fix_nv40_hw_cursor(dev, head);
725 wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); 731 wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
726 732
727 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); 733 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
728 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); 734 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
729 if (dev_priv->card_type >= NV_10) { 735 if (nv_device(drm->device)->card_type >= NV_10) {
730 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); 736 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
731 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB); 737 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
732 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B); 738 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B);
@@ -734,11 +740,11 @@ nv_load_state_ext(struct drm_device *dev, int head,
734 } 740 }
735 /* NV11 and NV20 stop at 0x52. */ 741 /* NV11 and NV20 stop at 0x52. */
736 if (nv_gf4_disp_arch(dev)) { 742 if (nv_gf4_disp_arch(dev)) {
737 if (dev_priv->card_type == NV_10) { 743 if (nv_device(drm->device)->card_type == NV_10) {
738 /* Not waiting for vertical retrace before modifying 744 /* Not waiting for vertical retrace before modifying
739 CRE_53/CRE_54 causes lockups. */ 745 CRE_53/CRE_54 causes lockups. */
740 nouveau_wait_eq(dev, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8); 746 nouveau_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8);
741 nouveau_wait_eq(dev, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0); 747 nouveau_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0);
742 } 748 }
743 749
744 wr_cio_state(dev, head, regp, NV_CIO_CRE_42); 750 wr_cio_state(dev, head, regp, NV_CIO_CRE_42);
@@ -761,14 +767,15 @@ static void
761nv_save_state_palette(struct drm_device *dev, int head, 767nv_save_state_palette(struct drm_device *dev, int head,
762 struct nv04_mode_state *state) 768 struct nv04_mode_state *state)
763{ 769{
770 struct nouveau_device *device = nouveau_dev(dev);
764 int head_offset = head * NV_PRMDIO_SIZE, i; 771 int head_offset = head * NV_PRMDIO_SIZE, i;
765 772
766 nv_wr08(dev, NV_PRMDIO_PIXEL_MASK + head_offset, 773 nv_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
767 NV_PRMDIO_PIXEL_MASK_MASK); 774 NV_PRMDIO_PIXEL_MASK_MASK);
768 nv_wr08(dev, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0); 775 nv_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0);
769 776
770 for (i = 0; i < 768; i++) { 777 for (i = 0; i < 768; i++) {
771 state->crtc_reg[head].DAC[i] = nv_rd08(dev, 778 state->crtc_reg[head].DAC[i] = nv_rd08(device,
772 NV_PRMDIO_PALETTE_DATA + head_offset); 779 NV_PRMDIO_PALETTE_DATA + head_offset);
773 } 780 }
774 781
@@ -779,14 +786,15 @@ void
779nouveau_hw_load_state_palette(struct drm_device *dev, int head, 786nouveau_hw_load_state_palette(struct drm_device *dev, int head,
780 struct nv04_mode_state *state) 787 struct nv04_mode_state *state)
781{ 788{
789 struct nouveau_device *device = nouveau_dev(dev);
782 int head_offset = head * NV_PRMDIO_SIZE, i; 790 int head_offset = head * NV_PRMDIO_SIZE, i;
783 791
784 nv_wr08(dev, NV_PRMDIO_PIXEL_MASK + head_offset, 792 nv_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
785 NV_PRMDIO_PIXEL_MASK_MASK); 793 NV_PRMDIO_PIXEL_MASK_MASK);
786 nv_wr08(dev, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0); 794 nv_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0);
787 795
788 for (i = 0; i < 768; i++) { 796 for (i = 0; i < 768; i++) {
789 nv_wr08(dev, NV_PRMDIO_PALETTE_DATA + head_offset, 797 nv_wr08(device, NV_PRMDIO_PALETTE_DATA + head_offset,
790 state->crtc_reg[head].DAC[i]); 798 state->crtc_reg[head].DAC[i]);
791 } 799 }
792 800
@@ -796,9 +804,9 @@ nouveau_hw_load_state_palette(struct drm_device *dev, int head,
796void nouveau_hw_save_state(struct drm_device *dev, int head, 804void nouveau_hw_save_state(struct drm_device *dev, int head,
797 struct nv04_mode_state *state) 805 struct nv04_mode_state *state)
798{ 806{
799 struct drm_nouveau_private *dev_priv = dev->dev_private; 807 struct nouveau_drm *drm = nouveau_drm(dev);
800 808
801 if (dev_priv->chipset == 0x11) 809 if (nv_device(drm->device)->chipset == 0x11)
802 /* NB: no attempt is made to restore the bad pll later on */ 810 /* NB: no attempt is made to restore the bad pll later on */
803 nouveau_hw_fix_bad_vpll(dev, head); 811 nouveau_hw_fix_bad_vpll(dev, head);
804 nv_save_state_ramdac(dev, head, state); 812 nv_save_state_ramdac(dev, head, state);
diff --git a/drivers/gpu/drm/nouveau/nouveau_hw.h b/drivers/gpu/drm/nouveau/nouveau_hw.h
index b1c22b788be8..ba8fc0f9e0db 100644
--- a/drivers/gpu/drm/nouveau/nouveau_hw.h
+++ b/drivers/gpu/drm/nouveau/nouveau_hw.h
@@ -24,7 +24,6 @@
24#define __NOUVEAU_HW_H__ 24#define __NOUVEAU_HW_H__
25 25
26#include "drmP.h" 26#include "drmP.h"
27#include "nouveau_drv.h"
28#include "nv04_display.h" 27#include "nv04_display.h"
29 28
30#include <subdev/bios/pll.h> 29#include <subdev/bios/pll.h>
@@ -60,37 +59,41 @@ extern void nouveau_calc_arb(struct drm_device *, int vclk, int bpp,
60static inline uint32_t NVReadCRTC(struct drm_device *dev, 59static inline uint32_t NVReadCRTC(struct drm_device *dev,
61 int head, uint32_t reg) 60 int head, uint32_t reg)
62{ 61{
62 struct nouveau_device *device = nouveau_dev(dev);
63 uint32_t val; 63 uint32_t val;
64 if (head) 64 if (head)
65 reg += NV_PCRTC0_SIZE; 65 reg += NV_PCRTC0_SIZE;
66 val = nv_rd32(dev, reg); 66 val = nv_rd32(device, reg);
67 return val; 67 return val;
68} 68}
69 69
70static inline void NVWriteCRTC(struct drm_device *dev, 70static inline void NVWriteCRTC(struct drm_device *dev,
71 int head, uint32_t reg, uint32_t val) 71 int head, uint32_t reg, uint32_t val)
72{ 72{
73 struct nouveau_device *device = nouveau_dev(dev);
73 if (head) 74 if (head)
74 reg += NV_PCRTC0_SIZE; 75 reg += NV_PCRTC0_SIZE;
75 nv_wr32(dev, reg, val); 76 nv_wr32(device, reg, val);
76} 77}
77 78
78static inline uint32_t NVReadRAMDAC(struct drm_device *dev, 79static inline uint32_t NVReadRAMDAC(struct drm_device *dev,
79 int head, uint32_t reg) 80 int head, uint32_t reg)
80{ 81{
82 struct nouveau_device *device = nouveau_dev(dev);
81 uint32_t val; 83 uint32_t val;
82 if (head) 84 if (head)
83 reg += NV_PRAMDAC0_SIZE; 85 reg += NV_PRAMDAC0_SIZE;
84 val = nv_rd32(dev, reg); 86 val = nv_rd32(device, reg);
85 return val; 87 return val;
86} 88}
87 89
88static inline void NVWriteRAMDAC(struct drm_device *dev, 90static inline void NVWriteRAMDAC(struct drm_device *dev,
89 int head, uint32_t reg, uint32_t val) 91 int head, uint32_t reg, uint32_t val)
90{ 92{
93 struct nouveau_device *device = nouveau_dev(dev);
91 if (head) 94 if (head)
92 reg += NV_PRAMDAC0_SIZE; 95 reg += NV_PRAMDAC0_SIZE;
93 nv_wr32(dev, reg, val); 96 nv_wr32(device, reg, val);
94} 97}
95 98
96static inline uint8_t nv_read_tmds(struct drm_device *dev, 99static inline uint8_t nv_read_tmds(struct drm_device *dev,
@@ -116,16 +119,18 @@ static inline void nv_write_tmds(struct drm_device *dev,
116static inline void NVWriteVgaCrtc(struct drm_device *dev, 119static inline void NVWriteVgaCrtc(struct drm_device *dev,
117 int head, uint8_t index, uint8_t value) 120 int head, uint8_t index, uint8_t value)
118{ 121{
119 nv_wr08(dev, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index); 122 struct nouveau_device *device = nouveau_dev(dev);
120 nv_wr08(dev, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value); 123 nv_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
124 nv_wr08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value);
121} 125}
122 126
123static inline uint8_t NVReadVgaCrtc(struct drm_device *dev, 127static inline uint8_t NVReadVgaCrtc(struct drm_device *dev,
124 int head, uint8_t index) 128 int head, uint8_t index)
125{ 129{
130 struct nouveau_device *device = nouveau_dev(dev);
126 uint8_t val; 131 uint8_t val;
127 nv_wr08(dev, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index); 132 nv_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
128 val = nv_rd08(dev, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE); 133 val = nv_rd08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE);
129 return val; 134 return val;
130} 135}
131 136
@@ -159,68 +164,74 @@ static inline uint8_t NVReadVgaCrtc5758(struct drm_device *dev, int head, uint8_
159static inline uint8_t NVReadPRMVIO(struct drm_device *dev, 164static inline uint8_t NVReadPRMVIO(struct drm_device *dev,
160 int head, uint32_t reg) 165 int head, uint32_t reg)
161{ 166{
162 struct drm_nouveau_private *dev_priv = dev->dev_private; 167 struct nouveau_device *device = nouveau_dev(dev);
168 struct nouveau_drm *drm = nouveau_drm(dev);
163 uint8_t val; 169 uint8_t val;
164 170
165 /* Only NV4x have two pvio ranges; other twoHeads cards MUST call 171 /* Only NV4x have two pvio ranges; other twoHeads cards MUST call
166 * NVSetOwner for the relevant head to be programmed */ 172 * NVSetOwner for the relevant head to be programmed */
167 if (head && dev_priv->card_type == NV_40) 173 if (head && nv_device(drm->device)->card_type == NV_40)
168 reg += NV_PRMVIO_SIZE; 174 reg += NV_PRMVIO_SIZE;
169 175
170 val = nv_rd08(dev, reg); 176 val = nv_rd08(device, reg);
171 return val; 177 return val;
172} 178}
173 179
174static inline void NVWritePRMVIO(struct drm_device *dev, 180static inline void NVWritePRMVIO(struct drm_device *dev,
175 int head, uint32_t reg, uint8_t value) 181 int head, uint32_t reg, uint8_t value)
176{ 182{
177 struct drm_nouveau_private *dev_priv = dev->dev_private; 183 struct nouveau_device *device = nouveau_dev(dev);
184 struct nouveau_drm *drm = nouveau_drm(dev);
178 185
179 /* Only NV4x have two pvio ranges; other twoHeads cards MUST call 186 /* Only NV4x have two pvio ranges; other twoHeads cards MUST call
180 * NVSetOwner for the relevant head to be programmed */ 187 * NVSetOwner for the relevant head to be programmed */
181 if (head && dev_priv->card_type == NV_40) 188 if (head && nv_device(drm->device)->card_type == NV_40)
182 reg += NV_PRMVIO_SIZE; 189 reg += NV_PRMVIO_SIZE;
183 190
184 nv_wr08(dev, reg, value); 191 nv_wr08(device, reg, value);
185} 192}
186 193
187static inline void NVSetEnablePalette(struct drm_device *dev, int head, bool enable) 194static inline void NVSetEnablePalette(struct drm_device *dev, int head, bool enable)
188{ 195{
189 nv_rd08(dev, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE); 196 struct nouveau_device *device = nouveau_dev(dev);
190 nv_wr08(dev, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20); 197 nv_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
198 nv_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20);
191} 199}
192 200
193static inline bool NVGetEnablePalette(struct drm_device *dev, int head) 201static inline bool NVGetEnablePalette(struct drm_device *dev, int head)
194{ 202{
195 nv_rd08(dev, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE); 203 struct nouveau_device *device = nouveau_dev(dev);
196 return !(nv_rd08(dev, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20); 204 nv_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
205 return !(nv_rd08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20);
197} 206}
198 207
199static inline void NVWriteVgaAttr(struct drm_device *dev, 208static inline void NVWriteVgaAttr(struct drm_device *dev,
200 int head, uint8_t index, uint8_t value) 209 int head, uint8_t index, uint8_t value)
201{ 210{
211 struct nouveau_device *device = nouveau_dev(dev);
202 if (NVGetEnablePalette(dev, head)) 212 if (NVGetEnablePalette(dev, head))
203 index &= ~0x20; 213 index &= ~0x20;
204 else 214 else
205 index |= 0x20; 215 index |= 0x20;
206 216
207 nv_rd08(dev, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE); 217 nv_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
208 nv_wr08(dev, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index); 218 nv_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
209 nv_wr08(dev, NV_PRMCIO_AR__WRITE + head * NV_PRMCIO_SIZE, value); 219 nv_wr08(device, NV_PRMCIO_AR__WRITE + head * NV_PRMCIO_SIZE, value);
210} 220}
211 221
212static inline uint8_t NVReadVgaAttr(struct drm_device *dev, 222static inline uint8_t NVReadVgaAttr(struct drm_device *dev,
213 int head, uint8_t index) 223 int head, uint8_t index)
214{ 224{
225 struct nouveau_device *device = nouveau_dev(dev);
215 uint8_t val; 226 uint8_t val;
216 if (NVGetEnablePalette(dev, head)) 227 if (NVGetEnablePalette(dev, head))
217 index &= ~0x20; 228 index &= ~0x20;
218 else 229 else
219 index |= 0x20; 230 index |= 0x20;
220 231
221 nv_rd08(dev, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE); 232 nv_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
222 nv_wr08(dev, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index); 233 nv_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
223 val = nv_rd08(dev, NV_PRMCIO_AR__READ + head * NV_PRMCIO_SIZE); 234 val = nv_rd08(device, NV_PRMCIO_AR__READ + head * NV_PRMCIO_SIZE);
224 return val; 235 return val;
225} 236}
226 237
@@ -247,10 +258,11 @@ static inline void NVVgaProtect(struct drm_device *dev, int head, bool protect)
247static inline bool 258static inline bool
248nv_heads_tied(struct drm_device *dev) 259nv_heads_tied(struct drm_device *dev)
249{ 260{
250 struct drm_nouveau_private *dev_priv = dev->dev_private; 261 struct nouveau_device *device = nouveau_dev(dev);
262 struct nouveau_drm *drm = nouveau_drm(dev);
251 263
252 if (dev_priv->chipset == 0x11) 264 if (nv_device(drm->device)->chipset == 0x11)
253 return !!(nv_rd32(dev, NV_PBUS_DEBUG_1) & (1 << 28)); 265 return !!(nv_rd32(device, NV_PBUS_DEBUG_1) & (1 << 28));
254 266
255 return NVReadVgaCrtc(dev, 0, NV_CIO_CRE_44) & 0x4; 267 return NVReadVgaCrtc(dev, 0, NV_CIO_CRE_44) & 0x4;
256} 268}
@@ -299,13 +311,13 @@ nv_lock_vga_crtc_shadow(struct drm_device *dev, int head, int lock)
299static inline bool 311static inline bool
300NVLockVgaCrtcs(struct drm_device *dev, bool lock) 312NVLockVgaCrtcs(struct drm_device *dev, bool lock)
301{ 313{
302 struct drm_nouveau_private *dev_priv = dev->dev_private; 314 struct nouveau_drm *drm = nouveau_drm(dev);
303 bool waslocked = !NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX); 315 bool waslocked = !NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX);
304 316
305 NVWriteVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX, 317 NVWriteVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX,
306 lock ? NV_CIO_SR_LOCK_VALUE : NV_CIO_SR_UNLOCK_RW_VALUE); 318 lock ? NV_CIO_SR_LOCK_VALUE : NV_CIO_SR_UNLOCK_RW_VALUE);
307 /* NV11 has independently lockable extended crtcs, except when tied */ 319 /* NV11 has independently lockable extended crtcs, except when tied */
308 if (dev_priv->chipset == 0x11 && !nv_heads_tied(dev)) 320 if (nv_device(drm->device)->chipset == 0x11 && !nv_heads_tied(dev))
309 NVWriteVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX, 321 NVWriteVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX,
310 lock ? NV_CIO_SR_LOCK_VALUE : 322 lock ? NV_CIO_SR_LOCK_VALUE :
311 NV_CIO_SR_UNLOCK_RW_VALUE); 323 NV_CIO_SR_UNLOCK_RW_VALUE);
@@ -320,9 +332,9 @@ NVLockVgaCrtcs(struct drm_device *dev, bool lock)
320 332
321static inline int nv_cursor_width(struct drm_device *dev) 333static inline int nv_cursor_width(struct drm_device *dev)
322{ 334{
323 struct drm_nouveau_private *dev_priv = dev->dev_private; 335 struct nouveau_drm *drm = nouveau_drm(dev);
324 336
325 return dev_priv->card_type >= NV_10 ? NV10_CURSOR_SIZE : NV04_CURSOR_SIZE; 337 return nv_device(drm->device)->card_type >= NV_10 ? NV10_CURSOR_SIZE : NV04_CURSOR_SIZE;
326} 338}
327 339
328static inline void 340static inline void
@@ -340,11 +352,11 @@ nv_fix_nv40_hw_cursor(struct drm_device *dev, int head)
340static inline void 352static inline void
341nv_set_crtc_base(struct drm_device *dev, int head, uint32_t offset) 353nv_set_crtc_base(struct drm_device *dev, int head, uint32_t offset)
342{ 354{
343 struct drm_nouveau_private *dev_priv = dev->dev_private; 355 struct nouveau_drm *drm = nouveau_drm(dev);
344 356
345 NVWriteCRTC(dev, head, NV_PCRTC_START, offset); 357 NVWriteCRTC(dev, head, NV_PCRTC_START, offset);
346 358
347 if (dev_priv->card_type == NV_04) { 359 if (nv_device(drm->device)->card_type == NV_04) {
348 /* 360 /*
349 * Hilarious, the 24th bit doesn't want to stick to 361 * Hilarious, the 24th bit doesn't want to stick to
350 * PCRTC_START... 362 * PCRTC_START...
@@ -359,7 +371,7 @@ nv_set_crtc_base(struct drm_device *dev, int head, uint32_t offset)
359static inline void 371static inline void
360nv_show_cursor(struct drm_device *dev, int head, bool show) 372nv_show_cursor(struct drm_device *dev, int head, bool show)
361{ 373{
362 struct drm_nouveau_private *dev_priv = dev->dev_private; 374 struct nouveau_drm *drm = nouveau_drm(dev);
363 uint8_t *curctl1 = 375 uint8_t *curctl1 =
364 &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX]; 376 &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];
365 377
@@ -369,14 +381,14 @@ nv_show_cursor(struct drm_device *dev, int head, bool show)
369 *curctl1 &= ~MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE); 381 *curctl1 &= ~MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE);
370 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, *curctl1); 382 NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, *curctl1);
371 383
372 if (dev_priv->card_type == NV_40) 384 if (nv_device(drm->device)->card_type == NV_40)
373 nv_fix_nv40_hw_cursor(dev, head); 385 nv_fix_nv40_hw_cursor(dev, head);
374} 386}
375 387
376static inline uint32_t 388static inline uint32_t
377nv_pitch_align(struct drm_device *dev, uint32_t width, int bpp) 389nv_pitch_align(struct drm_device *dev, uint32_t width, int bpp)
378{ 390{
379 struct drm_nouveau_private *dev_priv = dev->dev_private; 391 struct nouveau_drm *drm = nouveau_drm(dev);
380 int mask; 392 int mask;
381 393
382 if (bpp == 15) 394 if (bpp == 15)
@@ -385,7 +397,7 @@ nv_pitch_align(struct drm_device *dev, uint32_t width, int bpp)
385 bpp = 8; 397 bpp = 8;
386 398
387 /* Alignment requirements taken from the Haiku driver */ 399 /* Alignment requirements taken from the Haiku driver */
388 if (dev_priv->card_type == NV_04) 400 if (nv_device(drm->device)->card_type == NV_04)
389 mask = 128 / bpp - 1; 401 mask = 128 / bpp - 1;
390 else 402 else
391 mask = 512 / bpp - 1; 403 mask = 512 / bpp - 1;
diff --git a/drivers/gpu/drm/nouveau/nouveau_irq.c b/drivers/gpu/drm/nouveau/nouveau_irq.c
index d5281499744b..af0cfe81da69 100644
--- a/drivers/gpu/drm/nouveau/nouveau_irq.c
+++ b/drivers/gpu/drm/nouveau/nouveau_irq.c
@@ -1,145 +1,85 @@
1/* 1/*
2 * Copyright (C) 2006 Ben Skeggs. 2 * Copyright 2012 Red Hat Inc.
3 * 3 *
4 * All Rights Reserved. 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
5 * 10 *
6 * Permission is hereby granted, free of charge, to any person obtaining 11 * The above copyright notice and this permission notice shall be included in
7 * a copy of this software and associated documentation files (the 12 * all copies or substantial portions of the Software.
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 * 13 *
14 * The above copyright notice and this permission notice (including the 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * next paragraph) shall be included in all copies or substantial 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * portions of the Software. 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * OTHER DEALINGS IN THE SOFTWARE.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * 21 *
22 * Authors: Ben Skeggs
26 */ 23 */
27 24
28/* 25#include <subdev/mc.h>
29 * Authors:
30 * Ben Skeggs <darktama@iinet.net.au>
31 */
32 26
33#include "drmP.h" 27#include "nouveau_drm.h"
34#include "drm.h" 28#include "nv50_display.h"
35#include <nouveau_drm.h>
36#include "nouveau_drv.h"
37#include "nouveau_reg.h"
38 29
39void 30void
40nouveau_irq_preinstall(struct drm_device *dev) 31nouveau_irq_preinstall(struct drm_device *dev)
41{ 32{
42 /* Master disable */ 33 nv_wr32(nouveau_dev(dev), 0x000140, 0x00000000);
43 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
44} 34}
45 35
46int 36int
47nouveau_irq_postinstall(struct drm_device *dev) 37nouveau_irq_postinstall(struct drm_device *dev)
48{ 38{
49 struct drm_nouveau_private *dev_priv = dev->dev_private; 39 nv_wr32(nouveau_dev(dev), 0x000140, 0x00000001);
50
51 /* Master enable */
52 nv_wr32(dev, NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE);
53 if (dev_priv->msi_enabled)
54 nv_wr08(dev, 0x00088068, 0xff);
55
56 return 0; 40 return 0;
57} 41}
58 42
59void 43void
60nouveau_irq_uninstall(struct drm_device *dev) 44nouveau_irq_uninstall(struct drm_device *dev)
61{ 45{
62 /* Master disable */ 46 nv_wr32(nouveau_dev(dev), 0x000140, 0x00000000);
63 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
64} 47}
65 48
66irqreturn_t 49irqreturn_t
67nouveau_irq_handler(DRM_IRQ_ARGS) 50nouveau_irq_handler(DRM_IRQ_ARGS)
68{ 51{
69 struct drm_device *dev = (struct drm_device *)arg; 52 struct drm_device *dev = arg;
70 struct drm_nouveau_private *dev_priv = dev->dev_private; 53 struct nouveau_device *device = nouveau_dev(dev);
71 unsigned long flags; 54 struct nouveau_mc *pmc = nouveau_mc(device);
72 u32 stat; 55 u32 stat;
73 int i;
74 56
75 stat = nv_rd32(dev, NV03_PMC_INTR_0); 57 stat = nv_rd32(device, 0x000100);
76 if (stat == 0 || stat == ~0) 58 if (stat == 0 || stat == ~0)
77 return IRQ_NONE; 59 return IRQ_NONE;
78 60
79 spin_lock_irqsave(&dev_priv->context_switch_lock, flags); 61 nv_subdev(pmc)->intr(nv_subdev(pmc));
80 for (i = 0; i < 32 && stat; i++) {
81 if (!(stat & (1 << i)) || !dev_priv->irq_handler[i])
82 continue;
83 62
84 dev_priv->irq_handler[i](dev); 63 if (device->card_type >= NV_D0) {
85 stat &= ~(1 << i); 64 if (nv_rd32(device, 0x000100) & 0x04000000)
65 nvd0_display_intr(dev);
66 } else
67 if (device->card_type >= NV_50) {
68 if (nv_rd32(device, 0x000100) & 0x04000000)
69 nv50_display_intr(dev);
86 } 70 }
87 71
88 nv_intr(dev);
89
90 if (dev_priv->msi_enabled)
91 nv_wr08(dev, 0x00088068, 0xff);
92 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
93
94 return IRQ_HANDLED; 72 return IRQ_HANDLED;
95} 73}
96 74
97int 75int
98nouveau_irq_init(struct drm_device *dev) 76nouveau_irq_init(struct drm_device *dev)
99{ 77{
100 struct drm_nouveau_private *dev_priv = dev->dev_private;
101 int ret;
102
103 if (nouveau_msi != 0 && dev_priv->card_type >= NV_50) {
104 ret = pci_enable_msi(dev->pdev);
105 if (ret == 0) {
106 NV_INFO(dev, "enabled MSI\n");
107 dev_priv->msi_enabled = true;
108 }
109 }
110
111 return drm_irq_install(dev); 78 return drm_irq_install(dev);
112} 79}
113 80
114void 81void
115nouveau_irq_fini(struct drm_device *dev) 82nouveau_irq_fini(struct drm_device *dev)
116{ 83{
117 struct drm_nouveau_private *dev_priv = dev->dev_private;
118
119 drm_irq_uninstall(dev); 84 drm_irq_uninstall(dev);
120 if (dev_priv->msi_enabled)
121 pci_disable_msi(dev->pdev);
122}
123
124void
125nouveau_irq_register(struct drm_device *dev, int status_bit,
126 void (*handler)(struct drm_device *))
127{
128 struct drm_nouveau_private *dev_priv = dev->dev_private;
129 unsigned long flags;
130
131 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
132 dev_priv->irq_handler[status_bit] = handler;
133 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
134}
135
136void
137nouveau_irq_unregister(struct drm_device *dev, int status_bit)
138{
139 struct drm_nouveau_private *dev_priv = dev->dev_private;
140 unsigned long flags;
141
142 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
143 dev_priv->irq_handler[status_bit] = NULL;
144 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
145} 85}
diff --git a/drivers/gpu/drm/nouveau/nouveau_irq.h b/drivers/gpu/drm/nouveau/nouveau_irq.h
new file mode 100644
index 000000000000..06714ad857bb
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_irq.h
@@ -0,0 +1,11 @@
1#ifndef __NOUVEAU_IRQ_H__
2#define __NOUVEAU_IRQ_H__
3
4extern int nouveau_irq_init(struct drm_device *);
5extern void nouveau_irq_fini(struct drm_device *);
6extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
7extern void nouveau_irq_preinstall(struct drm_device *);
8extern int nouveau_irq_postinstall(struct drm_device *);
9extern void nouveau_irq_uninstall(struct drm_device *);
10
11#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 220c1a877ff5..8f8f421367bc 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -30,20 +30,19 @@
30 * Roy Spliet <r.spliet@student.tudelft.nl> 30 * Roy Spliet <r.spliet@student.tudelft.nl>
31 */ 31 */
32 32
33 33#include "nouveau_drm.h"
34#include "drmP.h"
35#include "drm.h"
36#include "drm_sarea.h"
37
38#include "nouveau_drv.h"
39#include "nouveau_pm.h" 34#include "nouveau_pm.h"
40 35
36#include <subdev/fb.h>
37
41static int 38static int
42nv40_mem_timing_calc(struct drm_device *dev, u32 freq, 39nv40_mem_timing_calc(struct drm_device *dev, u32 freq,
43 struct nouveau_pm_tbl_entry *e, u8 len, 40 struct nouveau_pm_tbl_entry *e, u8 len,
44 struct nouveau_pm_memtiming *boot, 41 struct nouveau_pm_memtiming *boot,
45 struct nouveau_pm_memtiming *t) 42 struct nouveau_pm_memtiming *t)
46{ 43{
44 struct nouveau_drm *drm = nouveau_drm(dev);
45
47 t->reg[0] = (e->tRP << 24 | e->tRAS << 16 | e->tRFC << 8 | e->tRC); 46 t->reg[0] = (e->tRP << 24 | e->tRAS << 16 | e->tRFC << 8 | e->tRC);
48 47
49 /* XXX: I don't trust the -1's and +1's... they must come 48 /* XXX: I don't trust the -1's and +1's... they must come
@@ -59,7 +58,7 @@ nv40_mem_timing_calc(struct drm_device *dev, u32 freq,
59 e->tRCDWR << 8 | 58 e->tRCDWR << 8 |
60 e->tRCDRD); 59 e->tRCDRD);
61 60
62 NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x\n", t->id, 61 NV_DEBUG(drm, "Entry %d: 220: %08x %08x %08x\n", t->id,
63 t->reg[0], t->reg[1], t->reg[2]); 62 t->reg[0], t->reg[1], t->reg[2]);
64 return 0; 63 return 0;
65} 64}
@@ -70,6 +69,9 @@ nv50_mem_timing_calc(struct drm_device *dev, u32 freq,
70 struct nouveau_pm_memtiming *boot, 69 struct nouveau_pm_memtiming *boot,
71 struct nouveau_pm_memtiming *t) 70 struct nouveau_pm_memtiming *t)
72{ 71{
72 struct nouveau_device *device = nouveau_dev(dev);
73 struct nouveau_fb *pfb = nouveau_fb(device);
74 struct nouveau_drm *drm = nouveau_drm(dev);
73 struct bit_entry P; 75 struct bit_entry P;
74 uint8_t unk18 = 1, unk20 = 0, unk21 = 0, tmp7_3; 76 uint8_t unk18 = 1, unk20 = 0, unk21 = 0, tmp7_3;
75 77
@@ -123,7 +125,7 @@ nv50_mem_timing_calc(struct drm_device *dev, u32 freq,
123 t->reg[7] = 0x4000202 | (e->tCL - 1) << 16; 125 t->reg[7] = 0x4000202 | (e->tCL - 1) << 16;
124 126
125 /* XXX: P.version == 1 only has DDR2 and GDDR3? */ 127 /* XXX: P.version == 1 only has DDR2 and GDDR3? */
126 if (nvfb_vram_type(dev) == NV_MEM_TYPE_DDR2) { 128 if (pfb->ram.type == NV_MEM_TYPE_DDR2) {
127 t->reg[5] |= (e->tCL + 3) << 8; 129 t->reg[5] |= (e->tCL + 3) << 8;
128 t->reg[6] |= (t->tCWL - 2) << 8; 130 t->reg[6] |= (t->tCWL - 2) << 8;
129 t->reg[8] |= (e->tCL - 4); 131 t->reg[8] |= (e->tCL - 4);
@@ -156,11 +158,11 @@ nv50_mem_timing_calc(struct drm_device *dev, u32 freq,
156 0x202; 158 0x202;
157 } 159 }
158 160
159 NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", t->id, 161 NV_DEBUG(drm, "Entry %d: 220: %08x %08x %08x %08x\n", t->id,
160 t->reg[0], t->reg[1], t->reg[2], t->reg[3]); 162 t->reg[0], t->reg[1], t->reg[2], t->reg[3]);
161 NV_DEBUG(dev, " 230: %08x %08x %08x %08x\n", 163 NV_DEBUG(drm, " 230: %08x %08x %08x %08x\n",
162 t->reg[4], t->reg[5], t->reg[6], t->reg[7]); 164 t->reg[4], t->reg[5], t->reg[6], t->reg[7]);
163 NV_DEBUG(dev, " 240: %08x\n", t->reg[8]); 165 NV_DEBUG(drm, " 240: %08x\n", t->reg[8]);
164 return 0; 166 return 0;
165} 167}
166 168
@@ -170,6 +172,8 @@ nvc0_mem_timing_calc(struct drm_device *dev, u32 freq,
170 struct nouveau_pm_memtiming *boot, 172 struct nouveau_pm_memtiming *boot,
171 struct nouveau_pm_memtiming *t) 173 struct nouveau_pm_memtiming *t)
172{ 174{
175 struct nouveau_drm *drm = nouveau_drm(dev);
176
173 if (e->tCWL > 0) 177 if (e->tCWL > 0)
174 t->tCWL = e->tCWL; 178 t->tCWL = e->tCWL;
175 179
@@ -192,9 +196,9 @@ nvc0_mem_timing_calc(struct drm_device *dev, u32 freq,
192 t->reg[4] = (boot->reg[4] & 0xfff00fff) | 196 t->reg[4] = (boot->reg[4] & 0xfff00fff) |
193 (e->tRRD&0x1f) << 15; 197 (e->tRRD&0x1f) << 15;
194 198
195 NV_DEBUG(dev, "Entry %d: 290: %08x %08x %08x %08x\n", t->id, 199 NV_DEBUG(drm, "Entry %d: 290: %08x %08x %08x %08x\n", t->id,
196 t->reg[0], t->reg[1], t->reg[2], t->reg[3]); 200 t->reg[0], t->reg[1], t->reg[2], t->reg[3]);
197 NV_DEBUG(dev, " 2a0: %08x\n", t->reg[4]); 201 NV_DEBUG(drm, " 2a0: %08x\n", t->reg[4]);
198 return 0; 202 return 0;
199} 203}
200 204
@@ -208,6 +212,8 @@ nouveau_mem_ddr2_mr(struct drm_device *dev, u32 freq,
208 struct nouveau_pm_memtiming *boot, 212 struct nouveau_pm_memtiming *boot,
209 struct nouveau_pm_memtiming *t) 213 struct nouveau_pm_memtiming *t)
210{ 214{
215 struct nouveau_drm *drm = nouveau_drm(dev);
216
211 t->drive_strength = 0; 217 t->drive_strength = 0;
212 if (len < 15) { 218 if (len < 15) {
213 t->odt = boot->odt; 219 t->odt = boot->odt;
@@ -216,17 +222,17 @@ nouveau_mem_ddr2_mr(struct drm_device *dev, u32 freq,
216 } 222 }
217 223
218 if (e->tCL >= NV_MEM_CL_DDR2_MAX) { 224 if (e->tCL >= NV_MEM_CL_DDR2_MAX) {
219 NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL); 225 NV_WARN(drm, "(%u) Invalid tCL: %u", t->id, e->tCL);
220 return -ERANGE; 226 return -ERANGE;
221 } 227 }
222 228
223 if (e->tWR >= NV_MEM_WR_DDR2_MAX) { 229 if (e->tWR >= NV_MEM_WR_DDR2_MAX) {
224 NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR); 230 NV_WARN(drm, "(%u) Invalid tWR: %u", t->id, e->tWR);
225 return -ERANGE; 231 return -ERANGE;
226 } 232 }
227 233
228 if (t->odt > 3) { 234 if (t->odt > 3) {
229 NV_WARN(dev, "(%u) Invalid odt value, assuming disabled: %x", 235 NV_WARN(drm, "(%u) Invalid odt value, assuming disabled: %x",
230 t->id, t->odt); 236 t->id, t->odt);
231 t->odt = 0; 237 t->odt = 0;
232 } 238 }
@@ -238,7 +244,7 @@ nouveau_mem_ddr2_mr(struct drm_device *dev, u32 freq,
238 (t->odt & 0x1) << 2 | 244 (t->odt & 0x1) << 2 |
239 (t->odt & 0x2) << 5; 245 (t->odt & 0x2) << 5;
240 246
241 NV_DEBUG(dev, "(%u) MR: %08x", t->id, t->mr[0]); 247 NV_DEBUG(drm, "(%u) MR: %08x", t->id, t->mr[0]);
242 return 0; 248 return 0;
243} 249}
244 250
@@ -251,6 +257,7 @@ nouveau_mem_ddr3_mr(struct drm_device *dev, u32 freq,
251 struct nouveau_pm_memtiming *boot, 257 struct nouveau_pm_memtiming *boot,
252 struct nouveau_pm_memtiming *t) 258 struct nouveau_pm_memtiming *t)
253{ 259{
260 struct nouveau_drm *drm = nouveau_drm(dev);
254 u8 cl = e->tCL - 4; 261 u8 cl = e->tCL - 4;
255 262
256 t->drive_strength = 0; 263 t->drive_strength = 0;
@@ -261,17 +268,17 @@ nouveau_mem_ddr3_mr(struct drm_device *dev, u32 freq,
261 } 268 }
262 269
263 if (e->tCL >= NV_MEM_CL_DDR3_MAX || e->tCL < 4) { 270 if (e->tCL >= NV_MEM_CL_DDR3_MAX || e->tCL < 4) {
264 NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL); 271 NV_WARN(drm, "(%u) Invalid tCL: %u", t->id, e->tCL);
265 return -ERANGE; 272 return -ERANGE;
266 } 273 }
267 274
268 if (e->tWR >= NV_MEM_WR_DDR3_MAX || e->tWR < 4) { 275 if (e->tWR >= NV_MEM_WR_DDR3_MAX || e->tWR < 4) {
269 NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR); 276 NV_WARN(drm, "(%u) Invalid tWR: %u", t->id, e->tWR);
270 return -ERANGE; 277 return -ERANGE;
271 } 278 }
272 279
273 if (e->tCWL < 5) { 280 if (e->tCWL < 5) {
274 NV_WARN(dev, "(%u) Invalid tCWL: %u", t->id, e->tCWL); 281 NV_WARN(drm, "(%u) Invalid tCWL: %u", t->id, e->tCWL);
275 return -ERANGE; 282 return -ERANGE;
276 } 283 }
277 284
@@ -286,7 +293,7 @@ nouveau_mem_ddr3_mr(struct drm_device *dev, u32 freq,
286 (t->odt & 0x4) << 7; 293 (t->odt & 0x4) << 7;
287 t->mr[2] = (boot->mr[2] & 0x20ffb7) | (e->tCWL - 5) << 3; 294 t->mr[2] = (boot->mr[2] & 0x20ffb7) | (e->tCWL - 5) << 3;
288 295
289 NV_DEBUG(dev, "(%u) MR: %08x %08x", t->id, t->mr[0], t->mr[2]); 296 NV_DEBUG(drm, "(%u) MR: %08x %08x", t->id, t->mr[0], t->mr[2]);
290 return 0; 297 return 0;
291} 298}
292 299
@@ -301,6 +308,8 @@ nouveau_mem_gddr3_mr(struct drm_device *dev, u32 freq,
301 struct nouveau_pm_memtiming *boot, 308 struct nouveau_pm_memtiming *boot,
302 struct nouveau_pm_memtiming *t) 309 struct nouveau_pm_memtiming *t)
303{ 310{
311 struct nouveau_drm *drm = nouveau_drm(dev);
312
304 if (len < 15) { 313 if (len < 15) {
305 t->drive_strength = boot->drive_strength; 314 t->drive_strength = boot->drive_strength;
306 t->odt = boot->odt; 315 t->odt = boot->odt;
@@ -310,17 +319,17 @@ nouveau_mem_gddr3_mr(struct drm_device *dev, u32 freq,
310 } 319 }
311 320
312 if (e->tCL >= NV_MEM_CL_GDDR3_MAX) { 321 if (e->tCL >= NV_MEM_CL_GDDR3_MAX) {
313 NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL); 322 NV_WARN(drm, "(%u) Invalid tCL: %u", t->id, e->tCL);
314 return -ERANGE; 323 return -ERANGE;
315 } 324 }
316 325
317 if (e->tWR >= NV_MEM_WR_GDDR3_MAX) { 326 if (e->tWR >= NV_MEM_WR_GDDR3_MAX) {
318 NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR); 327 NV_WARN(drm, "(%u) Invalid tWR: %u", t->id, e->tWR);
319 return -ERANGE; 328 return -ERANGE;
320 } 329 }
321 330
322 if (t->odt > 3) { 331 if (t->odt > 3) {
323 NV_WARN(dev, "(%u) Invalid odt value, assuming autocal: %x", 332 NV_WARN(drm, "(%u) Invalid odt value, assuming autocal: %x",
324 t->id, t->odt); 333 t->id, t->odt);
325 t->odt = 0; 334 t->odt = 0;
326 } 335 }
@@ -334,7 +343,7 @@ nouveau_mem_gddr3_mr(struct drm_device *dev, u32 freq,
334 (nv_mem_wr_lut_gddr3[e->tWR] & 0xf) << 4; 343 (nv_mem_wr_lut_gddr3[e->tWR] & 0xf) << 4;
335 t->mr[2] = boot->mr[2]; 344 t->mr[2] = boot->mr[2];
336 345
337 NV_DEBUG(dev, "(%u) MR: %08x %08x %08x", t->id, 346 NV_DEBUG(drm, "(%u) MR: %08x %08x %08x", t->id,
338 t->mr[0], t->mr[1], t->mr[2]); 347 t->mr[0], t->mr[1], t->mr[2]);
339 return 0; 348 return 0;
340} 349}
@@ -345,6 +354,8 @@ nouveau_mem_gddr5_mr(struct drm_device *dev, u32 freq,
345 struct nouveau_pm_memtiming *boot, 354 struct nouveau_pm_memtiming *boot,
346 struct nouveau_pm_memtiming *t) 355 struct nouveau_pm_memtiming *t)
347{ 356{
357 struct nouveau_drm *drm = nouveau_drm(dev);
358
348 if (len < 15) { 359 if (len < 15) {
349 t->drive_strength = boot->drive_strength; 360 t->drive_strength = boot->drive_strength;
350 t->odt = boot->odt; 361 t->odt = boot->odt;
@@ -354,17 +365,17 @@ nouveau_mem_gddr5_mr(struct drm_device *dev, u32 freq,
354 } 365 }
355 366
356 if (e->tCL >= NV_MEM_CL_GDDR5_MAX) { 367 if (e->tCL >= NV_MEM_CL_GDDR5_MAX) {
357 NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL); 368 NV_WARN(drm, "(%u) Invalid tCL: %u", t->id, e->tCL);
358 return -ERANGE; 369 return -ERANGE;
359 } 370 }
360 371
361 if (e->tWR >= NV_MEM_WR_GDDR5_MAX) { 372 if (e->tWR >= NV_MEM_WR_GDDR5_MAX) {
362 NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR); 373 NV_WARN(drm, "(%u) Invalid tWR: %u", t->id, e->tWR);
363 return -ERANGE; 374 return -ERANGE;
364 } 375 }
365 376
366 if (t->odt > 3) { 377 if (t->odt > 3) {
367 NV_WARN(dev, "(%u) Invalid odt value, assuming autocal: %x", 378 NV_WARN(drm, "(%u) Invalid odt value, assuming autocal: %x",
368 t->id, t->odt); 379 t->id, t->odt);
369 t->odt = 0; 380 t->odt = 0;
370 } 381 }
@@ -376,7 +387,7 @@ nouveau_mem_gddr5_mr(struct drm_device *dev, u32 freq,
376 t->drive_strength | 387 t->drive_strength |
377 (t->odt << 2); 388 (t->odt << 2);
378 389
379 NV_DEBUG(dev, "(%u) MR: %08x %08x", t->id, t->mr[0], t->mr[1]); 390 NV_DEBUG(drm, "(%u) MR: %08x %08x", t->id, t->mr[0], t->mr[1]);
380 return 0; 391 return 0;
381} 392}
382 393
@@ -384,8 +395,9 @@ int
384nouveau_mem_timing_calc(struct drm_device *dev, u32 freq, 395nouveau_mem_timing_calc(struct drm_device *dev, u32 freq,
385 struct nouveau_pm_memtiming *t) 396 struct nouveau_pm_memtiming *t)
386{ 397{
387 struct drm_nouveau_private *dev_priv = dev->dev_private; 398 struct nouveau_device *device = nouveau_dev(dev);
388 struct nouveau_pm_engine *pm = &dev_priv->engine.pm; 399 struct nouveau_fb *pfb = nouveau_fb(device);
400 struct nouveau_pm *pm = nouveau_pm(dev);
389 struct nouveau_pm_memtiming *boot = &pm->boot.timing; 401 struct nouveau_pm_memtiming *boot = &pm->boot.timing;
390 struct nouveau_pm_tbl_entry *e; 402 struct nouveau_pm_tbl_entry *e;
391 u8 ver, len, *ptr, *ramcfg; 403 u8 ver, len, *ptr, *ramcfg;
@@ -400,7 +412,7 @@ nouveau_mem_timing_calc(struct drm_device *dev, u32 freq,
400 412
401 t->tCWL = boot->tCWL; 413 t->tCWL = boot->tCWL;
402 414
403 switch (dev_priv->card_type) { 415 switch (device->card_type) {
404 case NV_40: 416 case NV_40:
405 ret = nv40_mem_timing_calc(dev, freq, e, len, boot, t); 417 ret = nv40_mem_timing_calc(dev, freq, e, len, boot, t);
406 break; 418 break;
@@ -416,7 +428,7 @@ nouveau_mem_timing_calc(struct drm_device *dev, u32 freq,
416 break; 428 break;
417 } 429 }
418 430
419 switch (nvfb_vram_type(dev) * !ret) { 431 switch (pfb->ram.type * !ret) {
420 case NV_MEM_TYPE_GDDR3: 432 case NV_MEM_TYPE_GDDR3:
421 ret = nouveau_mem_gddr3_mr(dev, freq, e, len, boot, t); 433 ret = nouveau_mem_gddr3_mr(dev, freq, e, len, boot, t);
422 break; 434 break;
@@ -443,7 +455,7 @@ nouveau_mem_timing_calc(struct drm_device *dev, u32 freq,
443 else 455 else
444 dll_off = !!(ramcfg[2] & 0x40); 456 dll_off = !!(ramcfg[2] & 0x40);
445 457
446 switch (nvfb_vram_type(dev)) { 458 switch (pfb->ram.type) {
447 case NV_MEM_TYPE_GDDR3: 459 case NV_MEM_TYPE_GDDR3:
448 t->mr[1] &= ~0x00000040; 460 t->mr[1] &= ~0x00000040;
449 t->mr[1] |= 0x00000040 * dll_off; 461 t->mr[1] |= 0x00000040 * dll_off;
@@ -461,11 +473,12 @@ nouveau_mem_timing_calc(struct drm_device *dev, u32 freq,
461void 473void
462nouveau_mem_timing_read(struct drm_device *dev, struct nouveau_pm_memtiming *t) 474nouveau_mem_timing_read(struct drm_device *dev, struct nouveau_pm_memtiming *t)
463{ 475{
464 struct drm_nouveau_private *dev_priv = dev->dev_private; 476 struct nouveau_device *device = nouveau_dev(dev);
477 struct nouveau_fb *pfb = nouveau_fb(device);
465 u32 timing_base, timing_regs, mr_base; 478 u32 timing_base, timing_regs, mr_base;
466 int i; 479 int i;
467 480
468 if (dev_priv->card_type >= 0xC0) { 481 if (device->card_type >= 0xC0) {
469 timing_base = 0x10f290; 482 timing_base = 0x10f290;
470 mr_base = 0x10f300; 483 mr_base = 0x10f300;
471 } else { 484 } else {
@@ -475,7 +488,7 @@ nouveau_mem_timing_read(struct drm_device *dev, struct nouveau_pm_memtiming *t)
475 488
476 t->id = -1; 489 t->id = -1;
477 490
478 switch (dev_priv->card_type) { 491 switch (device->card_type) {
479 case NV_50: 492 case NV_50:
480 timing_regs = 9; 493 timing_regs = 9;
481 break; 494 break;
@@ -492,24 +505,24 @@ nouveau_mem_timing_read(struct drm_device *dev, struct nouveau_pm_memtiming *t)
492 return; 505 return;
493 } 506 }
494 for(i = 0; i < timing_regs; i++) 507 for(i = 0; i < timing_regs; i++)
495 t->reg[i] = nv_rd32(dev, timing_base + (0x04 * i)); 508 t->reg[i] = nv_rd32(device, timing_base + (0x04 * i));
496 509
497 t->tCWL = 0; 510 t->tCWL = 0;
498 if (dev_priv->card_type < NV_C0) { 511 if (device->card_type < NV_C0) {
499 t->tCWL = ((nv_rd32(dev, 0x100228) & 0x0f000000) >> 24) + 1; 512 t->tCWL = ((nv_rd32(device, 0x100228) & 0x0f000000) >> 24) + 1;
500 } else if (dev_priv->card_type <= NV_D0) { 513 } else if (device->card_type <= NV_D0) {
501 t->tCWL = ((nv_rd32(dev, 0x10f294) & 0x00000f80) >> 7); 514 t->tCWL = ((nv_rd32(device, 0x10f294) & 0x00000f80) >> 7);
502 } 515 }
503 516
504 t->mr[0] = nv_rd32(dev, mr_base); 517 t->mr[0] = nv_rd32(device, mr_base);
505 t->mr[1] = nv_rd32(dev, mr_base + 0x04); 518 t->mr[1] = nv_rd32(device, mr_base + 0x04);
506 t->mr[2] = nv_rd32(dev, mr_base + 0x20); 519 t->mr[2] = nv_rd32(device, mr_base + 0x20);
507 t->mr[3] = nv_rd32(dev, mr_base + 0x24); 520 t->mr[3] = nv_rd32(device, mr_base + 0x24);
508 521
509 t->odt = 0; 522 t->odt = 0;
510 t->drive_strength = 0; 523 t->drive_strength = 0;
511 524
512 switch (nvfb_vram_type(dev)) { 525 switch (pfb->ram.type) {
513 case NV_MEM_TYPE_DDR3: 526 case NV_MEM_TYPE_DDR3:
514 t->odt |= (t->mr[1] & 0x200) >> 7; 527 t->odt |= (t->mr[1] & 0x200) >> 7;
515 case NV_MEM_TYPE_DDR2: 528 case NV_MEM_TYPE_DDR2:
@@ -530,13 +543,15 @@ int
530nouveau_mem_exec(struct nouveau_mem_exec_func *exec, 543nouveau_mem_exec(struct nouveau_mem_exec_func *exec,
531 struct nouveau_pm_level *perflvl) 544 struct nouveau_pm_level *perflvl)
532{ 545{
533 struct drm_nouveau_private *dev_priv = exec->dev->dev_private; 546 struct nouveau_drm *drm = nouveau_drm(exec->dev);
547 struct nouveau_device *device = nouveau_dev(exec->dev);
548 struct nouveau_fb *pfb = nouveau_fb(device);
534 struct nouveau_pm_memtiming *info = &perflvl->timing; 549 struct nouveau_pm_memtiming *info = &perflvl->timing;
535 u32 tMRD = 1000, tCKSRE = 0, tCKSRX = 0, tXS = 0, tDLLK = 0; 550 u32 tMRD = 1000, tCKSRE = 0, tCKSRX = 0, tXS = 0, tDLLK = 0;
536 u32 mr[3] = { info->mr[0], info->mr[1], info->mr[2] }; 551 u32 mr[3] = { info->mr[0], info->mr[1], info->mr[2] };
537 u32 mr1_dlloff; 552 u32 mr1_dlloff;
538 553
539 switch (nvfb_vram_type(dev_priv->dev)) { 554 switch (pfb->ram.type) {
540 case NV_MEM_TYPE_DDR2: 555 case NV_MEM_TYPE_DDR2:
541 tDLLK = 2000; 556 tDLLK = 2000;
542 mr1_dlloff = 0x00000001; 557 mr1_dlloff = 0x00000001;
@@ -552,12 +567,12 @@ nouveau_mem_exec(struct nouveau_mem_exec_func *exec,
552 mr1_dlloff = 0x00000040; 567 mr1_dlloff = 0x00000040;
553 break; 568 break;
554 default: 569 default:
555 NV_ERROR(exec->dev, "cannot reclock unsupported memtype\n"); 570 NV_ERROR(drm, "cannot reclock unsupported memtype\n");
556 return -ENODEV; 571 return -ENODEV;
557 } 572 }
558 573
559 /* fetch current MRs */ 574 /* fetch current MRs */
560 switch (nvfb_vram_type(dev_priv->dev)) { 575 switch (pfb->ram.type) {
561 case NV_MEM_TYPE_GDDR3: 576 case NV_MEM_TYPE_GDDR3:
562 case NV_MEM_TYPE_DDR3: 577 case NV_MEM_TYPE_DDR3:
563 mr[2] = exec->mrg(exec, 2); 578 mr[2] = exec->mrg(exec, 2);
@@ -624,7 +639,7 @@ nouveau_mem_exec(struct nouveau_mem_exec_func *exec,
624 exec->mrs (exec, 0, info->mr[0] | 0x00000000); 639 exec->mrs (exec, 0, info->mr[0] | 0x00000000);
625 exec->wait(exec, tMRD); 640 exec->wait(exec, tMRD);
626 exec->wait(exec, tDLLK); 641 exec->wait(exec, tDLLK);
627 if (nvfb_vram_type(dev_priv->dev) == NV_MEM_TYPE_GDDR3) 642 if (pfb->ram.type == NV_MEM_TYPE_GDDR3)
628 exec->precharge(exec); 643 exec->precharge(exec);
629 } 644 }
630 645
diff --git a/drivers/gpu/drm/nouveau/nouveau_perf.c b/drivers/gpu/drm/nouveau/nouveau_perf.c
index ea6acf1c4a78..b5c6a43511d9 100644
--- a/drivers/gpu/drm/nouveau/nouveau_perf.c
+++ b/drivers/gpu/drm/nouveau/nouveau_perf.c
@@ -24,14 +24,15 @@
24 24
25#include "drmP.h" 25#include "drmP.h"
26 26
27#include "nouveau_drv.h" 27#include "nouveau_drm.h"
28#include "nouveau_reg.h"
28#include "nouveau_pm.h" 29#include "nouveau_pm.h"
29 30
30static u8 * 31static u8 *
31nouveau_perf_table(struct drm_device *dev, u8 *ver) 32nouveau_perf_table(struct drm_device *dev, u8 *ver)
32{ 33{
33 struct drm_nouveau_private *dev_priv = dev->dev_private; 34 struct nouveau_drm *drm = nouveau_drm(dev);
34 struct nvbios *bios = &dev_priv->vbios; 35 struct nvbios *bios = &drm->vbios;
35 struct bit_entry P; 36 struct bit_entry P;
36 37
37 if (!bit_table(dev, 'P', &P) && P.version && P.version <= 2) { 38 if (!bit_table(dev, 'P', &P) && P.version && P.version <= 2) {
@@ -87,7 +88,7 @@ u8 *
87nouveau_perf_rammap(struct drm_device *dev, u32 freq, 88nouveau_perf_rammap(struct drm_device *dev, u32 freq,
88 u8 *ver, u8 *hdr, u8 *cnt, u8 *len) 89 u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
89{ 90{
90 struct drm_nouveau_private *dev_priv = dev->dev_private; 91 struct nouveau_drm *drm = nouveau_drm(dev);
91 struct bit_entry P; 92 struct bit_entry P;
92 u8 *perf, i = 0; 93 u8 *perf, i = 0;
93 94
@@ -114,8 +115,8 @@ nouveau_perf_rammap(struct drm_device *dev, u32 freq,
114 return NULL; 115 return NULL;
115 } 116 }
116 117
117 if (dev_priv->chipset == 0x49 || 118 if (nv_device(drm->device)->chipset == 0x49 ||
118 dev_priv->chipset == 0x4b) 119 nv_device(drm->device)->chipset == 0x4b)
119 freq /= 2; 120 freq /= 2;
120 121
121 while ((perf = nouveau_perf_entry(dev, i++, ver, hdr, cnt, len))) { 122 while ((perf = nouveau_perf_entry(dev, i++, ver, hdr, cnt, len))) {
@@ -142,12 +143,13 @@ nouveau_perf_rammap(struct drm_device *dev, u32 freq,
142u8 * 143u8 *
143nouveau_perf_ramcfg(struct drm_device *dev, u32 freq, u8 *ver, u8 *len) 144nouveau_perf_ramcfg(struct drm_device *dev, u32 freq, u8 *ver, u8 *len)
144{ 145{
145 struct drm_nouveau_private *dev_priv = dev->dev_private; 146 struct nouveau_device *device = nouveau_dev(dev);
146 struct nvbios *bios = &dev_priv->vbios; 147 struct nouveau_drm *drm = nouveau_drm(dev);
148 struct nvbios *bios = &drm->vbios;
147 u8 strap, hdr, cnt; 149 u8 strap, hdr, cnt;
148 u8 *rammap; 150 u8 *rammap;
149 151
150 strap = (nv_rd32(dev, 0x101000) & 0x0000003c) >> 2; 152 strap = (nv_rd32(device, 0x101000) & 0x0000003c) >> 2;
151 if (bios->ram_restrict_tbl_ptr) 153 if (bios->ram_restrict_tbl_ptr)
152 strap = bios->data[bios->ram_restrict_tbl_ptr + strap]; 154 strap = bios->data[bios->ram_restrict_tbl_ptr + strap];
153 155
@@ -161,8 +163,8 @@ nouveau_perf_ramcfg(struct drm_device *dev, u32 freq, u8 *ver, u8 *len)
161u8 * 163u8 *
162nouveau_perf_timing(struct drm_device *dev, u32 freq, u8 *ver, u8 *len) 164nouveau_perf_timing(struct drm_device *dev, u32 freq, u8 *ver, u8 *len)
163{ 165{
164 struct drm_nouveau_private *dev_priv = dev->dev_private; 166 struct nouveau_drm *drm = nouveau_drm(dev);
165 struct nvbios *bios = &dev_priv->vbios; 167 struct nvbios *bios = &drm->vbios;
166 struct bit_entry P; 168 struct bit_entry P;
167 u8 *perf, *timing = NULL; 169 u8 *perf, *timing = NULL;
168 u8 i = 0, hdr, cnt; 170 u8 i = 0, hdr, cnt;
@@ -202,20 +204,21 @@ nouveau_perf_timing(struct drm_device *dev, u32 freq, u8 *ver, u8 *len)
202static void 204static void
203legacy_perf_init(struct drm_device *dev) 205legacy_perf_init(struct drm_device *dev)
204{ 206{
205 struct drm_nouveau_private *dev_priv = dev->dev_private; 207 struct nouveau_device *device = nouveau_dev(dev);
206 struct nvbios *bios = &dev_priv->vbios; 208 struct nouveau_drm *drm = nouveau_drm(dev);
207 struct nouveau_pm_engine *pm = &dev_priv->engine.pm; 209 struct nvbios *bios = &drm->vbios;
210 struct nouveau_pm *pm = nouveau_pm(dev);
208 char *perf, *entry, *bmp = &bios->data[bios->offset]; 211 char *perf, *entry, *bmp = &bios->data[bios->offset];
209 int headerlen, use_straps; 212 int headerlen, use_straps;
210 213
211 if (bmp[5] < 0x5 || bmp[6] < 0x14) { 214 if (bmp[5] < 0x5 || bmp[6] < 0x14) {
212 NV_DEBUG(dev, "BMP version too old for perf\n"); 215 NV_DEBUG(drm, "BMP version too old for perf\n");
213 return; 216 return;
214 } 217 }
215 218
216 perf = ROMPTR(dev, bmp[0x73]); 219 perf = ROMPTR(dev, bmp[0x73]);
217 if (!perf) { 220 if (!perf) {
218 NV_DEBUG(dev, "No memclock table pointer found.\n"); 221 NV_DEBUG(drm, "No memclock table pointer found.\n");
219 return; 222 return;
220 } 223 }
221 224
@@ -231,13 +234,13 @@ legacy_perf_init(struct drm_device *dev)
231 headerlen = (use_straps ? 8 : 2); 234 headerlen = (use_straps ? 8 : 2);
232 break; 235 break;
233 default: 236 default:
234 NV_WARN(dev, "Unknown memclock table version %x.\n", perf[0]); 237 NV_WARN(drm, "Unknown memclock table version %x.\n", perf[0]);
235 return; 238 return;
236 } 239 }
237 240
238 entry = perf + headerlen; 241 entry = perf + headerlen;
239 if (use_straps) 242 if (use_straps)
240 entry += (nv_rd32(dev, NV_PEXTDEV_BOOT_0) & 0x3c) >> 1; 243 entry += (nv_rd32(device, NV_PEXTDEV_BOOT_0) & 0x3c) >> 1;
241 244
242 sprintf(pm->perflvl[0].name, "performance_level_0"); 245 sprintf(pm->perflvl[0].name, "performance_level_0");
243 pm->perflvl[0].memory = ROM16(entry[0]) * 20; 246 pm->perflvl[0].memory = ROM16(entry[0]) * 20;
@@ -247,7 +250,7 @@ legacy_perf_init(struct drm_device *dev)
247static void 250static void
248nouveau_perf_voltage(struct drm_device *dev, struct nouveau_pm_level *perflvl) 251nouveau_perf_voltage(struct drm_device *dev, struct nouveau_pm_level *perflvl)
249{ 252{
250 struct drm_nouveau_private *dev_priv = dev->dev_private; 253 struct nouveau_drm *drm = nouveau_drm(dev);
251 struct bit_entry P; 254 struct bit_entry P;
252 u8 *vmap; 255 u8 *vmap;
253 int id; 256 int id;
@@ -258,7 +261,7 @@ nouveau_perf_voltage(struct drm_device *dev, struct nouveau_pm_level *perflvl)
258 /* boards using voltage table version <0x40 store the voltage 261 /* boards using voltage table version <0x40 store the voltage
259 * level directly in the perflvl entry as a multiple of 10mV 262 * level directly in the perflvl entry as a multiple of 10mV
260 */ 263 */
261 if (dev_priv->engine.pm.voltage.version < 0x40) { 264 if (drm->pm->voltage.version < 0x40) {
262 perflvl->volt_min = id * 10000; 265 perflvl->volt_min = id * 10000;
263 perflvl->volt_max = perflvl->volt_min; 266 perflvl->volt_max = perflvl->volt_min;
264 return; 267 return;
@@ -268,14 +271,14 @@ nouveau_perf_voltage(struct drm_device *dev, struct nouveau_pm_level *perflvl)
268 * vbios table containing a min/max voltage value for the perflvl 271 * vbios table containing a min/max voltage value for the perflvl
269 */ 272 */
270 if (bit_table(dev, 'P', &P) || P.version != 2 || P.length < 34) { 273 if (bit_table(dev, 'P', &P) || P.version != 2 || P.length < 34) {
271 NV_DEBUG(dev, "where's our volt map table ptr? %d %d\n", 274 NV_DEBUG(drm, "where's our volt map table ptr? %d %d\n",
272 P.version, P.length); 275 P.version, P.length);
273 return; 276 return;
274 } 277 }
275 278
276 vmap = ROMPTR(dev, P.data[32]); 279 vmap = ROMPTR(dev, P.data[32]);
277 if (!vmap) { 280 if (!vmap) {
278 NV_DEBUG(dev, "volt map table pointer invalid\n"); 281 NV_DEBUG(drm, "volt map table pointer invalid\n");
279 return; 282 return;
280 } 283 }
281 284
@@ -289,9 +292,9 @@ nouveau_perf_voltage(struct drm_device *dev, struct nouveau_pm_level *perflvl)
289void 292void
290nouveau_perf_init(struct drm_device *dev) 293nouveau_perf_init(struct drm_device *dev)
291{ 294{
292 struct drm_nouveau_private *dev_priv = dev->dev_private; 295 struct nouveau_drm *drm = nouveau_drm(dev);
293 struct nouveau_pm_engine *pm = &dev_priv->engine.pm; 296 struct nouveau_pm *pm = nouveau_pm(dev);
294 struct nvbios *bios = &dev_priv->vbios; 297 struct nvbios *bios = &drm->vbios;
295 u8 *perf, ver, hdr, cnt, len; 298 u8 *perf, ver, hdr, cnt, len;
296 int ret, vid, i = -1; 299 int ret, vid, i = -1;
297 300
@@ -328,8 +331,8 @@ nouveau_perf_init(struct drm_device *dev)
328 perflvl->shader = ROM16(perf[6]) * 1000; 331 perflvl->shader = ROM16(perf[6]) * 1000;
329 perflvl->core = perflvl->shader; 332 perflvl->core = perflvl->shader;
330 perflvl->core += (signed char)perf[8] * 1000; 333 perflvl->core += (signed char)perf[8] * 1000;
331 if (dev_priv->chipset == 0x49 || 334 if (nv_device(drm->device)->chipset == 0x49 ||
332 dev_priv->chipset == 0x4b) 335 nv_device(drm->device)->chipset == 0x4b)
333 perflvl->memory = ROM16(perf[11]) * 1000; 336 perflvl->memory = ROM16(perf[11]) * 1000;
334 else 337 else
335 perflvl->memory = ROM16(perf[11]) * 2000; 338 perflvl->memory = ROM16(perf[11]) * 2000;
@@ -356,7 +359,7 @@ nouveau_perf_init(struct drm_device *dev)
356#define subent(n) ((ROM16(perf[hdr + (n) * len]) & 0xfff) * 1000) 359#define subent(n) ((ROM16(perf[hdr + (n) * len]) & 0xfff) * 1000)
357 perflvl->fanspeed = 0; /*XXX*/ 360 perflvl->fanspeed = 0; /*XXX*/
358 perflvl->volt_min = perf[2]; 361 perflvl->volt_min = perf[2];
359 if (dev_priv->card_type == NV_50) { 362 if (nv_device(drm->device)->card_type == NV_50) {
360 perflvl->core = subent(0); 363 perflvl->core = subent(0);
361 perflvl->shader = subent(1); 364 perflvl->shader = subent(1);
362 perflvl->memory = subent(2); 365 perflvl->memory = subent(2);
@@ -382,7 +385,7 @@ nouveau_perf_init(struct drm_device *dev)
382 if (pm->voltage.supported && perflvl->volt_min) { 385 if (pm->voltage.supported && perflvl->volt_min) {
383 vid = nouveau_volt_vid_lookup(dev, perflvl->volt_min); 386 vid = nouveau_volt_vid_lookup(dev, perflvl->volt_min);
384 if (vid < 0) { 387 if (vid < 0) {
385 NV_DEBUG(dev, "perflvl %d, bad vid\n", i); 388 NV_DEBUG(drm, "perflvl %d, bad vid\n", i);
386 continue; 389 continue;
387 } 390 }
388 } 391 }
@@ -391,7 +394,7 @@ nouveau_perf_init(struct drm_device *dev)
391 ret = nouveau_mem_timing_calc(dev, perflvl->memory, 394 ret = nouveau_mem_timing_calc(dev, perflvl->memory,
392 &perflvl->timing); 395 &perflvl->timing);
393 if (ret) { 396 if (ret) {
394 NV_DEBUG(dev, "perflvl %d, bad timing: %d\n", i, ret); 397 NV_DEBUG(drm, "perflvl %d, bad timing: %d\n", i, ret);
395 continue; 398 continue;
396 } 399 }
397 400
diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.c b/drivers/gpu/drm/nouveau/nouveau_pm.c
index 539e81c416cd..3c55ec2366d3 100644
--- a/drivers/gpu/drm/nouveau/nouveau_pm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_pm.c
@@ -22,12 +22,6 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24 24
25#include "drmP.h"
26
27#include "nouveau_drv.h"
28#include "nouveau_pm.h"
29#include <subdev/bios/gpio.h>
30
31#ifdef CONFIG_ACPI 25#ifdef CONFIG_ACPI
32#include <linux/acpi.h> 26#include <linux/acpi.h>
33#endif 27#endif
@@ -35,29 +29,48 @@
35#include <linux/hwmon.h> 29#include <linux/hwmon.h>
36#include <linux/hwmon-sysfs.h> 30#include <linux/hwmon-sysfs.h>
37 31
32#include "drmP.h"
33
34#include "nouveau_drm.h"
35#include "nouveau_pm.h"
36
37#include <subdev/bios/gpio.h>
38#include <subdev/gpio.h>
39#include <subdev/timer.h>
40
41MODULE_PARM_DESC(perflvl, "Performance level (default: boot)");
42static char *nouveau_perflvl;
43module_param_named(perflvl, nouveau_perflvl, charp, 0400);
44
45MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)");
46static int nouveau_perflvl_wr;
47module_param_named(perflvl_wr, nouveau_perflvl_wr, int, 0400);
48
38static int 49static int
39nouveau_pwmfan_get(struct drm_device *dev) 50nouveau_pwmfan_get(struct drm_device *dev)
40{ 51{
41 struct drm_nouveau_private *dev_priv = dev->dev_private; 52 struct nouveau_pm *pm = nouveau_pm(dev);
42 struct nouveau_pm_engine *pm = &dev_priv->engine.pm; 53 struct nouveau_drm *drm = nouveau_drm(dev);
43 struct dcb_gpio_func gpio; 54 struct nouveau_device *device = nv_device(drm->device);
55 struct nouveau_gpio *gpio = nouveau_gpio(device);
56 struct dcb_gpio_func func;
44 u32 divs, duty; 57 u32 divs, duty;
45 int ret; 58 int ret;
46 59
47 if (!pm->pwm_get) 60 if (!pm->pwm_get)
48 return -ENODEV; 61 return -ENODEV;
49 62
50 ret = nouveau_gpio_find(dev, 0, DCB_GPIO_PWM_FAN, 0xff, &gpio); 63 ret = gpio->find(gpio, 0, DCB_GPIO_PWM_FAN, 0xff, &func);
51 if (ret == 0) { 64 if (ret == 0) {
52 ret = pm->pwm_get(dev, gpio.line, &divs, &duty); 65 ret = pm->pwm_get(dev, func.line, &divs, &duty);
53 if (ret == 0 && divs) { 66 if (ret == 0 && divs) {
54 divs = max(divs, duty); 67 divs = max(divs, duty);
55 if (dev_priv->card_type <= NV_40 || (gpio.log[0] & 1)) 68 if (device->card_type <= NV_40 || (func.log[0] & 1))
56 duty = divs - duty; 69 duty = divs - duty;
57 return (duty * 100) / divs; 70 return (duty * 100) / divs;
58 } 71 }
59 72
60 return nouveau_gpio_func_get(dev, gpio.func) * 100; 73 return gpio->get(gpio, 0, func.func, func.line) * 100;
61 } 74 }
62 75
63 return -ENODEV; 76 return -ENODEV;
@@ -66,30 +79,32 @@ nouveau_pwmfan_get(struct drm_device *dev)
66static int 79static int
67nouveau_pwmfan_set(struct drm_device *dev, int percent) 80nouveau_pwmfan_set(struct drm_device *dev, int percent)
68{ 81{
69 struct drm_nouveau_private *dev_priv = dev->dev_private; 82 struct nouveau_pm *pm = nouveau_pm(dev);
70 struct nouveau_pm_engine *pm = &dev_priv->engine.pm; 83 struct nouveau_drm *drm = nouveau_drm(dev);
71 struct dcb_gpio_func gpio; 84 struct nouveau_device *device = nv_device(drm->device);
85 struct nouveau_gpio *gpio = nouveau_gpio(device);
86 struct dcb_gpio_func func;
72 u32 divs, duty; 87 u32 divs, duty;
73 int ret; 88 int ret;
74 89
75 if (!pm->pwm_set) 90 if (!pm->pwm_set)
76 return -ENODEV; 91 return -ENODEV;
77 92
78 ret = nouveau_gpio_find(dev, 0, DCB_GPIO_PWM_FAN, 0xff, &gpio); 93 ret = gpio->find(gpio, 0, DCB_GPIO_PWM_FAN, 0xff, &func);
79 if (ret == 0) { 94 if (ret == 0) {
80 divs = pm->fan.pwm_divisor; 95 divs = pm->fan.pwm_divisor;
81 if (pm->fan.pwm_freq) { 96 if (pm->fan.pwm_freq) {
82 /*XXX: PNVIO clock more than likely... */ 97 /*XXX: PNVIO clock more than likely... */
83 divs = 135000 / pm->fan.pwm_freq; 98 divs = 135000 / pm->fan.pwm_freq;
84 if (dev_priv->chipset < 0xa3) 99 if (nv_device(drm->device)->chipset < 0xa3)
85 divs /= 4; 100 divs /= 4;
86 } 101 }
87 102
88 duty = ((divs * percent) + 99) / 100; 103 duty = ((divs * percent) + 99) / 100;
89 if (dev_priv->card_type <= NV_40 || (gpio.log[0] & 1)) 104 if (device->card_type <= NV_40 || (func.log[0] & 1))
90 duty = divs - duty; 105 duty = divs - duty;
91 106
92 ret = pm->pwm_set(dev, gpio.line, divs, duty); 107 ret = pm->pwm_set(dev, func.line, divs, duty);
93 if (!ret) 108 if (!ret)
94 pm->fan.percent = percent; 109 pm->fan.percent = percent;
95 return ret; 110 return ret;
@@ -102,8 +117,8 @@ static int
102nouveau_pm_perflvl_aux(struct drm_device *dev, struct nouveau_pm_level *perflvl, 117nouveau_pm_perflvl_aux(struct drm_device *dev, struct nouveau_pm_level *perflvl,
103 struct nouveau_pm_level *a, struct nouveau_pm_level *b) 118 struct nouveau_pm_level *a, struct nouveau_pm_level *b)
104{ 119{
105 struct drm_nouveau_private *dev_priv = dev->dev_private; 120 struct nouveau_drm *drm = nouveau_drm(dev);
106 struct nouveau_pm_engine *pm = &dev_priv->engine.pm; 121 struct nouveau_pm *pm = nouveau_pm(dev);
107 int ret; 122 int ret;
108 123
109 /*XXX: not on all boards, we should control based on temperature 124 /*XXX: not on all boards, we should control based on temperature
@@ -113,7 +128,7 @@ nouveau_pm_perflvl_aux(struct drm_device *dev, struct nouveau_pm_level *perflvl,
113 if (a->fanspeed && b->fanspeed && b->fanspeed > a->fanspeed) { 128 if (a->fanspeed && b->fanspeed && b->fanspeed > a->fanspeed) {
114 ret = nouveau_pwmfan_set(dev, perflvl->fanspeed); 129 ret = nouveau_pwmfan_set(dev, perflvl->fanspeed);
115 if (ret && ret != -ENODEV) { 130 if (ret && ret != -ENODEV) {
116 NV_ERROR(dev, "fanspeed set failed: %d\n", ret); 131 NV_ERROR(drm, "fanspeed set failed: %d\n", ret);
117 return ret; 132 return ret;
118 } 133 }
119 } 134 }
@@ -122,7 +137,7 @@ nouveau_pm_perflvl_aux(struct drm_device *dev, struct nouveau_pm_level *perflvl,
122 if (perflvl->volt_min && b->volt_min > a->volt_min) { 137 if (perflvl->volt_min && b->volt_min > a->volt_min) {
123 ret = pm->voltage_set(dev, perflvl->volt_min); 138 ret = pm->voltage_set(dev, perflvl->volt_min);
124 if (ret) { 139 if (ret) {
125 NV_ERROR(dev, "voltage set failed: %d\n", ret); 140 NV_ERROR(drm, "voltage set failed: %d\n", ret);
126 return ret; 141 return ret;
127 } 142 }
128 } 143 }
@@ -134,8 +149,7 @@ nouveau_pm_perflvl_aux(struct drm_device *dev, struct nouveau_pm_level *perflvl,
134static int 149static int
135nouveau_pm_perflvl_set(struct drm_device *dev, struct nouveau_pm_level *perflvl) 150nouveau_pm_perflvl_set(struct drm_device *dev, struct nouveau_pm_level *perflvl)
136{ 151{
137 struct drm_nouveau_private *dev_priv = dev->dev_private; 152 struct nouveau_pm *pm = nouveau_pm(dev);
138 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
139 void *state; 153 void *state;
140 int ret; 154 int ret;
141 155
@@ -171,8 +185,9 @@ error:
171void 185void
172nouveau_pm_trigger(struct drm_device *dev) 186nouveau_pm_trigger(struct drm_device *dev)
173{ 187{
174 struct drm_nouveau_private *dev_priv = dev->dev_private; 188 struct nouveau_drm *drm = nouveau_drm(dev);
175 struct nouveau_pm_engine *pm = &dev_priv->engine.pm; 189 struct nouveau_timer *ptimer = nouveau_timer(drm->device);
190 struct nouveau_pm *pm = nouveau_pm(dev);
176 struct nouveau_pm_profile *profile = NULL; 191 struct nouveau_pm_profile *profile = NULL;
177 struct nouveau_pm_level *perflvl = NULL; 192 struct nouveau_pm_level *perflvl = NULL;
178 int ret; 193 int ret;
@@ -194,23 +209,22 @@ nouveau_pm_trigger(struct drm_device *dev)
194 209
195 /* change perflvl, if necessary */ 210 /* change perflvl, if necessary */
196 if (perflvl != pm->cur) { 211 if (perflvl != pm->cur) {
197 u64 time0 = nv_timer_read(dev); 212 u64 time0 = ptimer->read(ptimer);
198 213
199 NV_INFO(dev, "setting performance level: %d", perflvl->id); 214 NV_INFO(drm, "setting performance level: %d", perflvl->id);
200 ret = nouveau_pm_perflvl_set(dev, perflvl); 215 ret = nouveau_pm_perflvl_set(dev, perflvl);
201 if (ret) 216 if (ret)
202 NV_INFO(dev, "> reclocking failed: %d\n\n", ret); 217 NV_INFO(drm, "> reclocking failed: %d\n\n", ret);
203 218
204 NV_INFO(dev, "> reclocking took %lluns\n\n", 219 NV_INFO(drm, "> reclocking took %lluns\n\n",
205 nv_timer_read(dev) - time0); 220 ptimer->read(ptimer) - time0);
206 } 221 }
207} 222}
208 223
209static struct nouveau_pm_profile * 224static struct nouveau_pm_profile *
210profile_find(struct drm_device *dev, const char *string) 225profile_find(struct drm_device *dev, const char *string)
211{ 226{
212 struct drm_nouveau_private *dev_priv = dev->dev_private; 227 struct nouveau_pm *pm = nouveau_pm(dev);
213 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
214 struct nouveau_pm_profile *profile; 228 struct nouveau_pm_profile *profile;
215 229
216 list_for_each_entry(profile, &pm->profiles, head) { 230 list_for_each_entry(profile, &pm->profiles, head) {
@@ -224,8 +238,7 @@ profile_find(struct drm_device *dev, const char *string)
224static int 238static int
225nouveau_pm_profile_set(struct drm_device *dev, const char *profile) 239nouveau_pm_profile_set(struct drm_device *dev, const char *profile)
226{ 240{
227 struct drm_nouveau_private *dev_priv = dev->dev_private; 241 struct nouveau_pm *pm = nouveau_pm(dev);
228 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
229 struct nouveau_pm_profile *ac = NULL, *dc = NULL; 242 struct nouveau_pm_profile *ac = NULL, *dc = NULL;
230 char string[16], *cur = string, *ptr; 243 char string[16], *cur = string, *ptr;
231 244
@@ -278,8 +291,7 @@ const struct nouveau_pm_profile_func nouveau_pm_static_profile_func = {
278static int 291static int
279nouveau_pm_perflvl_get(struct drm_device *dev, struct nouveau_pm_level *perflvl) 292nouveau_pm_perflvl_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
280{ 293{
281 struct drm_nouveau_private *dev_priv = dev->dev_private; 294 struct nouveau_pm *pm = nouveau_pm(dev);
282 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
283 int ret; 295 int ret;
284 296
285 memset(perflvl, 0, sizeof(*perflvl)); 297 memset(perflvl, 0, sizeof(*perflvl));
@@ -361,8 +373,7 @@ static ssize_t
361nouveau_pm_get_perflvl(struct device *d, struct device_attribute *a, char *buf) 373nouveau_pm_get_perflvl(struct device *d, struct device_attribute *a, char *buf)
362{ 374{
363 struct drm_device *dev = pci_get_drvdata(to_pci_dev(d)); 375 struct drm_device *dev = pci_get_drvdata(to_pci_dev(d));
364 struct drm_nouveau_private *dev_priv = dev->dev_private; 376 struct nouveau_pm *pm = nouveau_pm(dev);
365 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
366 struct nouveau_pm_level cur; 377 struct nouveau_pm_level cur;
367 int len = PAGE_SIZE, ret; 378 int len = PAGE_SIZE, ret;
368 char *ptr = buf; 379 char *ptr = buf;
@@ -397,8 +408,8 @@ static DEVICE_ATTR(performance_level, S_IRUGO | S_IWUSR,
397static int 408static int
398nouveau_sysfs_init(struct drm_device *dev) 409nouveau_sysfs_init(struct drm_device *dev)
399{ 410{
400 struct drm_nouveau_private *dev_priv = dev->dev_private; 411 struct nouveau_drm *drm = nouveau_drm(dev);
401 struct nouveau_pm_engine *pm = &dev_priv->engine.pm; 412 struct nouveau_pm *pm = nouveau_pm(dev);
402 struct device *d = &dev->pdev->dev; 413 struct device *d = &dev->pdev->dev;
403 int ret, i; 414 int ret, i;
404 415
@@ -417,7 +428,7 @@ nouveau_sysfs_init(struct drm_device *dev)
417 428
418 ret = device_create_file(d, &perflvl->dev_attr); 429 ret = device_create_file(d, &perflvl->dev_attr);
419 if (ret) { 430 if (ret) {
420 NV_ERROR(dev, "failed pervlvl %d sysfs: %d\n", 431 NV_ERROR(drm, "failed pervlvl %d sysfs: %d\n",
421 perflvl->id, i); 432 perflvl->id, i);
422 perflvl->dev_attr.attr.name = NULL; 433 perflvl->dev_attr.attr.name = NULL;
423 nouveau_pm_fini(dev); 434 nouveau_pm_fini(dev);
@@ -431,8 +442,7 @@ nouveau_sysfs_init(struct drm_device *dev)
431static void 442static void
432nouveau_sysfs_fini(struct drm_device *dev) 443nouveau_sysfs_fini(struct drm_device *dev)
433{ 444{
434 struct drm_nouveau_private *dev_priv = dev->dev_private; 445 struct nouveau_pm *pm = nouveau_pm(dev);
435 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
436 struct device *d = &dev->pdev->dev; 446 struct device *d = &dev->pdev->dev;
437 int i; 447 int i;
438 448
@@ -452,8 +462,7 @@ static ssize_t
452nouveau_hwmon_show_temp(struct device *d, struct device_attribute *a, char *buf) 462nouveau_hwmon_show_temp(struct device *d, struct device_attribute *a, char *buf)
453{ 463{
454 struct drm_device *dev = dev_get_drvdata(d); 464 struct drm_device *dev = dev_get_drvdata(d);
455 struct drm_nouveau_private *dev_priv = dev->dev_private; 465 struct nouveau_pm *pm = nouveau_pm(dev);
456 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
457 466
458 return snprintf(buf, PAGE_SIZE, "%d\n", pm->temp_get(dev)*1000); 467 return snprintf(buf, PAGE_SIZE, "%d\n", pm->temp_get(dev)*1000);
459} 468}
@@ -464,8 +473,7 @@ static ssize_t
464nouveau_hwmon_max_temp(struct device *d, struct device_attribute *a, char *buf) 473nouveau_hwmon_max_temp(struct device *d, struct device_attribute *a, char *buf)
465{ 474{
466 struct drm_device *dev = dev_get_drvdata(d); 475 struct drm_device *dev = dev_get_drvdata(d);
467 struct drm_nouveau_private *dev_priv = dev->dev_private; 476 struct nouveau_pm *pm = nouveau_pm(dev);
468 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
469 struct nouveau_pm_threshold_temp *temp = &pm->threshold_temp; 477 struct nouveau_pm_threshold_temp *temp = &pm->threshold_temp;
470 478
471 return snprintf(buf, PAGE_SIZE, "%d\n", temp->down_clock*1000); 479 return snprintf(buf, PAGE_SIZE, "%d\n", temp->down_clock*1000);
@@ -475,8 +483,7 @@ nouveau_hwmon_set_max_temp(struct device *d, struct device_attribute *a,
475 const char *buf, size_t count) 483 const char *buf, size_t count)
476{ 484{
477 struct drm_device *dev = dev_get_drvdata(d); 485 struct drm_device *dev = dev_get_drvdata(d);
478 struct drm_nouveau_private *dev_priv = dev->dev_private; 486 struct nouveau_pm *pm = nouveau_pm(dev);
479 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
480 struct nouveau_pm_threshold_temp *temp = &pm->threshold_temp; 487 struct nouveau_pm_threshold_temp *temp = &pm->threshold_temp;
481 long value; 488 long value;
482 489
@@ -498,8 +505,7 @@ nouveau_hwmon_critical_temp(struct device *d, struct device_attribute *a,
498 char *buf) 505 char *buf)
499{ 506{
500 struct drm_device *dev = dev_get_drvdata(d); 507 struct drm_device *dev = dev_get_drvdata(d);
501 struct drm_nouveau_private *dev_priv = dev->dev_private; 508 struct nouveau_pm *pm = nouveau_pm(dev);
502 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
503 struct nouveau_pm_threshold_temp *temp = &pm->threshold_temp; 509 struct nouveau_pm_threshold_temp *temp = &pm->threshold_temp;
504 510
505 return snprintf(buf, PAGE_SIZE, "%d\n", temp->critical*1000); 511 return snprintf(buf, PAGE_SIZE, "%d\n", temp->critical*1000);
@@ -510,8 +516,7 @@ nouveau_hwmon_set_critical_temp(struct device *d, struct device_attribute *a,
510 size_t count) 516 size_t count)
511{ 517{
512 struct drm_device *dev = dev_get_drvdata(d); 518 struct drm_device *dev = dev_get_drvdata(d);
513 struct drm_nouveau_private *dev_priv = dev->dev_private; 519 struct nouveau_pm *pm = nouveau_pm(dev);
514 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
515 struct nouveau_pm_threshold_temp *temp = &pm->threshold_temp; 520 struct nouveau_pm_threshold_temp *temp = &pm->threshold_temp;
516 long value; 521 long value;
517 522
@@ -552,28 +557,32 @@ nouveau_hwmon_show_fan0_input(struct device *d, struct device_attribute *attr,
552 char *buf) 557 char *buf)
553{ 558{
554 struct drm_device *dev = dev_get_drvdata(d); 559 struct drm_device *dev = dev_get_drvdata(d);
560 struct nouveau_drm *drm = nouveau_drm(dev);
561 struct nouveau_timer *ptimer = nouveau_timer(drm->device);
562 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
563 struct dcb_gpio_func func;
555 u32 cycles, cur, prev; 564 u32 cycles, cur, prev;
556 u64 start; 565 u64 start;
557 566
558 if (!nouveau_gpio_func_valid(dev, DCB_GPIO_FAN_SENSE)) 567 if (gpio->find(gpio, 0, DCB_GPIO_FAN_SENSE, 0xff, &func))
559 return -ENODEV; 568 return -ENODEV;
560 569
561 /* Monitor the GPIO input 0x3b for 250ms. 570 /* Monitor the GPIO input 0x3b for 250ms.
562 * When the fan spins, it changes the value of GPIO FAN_SENSE. 571 * When the fan spins, it changes the value of GPIO FAN_SENSE.
563 * We get 4 changes (0 -> 1 -> 0 -> 1 -> [...]) per complete rotation. 572 * We get 4 changes (0 -> 1 -> 0 -> 1 -> [...]) per complete rotation.
564 */ 573 */
565 start = nv_timer_read(dev); 574 start = ptimer->read(ptimer);
566 prev = nouveau_gpio_func_get(dev, DCB_GPIO_FAN_SENSE); 575 prev = gpio->get(gpio, 0, func.func, func.line);
567 cycles = 0; 576 cycles = 0;
568 do { 577 do {
569 cur = nouveau_gpio_func_get(dev, DCB_GPIO_FAN_SENSE); 578 cur = gpio->get(gpio, 0, func.func, func.line);
570 if (prev != cur) { 579 if (prev != cur) {
571 cycles++; 580 cycles++;
572 prev = cur; 581 prev = cur;
573 } 582 }
574 583
575 usleep_range(500, 1000); /* supports 0 < rpm < 7500 */ 584 usleep_range(500, 1000); /* supports 0 < rpm < 7500 */
576 } while (nv_timer_read(dev) - start < 250000000); 585 } while (ptimer->read(ptimer) - start < 250000000);
577 586
578 /* interpolate to get rpm */ 587 /* interpolate to get rpm */
579 return sprintf(buf, "%i\n", cycles / 4 * 4 * 60); 588 return sprintf(buf, "%i\n", cycles / 4 * 4 * 60);
@@ -599,8 +608,7 @@ nouveau_hwmon_set_pwm0(struct device *d, struct device_attribute *a,
599 const char *buf, size_t count) 608 const char *buf, size_t count)
600{ 609{
601 struct drm_device *dev = dev_get_drvdata(d); 610 struct drm_device *dev = dev_get_drvdata(d);
602 struct drm_nouveau_private *dev_priv = dev->dev_private; 611 struct nouveau_pm *pm = nouveau_pm(dev);
603 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
604 int ret = -ENODEV; 612 int ret = -ENODEV;
605 long value; 613 long value;
606 614
@@ -631,8 +639,7 @@ nouveau_hwmon_get_pwm0_min(struct device *d,
631 struct device_attribute *a, char *buf) 639 struct device_attribute *a, char *buf)
632{ 640{
633 struct drm_device *dev = dev_get_drvdata(d); 641 struct drm_device *dev = dev_get_drvdata(d);
634 struct drm_nouveau_private *dev_priv = dev->dev_private; 642 struct nouveau_pm *pm = nouveau_pm(dev);
635 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
636 643
637 return sprintf(buf, "%i\n", pm->fan.min_duty); 644 return sprintf(buf, "%i\n", pm->fan.min_duty);
638} 645}
@@ -642,8 +649,7 @@ nouveau_hwmon_set_pwm0_min(struct device *d, struct device_attribute *a,
642 const char *buf, size_t count) 649 const char *buf, size_t count)
643{ 650{
644 struct drm_device *dev = dev_get_drvdata(d); 651 struct drm_device *dev = dev_get_drvdata(d);
645 struct drm_nouveau_private *dev_priv = dev->dev_private; 652 struct nouveau_pm *pm = nouveau_pm(dev);
646 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
647 long value; 653 long value;
648 654
649 if (kstrtol(buf, 10, &value) == -EINVAL) 655 if (kstrtol(buf, 10, &value) == -EINVAL)
@@ -672,8 +678,7 @@ nouveau_hwmon_get_pwm0_max(struct device *d,
672 struct device_attribute *a, char *buf) 678 struct device_attribute *a, char *buf)
673{ 679{
674 struct drm_device *dev = dev_get_drvdata(d); 680 struct drm_device *dev = dev_get_drvdata(d);
675 struct drm_nouveau_private *dev_priv = dev->dev_private; 681 struct nouveau_pm *pm = nouveau_pm(dev);
676 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
677 682
678 return sprintf(buf, "%i\n", pm->fan.max_duty); 683 return sprintf(buf, "%i\n", pm->fan.max_duty);
679} 684}
@@ -683,8 +688,7 @@ nouveau_hwmon_set_pwm0_max(struct device *d, struct device_attribute *a,
683 const char *buf, size_t count) 688 const char *buf, size_t count)
684{ 689{
685 struct drm_device *dev = dev_get_drvdata(d); 690 struct drm_device *dev = dev_get_drvdata(d);
686 struct drm_nouveau_private *dev_priv = dev->dev_private; 691 struct nouveau_pm *pm = nouveau_pm(dev);
687 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
688 long value; 692 long value;
689 693
690 if (kstrtol(buf, 10, &value) == -EINVAL) 694 if (kstrtol(buf, 10, &value) == -EINVAL)
@@ -741,8 +745,11 @@ static const struct attribute_group hwmon_pwm_fan_attrgroup = {
741static int 745static int
742nouveau_hwmon_init(struct drm_device *dev) 746nouveau_hwmon_init(struct drm_device *dev)
743{ 747{
744 struct drm_nouveau_private *dev_priv = dev->dev_private; 748 struct nouveau_pm *pm = nouveau_pm(dev);
745 struct nouveau_pm_engine *pm = &dev_priv->engine.pm; 749 struct nouveau_drm *drm = nouveau_drm(dev);
750 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
751 struct dcb_gpio_func func;
752
746#if defined(CONFIG_HWMON) || (defined(MODULE) && defined(CONFIG_HWMON_MODULE)) 753#if defined(CONFIG_HWMON) || (defined(MODULE) && defined(CONFIG_HWMON_MODULE))
747 struct device *hwmon_dev; 754 struct device *hwmon_dev;
748 int ret = 0; 755 int ret = 0;
@@ -753,8 +760,7 @@ nouveau_hwmon_init(struct drm_device *dev)
753 hwmon_dev = hwmon_device_register(&dev->pdev->dev); 760 hwmon_dev = hwmon_device_register(&dev->pdev->dev);
754 if (IS_ERR(hwmon_dev)) { 761 if (IS_ERR(hwmon_dev)) {
755 ret = PTR_ERR(hwmon_dev); 762 ret = PTR_ERR(hwmon_dev);
756 NV_ERROR(dev, 763 NV_ERROR(drm, "Unable to register hwmon device: %d\n", ret);
757 "Unable to register hwmon device: %d\n", ret);
758 return ret; 764 return ret;
759 } 765 }
760 dev_set_drvdata(hwmon_dev, dev); 766 dev_set_drvdata(hwmon_dev, dev);
@@ -778,7 +784,7 @@ nouveau_hwmon_init(struct drm_device *dev)
778 } 784 }
779 785
780 /* if the card can read the fan rpm */ 786 /* if the card can read the fan rpm */
781 if (nouveau_gpio_func_valid(dev, DCB_GPIO_FAN_SENSE)) { 787 if (!gpio->find(gpio, 0, DCB_GPIO_FAN_SENSE, 0xff, &func)) {
782 ret = sysfs_create_group(&dev->pdev->dev.kobj, 788 ret = sysfs_create_group(&dev->pdev->dev.kobj,
783 &hwmon_fan_rpm_attrgroup); 789 &hwmon_fan_rpm_attrgroup);
784 if (ret) 790 if (ret)
@@ -790,7 +796,7 @@ nouveau_hwmon_init(struct drm_device *dev)
790 return 0; 796 return 0;
791 797
792error: 798error:
793 NV_ERROR(dev, "Unable to create some hwmon sysfs files: %d\n", ret); 799 NV_ERROR(drm, "Unable to create some hwmon sysfs files: %d\n", ret);
794 hwmon_device_unregister(hwmon_dev); 800 hwmon_device_unregister(hwmon_dev);
795 pm->hwmon = NULL; 801 pm->hwmon = NULL;
796 return ret; 802 return ret;
@@ -804,8 +810,7 @@ static void
804nouveau_hwmon_fini(struct drm_device *dev) 810nouveau_hwmon_fini(struct drm_device *dev)
805{ 811{
806#if defined(CONFIG_HWMON) || (defined(MODULE) && defined(CONFIG_HWMON_MODULE)) 812#if defined(CONFIG_HWMON) || (defined(MODULE) && defined(CONFIG_HWMON_MODULE))
807 struct drm_nouveau_private *dev_priv = dev->dev_private; 813 struct nouveau_pm *pm = nouveau_pm(dev);
808 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
809 814
810 if (pm->hwmon) { 815 if (pm->hwmon) {
811 sysfs_remove_group(&dev->pdev->dev.kobj, &hwmon_attrgroup); 816 sysfs_remove_group(&dev->pdev->dev.kobj, &hwmon_attrgroup);
@@ -823,16 +828,15 @@ nouveau_hwmon_fini(struct drm_device *dev)
823static int 828static int
824nouveau_pm_acpi_event(struct notifier_block *nb, unsigned long val, void *data) 829nouveau_pm_acpi_event(struct notifier_block *nb, unsigned long val, void *data)
825{ 830{
826 struct drm_nouveau_private *dev_priv = 831 struct nouveau_pm *pm = container_of(nb, struct nouveau_pm, acpi_nb);
827 container_of(nb, struct drm_nouveau_private, engine.pm.acpi_nb); 832 struct nouveau_drm *drm = nouveau_drm(pm->dev);
828 struct drm_device *dev = dev_priv->dev;
829 struct acpi_bus_event *entry = (struct acpi_bus_event *)data; 833 struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
830 834
831 if (strcmp(entry->device_class, "ac_adapter") == 0) { 835 if (strcmp(entry->device_class, "ac_adapter") == 0) {
832 bool ac = power_supply_is_system_supplied(); 836 bool ac = power_supply_is_system_supplied();
833 837
834 NV_DEBUG(dev, "power supply changed: %s\n", ac ? "AC" : "DC"); 838 NV_DEBUG(drm, "power supply changed: %s\n", ac ? "AC" : "DC");
835 nouveau_pm_trigger(dev); 839 nouveau_pm_trigger(pm->dev);
836 } 840 }
837 841
838 return NOTIFY_OK; 842 return NOTIFY_OK;
@@ -842,11 +846,72 @@ nouveau_pm_acpi_event(struct notifier_block *nb, unsigned long val, void *data)
842int 846int
843nouveau_pm_init(struct drm_device *dev) 847nouveau_pm_init(struct drm_device *dev)
844{ 848{
845 struct drm_nouveau_private *dev_priv = dev->dev_private; 849 struct nouveau_device *device = nouveau_dev(dev);
846 struct nouveau_pm_engine *pm = &dev_priv->engine.pm; 850 struct nouveau_drm *drm = nouveau_drm(dev);
851 struct nouveau_pm *pm;
847 char info[256]; 852 char info[256];
848 int ret, i; 853 int ret, i;
849 854
855 pm = drm->pm = kzalloc(sizeof(*pm), GFP_KERNEL);
856 if (!pm)
857 return -ENOMEM;
858
859 pm->dev = dev;
860
861 if (device->card_type < NV_40) {
862 pm->clocks_get = nv04_pm_clocks_get;
863 pm->clocks_pre = nv04_pm_clocks_pre;
864 pm->clocks_set = nv04_pm_clocks_set;
865 if (nouveau_gpio(drm->device)) {
866 pm->voltage_get = nouveau_voltage_gpio_get;
867 pm->voltage_set = nouveau_voltage_gpio_set;
868 }
869 } else
870 if (device->card_type < NV_50) {
871 pm->clocks_get = nv40_pm_clocks_get;
872 pm->clocks_pre = nv40_pm_clocks_pre;
873 pm->clocks_set = nv40_pm_clocks_set;
874 pm->voltage_get = nouveau_voltage_gpio_get;
875 pm->voltage_set = nouveau_voltage_gpio_set;
876 pm->temp_get = nv40_temp_get;
877 pm->pwm_get = nv40_pm_pwm_get;
878 pm->pwm_set = nv40_pm_pwm_set;
879 } else
880 if (device->card_type < NV_C0) {
881 if (device->chipset < 0xa3 ||
882 device->chipset == 0xaa ||
883 device->chipset == 0xac) {
884 pm->clocks_get = nv50_pm_clocks_get;
885 pm->clocks_pre = nv50_pm_clocks_pre;
886 pm->clocks_set = nv50_pm_clocks_set;
887 } else {
888 pm->clocks_get = nva3_pm_clocks_get;
889 pm->clocks_pre = nva3_pm_clocks_pre;
890 pm->clocks_set = nva3_pm_clocks_set;
891 }
892 pm->voltage_get = nouveau_voltage_gpio_get;
893 pm->voltage_set = nouveau_voltage_gpio_set;
894 if (device->chipset == 0x50)
895 pm->temp_get = nv40_temp_get;
896 else
897 pm->temp_get = nv84_temp_get;
898 pm->pwm_get = nv50_pm_pwm_get;
899 pm->pwm_set = nv50_pm_pwm_set;
900 } else
901 if (device->card_type < NV_E0) {
902 pm->clocks_get = nvc0_pm_clocks_get;
903 pm->clocks_pre = nvc0_pm_clocks_pre;
904 pm->clocks_set = nvc0_pm_clocks_set;
905 pm->voltage_get = nouveau_voltage_gpio_get;
906 pm->voltage_set = nouveau_voltage_gpio_set;
907 pm->temp_get = nv84_temp_get;
908 if (device->card_type < NV_D0) {
909 pm->pwm_get = nv50_pm_pwm_get;
910 pm->pwm_set = nv50_pm_pwm_set;
911 }
912 }
913
914
850 /* parse aux tables from vbios */ 915 /* parse aux tables from vbios */
851 nouveau_volt_init(dev); 916 nouveau_volt_init(dev);
852 nouveau_temp_init(dev); 917 nouveau_temp_init(dev);
@@ -854,7 +919,7 @@ nouveau_pm_init(struct drm_device *dev)
854 /* determine current ("boot") performance level */ 919 /* determine current ("boot") performance level */
855 ret = nouveau_pm_perflvl_get(dev, &pm->boot); 920 ret = nouveau_pm_perflvl_get(dev, &pm->boot);
856 if (ret) { 921 if (ret) {
857 NV_ERROR(dev, "failed to determine boot perflvl\n"); 922 NV_ERROR(drm, "failed to determine boot perflvl\n");
858 return ret; 923 return ret;
859 } 924 }
860 925
@@ -874,14 +939,14 @@ nouveau_pm_init(struct drm_device *dev)
874 nouveau_perf_init(dev); 939 nouveau_perf_init(dev);
875 940
876 /* display available performance levels */ 941 /* display available performance levels */
877 NV_INFO(dev, "%d available performance level(s)\n", pm->nr_perflvl); 942 NV_INFO(drm, "%d available performance level(s)\n", pm->nr_perflvl);
878 for (i = 0; i < pm->nr_perflvl; i++) { 943 for (i = 0; i < pm->nr_perflvl; i++) {
879 nouveau_pm_perflvl_info(&pm->perflvl[i], info, sizeof(info)); 944 nouveau_pm_perflvl_info(&pm->perflvl[i], info, sizeof(info));
880 NV_INFO(dev, "%d:%s", pm->perflvl[i].id, info); 945 NV_INFO(drm, "%d:%s", pm->perflvl[i].id, info);
881 } 946 }
882 947
883 nouveau_pm_perflvl_info(&pm->boot, info, sizeof(info)); 948 nouveau_pm_perflvl_info(&pm->boot, info, sizeof(info));
884 NV_INFO(dev, "c:%s", info); 949 NV_INFO(drm, "c:%s", info);
885 950
886 /* switch performance levels now if requested */ 951 /* switch performance levels now if requested */
887 if (nouveau_perflvl != NULL) 952 if (nouveau_perflvl != NULL)
@@ -903,8 +968,7 @@ nouveau_pm_init(struct drm_device *dev)
903void 968void
904nouveau_pm_fini(struct drm_device *dev) 969nouveau_pm_fini(struct drm_device *dev)
905{ 970{
906 struct drm_nouveau_private *dev_priv = dev->dev_private; 971 struct nouveau_pm *pm = nouveau_pm(dev);
907 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
908 struct nouveau_pm_profile *profile, *tmp; 972 struct nouveau_pm_profile *profile, *tmp;
909 973
910 list_for_each_entry_safe(profile, tmp, &pm->profiles, head) { 974 list_for_each_entry_safe(profile, tmp, &pm->profiles, head) {
@@ -924,13 +988,15 @@ nouveau_pm_fini(struct drm_device *dev)
924#endif 988#endif
925 nouveau_hwmon_fini(dev); 989 nouveau_hwmon_fini(dev);
926 nouveau_sysfs_fini(dev); 990 nouveau_sysfs_fini(dev);
991
992 nouveau_drm(dev)->pm = NULL;
993 kfree(pm);
927} 994}
928 995
929void 996void
930nouveau_pm_resume(struct drm_device *dev) 997nouveau_pm_resume(struct drm_device *dev)
931{ 998{
932 struct drm_nouveau_private *dev_priv = dev->dev_private; 999 struct nouveau_pm *pm = nouveau_pm(dev);
933 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
934 struct nouveau_pm_level *perflvl; 1000 struct nouveau_pm_level *perflvl;
935 1001
936 if (!pm->cur || pm->cur == &pm->boot) 1002 if (!pm->cur || pm->cur == &pm->boot)
diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.h b/drivers/gpu/drm/nouveau/nouveau_pm.h
index 07cac72c72b4..e2ec9c0ed567 100644
--- a/drivers/gpu/drm/nouveau/nouveau_pm.h
+++ b/drivers/gpu/drm/nouveau/nouveau_pm.h
@@ -25,6 +25,178 @@
25#ifndef __NOUVEAU_PM_H__ 25#ifndef __NOUVEAU_PM_H__
26#define __NOUVEAU_PM_H__ 26#define __NOUVEAU_PM_H__
27 27
28#include <subdev/bios/pll.h>
29#include <subdev/clock.h>
30
31struct nouveau_pm_voltage_level {
32 u32 voltage; /* microvolts */
33 u8 vid;
34};
35
36struct nouveau_pm_voltage {
37 bool supported;
38 u8 version;
39 u8 vid_mask;
40
41 struct nouveau_pm_voltage_level *level;
42 int nr_level;
43};
44
45/* Exclusive upper limits */
46#define NV_MEM_CL_DDR2_MAX 8
47#define NV_MEM_WR_DDR2_MAX 9
48#define NV_MEM_CL_DDR3_MAX 17
49#define NV_MEM_WR_DDR3_MAX 17
50#define NV_MEM_CL_GDDR3_MAX 16
51#define NV_MEM_WR_GDDR3_MAX 18
52#define NV_MEM_CL_GDDR5_MAX 21
53#define NV_MEM_WR_GDDR5_MAX 20
54
55struct nouveau_pm_memtiming {
56 int id;
57
58 u32 reg[9];
59 u32 mr[4];
60
61 u8 tCWL;
62
63 u8 odt;
64 u8 drive_strength;
65};
66
67struct nouveau_pm_tbl_header {
68 u8 version;
69 u8 header_len;
70 u8 entry_cnt;
71 u8 entry_len;
72};
73
74struct nouveau_pm_tbl_entry {
75 u8 tWR;
76 u8 tWTR;
77 u8 tCL;
78 u8 tRC;
79 u8 empty_4;
80 u8 tRFC; /* Byte 5 */
81 u8 empty_6;
82 u8 tRAS; /* Byte 7 */
83 u8 empty_8;
84 u8 tRP; /* Byte 9 */
85 u8 tRCDRD;
86 u8 tRCDWR;
87 u8 tRRD;
88 u8 tUNK_13;
89 u8 RAM_FT1; /* 14, a bitmask of random RAM features */
90 u8 empty_15;
91 u8 tUNK_16;
92 u8 empty_17;
93 u8 tUNK_18;
94 u8 tCWL;
95 u8 tUNK_20, tUNK_21;
96};
97
98struct nouveau_pm_profile;
99struct nouveau_pm_profile_func {
100 void (*destroy)(struct nouveau_pm_profile *);
101 void (*init)(struct nouveau_pm_profile *);
102 void (*fini)(struct nouveau_pm_profile *);
103 struct nouveau_pm_level *(*select)(struct nouveau_pm_profile *);
104};
105
106struct nouveau_pm_profile {
107 const struct nouveau_pm_profile_func *func;
108 struct list_head head;
109 char name[8];
110};
111
112#define NOUVEAU_PM_MAX_LEVEL 8
113struct nouveau_pm_level {
114 struct nouveau_pm_profile profile;
115 struct device_attribute dev_attr;
116 char name[32];
117 int id;
118
119 struct nouveau_pm_memtiming timing;
120 u32 memory;
121 u16 memscript;
122
123 u32 core;
124 u32 shader;
125 u32 rop;
126 u32 copy;
127 u32 daemon;
128 u32 vdec;
129 u32 dom6;
130 u32 unka0; /* nva3:nvc0 */
131 u32 hub01; /* nvc0- */
132 u32 hub06; /* nvc0- */
133 u32 hub07; /* nvc0- */
134
135 u32 volt_min; /* microvolts */
136 u32 volt_max;
137 u8 fanspeed;
138};
139
140struct nouveau_pm_temp_sensor_constants {
141 u16 offset_constant;
142 s16 offset_mult;
143 s16 offset_div;
144 s16 slope_mult;
145 s16 slope_div;
146};
147
148struct nouveau_pm_threshold_temp {
149 s16 critical;
150 s16 down_clock;
151 s16 fan_boost;
152};
153
154struct nouveau_pm_fan {
155 u32 percent;
156 u32 min_duty;
157 u32 max_duty;
158 u32 pwm_freq;
159 u32 pwm_divisor;
160};
161
162struct nouveau_pm {
163 struct drm_device *dev;
164
165 struct nouveau_pm_voltage voltage;
166 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
167 int nr_perflvl;
168 struct nouveau_pm_temp_sensor_constants sensor_constants;
169 struct nouveau_pm_threshold_temp threshold_temp;
170 struct nouveau_pm_fan fan;
171
172 struct nouveau_pm_profile *profile_ac;
173 struct nouveau_pm_profile *profile_dc;
174 struct nouveau_pm_profile *profile;
175 struct list_head profiles;
176
177 struct nouveau_pm_level boot;
178 struct nouveau_pm_level *cur;
179
180 struct device *hwmon;
181 struct notifier_block acpi_nb;
182
183 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *);
184 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *);
185 int (*clocks_set)(struct drm_device *, void *);
186
187 int (*voltage_get)(struct drm_device *);
188 int (*voltage_set)(struct drm_device *, int voltage);
189 int (*pwm_get)(struct drm_device *, int line, u32*, u32*);
190 int (*pwm_set)(struct drm_device *, int line, u32, u32);
191 int (*temp_get)(struct drm_device *);
192};
193
194static inline struct nouveau_pm *
195nouveau_pm(struct drm_device *dev)
196{
197 return nouveau_drm(dev)->pm;
198}
199
28struct nouveau_mem_exec_func { 200struct nouveau_mem_exec_func {
29 struct drm_device *dev; 201 struct drm_device *dev;
30 void (*precharge)(struct nouveau_mem_exec_func *); 202 void (*precharge)(struct nouveau_mem_exec_func *);
@@ -106,4 +278,26 @@ void nouveau_temp_safety_checks(struct drm_device *dev);
106int nv40_temp_get(struct drm_device *dev); 278int nv40_temp_get(struct drm_device *dev);
107int nv84_temp_get(struct drm_device *dev); 279int nv84_temp_get(struct drm_device *dev);
108 280
281/* nouveau_mem.c */
282int nouveau_mem_timing_calc(struct drm_device *, u32 freq,
283 struct nouveau_pm_memtiming *);
284void nouveau_mem_timing_read(struct drm_device *,
285 struct nouveau_pm_memtiming *);
286
287static inline int
288nva3_calc_pll(struct drm_device *dev, struct nvbios_pll *pll, u32 freq,
289 int *N, int *fN, int *M, int *P)
290{
291 struct nouveau_device *device = nouveau_dev(dev);
292 struct nouveau_clock *clk = nouveau_clock(device);
293 struct nouveau_pll_vals pv;
294 int ret;
295
296 ret = clk->pll_calc(clk, pll, freq, &pv);
297 *N = pv.N1;
298 *M = pv.M1;
299 *P = pv.log2P;
300 return ret;
301}
302
109#endif 303#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_prime.c b/drivers/gpu/drm/nouveau/nouveau_prime.c
index de0b81fbdcc1..4ffa655545e5 100644
--- a/drivers/gpu/drm/nouveau/nouveau_prime.c
+++ b/drivers/gpu/drm/nouveau/nouveau_prime.c
@@ -22,13 +22,13 @@
22 * Authors: Dave Airlie 22 * Authors: Dave Airlie
23 */ 23 */
24 24
25#include <linux/dma-buf.h>
26
25#include "drmP.h" 27#include "drmP.h"
26#include "drm.h" 28#include "drm.h"
27 29
28#include "nouveau_drv.h" 30#include "nouveau_drm.h"
29#include <nouveau_drm.h> 31#include "nouveau_gem.h"
30
31#include <linux/dma-buf.h>
32 32
33static struct sg_table *nouveau_gem_map_dma_buf(struct dma_buf_attachment *attachment, 33static struct sg_table *nouveau_gem_map_dma_buf(struct dma_buf_attachment *attachment,
34 enum dma_data_direction dir) 34 enum dma_data_direction dir)
diff --git a/drivers/gpu/drm/nouveau/nouveau_revcompat.c b/drivers/gpu/drm/nouveau/nouveau_revcompat.c
deleted file mode 100644
index d5c3390503db..000000000000
--- a/drivers/gpu/drm/nouveau/nouveau_revcompat.c
+++ /dev/null
@@ -1,22 +0,0 @@
1#include "nouveau_revcompat.h"
2#include "nouveau_drv.h"
3#include "nv50_display.h"
4
5struct nouveau_drm *
6nouveau_newpriv(struct drm_device *dev)
7{
8 struct drm_nouveau_private *dev_priv = dev->dev_private;
9 return dev_priv->newpriv;
10}
11
12struct nouveau_bo *
13nv50sema(struct drm_device *dev, int crtc)
14{
15 return nv50_display(dev)->crtc[crtc].sem.bo;
16}
17
18struct nouveau_bo *
19nvd0sema(struct drm_device *dev, int crtc)
20{
21 return nvd0_display_crtc_sema(dev, crtc);
22}
diff --git a/drivers/gpu/drm/nouveau/nouveau_revcompat.h b/drivers/gpu/drm/nouveau/nouveau_revcompat.h
deleted file mode 100644
index 41cf61f1415f..000000000000
--- a/drivers/gpu/drm/nouveau/nouveau_revcompat.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef __NOUVEAU_REVCOMPAT_H__
2#define __NOUVEAU_REVCOMPAT_H__
3
4#include "drmP.h"
5
6struct nouveau_drm *
7nouveau_newpriv(struct drm_device *);
8
9struct nouveau_bo *nv50sema(struct drm_device *dev, int crtc);
10struct nouveau_bo *nvd0sema(struct drm_device *dev, int crtc);
11
12#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
deleted file mode 100644
index d4daba331bb8..000000000000
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ /dev/null
@@ -1,508 +0,0 @@
1/*
2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26#include <linux/swab.h>
27#include <linux/slab.h>
28#include "drmP.h"
29#include "drm.h"
30#include "drm_sarea.h"
31#include "drm_crtc_helper.h"
32#include <linux/vgaarb.h>
33#include <linux/vga_switcheroo.h>
34
35#include "nouveau_drv.h"
36#include <nouveau_drm.h>
37#include "nouveau_fbcon.h"
38#include "nouveau_pm.h"
39#include "nv04_display.h"
40#include "nv50_display.h"
41#include "nouveau_acpi.h"
42
43static void nouveau_stub_takedown(struct drm_device *dev) {}
44static int nouveau_stub_init(struct drm_device *dev) { return 0; }
45
46static int nouveau_init_engine_ptrs(struct drm_device *dev)
47{
48 struct drm_nouveau_private *dev_priv = dev->dev_private;
49 struct nouveau_engine *engine = &dev_priv->engine;
50
51 switch (dev_priv->chipset & 0xf0) {
52 case 0x00:
53 engine->display.early_init = nv04_display_early_init;
54 engine->display.late_takedown = nv04_display_late_takedown;
55 engine->display.create = nv04_display_create;
56 engine->display.destroy = nv04_display_destroy;
57 engine->display.init = nv04_display_init;
58 engine->display.fini = nv04_display_fini;
59 engine->pm.clocks_get = nv04_pm_clocks_get;
60 engine->pm.clocks_pre = nv04_pm_clocks_pre;
61 engine->pm.clocks_set = nv04_pm_clocks_set;
62 break;
63 case 0x10:
64 engine->display.early_init = nv04_display_early_init;
65 engine->display.late_takedown = nv04_display_late_takedown;
66 engine->display.create = nv04_display_create;
67 engine->display.destroy = nv04_display_destroy;
68 engine->display.init = nv04_display_init;
69 engine->display.fini = nv04_display_fini;
70 engine->pm.clocks_get = nv04_pm_clocks_get;
71 engine->pm.clocks_pre = nv04_pm_clocks_pre;
72 engine->pm.clocks_set = nv04_pm_clocks_set;
73 break;
74 case 0x20:
75 engine->display.early_init = nv04_display_early_init;
76 engine->display.late_takedown = nv04_display_late_takedown;
77 engine->display.create = nv04_display_create;
78 engine->display.destroy = nv04_display_destroy;
79 engine->display.init = nv04_display_init;
80 engine->display.fini = nv04_display_fini;
81 engine->pm.clocks_get = nv04_pm_clocks_get;
82 engine->pm.clocks_pre = nv04_pm_clocks_pre;
83 engine->pm.clocks_set = nv04_pm_clocks_set;
84 break;
85 case 0x30:
86 engine->display.early_init = nv04_display_early_init;
87 engine->display.late_takedown = nv04_display_late_takedown;
88 engine->display.create = nv04_display_create;
89 engine->display.destroy = nv04_display_destroy;
90 engine->display.init = nv04_display_init;
91 engine->display.fini = nv04_display_fini;
92 engine->pm.clocks_get = nv04_pm_clocks_get;
93 engine->pm.clocks_pre = nv04_pm_clocks_pre;
94 engine->pm.clocks_set = nv04_pm_clocks_set;
95 engine->pm.voltage_get = nouveau_voltage_gpio_get;
96 engine->pm.voltage_set = nouveau_voltage_gpio_set;
97 break;
98 case 0x40:
99 case 0x60:
100 engine->display.early_init = nv04_display_early_init;
101 engine->display.late_takedown = nv04_display_late_takedown;
102 engine->display.create = nv04_display_create;
103 engine->display.destroy = nv04_display_destroy;
104 engine->display.init = nv04_display_init;
105 engine->display.fini = nv04_display_fini;
106 engine->pm.clocks_get = nv40_pm_clocks_get;
107 engine->pm.clocks_pre = nv40_pm_clocks_pre;
108 engine->pm.clocks_set = nv40_pm_clocks_set;
109 engine->pm.voltage_get = nouveau_voltage_gpio_get;
110 engine->pm.voltage_set = nouveau_voltage_gpio_set;
111 engine->pm.temp_get = nv40_temp_get;
112 engine->pm.pwm_get = nv40_pm_pwm_get;
113 engine->pm.pwm_set = nv40_pm_pwm_set;
114 break;
115 case 0x50:
116 case 0x80: /* gotta love NVIDIA's consistency.. */
117 case 0x90:
118 case 0xa0:
119 engine->display.early_init = nv50_display_early_init;
120 engine->display.late_takedown = nv50_display_late_takedown;
121 engine->display.create = nv50_display_create;
122 engine->display.destroy = nv50_display_destroy;
123 engine->display.init = nv50_display_init;
124 engine->display.fini = nv50_display_fini;
125 switch (dev_priv->chipset) {
126 case 0x84:
127 case 0x86:
128 case 0x92:
129 case 0x94:
130 case 0x96:
131 case 0x98:
132 case 0xa0:
133 case 0xaa:
134 case 0xac:
135 case 0x50:
136 engine->pm.clocks_get = nv50_pm_clocks_get;
137 engine->pm.clocks_pre = nv50_pm_clocks_pre;
138 engine->pm.clocks_set = nv50_pm_clocks_set;
139 break;
140 default:
141 engine->pm.clocks_get = nva3_pm_clocks_get;
142 engine->pm.clocks_pre = nva3_pm_clocks_pre;
143 engine->pm.clocks_set = nva3_pm_clocks_set;
144 break;
145 }
146 engine->pm.voltage_get = nouveau_voltage_gpio_get;
147 engine->pm.voltage_set = nouveau_voltage_gpio_set;
148 if (dev_priv->chipset >= 0x84)
149 engine->pm.temp_get = nv84_temp_get;
150 else
151 engine->pm.temp_get = nv40_temp_get;
152 engine->pm.pwm_get = nv50_pm_pwm_get;
153 engine->pm.pwm_set = nv50_pm_pwm_set;
154 break;
155 case 0xc0:
156 engine->display.early_init = nv50_display_early_init;
157 engine->display.late_takedown = nv50_display_late_takedown;
158 engine->display.create = nv50_display_create;
159 engine->display.destroy = nv50_display_destroy;
160 engine->display.init = nv50_display_init;
161 engine->display.fini = nv50_display_fini;
162 engine->pm.temp_get = nv84_temp_get;
163 engine->pm.clocks_get = nvc0_pm_clocks_get;
164 engine->pm.clocks_pre = nvc0_pm_clocks_pre;
165 engine->pm.clocks_set = nvc0_pm_clocks_set;
166 engine->pm.voltage_get = nouveau_voltage_gpio_get;
167 engine->pm.voltage_set = nouveau_voltage_gpio_set;
168 engine->pm.pwm_get = nv50_pm_pwm_get;
169 engine->pm.pwm_set = nv50_pm_pwm_set;
170 break;
171 case 0xd0:
172 engine->display.early_init = nouveau_stub_init;
173 engine->display.late_takedown = nouveau_stub_takedown;
174 engine->display.create = nvd0_display_create;
175 engine->display.destroy = nvd0_display_destroy;
176 engine->display.init = nvd0_display_init;
177 engine->display.fini = nvd0_display_fini;
178 engine->pm.temp_get = nv84_temp_get;
179 engine->pm.clocks_get = nvc0_pm_clocks_get;
180 engine->pm.clocks_pre = nvc0_pm_clocks_pre;
181 engine->pm.clocks_set = nvc0_pm_clocks_set;
182 engine->pm.voltage_get = nouveau_voltage_gpio_get;
183 engine->pm.voltage_set = nouveau_voltage_gpio_set;
184 break;
185 case 0xe0:
186 engine->display.early_init = nouveau_stub_init;
187 engine->display.late_takedown = nouveau_stub_takedown;
188 engine->display.create = nvd0_display_create;
189 engine->display.destroy = nvd0_display_destroy;
190 engine->display.init = nvd0_display_init;
191 engine->display.fini = nvd0_display_fini;
192 break;
193 default:
194 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
195 return 1;
196 }
197
198 /* headless mode */
199 if (nouveau_modeset == 2) {
200 engine->display.early_init = nouveau_stub_init;
201 engine->display.late_takedown = nouveau_stub_takedown;
202 engine->display.create = nouveau_stub_init;
203 engine->display.init = nouveau_stub_init;
204 engine->display.destroy = nouveau_stub_takedown;
205 }
206
207 return 0;
208}
209
210static unsigned int
211nouveau_vga_set_decode(void *priv, bool state)
212{
213 struct drm_device *dev = priv;
214 struct drm_nouveau_private *dev_priv = dev->dev_private;
215
216 if (dev_priv->chipset >= 0x40)
217 nv_wr32(dev, 0x88054, state);
218 else
219 nv_wr32(dev, 0x1854, state);
220
221 if (state)
222 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
223 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
224 else
225 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
226}
227
228static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
229 enum vga_switcheroo_state state)
230{
231 struct drm_device *dev = pci_get_drvdata(pdev);
232 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
233 if (state == VGA_SWITCHEROO_ON) {
234 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
235 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
236 nouveau_pci_resume(pdev);
237 drm_kms_helper_poll_enable(dev);
238 dev->switch_power_state = DRM_SWITCH_POWER_ON;
239 } else {
240 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
241 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
242 drm_kms_helper_poll_disable(dev);
243 nouveau_switcheroo_optimus_dsm();
244 nouveau_pci_suspend(pdev, pmm);
245 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
246 }
247}
248
249static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
250{
251 struct drm_device *dev = pci_get_drvdata(pdev);
252 nouveau_fbcon_output_poll_changed(dev);
253}
254
255static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
256{
257 struct drm_device *dev = pci_get_drvdata(pdev);
258 bool can_switch;
259
260 spin_lock(&dev->count_lock);
261 can_switch = (dev->open_count == 0);
262 spin_unlock(&dev->count_lock);
263 return can_switch;
264}
265
266static const struct vga_switcheroo_client_ops nouveau_switcheroo_ops = {
267 .set_gpu_state = nouveau_switcheroo_set_state,
268 .reprobe = nouveau_switcheroo_reprobe,
269 .can_switch = nouveau_switcheroo_can_switch,
270};
271
272int
273nouveau_card_init(struct drm_device *dev)
274{
275 struct drm_nouveau_private *dev_priv = dev->dev_private;
276 struct nouveau_engine *engine;
277 int ret;
278
279 vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
280 vga_switcheroo_register_client(dev->pdev, &nouveau_switcheroo_ops);
281
282 /* Initialise internal driver API hooks */
283 ret = nouveau_init_engine_ptrs(dev);
284 if (ret)
285 goto out;
286 engine = &dev_priv->engine;
287 spin_lock_init(&dev_priv->context_switch_lock);
288
289 /* Make the CRTCs and I2C buses accessible */
290 ret = engine->display.early_init(dev);
291 if (ret)
292 goto out;
293
294 /* Parse BIOS tables / Run init tables if card not POSTed */
295 ret = nouveau_bios_init(dev);
296 if (ret)
297 goto out_display_early;
298
299 /* workaround an odd issue on nvc1 by disabling the device's
300 * nosnoop capability. hopefully won't cause issues until a
301 * better fix is found - assuming there is one...
302 */
303 if (dev_priv->chipset == 0xc1) {
304 nv_mask(dev, 0x00088080, 0x00000800, 0x00000000);
305 }
306
307 ret = nouveau_irq_init(dev);
308 if (ret)
309 goto out_bios;
310
311 ret = nouveau_display_create(dev);
312 if (ret)
313 goto out_irq;
314
315 nouveau_backlight_init(dev);
316 nouveau_pm_init(dev);
317
318 if (dev->mode_config.num_crtc) {
319 ret = nouveau_display_init(dev);
320 if (ret)
321 goto out_pm;
322 }
323
324 return 0;
325
326out_pm:
327 nouveau_pm_fini(dev);
328 nouveau_backlight_exit(dev);
329 nouveau_display_destroy(dev);
330out_irq:
331 nouveau_irq_fini(dev);
332out_bios:
333 nouveau_bios_takedown(dev);
334out_display_early:
335 engine->display.late_takedown(dev);
336out:
337 vga_switcheroo_unregister_client(dev->pdev);
338 vga_client_register(dev->pdev, NULL, NULL, NULL);
339 return ret;
340}
341
342static void nouveau_card_takedown(struct drm_device *dev)
343{
344 struct drm_nouveau_private *dev_priv = dev->dev_private;
345 struct nouveau_engine *engine = &dev_priv->engine;
346
347 if (dev->mode_config.num_crtc)
348 nouveau_display_fini(dev);
349
350 nouveau_pm_fini(dev);
351 nouveau_backlight_exit(dev);
352 nouveau_display_destroy(dev);
353
354 nouveau_bios_takedown(dev);
355 engine->display.late_takedown(dev);
356
357 nouveau_irq_fini(dev);
358
359 vga_switcheroo_unregister_client(dev->pdev);
360 vga_client_register(dev->pdev, NULL, NULL, NULL);
361}
362
363/* first module load, setup the mmio/fb mapping */
364/* KMS: we need mmio at load time, not when the first drm client opens. */
365int nouveau_firstopen(struct drm_device *dev)
366{
367 return 0;
368}
369
370/* if we have an OF card, copy vbios to RAMIN */
371static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
372{
373#if defined(__powerpc__)
374 int size, i;
375 const uint32_t *bios;
376 struct device_node *dn = pci_device_to_OF_node(dev->pdev);
377 if (!dn) {
378 NV_INFO(dev, "Unable to get the OF node\n");
379 return;
380 }
381
382 bios = of_get_property(dn, "NVDA,BMP", &size);
383 if (bios) {
384 for (i = 0; i < size; i += 4)
385 nv_wi32(dev, i, bios[i/4]);
386 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
387 } else {
388 NV_INFO(dev, "Unable to get the OF bios\n");
389 }
390#endif
391}
392
393int nouveau_load(struct drm_device *dev, unsigned long flags)
394{
395 struct drm_nouveau_private *dev_priv;
396 uint32_t reg0 = ~0, strap;
397 int ret;
398
399 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
400 if (!dev_priv) {
401 ret = -ENOMEM;
402 goto err_out;
403 }
404 dev_priv->newpriv = dev->dev_private;
405 dev->dev_private = dev_priv;
406 dev_priv->dev = dev;
407
408 NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
409 dev->pci_vendor, dev->pci_device, dev->pdev->class);
410
411 /* determine chipset and derive architecture from it */
412 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
413 if ((reg0 & 0x0f000000) > 0) {
414 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
415 switch (dev_priv->chipset & 0xf0) {
416 case 0x10:
417 case 0x20:
418 case 0x30:
419 dev_priv->card_type = dev_priv->chipset & 0xf0;
420 break;
421 case 0x40:
422 case 0x60:
423 dev_priv->card_type = NV_40;
424 break;
425 case 0x50:
426 case 0x80:
427 case 0x90:
428 case 0xa0:
429 dev_priv->card_type = NV_50;
430 break;
431 case 0xc0:
432 dev_priv->card_type = NV_C0;
433 break;
434 case 0xd0:
435 dev_priv->card_type = NV_D0;
436 break;
437 case 0xe0:
438 dev_priv->card_type = NV_E0;
439 break;
440 default:
441 break;
442 }
443 } else
444 if ((reg0 & 0xff00fff0) == 0x20004000) {
445 if (reg0 & 0x00f00000)
446 dev_priv->chipset = 0x05;
447 else
448 dev_priv->chipset = 0x04;
449 dev_priv->card_type = NV_04;
450 }
451
452 if (!dev_priv->card_type) {
453 NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0);
454 ret = -EINVAL;
455 goto err_priv;
456 }
457
458 NV_INFO(dev, "Detected an NV%02x generation card (0x%08x)\n",
459 dev_priv->card_type, reg0);
460
461 /* determine frequency of timing crystal */
462 strap = nv_rd32(dev, 0x101000);
463 if ( dev_priv->chipset < 0x17 ||
464 (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25))
465 strap &= 0x00000040;
466 else
467 strap &= 0x00400040;
468
469 switch (strap) {
470 case 0x00000000: dev_priv->crystal = 13500; break;
471 case 0x00000040: dev_priv->crystal = 14318; break;
472 case 0x00400000: dev_priv->crystal = 27000; break;
473 case 0x00400040: dev_priv->crystal = 25000; break;
474 }
475
476 NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal);
477
478 nouveau_OF_copy_vbios_to_ramin(dev);
479
480 /* For kernel modesetting, init card now and bring up fbcon */
481 ret = nouveau_card_init(dev);
482 if (ret)
483 goto err_priv;
484
485 return 0;
486
487err_priv:
488 dev->dev_private = dev_priv->newpriv;
489 kfree(dev_priv);
490err_out:
491 return ret;
492}
493
494void nouveau_lastclose(struct drm_device *dev)
495{
496 vga_switcheroo_process_delayed_switch();
497}
498
499int nouveau_unload(struct drm_device *dev)
500{
501 struct drm_nouveau_private *dev_priv = dev->dev_private;
502
503 nouveau_card_takedown(dev);
504
505 dev->dev_private = dev_priv->newpriv;
506 kfree(dev_priv);
507 return 0;
508}
diff --git a/drivers/gpu/drm/nouveau/nouveau_temp.c b/drivers/gpu/drm/nouveau/nouveau_temp.c
index d00b9012a8fd..7ae25e47be9f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_temp.c
+++ b/drivers/gpu/drm/nouveau/nouveau_temp.c
@@ -26,20 +26,22 @@
26 26
27#include "drmP.h" 27#include "drmP.h"
28 28
29#include "nouveau_drv.h" 29#include "nouveau_drm.h"
30#include "nouveau_pm.h" 30#include "nouveau_pm.h"
31 31
32#include <subdev/i2c.h>
33
32static void 34static void
33nouveau_temp_vbios_parse(struct drm_device *dev, u8 *temp) 35nouveau_temp_vbios_parse(struct drm_device *dev, u8 *temp)
34{ 36{
35 struct drm_nouveau_private *dev_priv = dev->dev_private; 37 struct nouveau_drm *drm = nouveau_drm(dev);
36 struct nouveau_pm_engine *pm = &dev_priv->engine.pm; 38 struct nouveau_pm *pm = nouveau_pm(dev);
37 struct nouveau_pm_temp_sensor_constants *sensor = &pm->sensor_constants; 39 struct nouveau_pm_temp_sensor_constants *sensor = &pm->sensor_constants;
38 struct nouveau_pm_threshold_temp *temps = &pm->threshold_temp; 40 struct nouveau_pm_threshold_temp *temps = &pm->threshold_temp;
39 int i, headerlen, recordlen, entries; 41 int i, headerlen, recordlen, entries;
40 42
41 if (!temp) { 43 if (!temp) {
42 NV_DEBUG(dev, "temperature table pointer invalid\n"); 44 NV_DEBUG(drm, "temperature table pointer invalid\n");
43 return; 45 return;
44 } 46 }
45 47
@@ -60,8 +62,8 @@ nouveau_temp_vbios_parse(struct drm_device *dev, u8 *temp)
60 pm->fan.max_duty = 100; 62 pm->fan.max_duty = 100;
61 63
62 /* Set the known default values to setup the temperature sensor */ 64 /* Set the known default values to setup the temperature sensor */
63 if (dev_priv->card_type >= NV_40) { 65 if (nv_device(drm->device)->card_type >= NV_40) {
64 switch (dev_priv->chipset) { 66 switch (nv_device(drm->device)->chipset) {
65 case 0x43: 67 case 0x43:
66 sensor->offset_mult = 32060; 68 sensor->offset_mult = 32060;
67 sensor->offset_div = 1000; 69 sensor->offset_div = 1000;
@@ -185,8 +187,9 @@ nouveau_temp_vbios_parse(struct drm_device *dev, u8 *temp)
185static int 187static int
186nv40_sensor_setup(struct drm_device *dev) 188nv40_sensor_setup(struct drm_device *dev)
187{ 189{
188 struct drm_nouveau_private *dev_priv = dev->dev_private; 190 struct nouveau_device *device = nouveau_dev(dev);
189 struct nouveau_pm_engine *pm = &dev_priv->engine.pm; 191 struct nouveau_drm *drm = nouveau_drm(dev);
192 struct nouveau_pm *pm = nouveau_pm(dev);
190 struct nouveau_pm_temp_sensor_constants *sensor = &pm->sensor_constants; 193 struct nouveau_pm_temp_sensor_constants *sensor = &pm->sensor_constants;
191 s32 offset = sensor->offset_mult / sensor->offset_div; 194 s32 offset = sensor->offset_mult / sensor->offset_div;
192 s32 sensor_calibration; 195 s32 sensor_calibration;
@@ -196,33 +199,34 @@ nv40_sensor_setup(struct drm_device *dev)
196 sensor_calibration = sensor_calibration * sensor->slope_div / 199 sensor_calibration = sensor_calibration * sensor->slope_div /
197 sensor->slope_mult; 200 sensor->slope_mult;
198 201
199 if (dev_priv->chipset >= 0x46) 202 if (nv_device(drm->device)->chipset >= 0x46)
200 sensor_calibration |= 0x80000000; 203 sensor_calibration |= 0x80000000;
201 else 204 else
202 sensor_calibration |= 0x10000000; 205 sensor_calibration |= 0x10000000;
203 206
204 nv_wr32(dev, 0x0015b0, sensor_calibration); 207 nv_wr32(device, 0x0015b0, sensor_calibration);
205 208
206 /* Wait for the sensor to update */ 209 /* Wait for the sensor to update */
207 msleep(5); 210 msleep(5);
208 211
209 /* read */ 212 /* read */
210 return nv_rd32(dev, 0x0015b4) & 0x1fff; 213 return nv_rd32(device, 0x0015b4) & 0x1fff;
211} 214}
212 215
213int 216int
214nv40_temp_get(struct drm_device *dev) 217nv40_temp_get(struct drm_device *dev)
215{ 218{
216 struct drm_nouveau_private *dev_priv = dev->dev_private; 219 struct nouveau_device *device = nouveau_dev(dev);
217 struct nouveau_pm_engine *pm = &dev_priv->engine.pm; 220 struct nouveau_drm *drm = nouveau_drm(dev);
221 struct nouveau_pm *pm = nouveau_pm(dev);
218 struct nouveau_pm_temp_sensor_constants *sensor = &pm->sensor_constants; 222 struct nouveau_pm_temp_sensor_constants *sensor = &pm->sensor_constants;
219 int offset = sensor->offset_mult / sensor->offset_div; 223 int offset = sensor->offset_mult / sensor->offset_div;
220 int core_temp; 224 int core_temp;
221 225
222 if (dev_priv->card_type >= NV_50) { 226 if (nv_device(drm->device)->card_type >= NV_50) {
223 core_temp = nv_rd32(dev, 0x20008); 227 core_temp = nv_rd32(device, 0x20008);
224 } else { 228 } else {
225 core_temp = nv_rd32(dev, 0x0015b4) & 0x1fff; 229 core_temp = nv_rd32(device, 0x0015b4) & 0x1fff;
226 /* Setup the sensor if the temperature is 0 */ 230 /* Setup the sensor if the temperature is 0 */
227 if (core_temp == 0) 231 if (core_temp == 0)
228 core_temp = nv40_sensor_setup(dev); 232 core_temp = nv40_sensor_setup(dev);
@@ -237,14 +241,14 @@ nv40_temp_get(struct drm_device *dev)
237int 241int
238nv84_temp_get(struct drm_device *dev) 242nv84_temp_get(struct drm_device *dev)
239{ 243{
240 return nv_rd32(dev, 0x20400); 244 struct nouveau_device *device = nouveau_dev(dev);
245 return nv_rd32(device, 0x20400);
241} 246}
242 247
243void 248void
244nouveau_temp_safety_checks(struct drm_device *dev) 249nouveau_temp_safety_checks(struct drm_device *dev)
245{ 250{
246 struct drm_nouveau_private *dev_priv = dev->dev_private; 251 struct nouveau_pm *pm = nouveau_pm(dev);
247 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
248 struct nouveau_pm_threshold_temp *temps = &pm->threshold_temp; 252 struct nouveau_pm_threshold_temp *temps = &pm->threshold_temp;
249 253
250 if (temps->critical > 120) 254 if (temps->critical > 120)
@@ -271,7 +275,7 @@ probe_monitoring_device(struct nouveau_i2c_port *i2c,
271 275
272 request_module("%s%s", I2C_MODULE_PREFIX, info->type); 276 request_module("%s%s", I2C_MODULE_PREFIX, info->type);
273 277
274 client = i2c_new_device(nouveau_i2c_adapter(i2c), info); 278 client = i2c_new_device(&i2c->adapter, info);
275 if (!client) 279 if (!client)
276 return false; 280 return false;
277 281
@@ -286,6 +290,8 @@ probe_monitoring_device(struct nouveau_i2c_port *i2c,
286static void 290static void
287nouveau_temp_probe_i2c(struct drm_device *dev) 291nouveau_temp_probe_i2c(struct drm_device *dev)
288{ 292{
293 struct nouveau_device *device = nouveau_dev(dev);
294 struct nouveau_i2c *i2c = nouveau_i2c(device);
289 struct i2c_board_info info[] = { 295 struct i2c_board_info info[] = {
290 { I2C_BOARD_INFO("w83l785ts", 0x2d) }, 296 { I2C_BOARD_INFO("w83l785ts", 0x2d) },
291 { I2C_BOARD_INFO("w83781d", 0x2d) }, 297 { I2C_BOARD_INFO("w83781d", 0x2d) },
@@ -295,15 +301,15 @@ nouveau_temp_probe_i2c(struct drm_device *dev)
295 { } 301 { }
296 }; 302 };
297 303
298 nouveau_i2c_identify(dev, "monitoring device", info, 304 i2c->identify(i2c, NV_I2C_DEFAULT(0), "monitoring device", info,
299 probe_monitoring_device, 0x80); //NV_I2C_DEFAULT(0)); 305 probe_monitoring_device);
300} 306}
301 307
302void 308void
303nouveau_temp_init(struct drm_device *dev) 309nouveau_temp_init(struct drm_device *dev)
304{ 310{
305 struct drm_nouveau_private *dev_priv = dev->dev_private; 311 struct nouveau_drm *drm = nouveau_drm(dev);
306 struct nvbios *bios = &dev_priv->vbios; 312 struct nvbios *bios = &drm->vbios;
307 struct bit_entry P; 313 struct bit_entry P;
308 u8 *temp = NULL; 314 u8 *temp = NULL;
309 315
@@ -316,7 +322,7 @@ nouveau_temp_init(struct drm_device *dev)
316 else if (P.version == 2) 322 else if (P.version == 2)
317 temp = ROMPTR(dev, P.data[16]); 323 temp = ROMPTR(dev, P.data[16]);
318 else 324 else
319 NV_WARN(dev, "unknown temp for BIT P %d\n", P.version); 325 NV_WARN(drm, "unknown temp for BIT P %d\n", P.version);
320 326
321 nouveau_temp_vbios_parse(dev, temp); 327 nouveau_temp_vbios_parse(dev, temp);
322 } 328 }
diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c
index 560e816138eb..030e4b84386c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_ttm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c
@@ -265,7 +265,7 @@ int
265nouveau_ttm_mmap(struct file *filp, struct vm_area_struct *vma) 265nouveau_ttm_mmap(struct file *filp, struct vm_area_struct *vma)
266{ 266{
267 struct drm_file *file_priv = filp->private_data; 267 struct drm_file *file_priv = filp->private_data;
268 struct nouveau_drm *drm = nouveau_newpriv(file_priv->minor->dev); 268 struct nouveau_drm *drm = nouveau_drm(file_priv->minor->dev);
269 269
270 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) 270 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
271 return drm_mmap(filp, vma); 271 return drm_mmap(filp, vma);
diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.h b/drivers/gpu/drm/nouveau/nouveau_ttm.h
index 9f4d2715584b..25b0de413352 100644
--- a/drivers/gpu/drm/nouveau/nouveau_ttm.h
+++ b/drivers/gpu/drm/nouveau/nouveau_ttm.h
@@ -17,5 +17,9 @@ struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *,
17 17
18int nouveau_ttm_init(struct nouveau_drm *drm); 18int nouveau_ttm_init(struct nouveau_drm *drm);
19void nouveau_ttm_fini(struct nouveau_drm *drm); 19void nouveau_ttm_fini(struct nouveau_drm *drm);
20int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
21
22int nouveau_ttm_global_init(struct nouveau_drm *);
23void nouveau_ttm_global_release(struct nouveau_drm *);
20 24
21#endif 25#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_vga.c b/drivers/gpu/drm/nouveau/nouveau_vga.c
new file mode 100644
index 000000000000..9d455444f958
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_vga.c
@@ -0,0 +1,98 @@
1#include <linux/vgaarb.h>
2#include <linux/vga_switcheroo.h>
3
4#include "drmP.h"
5#include "drm_crtc_helper.h"
6
7#include "nouveau_drm.h"
8#include "nouveau_acpi.h"
9#include "nouveau_fbcon.h"
10
11static unsigned int
12nouveau_vga_set_decode(void *priv, bool state)
13{
14 struct nouveau_device *device = nouveau_dev(priv);
15
16 if (device->chipset >= 0x40)
17 nv_wr32(device, 0x088054, state);
18 else
19 nv_wr32(device, 0x001854, state);
20
21 if (state)
22 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
23 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
24 else
25 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
26}
27
28static void
29nouveau_switcheroo_set_state(struct pci_dev *pdev,
30 enum vga_switcheroo_state state)
31{
32 struct drm_device *dev = pci_get_drvdata(pdev);
33 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
34
35 if (state == VGA_SWITCHEROO_ON) {
36 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
37 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
38 nouveau_drm_resume(pdev);
39 drm_kms_helper_poll_enable(dev);
40 dev->switch_power_state = DRM_SWITCH_POWER_ON;
41 } else {
42 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
43 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
44 drm_kms_helper_poll_disable(dev);
45 nouveau_switcheroo_optimus_dsm();
46 nouveau_drm_suspend(pdev, pmm);
47 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
48 }
49}
50
51static void
52nouveau_switcheroo_reprobe(struct pci_dev *pdev)
53{
54 struct drm_device *dev = pci_get_drvdata(pdev);
55 nouveau_fbcon_output_poll_changed(dev);
56}
57
58static bool
59nouveau_switcheroo_can_switch(struct pci_dev *pdev)
60{
61 struct drm_device *dev = pci_get_drvdata(pdev);
62 bool can_switch;
63
64 spin_lock(&dev->count_lock);
65 can_switch = (dev->open_count == 0);
66 spin_unlock(&dev->count_lock);
67 return can_switch;
68}
69
70static const struct vga_switcheroo_client_ops
71nouveau_switcheroo_ops = {
72 .set_gpu_state = nouveau_switcheroo_set_state,
73 .reprobe = nouveau_switcheroo_reprobe,
74 .can_switch = nouveau_switcheroo_can_switch,
75};
76
77void
78nouveau_vga_init(struct nouveau_drm *drm)
79{
80 struct drm_device *dev = drm->dev;
81 vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
82 vga_switcheroo_register_client(dev->pdev, &nouveau_switcheroo_ops);
83}
84
85void
86nouveau_vga_fini(struct nouveau_drm *drm)
87{
88 struct drm_device *dev = drm->dev;
89 vga_switcheroo_unregister_client(dev->pdev);
90 vga_client_register(dev->pdev, NULL, NULL, NULL);
91}
92
93
94void
95nouveau_vga_lastclose(struct drm_device *dev)
96{
97 vga_switcheroo_process_delayed_switch();
98}
diff --git a/drivers/gpu/drm/nouveau/nouveau_vga.h b/drivers/gpu/drm/nouveau/nouveau_vga.h
new file mode 100644
index 000000000000..ea3ad6974c65
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_vga.h
@@ -0,0 +1,8 @@
1#ifndef __NOUVEAU_VGA_H__
2#define __NOUVEAU_VGA_H__
3
4void nouveau_vga_init(struct nouveau_drm *);
5void nouveau_vga_fini(struct nouveau_drm *);
6void nouveau_vga_lastclose(struct drm_device *dev);
7
8#endif
diff --git a/drivers/gpu/drm/nouveau/nouveau_volt.c b/drivers/gpu/drm/nouveau/nouveau_volt.c
index da3222c5a30b..c2cc8e2d6539 100644
--- a/drivers/gpu/drm/nouveau/nouveau_volt.c
+++ b/drivers/gpu/drm/nouveau/nouveau_volt.c
@@ -24,10 +24,11 @@
24 24
25#include "drmP.h" 25#include "drmP.h"
26 26
27#include "nouveau_drv.h" 27#include "nouveau_drm.h"
28#include "nouveau_pm.h" 28#include "nouveau_pm.h"
29 29
30#include <subdev/bios/gpio.h> 30#include <subdev/bios/gpio.h>
31#include <subdev/gpio.h>
31 32
32static const enum dcb_gpio_func_name vidtag[] = { 0x04, 0x05, 0x06, 0x1a, 0x73 }; 33static const enum dcb_gpio_func_name vidtag[] = { 0x04, 0x05, 0x06, 0x1a, 0x73 };
33static int nr_vidtag = sizeof(vidtag) / sizeof(vidtag[0]); 34static int nr_vidtag = sizeof(vidtag) / sizeof(vidtag[0]);
@@ -35,8 +36,9 @@ static int nr_vidtag = sizeof(vidtag) / sizeof(vidtag[0]);
35int 36int
36nouveau_voltage_gpio_get(struct drm_device *dev) 37nouveau_voltage_gpio_get(struct drm_device *dev)
37{ 38{
38 struct drm_nouveau_private *dev_priv = dev->dev_private; 39 struct nouveau_pm_voltage *volt = &nouveau_pm(dev)->voltage;
39 struct nouveau_pm_voltage *volt = &dev_priv->engine.pm.voltage; 40 struct nouveau_device *device = nouveau_dev(dev);
41 struct nouveau_gpio *gpio = nouveau_gpio(device);
40 u8 vid = 0; 42 u8 vid = 0;
41 int i; 43 int i;
42 44
@@ -44,7 +46,7 @@ nouveau_voltage_gpio_get(struct drm_device *dev)
44 if (!(volt->vid_mask & (1 << i))) 46 if (!(volt->vid_mask & (1 << i)))
45 continue; 47 continue;
46 48
47 vid |= nouveau_gpio_func_get(dev, vidtag[i]) << i; 49 vid |= gpio->get(gpio, 0, vidtag[i], 0xff) << i;
48 } 50 }
49 51
50 return nouveau_volt_lvl_lookup(dev, vid); 52 return nouveau_volt_lvl_lookup(dev, vid);
@@ -53,8 +55,9 @@ nouveau_voltage_gpio_get(struct drm_device *dev)
53int 55int
54nouveau_voltage_gpio_set(struct drm_device *dev, int voltage) 56nouveau_voltage_gpio_set(struct drm_device *dev, int voltage)
55{ 57{
56 struct drm_nouveau_private *dev_priv = dev->dev_private; 58 struct nouveau_device *device = nouveau_dev(dev);
57 struct nouveau_pm_voltage *volt = &dev_priv->engine.pm.voltage; 59 struct nouveau_gpio *gpio = nouveau_gpio(device);
60 struct nouveau_pm_voltage *volt = &nouveau_pm(dev)->voltage;
58 int vid, i; 61 int vid, i;
59 62
60 vid = nouveau_volt_vid_lookup(dev, voltage); 63 vid = nouveau_volt_vid_lookup(dev, voltage);
@@ -65,7 +68,7 @@ nouveau_voltage_gpio_set(struct drm_device *dev, int voltage)
65 if (!(volt->vid_mask & (1 << i))) 68 if (!(volt->vid_mask & (1 << i)))
66 continue; 69 continue;
67 70
68 nouveau_gpio_func_set(dev, vidtag[i], !!(vid & (1 << i))); 71 gpio->set(gpio, 0, vidtag[i], 0xff, !!(vid & (1 << i)));
69 } 72 }
70 73
71 return 0; 74 return 0;
@@ -74,8 +77,7 @@ nouveau_voltage_gpio_set(struct drm_device *dev, int voltage)
74int 77int
75nouveau_volt_vid_lookup(struct drm_device *dev, int voltage) 78nouveau_volt_vid_lookup(struct drm_device *dev, int voltage)
76{ 79{
77 struct drm_nouveau_private *dev_priv = dev->dev_private; 80 struct nouveau_pm_voltage *volt = &nouveau_pm(dev)->voltage;
78 struct nouveau_pm_voltage *volt = &dev_priv->engine.pm.voltage;
79 int i; 81 int i;
80 82
81 for (i = 0; i < volt->nr_level; i++) { 83 for (i = 0; i < volt->nr_level; i++) {
@@ -89,8 +91,7 @@ nouveau_volt_vid_lookup(struct drm_device *dev, int voltage)
89int 91int
90nouveau_volt_lvl_lookup(struct drm_device *dev, int vid) 92nouveau_volt_lvl_lookup(struct drm_device *dev, int vid)
91{ 93{
92 struct drm_nouveau_private *dev_priv = dev->dev_private; 94 struct nouveau_pm_voltage *volt = &nouveau_pm(dev)->voltage;
93 struct nouveau_pm_voltage *volt = &dev_priv->engine.pm.voltage;
94 int i; 95 int i;
95 96
96 for (i = 0; i < volt->nr_level; i++) { 97 for (i = 0; i < volt->nr_level; i++) {
@@ -104,10 +105,12 @@ nouveau_volt_lvl_lookup(struct drm_device *dev, int vid)
104void 105void
105nouveau_volt_init(struct drm_device *dev) 106nouveau_volt_init(struct drm_device *dev)
106{ 107{
107 struct drm_nouveau_private *dev_priv = dev->dev_private; 108 struct nouveau_drm *drm = nouveau_drm(dev);
108 struct nouveau_pm_engine *pm = &dev_priv->engine.pm; 109 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
110 struct nouveau_pm *pm = nouveau_pm(dev);
109 struct nouveau_pm_voltage *voltage = &pm->voltage; 111 struct nouveau_pm_voltage *voltage = &pm->voltage;
110 struct nvbios *bios = &dev_priv->vbios; 112 struct nvbios *bios = &drm->vbios;
113 struct dcb_gpio_func func;
111 struct bit_entry P; 114 struct bit_entry P;
112 u8 *volt = NULL, *entry; 115 u8 *volt = NULL, *entry;
113 int i, headerlen, recordlen, entries, vidmask, vidshift; 116 int i, headerlen, recordlen, entries, vidmask, vidshift;
@@ -122,11 +125,11 @@ nouveau_volt_init(struct drm_device *dev)
122 if (P.version == 2) 125 if (P.version == 2)
123 volt = ROMPTR(dev, P.data[12]); 126 volt = ROMPTR(dev, P.data[12]);
124 else { 127 else {
125 NV_WARN(dev, "unknown volt for BIT P %d\n", P.version); 128 NV_WARN(drm, "unknown volt for BIT P %d\n", P.version);
126 } 129 }
127 } else { 130 } else {
128 if (bios->data[bios->offset + 6] < 0x27) { 131 if (bios->data[bios->offset + 6] < 0x27) {
129 NV_DEBUG(dev, "BMP version too old for voltage\n"); 132 NV_DEBUG(drm, "BMP version too old for voltage\n");
130 return; 133 return;
131 } 134 }
132 135
@@ -134,7 +137,7 @@ nouveau_volt_init(struct drm_device *dev)
134 } 137 }
135 138
136 if (!volt) { 139 if (!volt) {
137 NV_DEBUG(dev, "voltage table pointer invalid\n"); 140 NV_DEBUG(drm, "voltage table pointer invalid\n");
138 return; 141 return;
139 } 142 }
140 143
@@ -178,7 +181,7 @@ nouveau_volt_init(struct drm_device *dev)
178 vidshift = 0; 181 vidshift = 0;
179 break; 182 break;
180 default: 183 default:
181 NV_WARN(dev, "voltage table 0x%02x unknown\n", volt[0]); 184 NV_WARN(drm, "voltage table 0x%02x unknown\n", volt[0]);
182 return; 185 return;
183 } 186 }
184 187
@@ -190,12 +193,12 @@ nouveau_volt_init(struct drm_device *dev)
190 i = 0; 193 i = 0;
191 while (vidmask) { 194 while (vidmask) {
192 if (i > nr_vidtag) { 195 if (i > nr_vidtag) {
193 NV_DEBUG(dev, "vid bit %d unknown\n", i); 196 NV_DEBUG(drm, "vid bit %d unknown\n", i);
194 return; 197 return;
195 } 198 }
196 199
197 if (!nouveau_gpio_func_valid(dev, vidtag[i])) { 200 if (gpio && gpio->find(gpio, 0, vidtag[i], 0xff, &func)) {
198 NV_DEBUG(dev, "vid bit %d has no gpio tag\n", i); 201 NV_DEBUG(drm, "vid bit %d has no gpio tag\n", i);
199 return; 202 return;
200 } 203 }
201 204
@@ -241,8 +244,7 @@ nouveau_volt_init(struct drm_device *dev)
241void 244void
242nouveau_volt_fini(struct drm_device *dev) 245nouveau_volt_fini(struct drm_device *dev)
243{ 246{
244 struct drm_nouveau_private *dev_priv = dev->dev_private; 247 struct nouveau_pm_voltage *volt = &nouveau_pm(dev)->voltage;
245 struct nouveau_pm_voltage *volt = &dev_priv->engine.pm.voltage;
246 248
247 kfree(volt->level); 249 kfree(volt->level);
248} 250}
diff --git a/drivers/gpu/drm/nouveau/nv04_crtc.c b/drivers/gpu/drm/nouveau/nv04_crtc.c
index f5d17bf954ff..8b8a9d3d9e8b 100644
--- a/drivers/gpu/drm/nouveau/nv04_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv04_crtc.c
@@ -26,14 +26,20 @@
26#include "drmP.h" 26#include "drmP.h"
27#include "drm_crtc_helper.h" 27#include "drm_crtc_helper.h"
28 28
29#include "nouveau_drv.h" 29#include "nouveau_drm.h"
30#include "nouveau_reg.h"
31#include "nouveau_bo.h"
32#include "nouveau_gem.h"
30#include "nouveau_encoder.h" 33#include "nouveau_encoder.h"
31#include "nouveau_connector.h" 34#include "nouveau_connector.h"
32#include "nouveau_crtc.h" 35#include "nouveau_crtc.h"
33#include "nouveau_fb.h"
34#include "nouveau_hw.h" 36#include "nouveau_hw.h"
35#include "nvreg.h" 37#include "nvreg.h"
36#include "nouveau_fbcon.h" 38#include "nouveau_fbcon.h"
39#include "nv04_display.h"
40
41#include <subdev/bios/pll.h>
42#include <subdev/clock.h>
37 43
38static int 44static int
39nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 45nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
@@ -103,14 +109,17 @@ static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level)
103static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock) 109static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock)
104{ 110{
105 struct drm_device *dev = crtc->dev; 111 struct drm_device *dev = crtc->dev;
106 struct drm_nouveau_private *dev_priv = dev->dev_private; 112 struct nouveau_drm *drm = nouveau_drm(dev);
113 struct nouveau_bios *bios = nouveau_bios(drm->device);
114 struct nouveau_clock *clk = nouveau_clock(drm->device);
107 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 115 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
108 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; 116 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
109 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; 117 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
110 struct nouveau_pll_vals *pv = &regp->pllvals; 118 struct nouveau_pll_vals *pv = &regp->pllvals;
111 struct nvbios_pll pll_lim; 119 struct nvbios_pll pll_lim;
112 120
113 if (get_pll_limits(dev, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0, &pll_lim)) 121 if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0,
122 &pll_lim))
114 return; 123 return;
115 124
116 /* NM2 == 0 is used to determine single stage mode on two stage plls */ 125 /* NM2 == 0 is used to determine single stage mode on two stage plls */
@@ -126,28 +135,29 @@ static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mod
126 * has yet been observed in allowing the use a single stage pll on all 135 * has yet been observed in allowing the use a single stage pll on all
127 * nv43 however. the behaviour of single stage use is untested on nv40 136 * nv43 however. the behaviour of single stage use is untested on nv40
128 */ 137 */
129 if (dev_priv->chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2)) 138 if (nv_device(drm->device)->chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2))
130 memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2)); 139 memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2));
131 140
132 if (!nouveau_calc_pll_mnp(dev, &pll_lim, dot_clock, pv)) 141
142 if (!clk->pll_calc(clk, &pll_lim, dot_clock, pv))
133 return; 143 return;
134 144
135 state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK; 145 state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK;
136 146
137 /* The blob uses this always, so let's do the same */ 147 /* The blob uses this always, so let's do the same */
138 if (dev_priv->card_type == NV_40) 148 if (nv_device(drm->device)->card_type == NV_40)
139 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE; 149 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE;
140 /* again nv40 and some nv43 act more like nv3x as described above */ 150 /* again nv40 and some nv43 act more like nv3x as described above */
141 if (dev_priv->chipset < 0x41) 151 if (nv_device(drm->device)->chipset < 0x41)
142 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL | 152 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL |
143 NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL; 153 NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL;
144 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK; 154 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK;
145 155
146 if (pv->NM2) 156 if (pv->NM2)
147 NV_DEBUG_KMS(dev, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", 157 NV_DEBUG(drm, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n",
148 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); 158 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
149 else 159 else
150 NV_DEBUG_KMS(dev, "vpll: n %d m %d log2p %d\n", 160 NV_DEBUG(drm, "vpll: n %d m %d log2p %d\n",
151 pv->N1, pv->M1, pv->log2P); 161 pv->N1, pv->M1, pv->log2P);
152 162
153 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); 163 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
@@ -158,10 +168,11 @@ nv_crtc_dpms(struct drm_crtc *crtc, int mode)
158{ 168{
159 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 169 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
160 struct drm_device *dev = crtc->dev; 170 struct drm_device *dev = crtc->dev;
171 struct nouveau_drm *drm = nouveau_drm(dev);
161 unsigned char seq1 = 0, crtc17 = 0; 172 unsigned char seq1 = 0, crtc17 = 0;
162 unsigned char crtc1A; 173 unsigned char crtc1A;
163 174
164 NV_DEBUG_KMS(dev, "Setting dpms mode %d on CRTC %d\n", mode, 175 NV_DEBUG(drm, "Setting dpms mode %d on CRTC %d\n", mode,
165 nv_crtc->index); 176 nv_crtc->index);
166 177
167 if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */ 178 if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */
@@ -263,7 +274,7 @@ nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
263 horizEnd = horizTotal - 2; 274 horizEnd = horizTotal - 2;
264 horizBlankEnd = horizTotal + 4; 275 horizBlankEnd = horizTotal + 4;
265#if 0 276#if 0
266 if (dev->overlayAdaptor && dev_priv->card_type >= NV_10) 277 if (dev->overlayAdaptor && nv_device(drm->device)->card_type >= NV_10)
267 /* This reportedly works around some video overlay bandwidth problems */ 278 /* This reportedly works around some video overlay bandwidth problems */
268 horizTotal += 2; 279 horizTotal += 2;
269#endif 280#endif
@@ -451,7 +462,7 @@ static void
451nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) 462nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
452{ 463{
453 struct drm_device *dev = crtc->dev; 464 struct drm_device *dev = crtc->dev;
454 struct drm_nouveau_private *dev_priv = dev->dev_private; 465 struct nouveau_drm *drm = nouveau_drm(dev);
455 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 466 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
456 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 467 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
457 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; 468 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
@@ -499,7 +510,7 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
499 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 | 510 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 |
500 NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 | 511 NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 |
501 NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM; 512 NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM;
502 if (dev_priv->chipset >= 0x11) 513 if (nv_device(drm->device)->chipset >= 0x11)
503 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32; 514 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32;
504 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 515 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
505 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE; 516 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE;
@@ -540,26 +551,26 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
540 * 1 << 30 on 0x60.830), for no apparent reason */ 551 * 1 << 30 on 0x60.830), for no apparent reason */
541 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital; 552 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital;
542 553
543 if (dev_priv->card_type >= NV_30) 554 if (nv_device(drm->device)->card_type >= NV_30)
544 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1; 555 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1;
545 556
546 regp->crtc_830 = mode->crtc_vdisplay - 3; 557 regp->crtc_830 = mode->crtc_vdisplay - 3;
547 regp->crtc_834 = mode->crtc_vdisplay - 1; 558 regp->crtc_834 = mode->crtc_vdisplay - 1;
548 559
549 if (dev_priv->card_type == NV_40) 560 if (nv_device(drm->device)->card_type == NV_40)
550 /* This is what the blob does */ 561 /* This is what the blob does */
551 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850); 562 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850);
552 563
553 if (dev_priv->card_type >= NV_30) 564 if (nv_device(drm->device)->card_type >= NV_30)
554 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT); 565 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT);
555 566
556 if (dev_priv->card_type >= NV_10) 567 if (nv_device(drm->device)->card_type >= NV_10)
557 regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC; 568 regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC;
558 else 569 else
559 regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC; 570 regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC;
560 571
561 /* Some misc regs */ 572 /* Some misc regs */
562 if (dev_priv->card_type == NV_40) { 573 if (nv_device(drm->device)->card_type == NV_40) {
563 regp->CRTC[NV_CIO_CRE_85] = 0xFF; 574 regp->CRTC[NV_CIO_CRE_85] = 0xFF;
564 regp->CRTC[NV_CIO_CRE_86] = 0x1; 575 regp->CRTC[NV_CIO_CRE_86] = 0x1;
565 } 576 }
@@ -571,7 +582,7 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
571 582
572 /* Generic PRAMDAC regs */ 583 /* Generic PRAMDAC regs */
573 584
574 if (dev_priv->card_type >= NV_10) 585 if (nv_device(drm->device)->card_type >= NV_10)
575 /* Only bit that bios and blob set. */ 586 /* Only bit that bios and blob set. */
576 regp->nv10_cursync = (1 << 25); 587 regp->nv10_cursync = (1 << 25);
577 588
@@ -580,7 +591,7 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
580 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON; 591 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON;
581 if (crtc->fb->depth == 16) 592 if (crtc->fb->depth == 16)
582 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 593 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
583 if (dev_priv->chipset >= 0x11) 594 if (nv_device(drm->device)->chipset >= 0x11)
584 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG; 595 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG;
585 596
586 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */ 597 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */
@@ -610,9 +621,9 @@ nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
610{ 621{
611 struct drm_device *dev = crtc->dev; 622 struct drm_device *dev = crtc->dev;
612 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 623 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
613 struct drm_nouveau_private *dev_priv = dev->dev_private; 624 struct nouveau_drm *drm = nouveau_drm(dev);
614 625
615 NV_DEBUG_KMS(dev, "CTRC mode on CRTC %d:\n", nv_crtc->index); 626 NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index);
616 drm_mode_debug_printmodeline(adjusted_mode); 627 drm_mode_debug_printmodeline(adjusted_mode);
617 628
618 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */ 629 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */
@@ -620,7 +631,7 @@ nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
620 631
621 nv_crtc_mode_set_vga(crtc, adjusted_mode); 632 nv_crtc_mode_set_vga(crtc, adjusted_mode);
622 /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */ 633 /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */
623 if (dev_priv->card_type == NV_40) 634 if (nv_device(drm->device)->card_type == NV_40)
624 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); 635 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
625 nv_crtc_mode_set_regs(crtc, adjusted_mode); 636 nv_crtc_mode_set_regs(crtc, adjusted_mode);
626 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock); 637 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock);
@@ -667,7 +678,7 @@ static void nv_crtc_restore(struct drm_crtc *crtc)
667static void nv_crtc_prepare(struct drm_crtc *crtc) 678static void nv_crtc_prepare(struct drm_crtc *crtc)
668{ 679{
669 struct drm_device *dev = crtc->dev; 680 struct drm_device *dev = crtc->dev;
670 struct drm_nouveau_private *dev_priv = dev->dev_private; 681 struct nouveau_drm *drm = nouveau_drm(dev);
671 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 682 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
672 struct drm_crtc_helper_funcs *funcs = crtc->helper_private; 683 struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
673 684
@@ -681,7 +692,7 @@ static void nv_crtc_prepare(struct drm_crtc *crtc)
681 692
682 /* Some more preparation. */ 693 /* Some more preparation. */
683 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA); 694 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
684 if (dev_priv->card_type == NV_40) { 695 if (nv_device(drm->device)->card_type == NV_40) {
685 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900); 696 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900);
686 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000); 697 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000);
687 } 698 }
@@ -713,8 +724,6 @@ static void nv_crtc_destroy(struct drm_crtc *crtc)
713{ 724{
714 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 725 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
715 726
716 NV_DEBUG_KMS(crtc->dev, "\n");
717
718 if (!nv_crtc) 727 if (!nv_crtc)
719 return; 728 return;
720 729
@@ -776,18 +785,18 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
776{ 785{
777 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 786 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
778 struct drm_device *dev = crtc->dev; 787 struct drm_device *dev = crtc->dev;
779 struct drm_nouveau_private *dev_priv = dev->dev_private; 788 struct nouveau_drm *drm = nouveau_drm(dev);
780 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 789 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
781 struct drm_framebuffer *drm_fb; 790 struct drm_framebuffer *drm_fb;
782 struct nouveau_framebuffer *fb; 791 struct nouveau_framebuffer *fb;
783 int arb_burst, arb_lwm; 792 int arb_burst, arb_lwm;
784 int ret; 793 int ret;
785 794
786 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); 795 NV_DEBUG(drm, "index %d\n", nv_crtc->index);
787 796
788 /* no fb bound */ 797 /* no fb bound */
789 if (!atomic && !crtc->fb) { 798 if (!atomic && !crtc->fb) {
790 NV_DEBUG_KMS(dev, "No FB bound\n"); 799 NV_DEBUG(drm, "No FB bound\n");
791 return 0; 800 return 0;
792 } 801 }
793 802
@@ -855,7 +864,7 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
855 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX); 864 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX);
856 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX); 865 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX);
857 866
858 if (dev_priv->card_type >= NV_20) { 867 if (nv_device(drm->device)->card_type >= NV_20) {
859 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8; 868 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8;
860 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47); 869 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47);
861 } 870 }
@@ -875,8 +884,8 @@ nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
875 struct drm_framebuffer *fb, 884 struct drm_framebuffer *fb,
876 int x, int y, enum mode_set_atomic state) 885 int x, int y, enum mode_set_atomic state)
877{ 886{
878 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; 887 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
879 struct drm_device *dev = dev_priv->dev; 888 struct drm_device *dev = drm->dev;
880 889
881 if (state == ENTER_ATOMIC_MODE_SET) 890 if (state == ENTER_ATOMIC_MODE_SET)
882 nouveau_fbcon_save_disable_accel(dev); 891 nouveau_fbcon_save_disable_accel(dev);
@@ -931,9 +940,9 @@ static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
931 940
932#ifdef __BIG_ENDIAN 941#ifdef __BIG_ENDIAN
933 { 942 {
934 struct drm_nouveau_private *dev_priv = dev->dev_private; 943 struct nouveau_drm *drm = nouveau_drm(dev);
935 944
936 if (dev_priv->chipset == 0x11) { 945 if (nv_device(drm->device)->chipset == 0x11) {
937 pixel = ((pixel & 0x000000ff) << 24) | 946 pixel = ((pixel & 0x000000ff) << 24) |
938 ((pixel & 0x0000ff00) << 8) | 947 ((pixel & 0x0000ff00) << 8) |
939 ((pixel & 0x00ff0000) >> 8) | 948 ((pixel & 0x00ff0000) >> 8) |
@@ -950,8 +959,8 @@ static int
950nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, 959nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
951 uint32_t buffer_handle, uint32_t width, uint32_t height) 960 uint32_t buffer_handle, uint32_t width, uint32_t height)
952{ 961{
953 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; 962 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
954 struct drm_device *dev = dev_priv->dev; 963 struct drm_device *dev = drm->dev;
955 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 964 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
956 struct nouveau_bo *cursor = NULL; 965 struct nouveau_bo *cursor = NULL;
957 struct drm_gem_object *gem; 966 struct drm_gem_object *gem;
@@ -974,7 +983,7 @@ nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
974 if (ret) 983 if (ret)
975 goto out; 984 goto out;
976 985
977 if (dev_priv->chipset >= 0x11) 986 if (nv_device(drm->device)->chipset >= 0x11)
978 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); 987 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
979 else 988 else
980 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); 989 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
diff --git a/drivers/gpu/drm/nouveau/nv04_cursor.c b/drivers/gpu/drm/nouveau/nv04_cursor.c
index 62294b8712db..d2ea8b460364 100644
--- a/drivers/gpu/drm/nouveau/nv04_cursor.c
+++ b/drivers/gpu/drm/nouveau/nv04_cursor.c
@@ -1,7 +1,7 @@
1#include "drmP.h" 1#include "drmP.h"
2#include "drm_mode.h" 2#include "drm_mode.h"
3#include "nouveau_drm.h"
3#include "nouveau_reg.h" 4#include "nouveau_reg.h"
4#include "nouveau_drv.h"
5#include "nouveau_crtc.h" 5#include "nouveau_crtc.h"
6#include "nouveau_hw.h" 6#include "nouveau_hw.h"
7 7
@@ -38,7 +38,7 @@ static void
38nv04_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset) 38nv04_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
39{ 39{
40 struct drm_device *dev = nv_crtc->base.dev; 40 struct drm_device *dev = nv_crtc->base.dev;
41 struct drm_nouveau_private *dev_priv = dev->dev_private; 41 struct nouveau_drm *drm = nouveau_drm(dev);
42 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 42 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
43 struct drm_crtc *crtc = &nv_crtc->base; 43 struct drm_crtc *crtc = &nv_crtc->base;
44 44
@@ -55,7 +55,7 @@ nv04_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
55 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); 55 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
56 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); 56 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
57 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); 57 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
58 if (dev_priv->card_type == NV_40) 58 if (nv_device(drm->device)->card_type == NV_40)
59 nv_fix_nv40_hw_cursor(dev, nv_crtc->index); 59 nv_fix_nv40_hw_cursor(dev, nv_crtc->index);
60} 60}
61 61
diff --git a/drivers/gpu/drm/nouveau/nv04_dac.c b/drivers/gpu/drm/nouveau/nv04_dac.c
index 7ff2eb3bd340..336f953084f9 100644
--- a/drivers/gpu/drm/nouveau/nv04_dac.c
+++ b/drivers/gpu/drm/nouveau/nv04_dac.c
@@ -27,7 +27,7 @@
27#include "drmP.h" 27#include "drmP.h"
28#include "drm_crtc_helper.h" 28#include "drm_crtc_helper.h"
29 29
30#include "nouveau_drv.h" 30#include "nouveau_drm.h"
31#include "nouveau_encoder.h" 31#include "nouveau_encoder.h"
32#include "nouveau_connector.h" 32#include "nouveau_connector.h"
33#include "nouveau_crtc.h" 33#include "nouveau_crtc.h"
@@ -35,6 +35,8 @@
35#include "nvreg.h" 35#include "nvreg.h"
36 36
37#include <subdev/bios/gpio.h> 37#include <subdev/bios/gpio.h>
38#include <subdev/gpio.h>
39#include <subdev/timer.h>
38 40
39int nv04_dac_output_offset(struct drm_encoder *encoder) 41int nv04_dac_output_offset(struct drm_encoder *encoder)
40{ 42{
@@ -63,6 +65,8 @@ int nv04_dac_output_offset(struct drm_encoder *encoder)
63 65
64static int sample_load_twice(struct drm_device *dev, bool sense[2]) 66static int sample_load_twice(struct drm_device *dev, bool sense[2])
65{ 67{
68 struct nouveau_device *device = nouveau_dev(dev);
69 struct nouveau_timer *ptimer = nouveau_timer(device);
66 int i; 70 int i;
67 71
68 for (i = 0; i < 2; i++) { 72 for (i = 0; i < 2; i++) {
@@ -76,27 +80,30 @@ static int sample_load_twice(struct drm_device *dev, bool sense[2])
76 * use a 10ms timeout (guards against crtc being inactive, in 80 * use a 10ms timeout (guards against crtc being inactive, in
77 * which case blank state would never change) 81 * which case blank state would never change)
78 */ 82 */
79 if (!nouveau_wait_eq(dev, 10000000, NV_PRMCIO_INP0__COLOR, 83 if (!nouveau_timer_wait_eq(ptimer, 10000000,
80 0x00000001, 0x00000000)) 84 NV_PRMCIO_INP0__COLOR,
85 0x00000001, 0x00000000))
81 return -EBUSY; 86 return -EBUSY;
82 if (!nouveau_wait_eq(dev, 10000000, NV_PRMCIO_INP0__COLOR, 87 if (!nouveau_timer_wait_eq(ptimer, 10000000,
83 0x00000001, 0x00000001)) 88 NV_PRMCIO_INP0__COLOR,
89 0x00000001, 0x00000001))
84 return -EBUSY; 90 return -EBUSY;
85 if (!nouveau_wait_eq(dev, 10000000, NV_PRMCIO_INP0__COLOR, 91 if (!nouveau_timer_wait_eq(ptimer, 10000000,
86 0x00000001, 0x00000000)) 92 NV_PRMCIO_INP0__COLOR,
93 0x00000001, 0x00000000))
87 return -EBUSY; 94 return -EBUSY;
88 95
89 udelay(100); 96 udelay(100);
90 /* when level triggers, sense is _LO_ */ 97 /* when level triggers, sense is _LO_ */
91 sense_a = nv_rd08(dev, NV_PRMCIO_INP0) & 0x10; 98 sense_a = nv_rd08(device, NV_PRMCIO_INP0) & 0x10;
92 99
93 /* take another reading until it agrees with sense_a... */ 100 /* take another reading until it agrees with sense_a... */
94 do { 101 do {
95 udelay(100); 102 udelay(100);
96 sense_b = nv_rd08(dev, NV_PRMCIO_INP0) & 0x10; 103 sense_b = nv_rd08(device, NV_PRMCIO_INP0) & 0x10;
97 if (sense_a != sense_b) { 104 if (sense_a != sense_b) {
98 sense_b_prime = 105 sense_b_prime =
99 nv_rd08(dev, NV_PRMCIO_INP0) & 0x10; 106 nv_rd08(device, NV_PRMCIO_INP0) & 0x10;
100 if (sense_b == sense_b_prime) { 107 if (sense_b == sense_b_prime) {
101 /* ... unless two consecutive subsequent 108 /* ... unless two consecutive subsequent
102 * samples agree; sense_a is replaced */ 109 * samples agree; sense_a is replaced */
@@ -121,6 +128,8 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
121 struct drm_connector *connector) 128 struct drm_connector *connector)
122{ 129{
123 struct drm_device *dev = encoder->dev; 130 struct drm_device *dev = encoder->dev;
131 struct nouveau_device *device = nouveau_dev(dev);
132 struct nouveau_drm *drm = nouveau_drm(dev);
124 uint8_t saved_seq1, saved_pi, saved_rpc1, saved_cr_mode; 133 uint8_t saved_seq1, saved_pi, saved_rpc1, saved_cr_mode;
125 uint8_t saved_palette0[3], saved_palette_mask; 134 uint8_t saved_palette0[3], saved_palette_mask;
126 uint32_t saved_rtest_ctrl, saved_rgen_ctrl; 135 uint32_t saved_rtest_ctrl, saved_rgen_ctrl;
@@ -155,11 +164,11 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
155 saved_rpc1 = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX); 164 saved_rpc1 = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX);
156 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1 & ~0xc0); 165 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1 & ~0xc0);
157 166
158 nv_wr08(dev, NV_PRMDIO_READ_MODE_ADDRESS, 0x0); 167 nv_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS, 0x0);
159 for (i = 0; i < 3; i++) 168 for (i = 0; i < 3; i++)
160 saved_palette0[i] = nv_rd08(dev, NV_PRMDIO_PALETTE_DATA); 169 saved_palette0[i] = nv_rd08(device, NV_PRMDIO_PALETTE_DATA);
161 saved_palette_mask = nv_rd08(dev, NV_PRMDIO_PIXEL_MASK); 170 saved_palette_mask = nv_rd08(device, NV_PRMDIO_PIXEL_MASK);
162 nv_wr08(dev, NV_PRMDIO_PIXEL_MASK, 0); 171 nv_wr08(device, NV_PRMDIO_PIXEL_MASK, 0);
163 172
164 saved_rgen_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL); 173 saved_rgen_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL);
165 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL, 174 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL,
@@ -172,11 +181,11 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
172 do { 181 do {
173 bool sense_pair[2]; 182 bool sense_pair[2];
174 183
175 nv_wr08(dev, NV_PRMDIO_WRITE_MODE_ADDRESS, 0); 184 nv_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS, 0);
176 nv_wr08(dev, NV_PRMDIO_PALETTE_DATA, 0); 185 nv_wr08(device, NV_PRMDIO_PALETTE_DATA, 0);
177 nv_wr08(dev, NV_PRMDIO_PALETTE_DATA, 0); 186 nv_wr08(device, NV_PRMDIO_PALETTE_DATA, 0);
178 /* testing blue won't find monochrome monitors. I don't care */ 187 /* testing blue won't find monochrome monitors. I don't care */
179 nv_wr08(dev, NV_PRMDIO_PALETTE_DATA, blue); 188 nv_wr08(device, NV_PRMDIO_PALETTE_DATA, blue);
180 189
181 i = 0; 190 i = 0;
182 /* take sample pairs until both samples in the pair agree */ 191 /* take sample pairs until both samples in the pair agree */
@@ -199,11 +208,11 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
199 } while (++blue < 0x18 && sense); 208 } while (++blue < 0x18 && sense);
200 209
201out: 210out:
202 nv_wr08(dev, NV_PRMDIO_PIXEL_MASK, saved_palette_mask); 211 nv_wr08(device, NV_PRMDIO_PIXEL_MASK, saved_palette_mask);
203 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL, saved_rgen_ctrl); 212 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL, saved_rgen_ctrl);
204 nv_wr08(dev, NV_PRMDIO_WRITE_MODE_ADDRESS, 0); 213 nv_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS, 0);
205 for (i = 0; i < 3; i++) 214 for (i = 0; i < 3; i++)
206 nv_wr08(dev, NV_PRMDIO_PALETTE_DATA, saved_palette0[i]); 215 nv_wr08(device, NV_PRMDIO_PALETTE_DATA, saved_palette0[i]);
207 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL, saved_rtest_ctrl); 216 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL, saved_rtest_ctrl);
208 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, saved_pi); 217 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, saved_pi);
209 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1); 218 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1);
@@ -211,7 +220,7 @@ out:
211 NVWriteVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX, saved_cr_mode); 220 NVWriteVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX, saved_cr_mode);
212 221
213 if (blue == 0x18) { 222 if (blue == 0x18) {
214 NV_INFO(dev, "Load detected on head A\n"); 223 NV_INFO(drm, "Load detected on head A\n");
215 return connector_status_connected; 224 return connector_status_connected;
216 } 225 }
217 226
@@ -221,43 +230,46 @@ out:
221uint32_t nv17_dac_sample_load(struct drm_encoder *encoder) 230uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
222{ 231{
223 struct drm_device *dev = encoder->dev; 232 struct drm_device *dev = encoder->dev;
224 struct drm_nouveau_private *dev_priv = dev->dev_private; 233 struct nouveau_drm *drm = nouveau_drm(dev);
234 struct nouveau_device *device = nouveau_dev(dev);
235 struct nouveau_gpio *gpio = nouveau_gpio(device);
225 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; 236 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
226 uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder); 237 uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder);
227 uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput, 238 uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput,
228 saved_rtest_ctrl, saved_gpio0, saved_gpio1, temp, routput; 239 saved_rtest_ctrl, saved_gpio0 = 0, saved_gpio1 = 0, temp, routput;
229 int head; 240 int head;
230 241
231#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20) 242#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
232 if (dcb->type == DCB_OUTPUT_TV) { 243 if (dcb->type == DCB_OUTPUT_TV) {
233 testval = RGB_TEST_DATA(0xa0, 0xa0, 0xa0); 244 testval = RGB_TEST_DATA(0xa0, 0xa0, 0xa0);
234 245
235 if (dev_priv->vbios.tvdactestval) 246 if (drm->vbios.tvdactestval)
236 testval = dev_priv->vbios.tvdactestval; 247 testval = drm->vbios.tvdactestval;
237 } else { 248 } else {
238 testval = RGB_TEST_DATA(0x140, 0x140, 0x140); /* 0x94050140 */ 249 testval = RGB_TEST_DATA(0x140, 0x140, 0x140); /* 0x94050140 */
239 250
240 if (dev_priv->vbios.dactestval) 251 if (drm->vbios.dactestval)
241 testval = dev_priv->vbios.dactestval; 252 testval = drm->vbios.dactestval;
242 } 253 }
243 254
244 saved_rtest_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset); 255 saved_rtest_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
245 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 256 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset,
246 saved_rtest_ctrl & ~NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF); 257 saved_rtest_ctrl & ~NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF);
247 258
248 saved_powerctrl_2 = nv_rd32(dev, NV_PBUS_POWERCTRL_2); 259 saved_powerctrl_2 = nv_rd32(device, NV_PBUS_POWERCTRL_2);
249 260
250 nv_wr32(dev, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 & 0xd7ffffff); 261 nv_wr32(device, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 & 0xd7ffffff);
251 if (regoffset == 0x68) { 262 if (regoffset == 0x68) {
252 saved_powerctrl_4 = nv_rd32(dev, NV_PBUS_POWERCTRL_4); 263 saved_powerctrl_4 = nv_rd32(device, NV_PBUS_POWERCTRL_4);
253 nv_wr32(dev, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf); 264 nv_wr32(device, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf);
254 } 265 }
255 266
256 saved_gpio1 = nouveau_gpio_func_get(dev, DCB_GPIO_TVDAC1); 267 if (gpio) {
257 saved_gpio0 = nouveau_gpio_func_get(dev, DCB_GPIO_TVDAC0); 268 saved_gpio1 = gpio->get(gpio, 0, DCB_GPIO_TVDAC1, 0xff);
258 269 saved_gpio0 = gpio->get(gpio, 0, DCB_GPIO_TVDAC0, 0xff);
259 nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC1, dcb->type == DCB_OUTPUT_TV); 270 gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, dcb->type == DCB_OUTPUT_TV);
260 nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC0, dcb->type == DCB_OUTPUT_TV); 271 gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, dcb->type == DCB_OUTPUT_TV);
272 }
261 273
262 msleep(4); 274 msleep(4);
263 275
@@ -271,7 +283,7 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
271 /* nv driver and nv31 use 0xfffffeee, nv34 and 6600 use 0xfffffece */ 283 /* nv driver and nv31 use 0xfffffeee, nv34 and 6600 use 0xfffffece */
272 routput = (saved_routput & 0xfffffece) | head << 8; 284 routput = (saved_routput & 0xfffffece) | head << 8;
273 285
274 if (dev_priv->card_type >= NV_40) { 286 if (nv_device(drm->device)->card_type >= NV_40) {
275 if (dcb->type == DCB_OUTPUT_TV) 287 if (dcb->type == DCB_OUTPUT_TV)
276 routput |= 0x1a << 16; 288 routput |= 0x1a << 16;
277 else 289 else
@@ -304,11 +316,13 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
304 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, saved_routput); 316 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, saved_routput);
305 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl); 317 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl);
306 if (regoffset == 0x68) 318 if (regoffset == 0x68)
307 nv_wr32(dev, NV_PBUS_POWERCTRL_4, saved_powerctrl_4); 319 nv_wr32(device, NV_PBUS_POWERCTRL_4, saved_powerctrl_4);
308 nv_wr32(dev, NV_PBUS_POWERCTRL_2, saved_powerctrl_2); 320 nv_wr32(device, NV_PBUS_POWERCTRL_2, saved_powerctrl_2);
309 321
310 nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC1, saved_gpio1); 322 if (gpio) {
311 nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC0, saved_gpio0); 323 gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, saved_gpio1);
324 gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, saved_gpio0);
325 }
312 326
313 return sample; 327 return sample;
314} 328}
@@ -316,7 +330,7 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
316static enum drm_connector_status 330static enum drm_connector_status
317nv17_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 331nv17_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
318{ 332{
319 struct drm_device *dev = encoder->dev; 333 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
320 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; 334 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
321 335
322 if (nv04_dac_in_use(encoder)) 336 if (nv04_dac_in_use(encoder))
@@ -324,7 +338,7 @@ nv17_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
324 338
325 if (nv17_dac_sample_load(encoder) & 339 if (nv17_dac_sample_load(encoder) &
326 NV_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI) { 340 NV_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI) {
327 NV_INFO(dev, "Load detected on output %c\n", 341 NV_INFO(drm, "Load detected on output %c\n",
328 '@' + ffs(dcb->or)); 342 '@' + ffs(dcb->or));
329 return connector_status_connected; 343 return connector_status_connected;
330 } else { 344 } else {
@@ -358,7 +372,7 @@ static void nv04_dac_mode_set(struct drm_encoder *encoder,
358 struct drm_display_mode *adjusted_mode) 372 struct drm_display_mode *adjusted_mode)
359{ 373{
360 struct drm_device *dev = encoder->dev; 374 struct drm_device *dev = encoder->dev;
361 struct drm_nouveau_private *dev_priv = dev->dev_private; 375 struct nouveau_drm *drm = nouveau_drm(dev);
362 int head = nouveau_crtc(encoder->crtc)->index; 376 int head = nouveau_crtc(encoder->crtc)->index;
363 377
364 if (nv_gf4_disp_arch(dev)) { 378 if (nv_gf4_disp_arch(dev)) {
@@ -384,7 +398,7 @@ static void nv04_dac_mode_set(struct drm_encoder *encoder,
384 } 398 }
385 399
386 /* This could use refinement for flatpanels, but it should work this way */ 400 /* This could use refinement for flatpanels, but it should work this way */
387 if (dev_priv->chipset < 0x44) 401 if (nv_device(drm->device)->chipset < 0x44)
388 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000); 402 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000);
389 else 403 else
390 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000); 404 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
@@ -393,13 +407,13 @@ static void nv04_dac_mode_set(struct drm_encoder *encoder,
393static void nv04_dac_commit(struct drm_encoder *encoder) 407static void nv04_dac_commit(struct drm_encoder *encoder)
394{ 408{
395 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 409 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
396 struct drm_device *dev = encoder->dev; 410 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
397 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 411 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
398 struct drm_encoder_helper_funcs *helper = encoder->helper_private; 412 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
399 413
400 helper->dpms(encoder, DRM_MODE_DPMS_ON); 414 helper->dpms(encoder, DRM_MODE_DPMS_ON);
401 415
402 NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n", 416 NV_INFO(drm, "Output %s is running on CRTC %d using output %c\n",
403 drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base), 417 drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base),
404 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); 418 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
405} 419}
@@ -440,14 +454,14 @@ bool nv04_dac_in_use(struct drm_encoder *encoder)
440 454
441static void nv04_dac_dpms(struct drm_encoder *encoder, int mode) 455static void nv04_dac_dpms(struct drm_encoder *encoder, int mode)
442{ 456{
443 struct drm_device *dev = encoder->dev;
444 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 457 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
458 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
445 459
446 if (nv_encoder->last_dpms == mode) 460 if (nv_encoder->last_dpms == mode)
447 return; 461 return;
448 nv_encoder->last_dpms = mode; 462 nv_encoder->last_dpms = mode;
449 463
450 NV_INFO(dev, "Setting dpms mode %d on vga encoder (output %d)\n", 464 NV_INFO(drm, "Setting dpms mode %d on vga encoder (output %d)\n",
451 mode, nv_encoder->dcb->index); 465 mode, nv_encoder->dcb->index);
452 466
453 nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON); 467 nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON);
@@ -479,8 +493,6 @@ static void nv04_dac_destroy(struct drm_encoder *encoder)
479{ 493{
480 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 494 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
481 495
482 NV_DEBUG_KMS(encoder->dev, "\n");
483
484 drm_encoder_cleanup(encoder); 496 drm_encoder_cleanup(encoder);
485 kfree(nv_encoder); 497 kfree(nv_encoder);
486} 498}
diff --git a/drivers/gpu/drm/nouveau/nv04_dfp.c b/drivers/gpu/drm/nouveau/nv04_dfp.c
index b53de928dcaf..e53df742cc01 100644
--- a/drivers/gpu/drm/nouveau/nv04_dfp.c
+++ b/drivers/gpu/drm/nouveau/nv04_dfp.c
@@ -27,7 +27,8 @@
27#include "drmP.h" 27#include "drmP.h"
28#include "drm_crtc_helper.h" 28#include "drm_crtc_helper.h"
29 29
30#include "nouveau_drv.h" 30#include "nouveau_drm.h"
31#include "nouveau_reg.h"
31#include "nouveau_encoder.h" 32#include "nouveau_encoder.h"
32#include "nouveau_connector.h" 33#include "nouveau_connector.h"
33#include "nouveau_crtc.h" 34#include "nouveau_crtc.h"
@@ -36,6 +37,8 @@
36 37
37#include "i2c/sil164.h" 38#include "i2c/sil164.h"
38 39
40#include <subdev/i2c.h>
41
39#define FP_TG_CONTROL_ON (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | \ 42#define FP_TG_CONTROL_ON (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | \
40 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS | \ 43 NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS | \
41 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS) 44 NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS)
@@ -278,7 +281,8 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
278 struct drm_display_mode *adjusted_mode) 281 struct drm_display_mode *adjusted_mode)
279{ 282{
280 struct drm_device *dev = encoder->dev; 283 struct drm_device *dev = encoder->dev;
281 struct drm_nouveau_private *dev_priv = dev->dev_private; 284 struct nouveau_device *device = nouveau_dev(dev);
285 struct nouveau_drm *drm = nouveau_drm(dev);
282 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 286 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
283 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 287 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
284 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; 288 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
@@ -288,7 +292,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
288 struct drm_connector *connector = &nv_connector->base; 292 struct drm_connector *connector = &nv_connector->base;
289 uint32_t mode_ratio, panel_ratio; 293 uint32_t mode_ratio, panel_ratio;
290 294
291 NV_DEBUG_KMS(dev, "Output mode on CRTC %d:\n", nv_crtc->index); 295 NV_DEBUG(drm, "Output mode on CRTC %d:\n", nv_crtc->index);
292 drm_mode_debug_printmodeline(output_mode); 296 drm_mode_debug_printmodeline(output_mode);
293 297
294 /* Initialize the FP registers in this CRTC. */ 298 /* Initialize the FP registers in this CRTC. */
@@ -296,10 +300,10 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
296 regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1; 300 regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
297 if (!nv_gf4_disp_arch(dev) || 301 if (!nv_gf4_disp_arch(dev) ||
298 (output_mode->hsync_start - output_mode->hdisplay) >= 302 (output_mode->hsync_start - output_mode->hdisplay) >=
299 dev_priv->vbios.digital_min_front_porch) 303 drm->vbios.digital_min_front_porch)
300 regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay; 304 regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay;
301 else 305 else
302 regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - dev_priv->vbios.digital_min_front_porch - 1; 306 regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - drm->vbios.digital_min_front_porch - 1;
303 regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1; 307 regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1;
304 regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1; 308 regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
305 regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew; 309 regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew;
@@ -331,7 +335,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
331 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE; 335 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE;
332 else /* gpu needs to scale */ 336 else /* gpu needs to scale */
333 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE; 337 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE;
334 if (nv_rd32(dev, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT) 338 if (nv_rd32(device, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT)
335 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12; 339 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
336 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && 340 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP &&
337 output_mode->clock > 165000) 341 output_mode->clock > 165000)
@@ -412,7 +416,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
412 if ((nv_connector->dithering_mode == DITHERING_MODE_ON) || 416 if ((nv_connector->dithering_mode == DITHERING_MODE_ON) ||
413 (nv_connector->dithering_mode == DITHERING_MODE_AUTO && 417 (nv_connector->dithering_mode == DITHERING_MODE_AUTO &&
414 encoder->crtc->fb->depth > connector->display_info.bpc * 3)) { 418 encoder->crtc->fb->depth > connector->display_info.bpc * 3)) {
415 if (dev_priv->chipset == 0x11) 419 if (nv_device(drm->device)->chipset == 0x11)
416 regp->dither = savep->dither | 0x00010000; 420 regp->dither = savep->dither | 0x00010000;
417 else { 421 else {
418 int i; 422 int i;
@@ -423,7 +427,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
423 } 427 }
424 } 428 }
425 } else { 429 } else {
426 if (dev_priv->chipset != 0x11) { 430 if (nv_device(drm->device)->chipset != 0x11) {
427 /* reset them */ 431 /* reset them */
428 int i; 432 int i;
429 for (i = 0; i < 3; i++) { 433 for (i = 0; i < 3; i++) {
@@ -440,7 +444,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
440static void nv04_dfp_commit(struct drm_encoder *encoder) 444static void nv04_dfp_commit(struct drm_encoder *encoder)
441{ 445{
442 struct drm_device *dev = encoder->dev; 446 struct drm_device *dev = encoder->dev;
443 struct drm_nouveau_private *dev_priv = dev->dev_private; 447 struct nouveau_drm *drm = nouveau_drm(dev);
444 struct drm_encoder_helper_funcs *helper = encoder->helper_private; 448 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
445 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 449 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
446 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 450 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
@@ -459,7 +463,7 @@ static void nv04_dfp_commit(struct drm_encoder *encoder)
459 NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); 463 NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
460 464
461 /* This could use refinement for flatpanels, but it should work this way */ 465 /* This could use refinement for flatpanels, but it should work this way */
462 if (dev_priv->chipset < 0x44) 466 if (nv_device(drm->device)->chipset < 0x44)
463 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000); 467 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000);
464 else 468 else
465 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000); 469 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
@@ -472,7 +476,7 @@ static void nv04_dfp_commit(struct drm_encoder *encoder)
472 476
473 helper->dpms(encoder, DRM_MODE_DPMS_ON); 477 helper->dpms(encoder, DRM_MODE_DPMS_ON);
474 478
475 NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n", 479 NV_INFO(drm, "Output %s is running on CRTC %d using output %c\n",
476 drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base), 480 drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base),
477 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); 481 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
478} 482}
@@ -481,6 +485,7 @@ static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode)
481{ 485{
482#ifdef __powerpc__ 486#ifdef __powerpc__
483 struct drm_device *dev = encoder->dev; 487 struct drm_device *dev = encoder->dev;
488 struct nouveau_device *device = nouveau_dev(dev);
484 489
485 /* BIOS scripts usually take care of the backlight, thanks 490 /* BIOS scripts usually take care of the backlight, thanks
486 * Apple for your consistency. 491 * Apple for your consistency.
@@ -488,11 +493,11 @@ static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode)
488 if (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 || 493 if (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 ||
489 dev->pci_device == 0x0329) { 494 dev->pci_device == 0x0329) {
490 if (mode == DRM_MODE_DPMS_ON) { 495 if (mode == DRM_MODE_DPMS_ON) {
491 nv_mask(dev, NV_PBUS_DEBUG_DUALHEAD_CTL, 0, 1 << 31); 496 nv_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 0, 1 << 31);
492 nv_mask(dev, NV_PCRTC_GPIO_EXT, 3, 1); 497 nv_mask(device, NV_PCRTC_GPIO_EXT, 3, 1);
493 } else { 498 } else {
494 nv_mask(dev, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 0); 499 nv_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 0);
495 nv_mask(dev, NV_PCRTC_GPIO_EXT, 3, 0); 500 nv_mask(device, NV_PCRTC_GPIO_EXT, 3, 0);
496 } 501 }
497 } 502 }
498#endif 503#endif
@@ -507,6 +512,7 @@ static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode)
507{ 512{
508 struct drm_device *dev = encoder->dev; 513 struct drm_device *dev = encoder->dev;
509 struct drm_crtc *crtc = encoder->crtc; 514 struct drm_crtc *crtc = encoder->crtc;
515 struct nouveau_drm *drm = nouveau_drm(dev);
510 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 516 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
511 bool was_powersaving = is_powersaving_dpms(nv_encoder->last_dpms); 517 bool was_powersaving = is_powersaving_dpms(nv_encoder->last_dpms);
512 518
@@ -514,7 +520,7 @@ static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode)
514 return; 520 return;
515 nv_encoder->last_dpms = mode; 521 nv_encoder->last_dpms = mode;
516 522
517 NV_INFO(dev, "Setting dpms mode %d on lvds encoder (output %d)\n", 523 NV_INFO(drm, "Setting dpms mode %d on lvds encoder (output %d)\n",
518 mode, nv_encoder->dcb->index); 524 mode, nv_encoder->dcb->index);
519 525
520 if (was_powersaving && is_powersaving_dpms(mode)) 526 if (was_powersaving && is_powersaving_dpms(mode))
@@ -552,14 +558,14 @@ static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode)
552 558
553static void nv04_tmds_dpms(struct drm_encoder *encoder, int mode) 559static void nv04_tmds_dpms(struct drm_encoder *encoder, int mode)
554{ 560{
555 struct drm_device *dev = encoder->dev; 561 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
556 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 562 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
557 563
558 if (nv_encoder->last_dpms == mode) 564 if (nv_encoder->last_dpms == mode)
559 return; 565 return;
560 nv_encoder->last_dpms = mode; 566 nv_encoder->last_dpms = mode;
561 567
562 NV_INFO(dev, "Setting dpms mode %d on tmds encoder (output %d)\n", 568 NV_INFO(drm, "Setting dpms mode %d on tmds encoder (output %d)\n",
563 mode, nv_encoder->dcb->index); 569 mode, nv_encoder->dcb->index);
564 570
565 nv04_dfp_update_backlight(encoder, mode); 571 nv04_dfp_update_backlight(encoder, mode);
@@ -605,8 +611,6 @@ static void nv04_dfp_destroy(struct drm_encoder *encoder)
605{ 611{
606 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 612 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
607 613
608 NV_DEBUG_KMS(encoder->dev, "\n");
609
610 if (get_slave_funcs(encoder)) 614 if (get_slave_funcs(encoder))
611 get_slave_funcs(encoder)->destroy(encoder); 615 get_slave_funcs(encoder)->destroy(encoder);
612 616
@@ -618,7 +622,9 @@ static void nv04_tmds_slave_init(struct drm_encoder *encoder)
618{ 622{
619 struct drm_device *dev = encoder->dev; 623 struct drm_device *dev = encoder->dev;
620 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; 624 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
621 struct nouveau_i2c_port *i2c = nouveau_i2c_find(dev, 2); 625 struct nouveau_drm *drm = nouveau_drm(dev);
626 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
627 struct nouveau_i2c_port *port = i2c->find(i2c, 2);
622 struct i2c_board_info info[] = { 628 struct i2c_board_info info[] = {
623 { 629 {
624 .type = "sil164", 630 .type = "sil164",
@@ -631,16 +637,16 @@ static void nv04_tmds_slave_init(struct drm_encoder *encoder)
631 }; 637 };
632 int type; 638 int type;
633 639
634 if (!nv_gf4_disp_arch(dev) || !i2c || 640 if (!nv_gf4_disp_arch(dev) || !port ||
635 get_tmds_slave(encoder)) 641 get_tmds_slave(encoder))
636 return; 642 return;
637 643
638 type = nouveau_i2c_identify(dev, "TMDS transmitter", info, NULL, 2); 644 type = i2c->identify(i2c, 2, "TMDS transmitter", info, NULL);
639 if (type < 0) 645 if (type < 0)
640 return; 646 return;
641 647
642 drm_i2c_encoder_init(dev, to_encoder_slave(encoder), 648 drm_i2c_encoder_init(dev, to_encoder_slave(encoder),
643 nouveau_i2c_adapter(i2c), &info[type]); 649 &port->adapter, &info[type]);
644} 650}
645 651
646static const struct drm_encoder_helper_funcs nv04_lvds_helper_funcs = { 652static const struct drm_encoder_helper_funcs nv04_lvds_helper_funcs = {
diff --git a/drivers/gpu/drm/nouveau/nv04_display.c b/drivers/gpu/drm/nouveau/nv04_display.c
index 6ab936376c40..b25b8d9c2fcc 100644
--- a/drivers/gpu/drm/nouveau/nv04_display.c
+++ b/drivers/gpu/drm/nouveau/nv04_display.c
@@ -26,8 +26,8 @@
26#include "drm.h" 26#include "drm.h"
27#include "drm_crtc_helper.h" 27#include "drm_crtc_helper.h"
28 28
29#include "nouveau_drv.h" 29#include "nouveau_drm.h"
30#include "nouveau_fb.h" 30#include "nouveau_reg.h"
31#include "nouveau_hw.h" 31#include "nouveau_hw.h"
32#include "nouveau_encoder.h" 32#include "nouveau_encoder.h"
33#include "nouveau_connector.h" 33#include "nouveau_connector.h"
@@ -53,21 +53,25 @@ nv04_display_late_takedown(struct drm_device *dev)
53int 53int
54nv04_display_create(struct drm_device *dev) 54nv04_display_create(struct drm_device *dev)
55{ 55{
56 struct drm_nouveau_private *dev_priv = dev->dev_private; 56 struct nouveau_drm *drm = nouveau_drm(dev);
57 struct dcb_table *dcb = &dev_priv->vbios.dcb; 57 struct dcb_table *dcb = &drm->vbios.dcb;
58 struct drm_connector *connector, *ct; 58 struct drm_connector *connector, *ct;
59 struct drm_encoder *encoder; 59 struct drm_encoder *encoder;
60 struct drm_crtc *crtc; 60 struct drm_crtc *crtc;
61 struct nv04_display *disp; 61 struct nv04_display *disp;
62 int i, ret; 62 int i, ret;
63 63
64 NV_DEBUG_KMS(dev, "\n"); 64 NV_DEBUG(drm, "\n");
65 65
66 disp = kzalloc(sizeof(*disp), GFP_KERNEL); 66 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
67 dev_priv->engine.display.priv = disp;
68 if (!disp) 67 if (!disp)
69 return -ENOMEM; 68 return -ENOMEM;
70 69
70 nouveau_display(dev)->priv = disp;
71 nouveau_display(dev)->dtor = nv04_display_destroy;
72 nouveau_display(dev)->init = nv04_display_init;
73 nouveau_display(dev)->fini = nv04_display_fini;
74
71 nouveau_hw_save_vga_fonts(dev, 1); 75 nouveau_hw_save_vga_fonts(dev, 1);
72 76
73 nv04_crtc_create(dev, 0); 77 nv04_crtc_create(dev, 0);
@@ -96,7 +100,7 @@ nv04_display_create(struct drm_device *dev)
96 ret = nv04_tv_create(connector, dcbent); 100 ret = nv04_tv_create(connector, dcbent);
97 break; 101 break;
98 default: 102 default:
99 NV_WARN(dev, "DCB type %d not known\n", dcbent->type); 103 NV_WARN(drm, "DCB type %d not known\n", dcbent->type);
100 continue; 104 continue;
101 } 105 }
102 106
@@ -107,7 +111,7 @@ nv04_display_create(struct drm_device *dev)
107 list_for_each_entry_safe(connector, ct, 111 list_for_each_entry_safe(connector, ct,
108 &dev->mode_config.connector_list, head) { 112 &dev->mode_config.connector_list, head) {
109 if (!connector->encoder_ids[0]) { 113 if (!connector->encoder_ids[0]) {
110 NV_WARN(dev, "%s has no encoders, removing\n", 114 NV_WARN(drm, "%s has no encoders, removing\n",
111 drm_get_connector_name(connector)); 115 drm_get_connector_name(connector));
112 connector->funcs->destroy(connector); 116 connector->funcs->destroy(connector);
113 } 117 }
@@ -129,12 +133,12 @@ nv04_display_create(struct drm_device *dev)
129void 133void
130nv04_display_destroy(struct drm_device *dev) 134nv04_display_destroy(struct drm_device *dev)
131{ 135{
132 struct drm_nouveau_private *dev_priv = dev->dev_private; 136 struct nouveau_drm *drm = nouveau_drm(dev);
133 struct nv04_display *disp = nv04_display(dev); 137 struct nv04_display *disp = nv04_display(dev);
134 struct drm_encoder *encoder; 138 struct drm_encoder *encoder;
135 struct drm_crtc *crtc; 139 struct drm_crtc *crtc;
136 140
137 NV_DEBUG_KMS(dev, "\n"); 141 NV_DEBUG(drm, "\n");
138 142
139 /* Turn every CRTC off. */ 143 /* Turn every CRTC off. */
140 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 144 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
@@ -157,7 +161,7 @@ nv04_display_destroy(struct drm_device *dev)
157 161
158 nouveau_hw_save_vga_fonts(dev, 0); 162 nouveau_hw_save_vga_fonts(dev, 0);
159 163
160 dev_priv->engine.display.priv = NULL; 164 nouveau_display(dev)->priv = NULL;
161 kfree(disp); 165 kfree(disp);
162} 166}
163 167
diff --git a/drivers/gpu/drm/nouveau/nv04_display.h b/drivers/gpu/drm/nouveau/nv04_display.h
index 139b8b057534..45322802e37d 100644
--- a/drivers/gpu/drm/nouveau/nv04_display.h
+++ b/drivers/gpu/drm/nouveau/nv04_display.h
@@ -3,6 +3,8 @@
3 3
4#include <subdev/bios/pll.h> 4#include <subdev/bios/pll.h>
5 5
6#include "nouveau_display.h"
7
6enum nv04_fp_display_regs { 8enum nv04_fp_display_regs {
7 FP_DISPLAY_END, 9 FP_DISPLAY_END,
8 FP_TOTAL, 10 FP_TOTAL,
@@ -80,6 +82,12 @@ struct nv04_display {
80 uint32_t dac_users[4]; 82 uint32_t dac_users[4];
81}; 83};
82 84
85static inline struct nv04_display *
86nv04_display(struct drm_device *dev)
87{
88 return nouveau_display(dev)->priv;
89}
90
83/* nv04_display.c */ 91/* nv04_display.c */
84int nv04_display_early_init(struct drm_device *); 92int nv04_display_early_init(struct drm_device *);
85void nv04_display_late_takedown(struct drm_device *); 93void nv04_display_late_takedown(struct drm_device *);
@@ -113,4 +121,64 @@ int nv04_tv_create(struct drm_connector *, struct dcb_output *);
113/* nv17_tv.c */ 121/* nv17_tv.c */
114int nv17_tv_create(struct drm_connector *, struct dcb_output *); 122int nv17_tv_create(struct drm_connector *, struct dcb_output *);
115 123
124static inline bool
125nv_two_heads(struct drm_device *dev)
126{
127 struct nouveau_drm *drm = nouveau_drm(dev);
128 const int impl = dev->pci_device & 0x0ff0;
129
130 if (nv_device(drm->device)->card_type >= NV_10 && impl != 0x0100 &&
131 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
132 return true;
133
134 return false;
135}
136
137static inline bool
138nv_gf4_disp_arch(struct drm_device *dev)
139{
140 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
141}
142
143static inline bool
144nv_two_reg_pll(struct drm_device *dev)
145{
146 struct nouveau_drm *drm = nouveau_drm(dev);
147 const int impl = dev->pci_device & 0x0ff0;
148
149 if (impl == 0x0310 || impl == 0x0340 || nv_device(drm->device)->card_type >= NV_40)
150 return true;
151 return false;
152}
153
154static inline bool
155nv_match_device(struct drm_device *dev, unsigned device,
156 unsigned sub_vendor, unsigned sub_device)
157{
158 return dev->pdev->device == device &&
159 dev->pdev->subsystem_vendor == sub_vendor &&
160 dev->pdev->subsystem_device == sub_device;
161}
162
163#include <subdev/bios.h>
164#include <subdev/bios/init.h>
165
166static inline void
167nouveau_bios_run_init_table(struct drm_device *dev, u16 table,
168 struct dcb_output *outp, int crtc)
169{
170 struct nouveau_device *device = nouveau_dev(dev);
171 struct nouveau_bios *bios = nouveau_bios(device);
172 struct nvbios_init init = {
173 .subdev = nv_subdev(bios),
174 .bios = bios,
175 .offset = table,
176 .outp = outp,
177 .crtc = crtc,
178 .execute = 1,
179 };
180
181 nvbios_exec(&init);
182}
183
116#endif 184#endif
diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c
index 35480b6776f8..77dcc9c50777 100644
--- a/drivers/gpu/drm/nouveau/nv04_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c
@@ -32,7 +32,7 @@ int
32nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) 32nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
33{ 33{
34 struct nouveau_fbdev *nfbdev = info->par; 34 struct nouveau_fbdev *nfbdev = info->par;
35 struct nouveau_drm *drm = nouveau_newpriv(nfbdev->dev); 35 struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
36 struct nouveau_channel *chan = drm->channel; 36 struct nouveau_channel *chan = drm->channel;
37 int ret; 37 int ret;
38 38
@@ -52,7 +52,7 @@ int
52nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 52nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
53{ 53{
54 struct nouveau_fbdev *nfbdev = info->par; 54 struct nouveau_fbdev *nfbdev = info->par;
55 struct nouveau_drm *drm = nouveau_newpriv(nfbdev->dev); 55 struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
56 struct nouveau_channel *chan = drm->channel; 56 struct nouveau_channel *chan = drm->channel;
57 int ret; 57 int ret;
58 58
@@ -79,7 +79,7 @@ int
79nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) 79nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
80{ 80{
81 struct nouveau_fbdev *nfbdev = info->par; 81 struct nouveau_fbdev *nfbdev = info->par;
82 struct nouveau_drm *drm = nouveau_newpriv(nfbdev->dev); 82 struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
83 struct nouveau_channel *chan = drm->channel; 83 struct nouveau_channel *chan = drm->channel;
84 uint32_t fg; 84 uint32_t fg;
85 uint32_t bg; 85 uint32_t bg;
@@ -139,7 +139,7 @@ nv04_fbcon_accel_init(struct fb_info *info)
139{ 139{
140 struct nouveau_fbdev *nfbdev = info->par; 140 struct nouveau_fbdev *nfbdev = info->par;
141 struct drm_device *dev = nfbdev->dev; 141 struct drm_device *dev = nfbdev->dev;
142 struct nouveau_drm *drm = nouveau_newpriv(dev); 142 struct nouveau_drm *drm = nouveau_drm(dev);
143 struct nouveau_channel *chan = drm->channel; 143 struct nouveau_channel *chan = drm->channel;
144 struct nouveau_device *device = nv_device(drm->device); 144 struct nouveau_device *device = nv_device(drm->device);
145 struct nouveau_object *object; 145 struct nouveau_object *object;
diff --git a/drivers/gpu/drm/nouveau/nv04_pm.c b/drivers/gpu/drm/nouveau/nv04_pm.c
index 76b5340603a9..410be011c2f0 100644
--- a/drivers/gpu/drm/nouveau/nv04_pm.c
+++ b/drivers/gpu/drm/nouveau/nv04_pm.c
@@ -23,10 +23,15 @@
23 */ 23 */
24 24
25#include "drmP.h" 25#include "drmP.h"
26#include "nouveau_drv.h" 26#include "nouveau_drm.h"
27#include "nouveau_reg.h"
27#include "nouveau_hw.h" 28#include "nouveau_hw.h"
28#include "nouveau_pm.h" 29#include "nouveau_pm.h"
29 30
31#include <subdev/bios/pll.h>
32#include <subdev/clock.h>
33#include <subdev/timer.h>
34
30int 35int
31nv04_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl) 36nv04_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
32{ 37{
@@ -58,13 +63,16 @@ struct nv04_pm_state {
58static int 63static int
59calc_pll(struct drm_device *dev, u32 id, int khz, struct nv04_pm_clock *clk) 64calc_pll(struct drm_device *dev, u32 id, int khz, struct nv04_pm_clock *clk)
60{ 65{
66 struct nouveau_device *device = nouveau_dev(dev);
67 struct nouveau_bios *bios = nouveau_bios(device);
68 struct nouveau_clock *pclk = nouveau_clock(device);
61 int ret; 69 int ret;
62 70
63 ret = get_pll_limits(dev, id, &clk->pll); 71 ret = nvbios_pll_parse(bios, id, &clk->pll);
64 if (ret) 72 if (ret)
65 return ret; 73 return ret;
66 74
67 ret = nouveau_calc_pll_mnp(dev, &clk->pll, khz, &clk->calc); 75 ret = pclk->pll_calc(pclk, &clk->pll, khz, &clk->calc);
68 if (!ret) 76 if (!ret)
69 return -EINVAL; 77 return -EINVAL;
70 78
@@ -100,38 +108,38 @@ error:
100static void 108static void
101prog_pll(struct drm_device *dev, struct nv04_pm_clock *clk) 109prog_pll(struct drm_device *dev, struct nv04_pm_clock *clk)
102{ 110{
103 struct drm_nouveau_private *dev_priv = dev->dev_private; 111 struct nouveau_device *device = nouveau_dev(dev);
112 struct nouveau_clock *pclk = nouveau_clock(device);
104 u32 reg = clk->pll.reg; 113 u32 reg = clk->pll.reg;
105 114
106 /* thank the insane nouveau_hw_setpll() interface for this */ 115 /* thank the insane nouveau_hw_setpll() interface for this */
107 if (dev_priv->card_type >= NV_40) 116 if (device->card_type >= NV_40)
108 reg += 4; 117 reg += 4;
109 118
110 nouveau_hw_setpll(dev, reg, &clk->calc); 119 pclk->pll_prog(pclk, reg, &clk->calc);
111} 120}
112 121
113int 122int
114nv04_pm_clocks_set(struct drm_device *dev, void *pre_state) 123nv04_pm_clocks_set(struct drm_device *dev, void *pre_state)
115{ 124{
116 struct drm_nouveau_private *dev_priv = dev->dev_private; 125 struct nouveau_device *device = nouveau_dev(dev);
126 struct nouveau_timer *ptimer = nouveau_timer(device);
117 struct nv04_pm_state *state = pre_state; 127 struct nv04_pm_state *state = pre_state;
118 128
119 prog_pll(dev, &state->core); 129 prog_pll(dev, &state->core);
120 130
121 if (state->memory.pll.reg) { 131 if (state->memory.pll.reg) {
122 prog_pll(dev, &state->memory); 132 prog_pll(dev, &state->memory);
123 if (dev_priv->card_type < NV_30) { 133 if (device->card_type < NV_30) {
124 if (dev_priv->card_type == NV_20) 134 if (device->card_type == NV_20)
125 nv_mask(dev, 0x1002c4, 0, 1 << 20); 135 nv_mask(device, 0x1002c4, 0, 1 << 20);
126 136
127 /* Reset the DLLs */ 137 /* Reset the DLLs */
128 nv_mask(dev, 0x1002c0, 0, 1 << 8); 138 nv_mask(device, 0x1002c0, 0, 1 << 8);
129 } 139 }
130 } 140 }
131 141
132#if 0 /*XXX*/ 142 nv_ofuncs(ptimer)->init(nv_object(ptimer));
133 ptimer->init(dev);
134#endif
135 143
136 kfree(state); 144 kfree(state);
137 return 0; 145 return 0;
diff --git a/drivers/gpu/drm/nouveau/nv04_tv.c b/drivers/gpu/drm/nouveau/nv04_tv.c
index 5f5c25d77343..45c5c039e7e4 100644
--- a/drivers/gpu/drm/nouveau/nv04_tv.c
+++ b/drivers/gpu/drm/nouveau/nv04_tv.c
@@ -25,7 +25,8 @@
25 */ 25 */
26 26
27#include "drmP.h" 27#include "drmP.h"
28#include "nouveau_drv.h" 28#include "nouveau_drm.h"
29#include "nouveau_reg.h"
29#include "nouveau_encoder.h" 30#include "nouveau_encoder.h"
30#include "nouveau_connector.h" 31#include "nouveau_connector.h"
31#include "nouveau_crtc.h" 32#include "nouveau_crtc.h"
@@ -34,6 +35,8 @@
34 35
35#include "i2c/ch7006.h" 36#include "i2c/ch7006.h"
36 37
38#include <subdev/i2c.h>
39
37static struct i2c_board_info nv04_tv_encoder_info[] = { 40static struct i2c_board_info nv04_tv_encoder_info[] = {
38 { 41 {
39 I2C_BOARD_INFO("ch7006", 0x75), 42 I2C_BOARD_INFO("ch7006", 0x75),
@@ -49,8 +52,11 @@ static struct i2c_board_info nv04_tv_encoder_info[] = {
49 52
50int nv04_tv_identify(struct drm_device *dev, int i2c_index) 53int nv04_tv_identify(struct drm_device *dev, int i2c_index)
51{ 54{
52 return nouveau_i2c_identify(dev, "TV encoder", nv04_tv_encoder_info, 55 struct nouveau_drm *drm = nouveau_drm(dev);
53 NULL, i2c_index); 56 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
57
58 return i2c->identify(i2c, i2c_index, "TV encoder",
59 nv04_tv_encoder_info, NULL);
54} 60}
55 61
56 62
@@ -64,11 +70,12 @@ int nv04_tv_identify(struct drm_device *dev, int i2c_index)
64static void nv04_tv_dpms(struct drm_encoder *encoder, int mode) 70static void nv04_tv_dpms(struct drm_encoder *encoder, int mode)
65{ 71{
66 struct drm_device *dev = encoder->dev; 72 struct drm_device *dev = encoder->dev;
73 struct nouveau_drm *drm = nouveau_drm(dev);
67 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 74 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
68 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; 75 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
69 uint8_t crtc1A; 76 uint8_t crtc1A;
70 77
71 NV_INFO(dev, "Setting dpms mode %d on TV encoder (output %d)\n", 78 NV_INFO(drm, "Setting dpms mode %d on TV encoder (output %d)\n",
72 mode, nv_encoder->dcb->index); 79 mode, nv_encoder->dcb->index);
73 80
74 state->pllsel &= ~(PLLSEL_TV_CRTC1_MASK | PLLSEL_TV_CRTC2_MASK); 81 state->pllsel &= ~(PLLSEL_TV_CRTC1_MASK | PLLSEL_TV_CRTC2_MASK);
@@ -154,12 +161,13 @@ static void nv04_tv_commit(struct drm_encoder *encoder)
154{ 161{
155 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 162 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
156 struct drm_device *dev = encoder->dev; 163 struct drm_device *dev = encoder->dev;
164 struct nouveau_drm *drm = nouveau_drm(dev);
157 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 165 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
158 struct drm_encoder_helper_funcs *helper = encoder->helper_private; 166 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
159 167
160 helper->dpms(encoder, DRM_MODE_DPMS_ON); 168 helper->dpms(encoder, DRM_MODE_DPMS_ON);
161 169
162 NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n", 170 NV_INFO(drm, "Output %s is running on CRTC %d using output %c\n",
163 drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base), nv_crtc->index, 171 drm_get_connector_name(&nouveau_encoder_connector_get(nv_encoder)->base), nv_crtc->index,
164 '@' + ffs(nv_encoder->dcb->or)); 172 '@' + ffs(nv_encoder->dcb->or));
165} 173}
@@ -185,8 +193,9 @@ nv04_tv_create(struct drm_connector *connector, struct dcb_output *entry)
185 struct drm_device *dev = connector->dev; 193 struct drm_device *dev = connector->dev;
186 struct drm_encoder_helper_funcs *hfuncs; 194 struct drm_encoder_helper_funcs *hfuncs;
187 struct drm_encoder_slave_funcs *sfuncs; 195 struct drm_encoder_slave_funcs *sfuncs;
188 struct nouveau_i2c_port *i2c = 196 struct nouveau_drm *drm = nouveau_drm(dev);
189 nouveau_i2c_find(dev, entry->i2c_index); 197 struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
198 struct nouveau_i2c_port *port = i2c->find(i2c, entry->i2c_index);
190 int type, ret; 199 int type, ret;
191 200
192 /* Ensure that we can talk to this encoder */ 201 /* Ensure that we can talk to this encoder */
@@ -218,7 +227,7 @@ nv04_tv_create(struct drm_connector *connector, struct dcb_output *entry)
218 227
219 /* Run the slave-specific initialization */ 228 /* Run the slave-specific initialization */
220 ret = drm_i2c_encoder_init(dev, to_encoder_slave(encoder), 229 ret = drm_i2c_encoder_init(dev, to_encoder_slave(encoder),
221 nouveau_i2c_adapter(i2c), &nv04_tv_encoder_info[type]); 230 &port->adapter, &nv04_tv_encoder_info[type]);
222 if (ret < 0) 231 if (ret < 0)
223 goto fail_cleanup; 232 goto fail_cleanup;
224 233
diff --git a/drivers/gpu/drm/nouveau/nv17_tv.c b/drivers/gpu/drm/nouveau/nv17_tv.c
index 5d1f6f6de257..dd85f0f79acf 100644
--- a/drivers/gpu/drm/nouveau/nv17_tv.c
+++ b/drivers/gpu/drm/nouveau/nv17_tv.c
@@ -26,19 +26,32 @@
26 26
27#include "drmP.h" 27#include "drmP.h"
28#include "drm_crtc_helper.h" 28#include "drm_crtc_helper.h"
29#include "nouveau_drv.h" 29#include "nouveau_drm.h"
30#include "nouveau_reg.h"
30#include "nouveau_encoder.h" 31#include "nouveau_encoder.h"
31#include "nouveau_connector.h" 32#include "nouveau_connector.h"
32#include "nouveau_crtc.h" 33#include "nouveau_crtc.h"
33#include "nouveau_hw.h" 34#include "nouveau_hw.h"
34#include "nv17_tv.h" 35#include "nv17_tv.h"
35 36
37#include <core/device.h>
38
36#include <subdev/bios/gpio.h> 39#include <subdev/bios/gpio.h>
40#include <subdev/gpio.h>
41
42MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
43 "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
44 "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
45 "\t\tDefault: PAL\n"
46 "\t\t*NOTE* Ignored for cards with external TV encoders.");
47static char *nouveau_tv_norm;
48module_param_named(tv_norm, nouveau_tv_norm, charp, 0400);
37 49
38static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder) 50static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
39{ 51{
40 struct drm_device *dev = encoder->dev; 52 struct drm_device *dev = encoder->dev;
41 struct drm_nouveau_private *dev_priv = dev->dev_private; 53 struct nouveau_drm *drm = nouveau_drm(dev);
54 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
42 uint32_t testval, regoffset = nv04_dac_output_offset(encoder); 55 uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
43 uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end, 56 uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end,
44 fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c; 57 fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c;
@@ -47,15 +60,15 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
47 60
48#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20) 61#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
49 testval = RGB_TEST_DATA(0x82, 0xeb, 0x82); 62 testval = RGB_TEST_DATA(0x82, 0xeb, 0x82);
50 if (dev_priv->vbios.tvdactestval) 63 if (drm->vbios.tvdactestval)
51 testval = dev_priv->vbios.tvdactestval; 64 testval = drm->vbios.tvdactestval;
52 65
53 dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset); 66 dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
54 head = (dacclk & 0x100) >> 8; 67 head = (dacclk & 0x100) >> 8;
55 68
56 /* Save the previous state. */ 69 /* Save the previous state. */
57 gpio1 = nouveau_gpio_func_get(dev, DCB_GPIO_TVDAC1); 70 gpio1 = gpio->get(gpio, 0, DCB_GPIO_TVDAC1, 0xff);
58 gpio0 = nouveau_gpio_func_get(dev, DCB_GPIO_TVDAC0); 71 gpio0 = gpio->get(gpio, 0, DCB_GPIO_TVDAC0, 0xff);
59 fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL); 72 fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL);
60 fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START); 73 fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START);
61 fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END); 74 fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END);
@@ -66,8 +79,8 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
66 ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c); 79 ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c);
67 80
68 /* Prepare the DAC for load detection. */ 81 /* Prepare the DAC for load detection. */
69 nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC1, true); 82 gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, true);
70 nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC0, true); 83 gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, true);
71 84
72 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343); 85 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343);
73 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047); 86 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047);
@@ -112,8 +125,8 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
112 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end); 125 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end);
113 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start); 126 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start);
114 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal); 127 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal);
115 nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC1, gpio1); 128 gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, gpio1);
116 nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC0, gpio0); 129 gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, gpio0);
117 130
118 return sample; 131 return sample;
119} 132}
@@ -121,15 +134,18 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
121static bool 134static bool
122get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask) 135get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask)
123{ 136{
137 struct nouveau_drm *drm = nouveau_drm(dev);
138 struct nouveau_object *device = drm->device;
139
124 /* Zotac FX5200 */ 140 /* Zotac FX5200 */
125 if (nv_match_device(dev, 0x0322, 0x19da, 0x1035) || 141 if (nv_device_match(device, 0x0322, 0x19da, 0x1035) ||
126 nv_match_device(dev, 0x0322, 0x19da, 0x2035)) { 142 nv_device_match(device, 0x0322, 0x19da, 0x2035)) {
127 *pin_mask = 0xc; 143 *pin_mask = 0xc;
128 return false; 144 return false;
129 } 145 }
130 146
131 /* MSI nForce2 IGP */ 147 /* MSI nForce2 IGP */
132 if (nv_match_device(dev, 0x01f0, 0x1462, 0x5710)) { 148 if (nv_device_match(device, 0x01f0, 0x1462, 0x5710)) {
133 *pin_mask = 0xc; 149 *pin_mask = 0xc;
134 return false; 150 return false;
135 } 151 }
@@ -141,7 +157,7 @@ static enum drm_connector_status
141nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector) 157nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector)
142{ 158{
143 struct drm_device *dev = encoder->dev; 159 struct drm_device *dev = encoder->dev;
144 struct drm_nouveau_private *dev_priv = dev->dev_private; 160 struct nouveau_drm *drm = nouveau_drm(dev);
145 struct drm_mode_config *conf = &dev->mode_config; 161 struct drm_mode_config *conf = &dev->mode_config;
146 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 162 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
147 struct dcb_output *dcb = tv_enc->base.dcb; 163 struct dcb_output *dcb = tv_enc->base.dcb;
@@ -151,8 +167,8 @@ nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector)
151 return connector_status_disconnected; 167 return connector_status_disconnected;
152 168
153 if (reliable) { 169 if (reliable) {
154 if (dev_priv->chipset == 0x42 || 170 if (nv_device(drm->device)->chipset == 0x42 ||
155 dev_priv->chipset == 0x43) 171 nv_device(drm->device)->chipset == 0x43)
156 tv_enc->pin_mask = 172 tv_enc->pin_mask =
157 nv42_tv_sample_load(encoder) >> 28 & 0xe; 173 nv42_tv_sample_load(encoder) >> 28 & 0xe;
158 else 174 else
@@ -186,7 +202,7 @@ nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector)
186 if (!reliable) { 202 if (!reliable) {
187 return connector_status_unknown; 203 return connector_status_unknown;
188 } else if (tv_enc->subconnector) { 204 } else if (tv_enc->subconnector) {
189 NV_INFO(dev, "Load detected on output %c\n", 205 NV_INFO(drm, "Load detected on output %c\n",
190 '@' + ffs(dcb->or)); 206 '@' + ffs(dcb->or));
191 return connector_status_connected; 207 return connector_status_connected;
192 } else { 208 } else {
@@ -358,6 +374,8 @@ static bool nv17_tv_mode_fixup(struct drm_encoder *encoder,
358static void nv17_tv_dpms(struct drm_encoder *encoder, int mode) 374static void nv17_tv_dpms(struct drm_encoder *encoder, int mode)
359{ 375{
360 struct drm_device *dev = encoder->dev; 376 struct drm_device *dev = encoder->dev;
377 struct nouveau_drm *drm = nouveau_drm(dev);
378 struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
361 struct nv17_tv_state *regs = &to_tv_enc(encoder)->state; 379 struct nv17_tv_state *regs = &to_tv_enc(encoder)->state;
362 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 380 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
363 381
@@ -365,7 +383,7 @@ static void nv17_tv_dpms(struct drm_encoder *encoder, int mode)
365 return; 383 return;
366 nouveau_encoder(encoder)->last_dpms = mode; 384 nouveau_encoder(encoder)->last_dpms = mode;
367 385
368 NV_INFO(dev, "Setting dpms mode %d on TV encoder (output %d)\n", 386 NV_INFO(drm, "Setting dpms mode %d on TV encoder (output %d)\n",
369 mode, nouveau_encoder(encoder)->dcb->index); 387 mode, nouveau_encoder(encoder)->dcb->index);
370 388
371 regs->ptv_200 &= ~1; 389 regs->ptv_200 &= ~1;
@@ -382,8 +400,8 @@ static void nv17_tv_dpms(struct drm_encoder *encoder, int mode)
382 400
383 nv_load_ptv(dev, regs, 200); 401 nv_load_ptv(dev, regs, 200);
384 402
385 nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC1, mode == DRM_MODE_DPMS_ON); 403 gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, mode == DRM_MODE_DPMS_ON);
386 nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC0, mode == DRM_MODE_DPMS_ON); 404 gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, mode == DRM_MODE_DPMS_ON);
387 405
388 nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON); 406 nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON);
389} 407}
@@ -391,7 +409,7 @@ static void nv17_tv_dpms(struct drm_encoder *encoder, int mode)
391static void nv17_tv_prepare(struct drm_encoder *encoder) 409static void nv17_tv_prepare(struct drm_encoder *encoder)
392{ 410{
393 struct drm_device *dev = encoder->dev; 411 struct drm_device *dev = encoder->dev;
394 struct drm_nouveau_private *dev_priv = dev->dev_private; 412 struct nouveau_drm *drm = nouveau_drm(dev);
395 struct drm_encoder_helper_funcs *helper = encoder->helper_private; 413 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
396 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); 414 struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
397 int head = nouveau_crtc(encoder->crtc)->index; 415 int head = nouveau_crtc(encoder->crtc)->index;
@@ -418,7 +436,7 @@ static void nv17_tv_prepare(struct drm_encoder *encoder)
418 !enc->crtc && 436 !enc->crtc &&
419 nv04_dfp_get_bound_head(dev, dcb) == head) { 437 nv04_dfp_get_bound_head(dev, dcb) == head) {
420 nv04_dfp_bind_head(dev, dcb, head ^ 1, 438 nv04_dfp_bind_head(dev, dcb, head ^ 1,
421 dev_priv->vbios.fp.dual_link); 439 drm->vbios.fp.dual_link);
422 } 440 }
423 } 441 }
424 442
@@ -430,7 +448,7 @@ static void nv17_tv_prepare(struct drm_encoder *encoder)
430 /* Set the DACCLK register */ 448 /* Set the DACCLK register */
431 dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1; 449 dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;
432 450
433 if (dev_priv->card_type == NV_40) 451 if (nv_device(drm->device)->card_type == NV_40)
434 dacclk |= 0x1a << 16; 452 dacclk |= 0x1a << 16;
435 453
436 if (tv_norm->kind == CTV_ENC_MODE) { 454 if (tv_norm->kind == CTV_ENC_MODE) {
@@ -454,7 +472,7 @@ static void nv17_tv_mode_set(struct drm_encoder *encoder,
454 struct drm_display_mode *adjusted_mode) 472 struct drm_display_mode *adjusted_mode)
455{ 473{
456 struct drm_device *dev = encoder->dev; 474 struct drm_device *dev = encoder->dev;
457 struct drm_nouveau_private *dev_priv = dev->dev_private; 475 struct nouveau_drm *drm = nouveau_drm(dev);
458 int head = nouveau_crtc(encoder->crtc)->index; 476 int head = nouveau_crtc(encoder->crtc)->index;
459 struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head]; 477 struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head];
460 struct nv17_tv_state *tv_regs = &to_tv_enc(encoder)->state; 478 struct nv17_tv_state *tv_regs = &to_tv_enc(encoder)->state;
@@ -487,7 +505,7 @@ static void nv17_tv_mode_set(struct drm_encoder *encoder,
487 tv_regs->ptv_614 = 0x13; 505 tv_regs->ptv_614 = 0x13;
488 } 506 }
489 507
490 if (dev_priv->card_type >= NV_30) { 508 if (nv_device(drm->device)->card_type >= NV_30) {
491 tv_regs->ptv_500 = 0xe8e0; 509 tv_regs->ptv_500 = 0xe8e0;
492 tv_regs->ptv_504 = 0x1710; 510 tv_regs->ptv_504 = 0x1710;
493 tv_regs->ptv_604 = 0x0; 511 tv_regs->ptv_604 = 0x0;
@@ -567,7 +585,7 @@ static void nv17_tv_mode_set(struct drm_encoder *encoder,
567static void nv17_tv_commit(struct drm_encoder *encoder) 585static void nv17_tv_commit(struct drm_encoder *encoder)
568{ 586{
569 struct drm_device *dev = encoder->dev; 587 struct drm_device *dev = encoder->dev;
570 struct drm_nouveau_private *dev_priv = dev->dev_private; 588 struct nouveau_drm *drm = nouveau_drm(dev);
571 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 589 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
572 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 590 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
573 struct drm_encoder_helper_funcs *helper = encoder->helper_private; 591 struct drm_encoder_helper_funcs *helper = encoder->helper_private;
@@ -582,7 +600,7 @@ static void nv17_tv_commit(struct drm_encoder *encoder)
582 nv17_tv_state_load(dev, &to_tv_enc(encoder)->state); 600 nv17_tv_state_load(dev, &to_tv_enc(encoder)->state);
583 601
584 /* This could use refinement for flatpanels, but it should work */ 602 /* This could use refinement for flatpanels, but it should work */
585 if (dev_priv->chipset < 0x44) 603 if (nv_device(drm->device)->chipset < 0x44)
586 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + 604 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
587 nv04_dac_output_offset(encoder), 605 nv04_dac_output_offset(encoder),
588 0xf0000000); 606 0xf0000000);
@@ -593,7 +611,7 @@ static void nv17_tv_commit(struct drm_encoder *encoder)
593 611
594 helper->dpms(encoder, DRM_MODE_DPMS_ON); 612 helper->dpms(encoder, DRM_MODE_DPMS_ON);
595 613
596 NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n", 614 NV_INFO(drm, "Output %s is running on CRTC %d using output %c\n",
597 drm_get_connector_name( 615 drm_get_connector_name(
598 &nouveau_encoder_connector_get(nv_encoder)->base), 616 &nouveau_encoder_connector_get(nv_encoder)->base),
599 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); 617 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
@@ -631,6 +649,7 @@ static int nv17_tv_create_resources(struct drm_encoder *encoder,
631 struct drm_connector *connector) 649 struct drm_connector *connector)
632{ 650{
633 struct drm_device *dev = encoder->dev; 651 struct drm_device *dev = encoder->dev;
652 struct nouveau_drm *drm = nouveau_drm(dev);
634 struct drm_mode_config *conf = &dev->mode_config; 653 struct drm_mode_config *conf = &dev->mode_config;
635 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 654 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
636 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; 655 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
@@ -647,7 +666,7 @@ static int nv17_tv_create_resources(struct drm_encoder *encoder,
647 } 666 }
648 667
649 if (i == num_tv_norms) 668 if (i == num_tv_norms)
650 NV_WARN(dev, "Invalid TV norm setting \"%s\"\n", 669 NV_WARN(drm, "Invalid TV norm setting \"%s\"\n",
651 nouveau_tv_norm); 670 nouveau_tv_norm);
652 } 671 }
653 672
@@ -760,8 +779,6 @@ static void nv17_tv_destroy(struct drm_encoder *encoder)
760{ 779{
761 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); 780 struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
762 781
763 NV_DEBUG_KMS(encoder->dev, "\n");
764
765 drm_encoder_cleanup(encoder); 782 drm_encoder_cleanup(encoder);
766 kfree(tv_enc); 783 kfree(tv_enc);
767} 784}
diff --git a/drivers/gpu/drm/nouveau/nv17_tv.h b/drivers/gpu/drm/nouveau/nv17_tv.h
index 622e72221682..7b331543a41b 100644
--- a/drivers/gpu/drm/nouveau/nv17_tv.h
+++ b/drivers/gpu/drm/nouveau/nv17_tv.h
@@ -130,12 +130,14 @@ void nv17_ctv_update_rescaler(struct drm_encoder *encoder);
130static inline void nv_write_ptv(struct drm_device *dev, uint32_t reg, 130static inline void nv_write_ptv(struct drm_device *dev, uint32_t reg,
131 uint32_t val) 131 uint32_t val)
132{ 132{
133 nv_wr32(dev, reg, val); 133 struct nouveau_device *device = nouveau_dev(dev);
134 nv_wr32(device, reg, val);
134} 135}
135 136
136static inline uint32_t nv_read_ptv(struct drm_device *dev, uint32_t reg) 137static inline uint32_t nv_read_ptv(struct drm_device *dev, uint32_t reg)
137{ 138{
138 return nv_rd32(dev, reg); 139 struct nouveau_device *device = nouveau_dev(dev);
140 return nv_rd32(device, reg);
139} 141}
140 142
141static inline void nv_write_tv_enc(struct drm_device *dev, uint8_t reg, 143static inline void nv_write_tv_enc(struct drm_device *dev, uint8_t reg,
diff --git a/drivers/gpu/drm/nouveau/nv17_tv_modes.c b/drivers/gpu/drm/nouveau/nv17_tv_modes.c
index 381d388def3a..a4c4b0c2c7ce 100644
--- a/drivers/gpu/drm/nouveau/nv17_tv_modes.c
+++ b/drivers/gpu/drm/nouveau/nv17_tv_modes.c
@@ -26,7 +26,7 @@
26 26
27#include "drmP.h" 27#include "drmP.h"
28#include "drm_crtc_helper.h" 28#include "drm_crtc_helper.h"
29#include "nouveau_drv.h" 29#include "nouveau_drm.h"
30#include "nouveau_encoder.h" 30#include "nouveau_encoder.h"
31#include "nouveau_crtc.h" 31#include "nouveau_crtc.h"
32#include "nouveau_hw.h" 32#include "nouveau_hw.h"
diff --git a/drivers/gpu/drm/nouveau/nv40_pm.c b/drivers/gpu/drm/nouveau/nv40_pm.c
index 93f536de3779..23f200630d8b 100644
--- a/drivers/gpu/drm/nouveau/nv40_pm.c
+++ b/drivers/gpu/drm/nouveau/nv40_pm.c
@@ -23,17 +23,24 @@
23 */ 23 */
24 24
25#include "drmP.h" 25#include "drmP.h"
26#include "nouveau_drv.h" 26#include "nouveau_drm.h"
27#include <nouveau_bios.h> 27#include "nouveau_bios.h"
28#include "nouveau_pm.h" 28#include "nouveau_pm.h"
29#include "nouveau_hw.h" 29#include "nouveau_hw.h"
30 30
31#include <subdev/bios/pll.h>
32#include <subdev/clock.h>
33#include <subdev/timer.h>
34
35#include <engine/fifo.h>
36
31#define min2(a,b) ((a) < (b) ? (a) : (b)) 37#define min2(a,b) ((a) < (b) ? (a) : (b))
32 38
33static u32 39static u32
34read_pll_1(struct drm_device *dev, u32 reg) 40read_pll_1(struct drm_device *dev, u32 reg)
35{ 41{
36 u32 ctrl = nv_rd32(dev, reg + 0x00); 42 struct nouveau_device *device = nouveau_dev(dev);
43 u32 ctrl = nv_rd32(device, reg + 0x00);
37 int P = (ctrl & 0x00070000) >> 16; 44 int P = (ctrl & 0x00070000) >> 16;
38 int N = (ctrl & 0x0000ff00) >> 8; 45 int N = (ctrl & 0x0000ff00) >> 8;
39 int M = (ctrl & 0x000000ff) >> 0; 46 int M = (ctrl & 0x000000ff) >> 0;
@@ -48,8 +55,9 @@ read_pll_1(struct drm_device *dev, u32 reg)
48static u32 55static u32
49read_pll_2(struct drm_device *dev, u32 reg) 56read_pll_2(struct drm_device *dev, u32 reg)
50{ 57{
51 u32 ctrl = nv_rd32(dev, reg + 0x00); 58 struct nouveau_device *device = nouveau_dev(dev);
52 u32 coef = nv_rd32(dev, reg + 0x04); 59 u32 ctrl = nv_rd32(device, reg + 0x00);
60 u32 coef = nv_rd32(device, reg + 0x04);
53 int N2 = (coef & 0xff000000) >> 24; 61 int N2 = (coef & 0xff000000) >> 24;
54 int M2 = (coef & 0x00ff0000) >> 16; 62 int M2 = (coef & 0x00ff0000) >> 16;
55 int N1 = (coef & 0x0000ff00) >> 8; 63 int N1 = (coef & 0x0000ff00) >> 8;
@@ -88,7 +96,8 @@ read_clk(struct drm_device *dev, u32 src)
88int 96int
89nv40_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl) 97nv40_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
90{ 98{
91 u32 ctrl = nv_rd32(dev, 0x00c040); 99 struct nouveau_device *device = nouveau_dev(dev);
100 u32 ctrl = nv_rd32(device, 0x00c040);
92 101
93 perflvl->core = read_clk(dev, (ctrl & 0x00000003) >> 0); 102 perflvl->core = read_clk(dev, (ctrl & 0x00000003) >> 0);
94 perflvl->shader = read_clk(dev, (ctrl & 0x00000030) >> 4); 103 perflvl->shader = read_clk(dev, (ctrl & 0x00000030) >> 4);
@@ -109,17 +118,20 @@ static int
109nv40_calc_pll(struct drm_device *dev, u32 reg, struct nvbios_pll *pll, 118nv40_calc_pll(struct drm_device *dev, u32 reg, struct nvbios_pll *pll,
110 u32 clk, int *N1, int *M1, int *N2, int *M2, int *log2P) 119 u32 clk, int *N1, int *M1, int *N2, int *M2, int *log2P)
111{ 120{
121 struct nouveau_device *device = nouveau_dev(dev);
122 struct nouveau_bios *bios = nouveau_bios(device);
123 struct nouveau_clock *pclk = nouveau_clock(device);
112 struct nouveau_pll_vals coef; 124 struct nouveau_pll_vals coef;
113 int ret; 125 int ret;
114 126
115 ret = get_pll_limits(dev, reg, pll); 127 ret = nvbios_pll_parse(bios, reg, pll);
116 if (ret) 128 if (ret)
117 return ret; 129 return ret;
118 130
119 if (clk < pll->vco1.max_freq) 131 if (clk < pll->vco1.max_freq)
120 pll->vco2.max_freq = 0; 132 pll->vco2.max_freq = 0;
121 133
122 ret = nouveau_calc_pll_mnp(dev, pll, clk, &coef); 134 pclk->pll_calc(pclk, pll, clk, &coef);
123 if (ret == 0) 135 if (ret == 0)
124 return -ERANGE; 136 return -ERANGE;
125 137
@@ -211,12 +223,13 @@ static bool
211nv40_pm_gr_idle(void *data) 223nv40_pm_gr_idle(void *data)
212{ 224{
213 struct drm_device *dev = data; 225 struct drm_device *dev = data;
226 struct nouveau_device *device = nouveau_dev(dev);
214 227
215 if ((nv_rd32(dev, 0x400760) & 0x000000f0) >> 4 != 228 if ((nv_rd32(device, 0x400760) & 0x000000f0) >> 4 !=
216 (nv_rd32(dev, 0x400760) & 0x0000000f)) 229 (nv_rd32(device, 0x400760) & 0x0000000f))
217 return false; 230 return false;
218 231
219 if (nv_rd32(dev, 0x400700)) 232 if (nv_rd32(device, 0x400700))
220 return false; 233 return false;
221 234
222 return true; 235 return true;
@@ -225,7 +238,9 @@ nv40_pm_gr_idle(void *data)
225int 238int
226nv40_pm_clocks_set(struct drm_device *dev, void *pre_state) 239nv40_pm_clocks_set(struct drm_device *dev, void *pre_state)
227{ 240{
228 struct drm_nouveau_private *dev_priv = dev->dev_private; 241 struct nouveau_device *device = nouveau_dev(dev);
242 struct nouveau_fifo *pfifo = nouveau_fifo(device);
243 struct nouveau_drm *drm = nouveau_drm(dev);
229 struct nv40_pm_state *info = pre_state; 244 struct nv40_pm_state *info = pre_state;
230 unsigned long flags; 245 unsigned long flags;
231 struct bit_entry M; 246 struct bit_entry M;
@@ -235,12 +250,12 @@ nv40_pm_clocks_set(struct drm_device *dev, void *pre_state)
235 250
236 /* determine which CRTCs are active, fetch VGA_SR1 for each */ 251 /* determine which CRTCs are active, fetch VGA_SR1 for each */
237 for (i = 0; i < 2; i++) { 252 for (i = 0; i < 2; i++) {
238 u32 vbl = nv_rd32(dev, 0x600808 + (i * 0x2000)); 253 u32 vbl = nv_rd32(device, 0x600808 + (i * 0x2000));
239 u32 cnt = 0; 254 u32 cnt = 0;
240 do { 255 do {
241 if (vbl != nv_rd32(dev, 0x600808 + (i * 0x2000))) { 256 if (vbl != nv_rd32(device, 0x600808 + (i * 0x2000))) {
242 nv_wr08(dev, 0x0c03c4 + (i * 0x2000), 0x01); 257 nv_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01);
243 sr1[i] = nv_rd08(dev, 0x0c03c5 + (i * 0x2000)); 258 sr1[i] = nv_rd08(device, 0x0c03c5 + (i * 0x2000));
244 if (!(sr1[i] & 0x20)) 259 if (!(sr1[i] & 0x20))
245 crtc_mask |= (1 << i); 260 crtc_mask |= (1 << i);
246 break; 261 break;
@@ -250,28 +265,20 @@ nv40_pm_clocks_set(struct drm_device *dev, void *pre_state)
250 } 265 }
251 266
252 /* halt and idle engines */ 267 /* halt and idle engines */
253 spin_lock_irqsave(&dev_priv->context_switch_lock, flags); 268 pfifo->pause(pfifo, &flags);
254 nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
255 if (!nv_wait(dev, 0x002500, 0x00000010, 0x00000000))
256 goto resume;
257 nv_mask(dev, 0x003220, 0x00000001, 0x00000000);
258 if (!nv_wait(dev, 0x003220, 0x00000010, 0x00000000))
259 goto resume;
260 nv_mask(dev, 0x003200, 0x00000001, 0x00000000);
261 //XXX: nv04_fifo_cache_pull(dev, false);
262 269
263 if (!nv_wait_cb(dev, nv40_pm_gr_idle, dev)) 270 if (!nv_wait_cb(device, nv40_pm_gr_idle, dev))
264 goto resume; 271 goto resume;
265 272
266 ret = 0; 273 ret = 0;
267 274
268 /* set engine clocks */ 275 /* set engine clocks */
269 nv_mask(dev, 0x00c040, 0x00000333, 0x00000000); 276 nv_mask(device, 0x00c040, 0x00000333, 0x00000000);
270 nv_wr32(dev, 0x004004, info->npll_coef); 277 nv_wr32(device, 0x004004, info->npll_coef);
271 nv_mask(dev, 0x004000, 0xc0070100, info->npll_ctrl); 278 nv_mask(device, 0x004000, 0xc0070100, info->npll_ctrl);
272 nv_mask(dev, 0x004008, 0xc007ffff, info->spll); 279 nv_mask(device, 0x004008, 0xc007ffff, info->spll);
273 mdelay(5); 280 mdelay(5);
274 nv_mask(dev, 0x00c040, 0x00000333, info->ctrl); 281 nv_mask(device, 0x00c040, 0x00000333, info->ctrl);
275 282
276 if (!info->mpll_ctrl) 283 if (!info->mpll_ctrl)
277 goto resume; 284 goto resume;
@@ -280,52 +287,52 @@ nv40_pm_clocks_set(struct drm_device *dev, void *pre_state)
280 for (i = 0; i < 2; i++) { 287 for (i = 0; i < 2; i++) {
281 if (!(crtc_mask & (1 << i))) 288 if (!(crtc_mask & (1 << i)))
282 continue; 289 continue;
283 nv_wait(dev, 0x600808 + (i * 0x2000), 0x00010000, 0x00000000); 290 nv_wait(device, 0x600808 + (i * 0x2000), 0x00010000, 0x00000000);
284 nv_wait(dev, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000); 291 nv_wait(device, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
285 nv_wr08(dev, 0x0c03c4 + (i * 0x2000), 0x01); 292 nv_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01);
286 nv_wr08(dev, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20); 293 nv_wr08(device, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20);
287 } 294 }
288 295
289 /* prepare ram for reclocking */ 296 /* prepare ram for reclocking */
290 nv_wr32(dev, 0x1002d4, 0x00000001); /* precharge */ 297 nv_wr32(device, 0x1002d4, 0x00000001); /* precharge */
291 nv_wr32(dev, 0x1002d0, 0x00000001); /* refresh */ 298 nv_wr32(device, 0x1002d0, 0x00000001); /* refresh */
292 nv_wr32(dev, 0x1002d0, 0x00000001); /* refresh */ 299 nv_wr32(device, 0x1002d0, 0x00000001); /* refresh */
293 nv_mask(dev, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */ 300 nv_mask(device, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */
294 nv_wr32(dev, 0x1002dc, 0x00000001); /* enable self-refresh */ 301 nv_wr32(device, 0x1002dc, 0x00000001); /* enable self-refresh */
295 302
296 /* change the PLL of each memory partition */ 303 /* change the PLL of each memory partition */
297 nv_mask(dev, 0x00c040, 0x0000c000, 0x00000000); 304 nv_mask(device, 0x00c040, 0x0000c000, 0x00000000);
298 switch (dev_priv->chipset) { 305 switch (nv_device(drm->device)->chipset) {
299 case 0x40: 306 case 0x40:
300 case 0x45: 307 case 0x45:
301 case 0x41: 308 case 0x41:
302 case 0x42: 309 case 0x42:
303 case 0x47: 310 case 0x47:
304 nv_mask(dev, 0x004044, 0xc0771100, info->mpll_ctrl); 311 nv_mask(device, 0x004044, 0xc0771100, info->mpll_ctrl);
305 nv_mask(dev, 0x00402c, 0xc0771100, info->mpll_ctrl); 312 nv_mask(device, 0x00402c, 0xc0771100, info->mpll_ctrl);
306 nv_wr32(dev, 0x004048, info->mpll_coef); 313 nv_wr32(device, 0x004048, info->mpll_coef);
307 nv_wr32(dev, 0x004030, info->mpll_coef); 314 nv_wr32(device, 0x004030, info->mpll_coef);
308 case 0x43: 315 case 0x43:
309 case 0x49: 316 case 0x49:
310 case 0x4b: 317 case 0x4b:
311 nv_mask(dev, 0x004038, 0xc0771100, info->mpll_ctrl); 318 nv_mask(device, 0x004038, 0xc0771100, info->mpll_ctrl);
312 nv_wr32(dev, 0x00403c, info->mpll_coef); 319 nv_wr32(device, 0x00403c, info->mpll_coef);
313 default: 320 default:
314 nv_mask(dev, 0x004020, 0xc0771100, info->mpll_ctrl); 321 nv_mask(device, 0x004020, 0xc0771100, info->mpll_ctrl);
315 nv_wr32(dev, 0x004024, info->mpll_coef); 322 nv_wr32(device, 0x004024, info->mpll_coef);
316 break; 323 break;
317 } 324 }
318 udelay(100); 325 udelay(100);
319 nv_mask(dev, 0x00c040, 0x0000c000, 0x0000c000); 326 nv_mask(device, 0x00c040, 0x0000c000, 0x0000c000);
320 327
321 /* re-enable normal operation of memory controller */ 328 /* re-enable normal operation of memory controller */
322 nv_wr32(dev, 0x1002dc, 0x00000000); 329 nv_wr32(device, 0x1002dc, 0x00000000);
323 nv_mask(dev, 0x100210, 0x80000000, 0x80000000); 330 nv_mask(device, 0x100210, 0x80000000, 0x80000000);
324 udelay(100); 331 udelay(100);
325 332
326 /* execute memory reset script from vbios */ 333 /* execute memory reset script from vbios */
327 if (!bit_table(dev, 'M', &M)) 334 if (!bit_table(dev, 'M', &M))
328 nouveau_bios_init_exec(dev, ROM16(M.data[0])); 335 nouveau_bios_run_init_table(dev, ROM16(M.data[0]), NULL, 0);
329 336
330 /* make sure we're in vblank (hopefully the same one as before), and 337 /* make sure we're in vblank (hopefully the same one as before), and
331 * then re-enable crtc memory access 338 * then re-enable crtc memory access
@@ -333,19 +340,14 @@ nv40_pm_clocks_set(struct drm_device *dev, void *pre_state)
333 for (i = 0; i < 2; i++) { 340 for (i = 0; i < 2; i++) {
334 if (!(crtc_mask & (1 << i))) 341 if (!(crtc_mask & (1 << i)))
335 continue; 342 continue;
336 nv_wait(dev, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000); 343 nv_wait(device, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
337 nv_wr08(dev, 0x0c03c4 + (i * 0x2000), 0x01); 344 nv_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01);
338 nv_wr08(dev, 0x0c03c5 + (i * 0x2000), sr1[i]); 345 nv_wr08(device, 0x0c03c5 + (i * 0x2000), sr1[i]);
339 } 346 }
340 347
341 /* resume engines */ 348 /* resume engines */
342resume: 349resume:
343 nv_wr32(dev, 0x003250, 0x00000001); 350 pfifo->start(pfifo, &flags);
344 nv_mask(dev, 0x003220, 0x00000001, 0x00000001);
345 nv_wr32(dev, 0x003200, 0x00000001);
346 nv_wr32(dev, 0x002500, 0x00000001);
347 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
348
349 kfree(info); 351 kfree(info);
350 return ret; 352 return ret;
351} 353}
@@ -353,8 +355,11 @@ resume:
353int 355int
354nv40_pm_pwm_get(struct drm_device *dev, int line, u32 *divs, u32 *duty) 356nv40_pm_pwm_get(struct drm_device *dev, int line, u32 *divs, u32 *duty)
355{ 357{
358 struct nouveau_drm *drm = nouveau_drm(dev);
359 struct nouveau_device *device = nouveau_dev(dev);
360
356 if (line == 2) { 361 if (line == 2) {
357 u32 reg = nv_rd32(dev, 0x0010f0); 362 u32 reg = nv_rd32(device, 0x0010f0);
358 if (reg & 0x80000000) { 363 if (reg & 0x80000000) {
359 *duty = (reg & 0x7fff0000) >> 16; 364 *duty = (reg & 0x7fff0000) >> 16;
360 *divs = (reg & 0x00007fff); 365 *divs = (reg & 0x00007fff);
@@ -362,14 +367,14 @@ nv40_pm_pwm_get(struct drm_device *dev, int line, u32 *divs, u32 *duty)
362 } 367 }
363 } else 368 } else
364 if (line == 9) { 369 if (line == 9) {
365 u32 reg = nv_rd32(dev, 0x0015f4); 370 u32 reg = nv_rd32(device, 0x0015f4);
366 if (reg & 0x80000000) { 371 if (reg & 0x80000000) {
367 *divs = nv_rd32(dev, 0x0015f8); 372 *divs = nv_rd32(device, 0x0015f8);
368 *duty = (reg & 0x7fffffff); 373 *duty = (reg & 0x7fffffff);
369 return 0; 374 return 0;
370 } 375 }
371 } else { 376 } else {
372 NV_ERROR(dev, "unknown pwm ctrl for gpio %d\n", line); 377 NV_ERROR(drm, "unknown pwm ctrl for gpio %d\n", line);
373 return -ENODEV; 378 return -ENODEV;
374 } 379 }
375 380
@@ -379,14 +384,17 @@ nv40_pm_pwm_get(struct drm_device *dev, int line, u32 *divs, u32 *duty)
379int 384int
380nv40_pm_pwm_set(struct drm_device *dev, int line, u32 divs, u32 duty) 385nv40_pm_pwm_set(struct drm_device *dev, int line, u32 divs, u32 duty)
381{ 386{
387 struct nouveau_device *device = nouveau_dev(dev);
388 struct nouveau_drm *drm = nouveau_drm(dev);
389
382 if (line == 2) { 390 if (line == 2) {
383 nv_wr32(dev, 0x0010f0, 0x80000000 | (duty << 16) | divs); 391 nv_wr32(device, 0x0010f0, 0x80000000 | (duty << 16) | divs);
384 } else 392 } else
385 if (line == 9) { 393 if (line == 9) {
386 nv_wr32(dev, 0x0015f8, divs); 394 nv_wr32(device, 0x0015f8, divs);
387 nv_wr32(dev, 0x0015f4, duty | 0x80000000); 395 nv_wr32(device, 0x0015f4, duty | 0x80000000);
388 } else { 396 } else {
389 NV_ERROR(dev, "unknown pwm ctrl for gpio %d\n", line); 397 NV_ERROR(drm, "unknown pwm ctrl for gpio %d\n", line);
390 return -ENODEV; 398 return -ENODEV;
391 } 399 }
392 400
diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c
index 40042c1bbc6e..a771e9067ebf 100644
--- a/drivers/gpu/drm/nouveau/nv50_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv50_crtc.c
@@ -28,24 +28,27 @@
28#include "drm_mode.h" 28#include "drm_mode.h"
29#include "drm_crtc_helper.h" 29#include "drm_crtc_helper.h"
30 30
31#define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
32#include "nouveau_reg.h" 31#include "nouveau_reg.h"
33#include "nouveau_drv.h" 32#include "nouveau_drm.h"
33#include "nouveau_dma.h"
34#include "nouveau_gem.h"
34#include "nouveau_hw.h" 35#include "nouveau_hw.h"
35#include "nouveau_encoder.h" 36#include "nouveau_encoder.h"
36#include "nouveau_crtc.h" 37#include "nouveau_crtc.h"
37#include "nouveau_fb.h"
38#include "nouveau_connector.h" 38#include "nouveau_connector.h"
39#include "nv50_display.h" 39#include "nv50_display.h"
40 40
41#include <subdev/clock.h>
42
41static void 43static void
42nv50_crtc_lut_load(struct drm_crtc *crtc) 44nv50_crtc_lut_load(struct drm_crtc *crtc)
43{ 45{
46 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
44 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 47 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
45 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo); 48 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
46 int i; 49 int i;
47 50
48 NV_DEBUG_KMS(crtc->dev, "\n"); 51 NV_DEBUG(drm, "\n");
49 52
50 for (i = 0; i < 256; i++) { 53 for (i = 0; i < 256; i++) {
51 writew(nv_crtc->lut.r[i] >> 2, lut + 8*i + 0); 54 writew(nv_crtc->lut.r[i] >> 2, lut + 8*i + 0);
@@ -64,25 +67,25 @@ int
64nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked) 67nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked)
65{ 68{
66 struct drm_device *dev = nv_crtc->base.dev; 69 struct drm_device *dev = nv_crtc->base.dev;
67 struct drm_nouveau_private *dev_priv = dev->dev_private; 70 struct nouveau_drm *drm = nouveau_drm(dev);
68 struct nouveau_channel *evo = nv50_display(dev)->master; 71 struct nouveau_channel *evo = nv50_display(dev)->master;
69 int index = nv_crtc->index, ret; 72 int index = nv_crtc->index, ret;
70 73
71 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); 74 NV_DEBUG(drm, "index %d\n", nv_crtc->index);
72 NV_DEBUG_KMS(dev, "%s\n", blanked ? "blanked" : "unblanked"); 75 NV_DEBUG(drm, "%s\n", blanked ? "blanked" : "unblanked");
73 76
74 if (blanked) { 77 if (blanked) {
75 nv_crtc->cursor.hide(nv_crtc, false); 78 nv_crtc->cursor.hide(nv_crtc, false);
76 79
77 ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 7 : 5); 80 ret = RING_SPACE(evo, nv_device(drm->device)->chipset != 0x50 ? 7 : 5);
78 if (ret) { 81 if (ret) {
79 NV_ERROR(dev, "no space while blanking crtc\n"); 82 NV_ERROR(drm, "no space while blanking crtc\n");
80 return ret; 83 return ret;
81 } 84 }
82 BEGIN_NV04(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2); 85 BEGIN_NV04(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2);
83 OUT_RING(evo, NV50_EVO_CRTC_CLUT_MODE_BLANK); 86 OUT_RING(evo, NV50_EVO_CRTC_CLUT_MODE_BLANK);
84 OUT_RING(evo, 0); 87 OUT_RING(evo, 0);
85 if (dev_priv->chipset != 0x50) { 88 if (nv_device(drm->device)->chipset != 0x50) {
86 BEGIN_NV04(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1); 89 BEGIN_NV04(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1);
87 OUT_RING(evo, NV84_EVO_CRTC_CLUT_DMA_HANDLE_NONE); 90 OUT_RING(evo, NV84_EVO_CRTC_CLUT_DMA_HANDLE_NONE);
88 } 91 }
@@ -95,9 +98,9 @@ nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked)
95 else 98 else
96 nv_crtc->cursor.hide(nv_crtc, false); 99 nv_crtc->cursor.hide(nv_crtc, false);
97 100
98 ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 10 : 8); 101 ret = RING_SPACE(evo, nv_device(drm->device)->chipset != 0x50 ? 10 : 8);
99 if (ret) { 102 if (ret) {
100 NV_ERROR(dev, "no space while unblanking crtc\n"); 103 NV_ERROR(drm, "no space while unblanking crtc\n");
101 return ret; 104 return ret;
102 } 105 }
103 BEGIN_NV04(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2); 106 BEGIN_NV04(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2);
@@ -105,7 +108,7 @@ nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked)
105 NV50_EVO_CRTC_CLUT_MODE_OFF : 108 NV50_EVO_CRTC_CLUT_MODE_OFF :
106 NV50_EVO_CRTC_CLUT_MODE_ON); 109 NV50_EVO_CRTC_CLUT_MODE_ON);
107 OUT_RING(evo, nv_crtc->lut.nvbo->bo.offset >> 8); 110 OUT_RING(evo, nv_crtc->lut.nvbo->bo.offset >> 8);
108 if (dev_priv->chipset != 0x50) { 111 if (nv_device(drm->device)->chipset != 0x50) {
109 BEGIN_NV04(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1); 112 BEGIN_NV04(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1);
110 OUT_RING(evo, NvEvoVRAM); 113 OUT_RING(evo, NvEvoVRAM);
111 } 114 }
@@ -114,7 +117,7 @@ nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked)
114 OUT_RING(evo, nv_crtc->fb.offset >> 8); 117 OUT_RING(evo, nv_crtc->fb.offset >> 8);
115 OUT_RING(evo, 0); 118 OUT_RING(evo, 0);
116 BEGIN_NV04(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1); 119 BEGIN_NV04(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1);
117 if (dev_priv->chipset != 0x50) 120 if (nv_device(drm->device)->chipset != 0x50)
118 if (nv_crtc->fb.tile_flags == 0x7a00 || 121 if (nv_crtc->fb.tile_flags == 0x7a00 ||
119 nv_crtc->fb.tile_flags == 0xfe00) 122 nv_crtc->fb.tile_flags == 0xfe00)
120 OUT_RING(evo, NvEvoFB32); 123 OUT_RING(evo, NvEvoFB32);
@@ -174,17 +177,18 @@ static int
174nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update) 177nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
175{ 178{
176 struct drm_device *dev = nv_crtc->base.dev; 179 struct drm_device *dev = nv_crtc->base.dev;
180 struct nouveau_drm *drm = nouveau_drm(dev);
177 struct nouveau_channel *evo = nv50_display(dev)->master; 181 struct nouveau_channel *evo = nv50_display(dev)->master;
178 int ret; 182 int ret;
179 int adj; 183 int adj;
180 u32 hue, vib; 184 u32 hue, vib;
181 185
182 NV_DEBUG_KMS(dev, "vibrance = %i, hue = %i\n", 186 NV_DEBUG(drm, "vibrance = %i, hue = %i\n",
183 nv_crtc->color_vibrance, nv_crtc->vibrant_hue); 187 nv_crtc->color_vibrance, nv_crtc->vibrant_hue);
184 188
185 ret = RING_SPACE(evo, 2 + (update ? 2 : 0)); 189 ret = RING_SPACE(evo, 2 + (update ? 2 : 0));
186 if (ret) { 190 if (ret) {
187 NV_ERROR(dev, "no space while setting color vibrance\n"); 191 NV_ERROR(drm, "no space while setting color vibrance\n");
188 return ret; 192 return ret;
189 } 193 }
190 194
@@ -229,17 +233,18 @@ nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
229 struct nouveau_connector *nv_connector; 233 struct nouveau_connector *nv_connector;
230 struct drm_crtc *crtc = &nv_crtc->base; 234 struct drm_crtc *crtc = &nv_crtc->base;
231 struct drm_device *dev = crtc->dev; 235 struct drm_device *dev = crtc->dev;
236 struct nouveau_drm *drm = nouveau_drm(dev);
232 struct nouveau_channel *evo = nv50_display(dev)->master; 237 struct nouveau_channel *evo = nv50_display(dev)->master;
233 struct drm_display_mode *umode = &crtc->mode; 238 struct drm_display_mode *umode = &crtc->mode;
234 struct drm_display_mode *omode; 239 struct drm_display_mode *omode;
235 int scaling_mode, ret; 240 int scaling_mode, ret;
236 u32 ctrl = 0, oX, oY; 241 u32 ctrl = 0, oX, oY;
237 242
238 NV_DEBUG_KMS(dev, "\n"); 243 NV_DEBUG(drm, "\n");
239 244
240 nv_connector = nouveau_crtc_connector_get(nv_crtc); 245 nv_connector = nouveau_crtc_connector_get(nv_crtc);
241 if (!nv_connector || !nv_connector->native_mode) { 246 if (!nv_connector || !nv_connector->native_mode) {
242 NV_ERROR(dev, "no native mode, forcing panel scaling\n"); 247 NV_ERROR(drm, "no native mode, forcing panel scaling\n");
243 scaling_mode = DRM_MODE_SCALE_NONE; 248 scaling_mode = DRM_MODE_SCALE_NONE;
244 } else { 249 } else {
245 scaling_mode = nv_connector->scaling_mode; 250 scaling_mode = nv_connector->scaling_mode;
@@ -329,15 +334,19 @@ nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
329int 334int
330nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk) 335nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
331{ 336{
332 return setPLL(dev, PLL_VPLL0 + head, pclk); 337 struct nouveau_device *device = nouveau_dev(dev);
338 struct nouveau_clock *clk = nouveau_clock(device);
339
340 return clk->pll_set(clk, PLL_VPLL0 + head, pclk);
333} 341}
334 342
335static void 343static void
336nv50_crtc_destroy(struct drm_crtc *crtc) 344nv50_crtc_destroy(struct drm_crtc *crtc)
337{ 345{
338 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 346 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
347 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
339 348
340 NV_DEBUG_KMS(crtc->dev, "\n"); 349 NV_DEBUG(drm, "\n");
341 350
342 nouveau_bo_unmap(nv_crtc->lut.nvbo); 351 nouveau_bo_unmap(nv_crtc->lut.nvbo);
343 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); 352 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
@@ -426,13 +435,15 @@ nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
426static void 435static void
427nv50_crtc_save(struct drm_crtc *crtc) 436nv50_crtc_save(struct drm_crtc *crtc)
428{ 437{
429 NV_ERROR(crtc->dev, "!!\n"); 438 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
439 NV_ERROR(drm, "!!\n");
430} 440}
431 441
432static void 442static void
433nv50_crtc_restore(struct drm_crtc *crtc) 443nv50_crtc_restore(struct drm_crtc *crtc)
434{ 444{
435 NV_ERROR(crtc->dev, "!!\n"); 445 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
446 NV_ERROR(drm, "!!\n");
436} 447}
437 448
438static const struct drm_crtc_funcs nv50_crtc_funcs = { 449static const struct drm_crtc_funcs nv50_crtc_funcs = {
@@ -456,8 +467,9 @@ nv50_crtc_prepare(struct drm_crtc *crtc)
456{ 467{
457 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 468 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
458 struct drm_device *dev = crtc->dev; 469 struct drm_device *dev = crtc->dev;
470 struct nouveau_drm *drm = nouveau_drm(dev);
459 471
460 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); 472 NV_DEBUG(drm, "index %d\n", nv_crtc->index);
461 473
462 nv50_display_flip_stop(crtc); 474 nv50_display_flip_stop(crtc);
463 drm_vblank_pre_modeset(dev, nv_crtc->index); 475 drm_vblank_pre_modeset(dev, nv_crtc->index);
@@ -468,9 +480,10 @@ static void
468nv50_crtc_commit(struct drm_crtc *crtc) 480nv50_crtc_commit(struct drm_crtc *crtc)
469{ 481{
470 struct drm_device *dev = crtc->dev; 482 struct drm_device *dev = crtc->dev;
483 struct nouveau_drm *drm = nouveau_drm(dev);
471 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 484 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
472 485
473 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); 486 NV_DEBUG(drm, "index %d\n", nv_crtc->index);
474 487
475 nv50_crtc_blank(nv_crtc, false); 488 nv50_crtc_blank(nv_crtc, false);
476 drm_vblank_post_modeset(dev, nv_crtc->index); 489 drm_vblank_post_modeset(dev, nv_crtc->index);
@@ -492,17 +505,17 @@ nv50_crtc_do_mode_set_base(struct drm_crtc *crtc,
492{ 505{
493 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 506 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
494 struct drm_device *dev = nv_crtc->base.dev; 507 struct drm_device *dev = nv_crtc->base.dev;
495 struct drm_nouveau_private *dev_priv = dev->dev_private; 508 struct nouveau_drm *drm = nouveau_drm(dev);
496 struct nouveau_channel *evo = nv50_display(dev)->master; 509 struct nouveau_channel *evo = nv50_display(dev)->master;
497 struct drm_framebuffer *drm_fb; 510 struct drm_framebuffer *drm_fb;
498 struct nouveau_framebuffer *fb; 511 struct nouveau_framebuffer *fb;
499 int ret; 512 int ret;
500 513
501 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); 514 NV_DEBUG(drm, "index %d\n", nv_crtc->index);
502 515
503 /* no fb bound */ 516 /* no fb bound */
504 if (!atomic && !crtc->fb) { 517 if (!atomic && !crtc->fb) {
505 NV_DEBUG_KMS(dev, "No FB bound\n"); 518 NV_DEBUG(drm, "No FB bound\n");
506 return 0; 519 return 0;
507 } 520 }
508 521
@@ -532,7 +545,7 @@ nv50_crtc_do_mode_set_base(struct drm_crtc *crtc,
532 nv_crtc->fb.offset = fb->nvbo->bo.offset; 545 nv_crtc->fb.offset = fb->nvbo->bo.offset;
533 nv_crtc->fb.tile_flags = nouveau_bo_tile_layout(fb->nvbo); 546 nv_crtc->fb.tile_flags = nouveau_bo_tile_layout(fb->nvbo);
534 nv_crtc->fb.cpp = drm_fb->bits_per_pixel / 8; 547 nv_crtc->fb.cpp = drm_fb->bits_per_pixel / 8;
535 if (!nv_crtc->fb.blanked && dev_priv->chipset != 0x50) { 548 if (!nv_crtc->fb.blanked && nv_device(drm->device)->chipset != 0x50) {
536 ret = RING_SPACE(evo, 2); 549 ret = RING_SPACE(evo, 2);
537 if (ret) 550 if (ret)
538 return ret; 551 return ret;
@@ -690,10 +703,11 @@ static const struct drm_crtc_helper_funcs nv50_crtc_helper_funcs = {
690int 703int
691nv50_crtc_create(struct drm_device *dev, int index) 704nv50_crtc_create(struct drm_device *dev, int index)
692{ 705{
706 struct nouveau_drm *drm = nouveau_drm(dev);
693 struct nouveau_crtc *nv_crtc = NULL; 707 struct nouveau_crtc *nv_crtc = NULL;
694 int ret, i; 708 int ret, i;
695 709
696 NV_DEBUG_KMS(dev, "\n"); 710 NV_DEBUG(drm, "\n");
697 711
698 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); 712 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
699 if (!nv_crtc) 713 if (!nv_crtc)
diff --git a/drivers/gpu/drm/nouveau/nv50_cursor.c b/drivers/gpu/drm/nouveau/nv50_cursor.c
index af4ec7bf3670..ba047e9251b3 100644
--- a/drivers/gpu/drm/nouveau/nv50_cursor.c
+++ b/drivers/gpu/drm/nouveau/nv50_cursor.c
@@ -27,9 +27,8 @@
27#include "drmP.h" 27#include "drmP.h"
28#include "drm_mode.h" 28#include "drm_mode.h"
29 29
30#define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO) 30#include "nouveau_drm.h"
31#include "nouveau_reg.h" 31#include "nouveau_dma.h"
32#include "nouveau_drv.h"
33#include "nouveau_crtc.h" 32#include "nouveau_crtc.h"
34#include "nv50_display.h" 33#include "nv50_display.h"
35 34
@@ -37,22 +36,22 @@ static void
37nv50_cursor_show(struct nouveau_crtc *nv_crtc, bool update) 36nv50_cursor_show(struct nouveau_crtc *nv_crtc, bool update)
38{ 37{
39 struct drm_device *dev = nv_crtc->base.dev; 38 struct drm_device *dev = nv_crtc->base.dev;
40 struct drm_nouveau_private *dev_priv = dev->dev_private; 39 struct nouveau_drm *drm = nouveau_drm(dev);
41 struct nouveau_channel *evo = nv50_display(dev)->master; 40 struct nouveau_channel *evo = nv50_display(dev)->master;
42 int ret; 41 int ret;
43 42
44 NV_DEBUG_KMS(dev, "\n"); 43 NV_DEBUG(drm, "\n");
45 44
46 if (update && nv_crtc->cursor.visible) 45 if (update && nv_crtc->cursor.visible)
47 return; 46 return;
48 47
49 ret = RING_SPACE(evo, (dev_priv->chipset != 0x50 ? 5 : 3) + update * 2); 48 ret = RING_SPACE(evo, (nv_device(drm->device)->chipset != 0x50 ? 5 : 3) + update * 2);
50 if (ret) { 49 if (ret) {
51 NV_ERROR(dev, "no space while unhiding cursor\n"); 50 NV_ERROR(drm, "no space while unhiding cursor\n");
52 return; 51 return;
53 } 52 }
54 53
55 if (dev_priv->chipset != 0x50) { 54 if (nv_device(drm->device)->chipset != 0x50) {
56 BEGIN_NV04(evo, 0, NV84_EVO_CRTC(nv_crtc->index, CURSOR_DMA), 1); 55 BEGIN_NV04(evo, 0, NV84_EVO_CRTC(nv_crtc->index, CURSOR_DMA), 1);
57 OUT_RING(evo, NvEvoVRAM); 56 OUT_RING(evo, NvEvoVRAM);
58 } 57 }
@@ -72,24 +71,24 @@ static void
72nv50_cursor_hide(struct nouveau_crtc *nv_crtc, bool update) 71nv50_cursor_hide(struct nouveau_crtc *nv_crtc, bool update)
73{ 72{
74 struct drm_device *dev = nv_crtc->base.dev; 73 struct drm_device *dev = nv_crtc->base.dev;
75 struct drm_nouveau_private *dev_priv = dev->dev_private; 74 struct nouveau_drm *drm = nouveau_drm(dev);
76 struct nouveau_channel *evo = nv50_display(dev)->master; 75 struct nouveau_channel *evo = nv50_display(dev)->master;
77 int ret; 76 int ret;
78 77
79 NV_DEBUG_KMS(dev, "\n"); 78 NV_DEBUG(drm, "\n");
80 79
81 if (update && !nv_crtc->cursor.visible) 80 if (update && !nv_crtc->cursor.visible)
82 return; 81 return;
83 82
84 ret = RING_SPACE(evo, (dev_priv->chipset != 0x50 ? 5 : 3) + update * 2); 83 ret = RING_SPACE(evo, (nv_device(drm->device)->chipset != 0x50 ? 5 : 3) + update * 2);
85 if (ret) { 84 if (ret) {
86 NV_ERROR(dev, "no space while hiding cursor\n"); 85 NV_ERROR(drm, "no space while hiding cursor\n");
87 return; 86 return;
88 } 87 }
89 BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CURSOR_CTRL), 2); 88 BEGIN_NV04(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CURSOR_CTRL), 2);
90 OUT_RING(evo, NV50_EVO_CRTC_CURSOR_CTRL_HIDE); 89 OUT_RING(evo, NV50_EVO_CRTC_CURSOR_CTRL_HIDE);
91 OUT_RING(evo, 0); 90 OUT_RING(evo, 0);
92 if (dev_priv->chipset != 0x50) { 91 if (nv_device(drm->device)->chipset != 0x50) {
93 BEGIN_NV04(evo, 0, NV84_EVO_CRTC(nv_crtc->index, CURSOR_DMA), 1); 92 BEGIN_NV04(evo, 0, NV84_EVO_CRTC(nv_crtc->index, CURSOR_DMA), 1);
94 OUT_RING(evo, NV84_EVO_CRTC_CURSOR_DMA_HANDLE_NONE); 93 OUT_RING(evo, NV84_EVO_CRTC_CURSOR_DMA_HANDLE_NONE);
95 } 94 }
@@ -105,19 +104,18 @@ nv50_cursor_hide(struct nouveau_crtc *nv_crtc, bool update)
105static void 104static void
106nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y) 105nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
107{ 106{
108 struct drm_device *dev = nv_crtc->base.dev; 107 struct nouveau_device *device = nouveau_dev(nv_crtc->base.dev);
109 108
110 nv_crtc->cursor_saved_x = x; nv_crtc->cursor_saved_y = y; 109 nv_crtc->cursor_saved_x = x; nv_crtc->cursor_saved_y = y;
111 nv_wr32(dev, NV50_PDISPLAY_CURSOR_USER_POS(nv_crtc->index), 110 nv_wr32(device, NV50_PDISPLAY_CURSOR_USER_POS(nv_crtc->index),
112 ((y & 0xFFFF) << 16) | (x & 0xFFFF)); 111 ((y & 0xFFFF) << 16) | (x & 0xFFFF));
113 /* Needed to make the cursor move. */ 112 /* Needed to make the cursor move. */
114 nv_wr32(dev, NV50_PDISPLAY_CURSOR_USER_POS_CTRL(nv_crtc->index), 0); 113 nv_wr32(device, NV50_PDISPLAY_CURSOR_USER_POS_CTRL(nv_crtc->index), 0);
115} 114}
116 115
117static void 116static void
118nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset) 117nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
119{ 118{
120 NV_DEBUG_KMS(nv_crtc->base.dev, "\n");
121 if (offset == nv_crtc->cursor.offset) 119 if (offset == nv_crtc->cursor.offset)
122 return; 120 return;
123 121
diff --git a/drivers/gpu/drm/nouveau/nv50_dac.c b/drivers/gpu/drm/nouveau/nv50_dac.c
index dd3b8f2a3960..4a01b49d5ece 100644
--- a/drivers/gpu/drm/nouveau/nv50_dac.c
+++ b/drivers/gpu/drm/nouveau/nv50_dac.c
@@ -29,18 +29,21 @@
29 29
30#define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO) 30#define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
31#include "nouveau_reg.h" 31#include "nouveau_reg.h"
32#include "nouveau_drv.h" 32#include "nouveau_drm.h"
33#include "nouveau_dma.h" 33#include "nouveau_dma.h"
34#include "nouveau_encoder.h" 34#include "nouveau_encoder.h"
35#include "nouveau_connector.h" 35#include "nouveau_connector.h"
36#include "nouveau_crtc.h" 36#include "nouveau_crtc.h"
37#include "nv50_display.h" 37#include "nv50_display.h"
38 38
39#include <subdev/timer.h>
40
39static void 41static void
40nv50_dac_disconnect(struct drm_encoder *encoder) 42nv50_dac_disconnect(struct drm_encoder *encoder)
41{ 43{
42 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 44 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
43 struct drm_device *dev = encoder->dev; 45 struct drm_device *dev = encoder->dev;
46 struct nouveau_drm *drm = nouveau_drm(dev);
44 struct nouveau_channel *evo = nv50_display(dev)->master; 47 struct nouveau_channel *evo = nv50_display(dev)->master;
45 int ret; 48 int ret;
46 49
@@ -48,11 +51,11 @@ nv50_dac_disconnect(struct drm_encoder *encoder)
48 return; 51 return;
49 nv50_crtc_blank(nouveau_crtc(nv_encoder->crtc), true); 52 nv50_crtc_blank(nouveau_crtc(nv_encoder->crtc), true);
50 53
51 NV_DEBUG_KMS(dev, "Disconnecting DAC %d\n", nv_encoder->or); 54 NV_DEBUG(drm, "Disconnecting DAC %d\n", nv_encoder->or);
52 55
53 ret = RING_SPACE(evo, 4); 56 ret = RING_SPACE(evo, 4);
54 if (ret) { 57 if (ret) {
55 NV_ERROR(dev, "no space while disconnecting DAC\n"); 58 NV_ERROR(drm, "no space while disconnecting DAC\n");
56 return; 59 return;
57 } 60 }
58 BEGIN_NV04(evo, 0, NV50_EVO_DAC(nv_encoder->or, MODE_CTRL), 1); 61 BEGIN_NV04(evo, 0, NV50_EVO_DAC(nv_encoder->or, MODE_CTRL), 1);
@@ -67,43 +70,43 @@ static enum drm_connector_status
67nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 70nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
68{ 71{
69 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 72 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
70 struct drm_device *dev = encoder->dev; 73 struct nouveau_device *device = nouveau_dev(encoder->dev);
71 struct drm_nouveau_private *dev_priv = dev->dev_private; 74 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
72 enum drm_connector_status status = connector_status_disconnected; 75 enum drm_connector_status status = connector_status_disconnected;
73 uint32_t dpms_state, load_pattern, load_state; 76 uint32_t dpms_state, load_pattern, load_state;
74 int or = nv_encoder->or; 77 int or = nv_encoder->or;
75 78
76 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(or), 0x00000001); 79 nv_wr32(device, NV50_PDISPLAY_DAC_CLK_CTRL1(or), 0x00000001);
77 dpms_state = nv_rd32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(or)); 80 dpms_state = nv_rd32(device, NV50_PDISPLAY_DAC_DPMS_CTRL(or));
78 81
79 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(or), 82 nv_wr32(device, NV50_PDISPLAY_DAC_DPMS_CTRL(or),
80 0x00150000 | NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING); 83 0x00150000 | NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
81 if (!nv_wait(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(or), 84 if (!nv_wait(device, NV50_PDISPLAY_DAC_DPMS_CTRL(or),
82 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING, 0)) { 85 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING, 0)) {
83 NV_ERROR(dev, "timeout: DAC_DPMS_CTRL_PENDING(%d) == 0\n", or); 86 NV_ERROR(drm, "timeout: DAC_DPMS_CTRL_PENDING(%d) == 0\n", or);
84 NV_ERROR(dev, "DAC_DPMS_CTRL(%d) = 0x%08x\n", or, 87 NV_ERROR(drm, "DAC_DPMS_CTRL(%d) = 0x%08x\n", or,
85 nv_rd32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(or))); 88 nv_rd32(device, NV50_PDISPLAY_DAC_DPMS_CTRL(or)));
86 return status; 89 return status;
87 } 90 }
88 91
89 /* Use bios provided value if possible. */ 92 /* Use bios provided value if possible. */
90 if (dev_priv->vbios.dactestval) { 93 if (drm->vbios.dactestval) {
91 load_pattern = dev_priv->vbios.dactestval; 94 load_pattern = drm->vbios.dactestval;
92 NV_DEBUG_KMS(dev, "Using bios provided load_pattern of %d\n", 95 NV_DEBUG(drm, "Using bios provided load_pattern of %d\n",
93 load_pattern); 96 load_pattern);
94 } else { 97 } else {
95 load_pattern = 340; 98 load_pattern = 340;
96 NV_DEBUG_KMS(dev, "Using default load_pattern of %d\n", 99 NV_DEBUG(drm, "Using default load_pattern of %d\n",
97 load_pattern); 100 load_pattern);
98 } 101 }
99 102
100 nv_wr32(dev, NV50_PDISPLAY_DAC_LOAD_CTRL(or), 103 nv_wr32(device, NV50_PDISPLAY_DAC_LOAD_CTRL(or),
101 NV50_PDISPLAY_DAC_LOAD_CTRL_ACTIVE | load_pattern); 104 NV50_PDISPLAY_DAC_LOAD_CTRL_ACTIVE | load_pattern);
102 mdelay(45); /* give it some time to process */ 105 mdelay(45); /* give it some time to process */
103 load_state = nv_rd32(dev, NV50_PDISPLAY_DAC_LOAD_CTRL(or)); 106 load_state = nv_rd32(device, NV50_PDISPLAY_DAC_LOAD_CTRL(or));
104 107
105 nv_wr32(dev, NV50_PDISPLAY_DAC_LOAD_CTRL(or), 0); 108 nv_wr32(device, NV50_PDISPLAY_DAC_LOAD_CTRL(or), 0);
106 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(or), dpms_state | 109 nv_wr32(device, NV50_PDISPLAY_DAC_DPMS_CTRL(or), dpms_state |
107 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING); 110 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
108 111
109 if ((load_state & NV50_PDISPLAY_DAC_LOAD_CTRL_PRESENT) == 112 if ((load_state & NV50_PDISPLAY_DAC_LOAD_CTRL_PRESENT) ==
@@ -111,9 +114,9 @@ nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
111 status = connector_status_connected; 114 status = connector_status_connected;
112 115
113 if (status == connector_status_connected) 116 if (status == connector_status_connected)
114 NV_DEBUG_KMS(dev, "Load was detected on output with or %d\n", or); 117 NV_DEBUG(drm, "Load was detected on output with or %d\n", or);
115 else 118 else
116 NV_DEBUG_KMS(dev, "Load was not detected on output with or %d\n", or); 119 NV_DEBUG(drm, "Load was not detected on output with or %d\n", or);
117 120
118 return status; 121 return status;
119} 122}
@@ -121,23 +124,24 @@ nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
121static void 124static void
122nv50_dac_dpms(struct drm_encoder *encoder, int mode) 125nv50_dac_dpms(struct drm_encoder *encoder, int mode)
123{ 126{
124 struct drm_device *dev = encoder->dev; 127 struct nouveau_device *device = nouveau_dev(encoder->dev);
128 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
125 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 129 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
126 uint32_t val; 130 uint32_t val;
127 int or = nv_encoder->or; 131 int or = nv_encoder->or;
128 132
129 NV_DEBUG_KMS(dev, "or %d mode %d\n", or, mode); 133 NV_DEBUG(drm, "or %d mode %d\n", or, mode);
130 134
131 /* wait for it to be done */ 135 /* wait for it to be done */
132 if (!nv_wait(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(or), 136 if (!nv_wait(device, NV50_PDISPLAY_DAC_DPMS_CTRL(or),
133 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING, 0)) { 137 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING, 0)) {
134 NV_ERROR(dev, "timeout: DAC_DPMS_CTRL_PENDING(%d) == 0\n", or); 138 NV_ERROR(drm, "timeout: DAC_DPMS_CTRL_PENDING(%d) == 0\n", or);
135 NV_ERROR(dev, "DAC_DPMS_CTRL(%d) = 0x%08x\n", or, 139 NV_ERROR(drm, "DAC_DPMS_CTRL(%d) = 0x%08x\n", or,
136 nv_rd32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(or))); 140 nv_rd32(device, NV50_PDISPLAY_DAC_DPMS_CTRL(or)));
137 return; 141 return;
138 } 142 }
139 143
140 val = nv_rd32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(or)) & ~0x7F; 144 val = nv_rd32(device, NV50_PDISPLAY_DAC_DPMS_CTRL(or)) & ~0x7F;
141 145
142 if (mode != DRM_MODE_DPMS_ON) 146 if (mode != DRM_MODE_DPMS_ON)
143 val |= NV50_PDISPLAY_DAC_DPMS_CTRL_BLANKED; 147 val |= NV50_PDISPLAY_DAC_DPMS_CTRL_BLANKED;
@@ -158,20 +162,22 @@ nv50_dac_dpms(struct drm_encoder *encoder, int mode)
158 break; 162 break;
159 } 163 }
160 164
161 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(or), val | 165 nv_wr32(device, NV50_PDISPLAY_DAC_DPMS_CTRL(or), val |
162 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING); 166 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
163} 167}
164 168
165static void 169static void
166nv50_dac_save(struct drm_encoder *encoder) 170nv50_dac_save(struct drm_encoder *encoder)
167{ 171{
168 NV_ERROR(encoder->dev, "!!\n"); 172 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
173 NV_ERROR(drm, "!!\n");
169} 174}
170 175
171static void 176static void
172nv50_dac_restore(struct drm_encoder *encoder) 177nv50_dac_restore(struct drm_encoder *encoder)
173{ 178{
174 NV_ERROR(encoder->dev, "!!\n"); 179 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
180 NV_ERROR(drm, "!!\n");
175} 181}
176 182
177static bool 183static bool
@@ -179,14 +185,15 @@ nv50_dac_mode_fixup(struct drm_encoder *encoder,
179 const struct drm_display_mode *mode, 185 const struct drm_display_mode *mode,
180 struct drm_display_mode *adjusted_mode) 186 struct drm_display_mode *adjusted_mode)
181{ 187{
188 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
182 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 189 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
183 struct nouveau_connector *connector; 190 struct nouveau_connector *connector;
184 191
185 NV_DEBUG_KMS(encoder->dev, "or %d\n", nv_encoder->or); 192 NV_DEBUG(drm, "or %d\n", nv_encoder->or);
186 193
187 connector = nouveau_encoder_connector_get(nv_encoder); 194 connector = nouveau_encoder_connector_get(nv_encoder);
188 if (!connector) { 195 if (!connector) {
189 NV_ERROR(encoder->dev, "Encoder has no connector\n"); 196 NV_ERROR(drm, "Encoder has no connector\n");
190 return false; 197 return false;
191 } 198 }
192 199
@@ -207,13 +214,14 @@ nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
207 struct drm_display_mode *adjusted_mode) 214 struct drm_display_mode *adjusted_mode)
208{ 215{
209 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 216 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
217 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
210 struct drm_device *dev = encoder->dev; 218 struct drm_device *dev = encoder->dev;
211 struct nouveau_channel *evo = nv50_display(dev)->master; 219 struct nouveau_channel *evo = nv50_display(dev)->master;
212 struct nouveau_crtc *crtc = nouveau_crtc(encoder->crtc); 220 struct nouveau_crtc *crtc = nouveau_crtc(encoder->crtc);
213 uint32_t mode_ctl = 0, mode_ctl2 = 0; 221 uint32_t mode_ctl = 0, mode_ctl2 = 0;
214 int ret; 222 int ret;
215 223
216 NV_DEBUG_KMS(dev, "or %d type %d crtc %d\n", 224 NV_DEBUG(drm, "or %d type %d crtc %d\n",
217 nv_encoder->or, nv_encoder->dcb->type, crtc->index); 225 nv_encoder->or, nv_encoder->dcb->type, crtc->index);
218 226
219 nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON); 227 nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
@@ -238,7 +246,7 @@ nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
238 246
239 ret = RING_SPACE(evo, 3); 247 ret = RING_SPACE(evo, 3);
240 if (ret) { 248 if (ret) {
241 NV_ERROR(dev, "no space while connecting DAC\n"); 249 NV_ERROR(drm, "no space while connecting DAC\n");
242 return; 250 return;
243 } 251 }
244 BEGIN_NV04(evo, 0, NV50_EVO_DAC(nv_encoder->or, MODE_CTRL), 2); 252 BEGIN_NV04(evo, 0, NV50_EVO_DAC(nv_encoder->or, MODE_CTRL), 2);
@@ -271,11 +279,12 @@ static void
271nv50_dac_destroy(struct drm_encoder *encoder) 279nv50_dac_destroy(struct drm_encoder *encoder)
272{ 280{
273 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 281 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
282 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
274 283
275 if (!encoder) 284 if (!encoder)
276 return; 285 return;
277 286
278 NV_DEBUG_KMS(encoder->dev, "\n"); 287 NV_DEBUG(drm, "\n");
279 288
280 drm_encoder_cleanup(encoder); 289 drm_encoder_cleanup(encoder);
281 kfree(nv_encoder); 290 kfree(nv_encoder);
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index ae72f7656106..787ddc9f314c 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -24,27 +24,30 @@
24 * 24 *
25 */ 25 */
26 26
27#define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO) 27#include "nouveau_drm.h"
28#include "nouveau_dma.h"
29
28#include "nv50_display.h" 30#include "nv50_display.h"
29#include "nouveau_crtc.h" 31#include "nouveau_crtc.h"
30#include "nouveau_encoder.h" 32#include "nouveau_encoder.h"
31#include "nouveau_connector.h" 33#include "nouveau_connector.h"
32#include "nouveau_fb.h"
33#include "nouveau_fbcon.h" 34#include "nouveau_fbcon.h"
34#include "drm_crtc_helper.h" 35#include "drm_crtc_helper.h"
35#include "nouveau_fence.h" 36#include "nouveau_fence.h"
36 37
37static void nv50_display_isr(struct drm_device *); 38#include <core/gpuobj.h>
39#include <subdev/timer.h>
40
38static void nv50_display_bh(unsigned long); 41static void nv50_display_bh(unsigned long);
39 42
40static inline int 43static inline int
41nv50_sor_nr(struct drm_device *dev) 44nv50_sor_nr(struct drm_device *dev)
42{ 45{
43 struct drm_nouveau_private *dev_priv = dev->dev_private; 46 struct nouveau_device *device = nouveau_dev(dev);
44 47
45 if (dev_priv->chipset < 0x90 || 48 if (device->chipset < 0x90 ||
46 dev_priv->chipset == 0x92 || 49 device->chipset == 0x92 ||
47 dev_priv->chipset == 0xa0) 50 device->chipset == 0xa0)
48 return 2; 51 return 2;
49 52
50 return 4; 53 return 4;
@@ -53,22 +56,22 @@ nv50_sor_nr(struct drm_device *dev)
53u32 56u32
54nv50_display_active_crtcs(struct drm_device *dev) 57nv50_display_active_crtcs(struct drm_device *dev)
55{ 58{
56 struct drm_nouveau_private *dev_priv = dev->dev_private; 59 struct nouveau_device *device = nouveau_dev(dev);
57 u32 mask = 0; 60 u32 mask = 0;
58 int i; 61 int i;
59 62
60 if (dev_priv->chipset < 0x90 || 63 if (device->chipset < 0x90 ||
61 dev_priv->chipset == 0x92 || 64 device->chipset == 0x92 ||
62 dev_priv->chipset == 0xa0) { 65 device->chipset == 0xa0) {
63 for (i = 0; i < 2; i++) 66 for (i = 0; i < 2; i++)
64 mask |= nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i)); 67 mask |= nv_rd32(device, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
65 } else { 68 } else {
66 for (i = 0; i < 4; i++) 69 for (i = 0; i < 4; i++)
67 mask |= nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i)); 70 mask |= nv_rd32(device, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
68 } 71 }
69 72
70 for (i = 0; i < 3; i++) 73 for (i = 0; i < 3; i++)
71 mask |= nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i)); 74 mask |= nv_rd32(device, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
72 75
73 return mask & 3; 76 return mask & 3;
74} 77}
@@ -89,7 +92,6 @@ nv50_display_sync(struct drm_device *dev)
89{ 92{
90 struct nv50_display *disp = nv50_display(dev); 93 struct nv50_display *disp = nv50_display(dev);
91 struct nouveau_channel *evo = disp->master; 94 struct nouveau_channel *evo = disp->master;
92 u64 start;
93 int ret; 95 int ret;
94 96
95 ret = RING_SPACE(evo, 6); 97 ret = RING_SPACE(evo, 6);
@@ -104,11 +106,8 @@ nv50_display_sync(struct drm_device *dev)
104 nv_wo32(disp->ramin, 0x2000, 0x00000000); 106 nv_wo32(disp->ramin, 0x2000, 0x00000000);
105 FIRE_RING (evo); 107 FIRE_RING (evo);
106 108
107 start = nv_timer_read(dev); 109 if (nv_wait_ne(disp->ramin, 0x2000, 0xffffffff, 0x00000000))
108 do { 110 return 0;
109 if (nv_ro32(disp->ramin, 0x2000))
110 return 0;
111 } while (nv_timer_read(dev) - start < 2000000000ULL);
112 } 111 }
113 112
114 return 0; 113 return 0;
@@ -117,13 +116,15 @@ nv50_display_sync(struct drm_device *dev)
117int 116int
118nv50_display_init(struct drm_device *dev) 117nv50_display_init(struct drm_device *dev)
119{ 118{
119 struct nouveau_drm *drm = nouveau_drm(dev);
120 struct nouveau_device *device = nouveau_dev(dev);
120 struct nouveau_channel *evo; 121 struct nouveau_channel *evo;
121 int ret, i; 122 int ret, i;
122 u32 val; 123 u32 val;
123 124
124 NV_DEBUG_KMS(dev, "\n"); 125 NV_DEBUG(drm, "\n");
125 126
126 nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004)); 127 nv_wr32(device, 0x00610184, nv_rd32(device, 0x00614004));
127 128
128 /* 129 /*
129 * I think the 0x006101XX range is some kind of main control area 130 * I think the 0x006101XX range is some kind of main control area
@@ -131,82 +132,82 @@ nv50_display_init(struct drm_device *dev)
131 */ 132 */
132 /* CRTC? */ 133 /* CRTC? */
133 for (i = 0; i < 2; i++) { 134 for (i = 0; i < 2; i++) {
134 val = nv_rd32(dev, 0x00616100 + (i * 0x800)); 135 val = nv_rd32(device, 0x00616100 + (i * 0x800));
135 nv_wr32(dev, 0x00610190 + (i * 0x10), val); 136 nv_wr32(device, 0x00610190 + (i * 0x10), val);
136 val = nv_rd32(dev, 0x00616104 + (i * 0x800)); 137 val = nv_rd32(device, 0x00616104 + (i * 0x800));
137 nv_wr32(dev, 0x00610194 + (i * 0x10), val); 138 nv_wr32(device, 0x00610194 + (i * 0x10), val);
138 val = nv_rd32(dev, 0x00616108 + (i * 0x800)); 139 val = nv_rd32(device, 0x00616108 + (i * 0x800));
139 nv_wr32(dev, 0x00610198 + (i * 0x10), val); 140 nv_wr32(device, 0x00610198 + (i * 0x10), val);
140 val = nv_rd32(dev, 0x0061610c + (i * 0x800)); 141 val = nv_rd32(device, 0x0061610c + (i * 0x800));
141 nv_wr32(dev, 0x0061019c + (i * 0x10), val); 142 nv_wr32(device, 0x0061019c + (i * 0x10), val);
142 } 143 }
143 144
144 /* DAC */ 145 /* DAC */
145 for (i = 0; i < 3; i++) { 146 for (i = 0; i < 3; i++) {
146 val = nv_rd32(dev, 0x0061a000 + (i * 0x800)); 147 val = nv_rd32(device, 0x0061a000 + (i * 0x800));
147 nv_wr32(dev, 0x006101d0 + (i * 0x04), val); 148 nv_wr32(device, 0x006101d0 + (i * 0x04), val);
148 } 149 }
149 150
150 /* SOR */ 151 /* SOR */
151 for (i = 0; i < nv50_sor_nr(dev); i++) { 152 for (i = 0; i < nv50_sor_nr(dev); i++) {
152 val = nv_rd32(dev, 0x0061c000 + (i * 0x800)); 153 val = nv_rd32(device, 0x0061c000 + (i * 0x800));
153 nv_wr32(dev, 0x006101e0 + (i * 0x04), val); 154 nv_wr32(device, 0x006101e0 + (i * 0x04), val);
154 } 155 }
155 156
156 /* EXT */ 157 /* EXT */
157 for (i = 0; i < 3; i++) { 158 for (i = 0; i < 3; i++) {
158 val = nv_rd32(dev, 0x0061e000 + (i * 0x800)); 159 val = nv_rd32(device, 0x0061e000 + (i * 0x800));
159 nv_wr32(dev, 0x006101f0 + (i * 0x04), val); 160 nv_wr32(device, 0x006101f0 + (i * 0x04), val);
160 } 161 }
161 162
162 for (i = 0; i < 3; i++) { 163 for (i = 0; i < 3; i++) {
163 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 | 164 nv_wr32(device, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
164 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING); 165 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
165 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001); 166 nv_wr32(device, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
166 } 167 }
167 168
168 /* The precise purpose is unknown, i suspect it has something to do 169 /* The precise purpose is unknown, i suspect it has something to do
169 * with text mode. 170 * with text mode.
170 */ 171 */
171 if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) { 172 if (nv_rd32(device, NV50_PDISPLAY_INTR_1) & 0x100) {
172 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100); 173 nv_wr32(device, NV50_PDISPLAY_INTR_1, 0x100);
173 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1); 174 nv_wr32(device, 0x006194e8, nv_rd32(device, 0x006194e8) & ~1);
174 if (!nv_wait(dev, 0x006194e8, 2, 0)) { 175 if (!nv_wait(device, 0x006194e8, 2, 0)) {
175 NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n"); 176 NV_ERROR(drm, "timeout: (0x6194e8 & 2) != 0\n");
176 NV_ERROR(dev, "0x6194e8 = 0x%08x\n", 177 NV_ERROR(drm, "0x6194e8 = 0x%08x\n",
177 nv_rd32(dev, 0x6194e8)); 178 nv_rd32(device, 0x6194e8));
178 return -EBUSY; 179 return -EBUSY;
179 } 180 }
180 } 181 }
181 182
182 for (i = 0; i < 2; i++) { 183 for (i = 0; i < 2; i++) {
183 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000); 184 nv_wr32(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
184 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 185 if (!nv_wait(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
185 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) { 186 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
186 NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n"); 187 NV_ERROR(drm, "timeout: CURSOR_CTRL2_STATUS == 0\n");
187 NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n", 188 NV_ERROR(drm, "CURSOR_CTRL2 = 0x%08x\n",
188 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i))); 189 nv_rd32(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
189 return -EBUSY; 190 return -EBUSY;
190 } 191 }
191 192
192 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 193 nv_wr32(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
193 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON); 194 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
194 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 195 if (!nv_wait(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
195 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 196 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
196 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) { 197 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
197 NV_ERROR(dev, "timeout: " 198 NV_ERROR(drm, "timeout: "
198 "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i); 199 "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
199 NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i, 200 NV_ERROR(drm, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
200 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i))); 201 nv_rd32(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
201 return -EBUSY; 202 return -EBUSY;
202 } 203 }
203 } 204 }
204 205
205 nv_wr32(dev, NV50_PDISPLAY_PIO_CTRL, 0x00000000); 206 nv_wr32(device, NV50_PDISPLAY_PIO_CTRL, 0x00000000);
206 nv_mask(dev, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000); 207 nv_mask(device, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000);
207 nv_wr32(dev, NV50_PDISPLAY_INTR_EN_0, 0x00000000); 208 nv_wr32(device, NV50_PDISPLAY_INTR_EN_0, 0x00000000);
208 nv_mask(dev, NV50_PDISPLAY_INTR_1, 0x00000000, 0x00000000); 209 nv_mask(device, NV50_PDISPLAY_INTR_1, 0x00000000, 0x00000000);
209 nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1, 210 nv_wr32(device, NV50_PDISPLAY_INTR_EN_1,
210 NV50_PDISPLAY_INTR_EN_1_CLK_UNK10 | 211 NV50_PDISPLAY_INTR_EN_1_CLK_UNK10 |
211 NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 | 212 NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 |
212 NV50_PDISPLAY_INTR_EN_1_CLK_UNK40); 213 NV50_PDISPLAY_INTR_EN_1_CLK_UNK40);
@@ -216,7 +217,7 @@ nv50_display_init(struct drm_device *dev)
216 return ret; 217 return ret;
217 evo = nv50_display(dev)->master; 218 evo = nv50_display(dev)->master;
218 219
219 nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (nv50_display(dev)->ramin->addr >> 8) | 9); 220 nv_wr32(device, NV50_PDISPLAY_OBJECTS, (nv50_display(dev)->ramin->addr >> 8) | 9);
220 221
221 ret = RING_SPACE(evo, 3); 222 ret = RING_SPACE(evo, 3);
222 if (ret) 223 if (ret)
@@ -231,12 +232,14 @@ nv50_display_init(struct drm_device *dev)
231void 232void
232nv50_display_fini(struct drm_device *dev) 233nv50_display_fini(struct drm_device *dev)
233{ 234{
235 struct nouveau_drm *drm = nouveau_drm(dev);
236 struct nouveau_device *device = nouveau_dev(dev);
234 struct nv50_display *disp = nv50_display(dev); 237 struct nv50_display *disp = nv50_display(dev);
235 struct nouveau_channel *evo = disp->master; 238 struct nouveau_channel *evo = disp->master;
236 struct drm_crtc *drm_crtc; 239 struct drm_crtc *drm_crtc;
237 int ret, i; 240 int ret, i;
238 241
239 NV_DEBUG_KMS(dev, "\n"); 242 NV_DEBUG(drm, "\n");
240 243
241 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) { 244 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
242 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc); 245 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
@@ -261,55 +264,59 @@ nv50_display_fini(struct drm_device *dev)
261 if (!crtc->base.enabled) 264 if (!crtc->base.enabled)
262 continue; 265 continue;
263 266
264 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask); 267 nv_wr32(device, NV50_PDISPLAY_INTR_1, mask);
265 if (!nv_wait(dev, NV50_PDISPLAY_INTR_1, mask, mask)) { 268 if (!nv_wait(device, NV50_PDISPLAY_INTR_1, mask, mask)) {
266 NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == " 269 NV_ERROR(drm, "timeout: (0x610024 & 0x%08x) == "
267 "0x%08x\n", mask, mask); 270 "0x%08x\n", mask, mask);
268 NV_ERROR(dev, "0x610024 = 0x%08x\n", 271 NV_ERROR(drm, "0x610024 = 0x%08x\n",
269 nv_rd32(dev, NV50_PDISPLAY_INTR_1)); 272 nv_rd32(device, NV50_PDISPLAY_INTR_1));
270 } 273 }
271 } 274 }
272 275
273 for (i = 0; i < 2; i++) { 276 for (i = 0; i < 2; i++) {
274 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0); 277 nv_wr32(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0);
275 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 278 if (!nv_wait(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
276 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) { 279 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
277 NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n"); 280 NV_ERROR(drm, "timeout: CURSOR_CTRL2_STATUS == 0\n");
278 NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n", 281 NV_ERROR(drm, "CURSOR_CTRL2 = 0x%08x\n",
279 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i))); 282 nv_rd32(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
280 } 283 }
281 } 284 }
282 285
283 nv50_evo_fini(dev); 286 nv50_evo_fini(dev);
284 287
285 for (i = 0; i < 3; i++) { 288 for (i = 0; i < 3; i++) {
286 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i), 289 if (!nv_wait(device, NV50_PDISPLAY_SOR_DPMS_STATE(i),
287 NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) { 290 NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
288 NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i); 291 NV_ERROR(drm, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
289 NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i, 292 NV_ERROR(drm, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
290 nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i))); 293 nv_rd32(device, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
291 } 294 }
292 } 295 }
293 296
294 /* disable interrupts. */ 297 /* disable interrupts. */
295 nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1, 0x00000000); 298 nv_wr32(device, NV50_PDISPLAY_INTR_EN_1, 0x00000000);
296} 299}
297 300
298int 301int
299nv50_display_create(struct drm_device *dev) 302nv50_display_create(struct drm_device *dev)
300{ 303{
301 struct drm_nouveau_private *dev_priv = dev->dev_private; 304 struct nouveau_drm *drm = nouveau_drm(dev);
302 struct dcb_table *dcb = &dev_priv->vbios.dcb; 305 struct dcb_table *dcb = &drm->vbios.dcb;
303 struct drm_connector *connector, *ct; 306 struct drm_connector *connector, *ct;
304 struct nv50_display *priv; 307 struct nv50_display *priv;
305 int ret, i; 308 int ret, i;
306 309
307 NV_DEBUG_KMS(dev, "\n"); 310 NV_DEBUG(drm, "\n");
308 311
309 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 312 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
310 if (!priv) 313 if (!priv)
311 return -ENOMEM; 314 return -ENOMEM;
312 dev_priv->engine.display.priv = priv; 315
316 nouveau_display(dev)->priv = priv;
317 nouveau_display(dev)->dtor = nv50_display_destroy;
318 nouveau_display(dev)->init = nv50_display_init;
319 nouveau_display(dev)->fini = nv50_display_fini;
313 320
314 /* Create CRTC objects */ 321 /* Create CRTC objects */
315 for (i = 0; i < 2; i++) { 322 for (i = 0; i < 2; i++) {
@@ -323,7 +330,7 @@ nv50_display_create(struct drm_device *dev)
323 struct dcb_output *entry = &dcb->entry[i]; 330 struct dcb_output *entry = &dcb->entry[i];
324 331
325 if (entry->location != DCB_LOC_ON_CHIP) { 332 if (entry->location != DCB_LOC_ON_CHIP) {
326 NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n", 333 NV_WARN(drm, "Off-chip encoder %d/%d unsupported\n",
327 entry->type, ffs(entry->or) - 1); 334 entry->type, ffs(entry->or) - 1);
328 continue; 335 continue;
329 } 336 }
@@ -342,7 +349,7 @@ nv50_display_create(struct drm_device *dev)
342 nv50_dac_create(connector, entry); 349 nv50_dac_create(connector, entry);
343 break; 350 break;
344 default: 351 default:
345 NV_WARN(dev, "DCB encoder %d unknown\n", entry->type); 352 NV_WARN(drm, "DCB encoder %d unknown\n", entry->type);
346 continue; 353 continue;
347 } 354 }
348 } 355 }
@@ -350,14 +357,13 @@ nv50_display_create(struct drm_device *dev)
350 list_for_each_entry_safe(connector, ct, 357 list_for_each_entry_safe(connector, ct,
351 &dev->mode_config.connector_list, head) { 358 &dev->mode_config.connector_list, head) {
352 if (!connector->encoder_ids[0]) { 359 if (!connector->encoder_ids[0]) {
353 NV_WARN(dev, "%s has no encoders, removing\n", 360 NV_WARN(drm, "%s has no encoders, removing\n",
354 drm_get_connector_name(connector)); 361 drm_get_connector_name(connector));
355 connector->funcs->destroy(connector); 362 connector->funcs->destroy(connector);
356 } 363 }
357 } 364 }
358 365
359 tasklet_init(&priv->tasklet, nv50_display_bh, (unsigned long)dev); 366 tasklet_init(&priv->tasklet, nv50_display_bh, (unsigned long)dev);
360 nouveau_irq_register(dev, 26, nv50_display_isr);
361 367
362 ret = nv50_evo_create(dev); 368 ret = nv50_evo_create(dev);
363 if (ret) { 369 if (ret) {
@@ -373,13 +379,16 @@ nv50_display_destroy(struct drm_device *dev)
373{ 379{
374 struct nv50_display *disp = nv50_display(dev); 380 struct nv50_display *disp = nv50_display(dev);
375 381
376 NV_DEBUG_KMS(dev, "\n");
377
378 nv50_evo_destroy(dev); 382 nv50_evo_destroy(dev);
379 nouveau_irq_unregister(dev, 26);
380 kfree(disp); 383 kfree(disp);
381} 384}
382 385
386struct nouveau_bo *
387nv50_display_crtc_sema(struct drm_device *dev, int crtc)
388{
389 return nv50_display(dev)->crtc[crtc].sem.bo;
390}
391
383void 392void
384nv50_display_flip_stop(struct drm_crtc *crtc) 393nv50_display_flip_stop(struct drm_crtc *crtc)
385{ 394{
@@ -410,7 +419,7 @@ int
410nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, 419nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
411 struct nouveau_channel *chan) 420 struct nouveau_channel *chan)
412{ 421{
413 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; 422 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
414 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); 423 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
415 struct nv50_display *disp = nv50_display(crtc->dev); 424 struct nv50_display *disp = nv50_display(crtc->dev);
416 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 425 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
@@ -430,7 +439,7 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
430 return ret; 439 return ret;
431 } 440 }
432 441
433 if (dev_priv->chipset < 0xc0) { 442 if (nv_device(drm->device)->chipset < 0xc0) {
434 BEGIN_NV04(chan, 0, 0x0060, 2); 443 BEGIN_NV04(chan, 0, 0x0060, 2);
435 OUT_RING (chan, NvEvoSema0 + nv_crtc->index); 444 OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
436 OUT_RING (chan, dispc->sem.offset); 445 OUT_RING (chan, dispc->sem.offset);
@@ -440,7 +449,7 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
440 OUT_RING (chan, dispc->sem.offset ^ 0x10); 449 OUT_RING (chan, dispc->sem.offset ^ 0x10);
441 OUT_RING (chan, 0x74b1e000); 450 OUT_RING (chan, 0x74b1e000);
442 BEGIN_NV04(chan, 0, 0x0060, 1); 451 BEGIN_NV04(chan, 0, 0x0060, 1);
443 if (dev_priv->chipset < 0x84) 452 if (nv_device(drm->device)->chipset < 0x84)
444 OUT_RING (chan, NvSema); 453 OUT_RING (chan, NvSema);
445 else 454 else
446 OUT_RING (chan, chan->vram); 455 OUT_RING (chan, chan->vram);
@@ -511,10 +520,10 @@ static u16
511nv50_display_script_select(struct drm_device *dev, struct dcb_output *dcb, 520nv50_display_script_select(struct drm_device *dev, struct dcb_output *dcb,
512 u32 mc, int pxclk) 521 u32 mc, int pxclk)
513{ 522{
514 struct drm_nouveau_private *dev_priv = dev->dev_private; 523 struct nouveau_drm *drm = nouveau_drm(dev);
515 struct nouveau_connector *nv_connector = NULL; 524 struct nouveau_connector *nv_connector = NULL;
516 struct drm_encoder *encoder; 525 struct drm_encoder *encoder;
517 struct nvbios *bios = &dev_priv->vbios; 526 struct nvbios *bios = &drm->vbios;
518 u32 script = 0, or; 527 u32 script = 0, or;
519 528
520 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 529 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
@@ -562,25 +571,11 @@ nv50_display_script_select(struct drm_device *dev, struct dcb_output *dcb,
562 (nv_connector->edid->input & 0x70) >= 0x20) 571 (nv_connector->edid->input & 0x70) >= 0x20)
563 script |= 0x0200; 572 script |= 0x0200;
564 } 573 }
565
566 if (nouveau_uscript_lvds >= 0) {
567 NV_INFO(dev, "override script 0x%04x with 0x%04x "
568 "for output LVDS-%d\n", script,
569 nouveau_uscript_lvds, or);
570 script = nouveau_uscript_lvds;
571 }
572 break; 574 break;
573 case DCB_OUTPUT_TMDS: 575 case DCB_OUTPUT_TMDS:
574 script = (mc >> 8) & 0xf; 576 script = (mc >> 8) & 0xf;
575 if (pxclk >= 165000) 577 if (pxclk >= 165000)
576 script |= 0x0100; 578 script |= 0x0100;
577
578 if (nouveau_uscript_tmds >= 0) {
579 NV_INFO(dev, "override script 0x%04x with 0x%04x "
580 "for output TMDS-%d\n", script,
581 nouveau_uscript_tmds, or);
582 script = nouveau_uscript_tmds;
583 }
584 break; 579 break;
585 case DCB_OUTPUT_DP: 580 case DCB_OUTPUT_DP:
586 script = (mc >> 8) & 0xf; 581 script = (mc >> 8) & 0xf;
@@ -589,7 +584,7 @@ nv50_display_script_select(struct drm_device *dev, struct dcb_output *dcb,
589 script = 0xff; 584 script = 0xff;
590 break; 585 break;
591 default: 586 default:
592 NV_ERROR(dev, "modeset on unsupported output type!\n"); 587 NV_ERROR(drm, "modeset on unsupported output type!\n");
593 break; 588 break;
594 } 589 }
595 590
@@ -599,15 +594,16 @@ nv50_display_script_select(struct drm_device *dev, struct dcb_output *dcb,
599static void 594static void
600nv50_display_unk10_handler(struct drm_device *dev) 595nv50_display_unk10_handler(struct drm_device *dev)
601{ 596{
602 struct drm_nouveau_private *dev_priv = dev->dev_private; 597 struct nouveau_device *device = nouveau_dev(dev);
598 struct nouveau_drm *drm = nouveau_drm(dev);
603 struct nv50_display *disp = nv50_display(dev); 599 struct nv50_display *disp = nv50_display(dev);
604 u32 unk30 = nv_rd32(dev, 0x610030), mc; 600 u32 unk30 = nv_rd32(device, 0x610030), mc;
605 int i, crtc, or = 0, type = DCB_OUTPUT_ANY; 601 int i, crtc, or = 0, type = DCB_OUTPUT_ANY;
606 602
607 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30); 603 NV_DEBUG(drm, "0x610030: 0x%08x\n", unk30);
608 disp->irq.dcb = NULL; 604 disp->irq.dcb = NULL;
609 605
610 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8); 606 nv_wr32(device, 0x619494, nv_rd32(device, 0x619494) & ~8);
611 607
612 /* Determine which CRTC we're dealing with, only 1 ever will be 608 /* Determine which CRTC we're dealing with, only 1 ever will be
613 * signalled at the same time with the current nouveau code. 609 * signalled at the same time with the current nouveau code.
@@ -623,8 +619,8 @@ nv50_display_unk10_handler(struct drm_device *dev)
623 619
624 /* Find which encoder was connected to the CRTC */ 620 /* Find which encoder was connected to the CRTC */
625 for (i = 0; type == DCB_OUTPUT_ANY && i < 3; i++) { 621 for (i = 0; type == DCB_OUTPUT_ANY && i < 3; i++) {
626 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i)); 622 mc = nv_rd32(device, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
627 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc); 623 NV_DEBUG(drm, "DAC-%d mc: 0x%08x\n", i, mc);
628 if (!(mc & (1 << crtc))) 624 if (!(mc & (1 << crtc)))
629 continue; 625 continue;
630 626
@@ -632,7 +628,7 @@ nv50_display_unk10_handler(struct drm_device *dev)
632 case 0: type = DCB_OUTPUT_ANALOG; break; 628 case 0: type = DCB_OUTPUT_ANALOG; break;
633 case 1: type = DCB_OUTPUT_TV; break; 629 case 1: type = DCB_OUTPUT_TV; break;
634 default: 630 default:
635 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc); 631 NV_ERROR(drm, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
636 goto ack; 632 goto ack;
637 } 633 }
638 634
@@ -640,14 +636,14 @@ nv50_display_unk10_handler(struct drm_device *dev)
640 } 636 }
641 637
642 for (i = 0; type == DCB_OUTPUT_ANY && i < nv50_sor_nr(dev); i++) { 638 for (i = 0; type == DCB_OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
643 if (dev_priv->chipset < 0x90 || 639 if (nv_device(drm->device)->chipset < 0x90 ||
644 dev_priv->chipset == 0x92 || 640 nv_device(drm->device)->chipset == 0x92 ||
645 dev_priv->chipset == 0xa0) 641 nv_device(drm->device)->chipset == 0xa0)
646 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i)); 642 mc = nv_rd32(device, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
647 else 643 else
648 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i)); 644 mc = nv_rd32(device, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
649 645
650 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc); 646 NV_DEBUG(drm, "SOR-%d mc: 0x%08x\n", i, mc);
651 if (!(mc & (1 << crtc))) 647 if (!(mc & (1 << crtc)))
652 continue; 648 continue;
653 649
@@ -659,7 +655,7 @@ nv50_display_unk10_handler(struct drm_device *dev)
659 case 8: type = DCB_OUTPUT_DP; break; 655 case 8: type = DCB_OUTPUT_DP; break;
660 case 9: type = DCB_OUTPUT_DP; break; 656 case 9: type = DCB_OUTPUT_DP; break;
661 default: 657 default:
662 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc); 658 NV_ERROR(drm, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
663 goto ack; 659 goto ack;
664 } 660 }
665 661
@@ -671,8 +667,8 @@ nv50_display_unk10_handler(struct drm_device *dev)
671 goto ack; 667 goto ack;
672 668
673 /* Disable the encoder */ 669 /* Disable the encoder */
674 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) { 670 for (i = 0; i < drm->vbios.dcb.entries; i++) {
675 struct dcb_output *dcb = &dev_priv->vbios.dcb.entry[i]; 671 struct dcb_output *dcb = &drm->vbios.dcb.entry[i];
676 672
677 if (dcb->type == type && (dcb->or & (1 << or))) { 673 if (dcb->type == type && (dcb->or & (1 << or))) {
678 nouveau_bios_run_display_table(dev, 0, -1, dcb, -1); 674 nouveau_bios_run_display_table(dev, 0, -1, dcb, -1);
@@ -681,22 +677,23 @@ nv50_display_unk10_handler(struct drm_device *dev)
681 } 677 }
682 } 678 }
683 679
684 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc); 680 NV_ERROR(drm, "no dcb for %d %d 0x%08x\n", or, type, mc);
685ack: 681ack:
686 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10); 682 nv_wr32(device, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
687 nv_wr32(dev, 0x610030, 0x80000000); 683 nv_wr32(device, 0x610030, 0x80000000);
688} 684}
689 685
690static void 686static void
691nv50_display_unk20_handler(struct drm_device *dev) 687nv50_display_unk20_handler(struct drm_device *dev)
692{ 688{
693 struct drm_nouveau_private *dev_priv = dev->dev_private; 689 struct nouveau_device *device = nouveau_dev(dev);
690 struct nouveau_drm *drm = nouveau_drm(dev);
694 struct nv50_display *disp = nv50_display(dev); 691 struct nv50_display *disp = nv50_display(dev);
695 u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc = 0; 692 u32 unk30 = nv_rd32(device, 0x610030), tmp, pclk, script, mc = 0;
696 struct dcb_output *dcb; 693 struct dcb_output *dcb;
697 int i, crtc, or = 0, type = DCB_OUTPUT_ANY; 694 int i, crtc, or = 0, type = DCB_OUTPUT_ANY;
698 695
699 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30); 696 NV_DEBUG(drm, "0x610030: 0x%08x\n", unk30);
700 dcb = disp->irq.dcb; 697 dcb = disp->irq.dcb;
701 if (dcb) { 698 if (dcb) {
702 nouveau_bios_run_display_table(dev, 0, -2, dcb, -1); 699 nouveau_bios_run_display_table(dev, 0, -2, dcb, -1);
@@ -706,26 +703,26 @@ nv50_display_unk20_handler(struct drm_device *dev)
706 /* CRTC clock change requested? */ 703 /* CRTC clock change requested? */
707 crtc = ffs((unk30 & 0x00000600) >> 9) - 1; 704 crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
708 if (crtc >= 0) { 705 if (crtc >= 0) {
709 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)); 706 pclk = nv_rd32(device, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
710 pclk &= 0x003fffff; 707 pclk &= 0x003fffff;
711 if (pclk) 708 if (pclk)
712 nv50_crtc_set_clock(dev, crtc, pclk); 709 nv50_crtc_set_clock(dev, crtc, pclk);
713 710
714 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc)); 711 tmp = nv_rd32(device, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
715 tmp &= ~0x000000f; 712 tmp &= ~0x000000f;
716 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp); 713 nv_wr32(device, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
717 } 714 }
718 715
719 /* Nothing needs to be done for the encoder */ 716 /* Nothing needs to be done for the encoder */
720 crtc = ffs((unk30 & 0x00000180) >> 7) - 1; 717 crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
721 if (crtc < 0) 718 if (crtc < 0)
722 goto ack; 719 goto ack;
723 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff; 720 pclk = nv_rd32(device, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
724 721
725 /* Find which encoder is connected to the CRTC */ 722 /* Find which encoder is connected to the CRTC */
726 for (i = 0; type == DCB_OUTPUT_ANY && i < 3; i++) { 723 for (i = 0; type == DCB_OUTPUT_ANY && i < 3; i++) {
727 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i)); 724 mc = nv_rd32(device, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
728 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc); 725 NV_DEBUG(drm, "DAC-%d mc: 0x%08x\n", i, mc);
729 if (!(mc & (1 << crtc))) 726 if (!(mc & (1 << crtc)))
730 continue; 727 continue;
731 728
@@ -733,7 +730,7 @@ nv50_display_unk20_handler(struct drm_device *dev)
733 case 0: type = DCB_OUTPUT_ANALOG; break; 730 case 0: type = DCB_OUTPUT_ANALOG; break;
734 case 1: type = DCB_OUTPUT_TV; break; 731 case 1: type = DCB_OUTPUT_TV; break;
735 default: 732 default:
736 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc); 733 NV_ERROR(drm, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
737 goto ack; 734 goto ack;
738 } 735 }
739 736
@@ -741,14 +738,14 @@ nv50_display_unk20_handler(struct drm_device *dev)
741 } 738 }
742 739
743 for (i = 0; type == DCB_OUTPUT_ANY && i < nv50_sor_nr(dev); i++) { 740 for (i = 0; type == DCB_OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
744 if (dev_priv->chipset < 0x90 || 741 if (nv_device(drm->device)->chipset < 0x90 ||
745 dev_priv->chipset == 0x92 || 742 nv_device(drm->device)->chipset == 0x92 ||
746 dev_priv->chipset == 0xa0) 743 nv_device(drm->device)->chipset == 0xa0)
747 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i)); 744 mc = nv_rd32(device, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
748 else 745 else
749 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i)); 746 mc = nv_rd32(device, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
750 747
751 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc); 748 NV_DEBUG(drm, "SOR-%d mc: 0x%08x\n", i, mc);
752 if (!(mc & (1 << crtc))) 749 if (!(mc & (1 << crtc)))
753 continue; 750 continue;
754 751
@@ -760,7 +757,7 @@ nv50_display_unk20_handler(struct drm_device *dev)
760 case 8: type = DCB_OUTPUT_DP; break; 757 case 8: type = DCB_OUTPUT_DP; break;
761 case 9: type = DCB_OUTPUT_DP; break; 758 case 9: type = DCB_OUTPUT_DP; break;
762 default: 759 default:
763 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc); 760 NV_ERROR(drm, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
764 goto ack; 761 goto ack;
765 } 762 }
766 763
@@ -771,14 +768,14 @@ nv50_display_unk20_handler(struct drm_device *dev)
771 goto ack; 768 goto ack;
772 769
773 /* Enable the encoder */ 770 /* Enable the encoder */
774 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) { 771 for (i = 0; i < drm->vbios.dcb.entries; i++) {
775 dcb = &dev_priv->vbios.dcb.entry[i]; 772 dcb = &drm->vbios.dcb.entry[i];
776 if (dcb->type == type && (dcb->or & (1 << or))) 773 if (dcb->type == type && (dcb->or & (1 << or)))
777 break; 774 break;
778 } 775 }
779 776
780 if (i == dev_priv->vbios.dcb.entries) { 777 if (i == drm->vbios.dcb.entries) {
781 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc); 778 NV_ERROR(drm, "no dcb for %d %d 0x%08x\n", or, type, mc);
782 goto ack; 779 goto ack;
783 } 780 }
784 781
@@ -794,13 +791,13 @@ nv50_display_unk20_handler(struct drm_device *dev)
794 } 791 }
795 792
796 if (dcb->type != DCB_OUTPUT_ANALOG) { 793 if (dcb->type != DCB_OUTPUT_ANALOG) {
797 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or)); 794 tmp = nv_rd32(device, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
798 tmp &= ~0x00000f0f; 795 tmp &= ~0x00000f0f;
799 if (script & 0x0100) 796 if (script & 0x0100)
800 tmp |= 0x00000101; 797 tmp |= 0x00000101;
801 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp); 798 nv_wr32(device, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
802 } else { 799 } else {
803 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0); 800 nv_wr32(device, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
804 } 801 }
805 802
806 disp->irq.dcb = dcb; 803 disp->irq.dcb = dcb;
@@ -808,8 +805,8 @@ nv50_display_unk20_handler(struct drm_device *dev)
808 disp->irq.script = script; 805 disp->irq.script = script;
809 806
810ack: 807ack:
811 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20); 808 nv_wr32(device, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
812 nv_wr32(dev, 0x610030, 0x80000000); 809 nv_wr32(device, 0x610030, 0x80000000);
813} 810}
814 811
815/* If programming a TMDS output on a SOR that can also be configured for 812/* If programming a TMDS output on a SOR that can also be configured for
@@ -823,6 +820,7 @@ ack:
823static void 820static void
824nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_output *dcb) 821nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_output *dcb)
825{ 822{
823 struct nouveau_device *device = nouveau_dev(dev);
826 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1); 824 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
827 struct drm_encoder *encoder; 825 struct drm_encoder *encoder;
828 u32 tmp; 826 u32 tmp;
@@ -835,9 +833,9 @@ nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_output *dcb)
835 833
836 if (nv_encoder->dcb->type == DCB_OUTPUT_DP && 834 if (nv_encoder->dcb->type == DCB_OUTPUT_DP &&
837 nv_encoder->dcb->or & (1 << or)) { 835 nv_encoder->dcb->or & (1 << or)) {
838 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link)); 836 tmp = nv_rd32(device, NV50_SOR_DP_CTRL(or, link));
839 tmp &= ~NV50_SOR_DP_CTRL_ENABLED; 837 tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
840 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp); 838 nv_wr32(device, NV50_SOR_DP_CTRL(or, link), tmp);
841 break; 839 break;
842 } 840 }
843 } 841 }
@@ -846,12 +844,14 @@ nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_output *dcb)
846static void 844static void
847nv50_display_unk40_handler(struct drm_device *dev) 845nv50_display_unk40_handler(struct drm_device *dev)
848{ 846{
847 struct nouveau_device *device = nouveau_dev(dev);
848 struct nouveau_drm *drm = nouveau_drm(dev);
849 struct nv50_display *disp = nv50_display(dev); 849 struct nv50_display *disp = nv50_display(dev);
850 struct dcb_output *dcb = disp->irq.dcb; 850 struct dcb_output *dcb = disp->irq.dcb;
851 u16 script = disp->irq.script; 851 u16 script = disp->irq.script;
852 u32 unk30 = nv_rd32(dev, 0x610030), pclk = disp->irq.pclk; 852 u32 unk30 = nv_rd32(device, 0x610030), pclk = disp->irq.pclk;
853 853
854 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30); 854 NV_DEBUG(drm, "0x610030: 0x%08x\n", unk30);
855 disp->irq.dcb = NULL; 855 disp->irq.dcb = NULL;
856 if (!dcb) 856 if (!dcb)
857 goto ack; 857 goto ack;
@@ -860,21 +860,23 @@ nv50_display_unk40_handler(struct drm_device *dev)
860 nv50_display_unk40_dp_set_tmds(dev, dcb); 860 nv50_display_unk40_dp_set_tmds(dev, dcb);
861 861
862ack: 862ack:
863 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40); 863 nv_wr32(device, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
864 nv_wr32(dev, 0x610030, 0x80000000); 864 nv_wr32(device, 0x610030, 0x80000000);
865 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8); 865 nv_wr32(device, 0x619494, nv_rd32(device, 0x619494) | 8);
866} 866}
867 867
868static void 868static void
869nv50_display_bh(unsigned long data) 869nv50_display_bh(unsigned long data)
870{ 870{
871 struct drm_device *dev = (struct drm_device *)data; 871 struct drm_device *dev = (struct drm_device *)data;
872 struct nouveau_device *device = nouveau_dev(dev);
873 struct nouveau_drm *drm = nouveau_drm(dev);
872 874
873 for (;;) { 875 for (;;) {
874 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0); 876 uint32_t intr0 = nv_rd32(device, NV50_PDISPLAY_INTR_0);
875 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1); 877 uint32_t intr1 = nv_rd32(device, NV50_PDISPLAY_INTR_1);
876 878
877 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1); 879 NV_DEBUG(drm, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
878 880
879 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10) 881 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
880 nv50_display_unk10_handler(dev); 882 nv50_display_unk10_handler(dev);
@@ -888,13 +890,15 @@ nv50_display_bh(unsigned long data)
888 break; 890 break;
889 } 891 }
890 892
891 nv_wr32(dev, NV03_PMC_INTR_EN_0, 1); 893 nv_wr32(device, NV03_PMC_INTR_EN_0, 1);
892} 894}
893 895
894static void 896static void
895nv50_display_error_handler(struct drm_device *dev) 897nv50_display_error_handler(struct drm_device *dev)
896{ 898{
897 u32 channels = (nv_rd32(dev, NV50_PDISPLAY_INTR_0) & 0x001f0000) >> 16; 899 struct nouveau_device *device = nouveau_dev(dev);
900 struct nouveau_drm *drm = nouveau_drm(dev);
901 u32 channels = (nv_rd32(device, NV50_PDISPLAY_INTR_0) & 0x001f0000) >> 16;
898 u32 addr, data; 902 u32 addr, data;
899 int chid; 903 int chid;
900 904
@@ -902,29 +906,31 @@ nv50_display_error_handler(struct drm_device *dev)
902 if (!(channels & (1 << chid))) 906 if (!(channels & (1 << chid)))
903 continue; 907 continue;
904 908
905 nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000 << chid); 909 nv_wr32(device, NV50_PDISPLAY_INTR_0, 0x00010000 << chid);
906 addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid)); 910 addr = nv_rd32(device, NV50_PDISPLAY_TRAPPED_ADDR(chid));
907 data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA(chid)); 911 data = nv_rd32(device, NV50_PDISPLAY_TRAPPED_DATA(chid));
908 NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x " 912 NV_ERROR(drm, "EvoCh %d Mthd 0x%04x Data 0x%08x "
909 "(0x%04x 0x%02x)\n", chid, 913 "(0x%04x 0x%02x)\n", chid,
910 addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf); 914 addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
911 915
912 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid), 0x90000000); 916 nv_wr32(device, NV50_PDISPLAY_TRAPPED_ADDR(chid), 0x90000000);
913 } 917 }
914} 918}
915 919
916static void 920void
917nv50_display_isr(struct drm_device *dev) 921nv50_display_intr(struct drm_device *dev)
918{ 922{
923 struct nouveau_device *device = nouveau_dev(dev);
924 struct nouveau_drm *drm = nouveau_drm(dev);
919 struct nv50_display *disp = nv50_display(dev); 925 struct nv50_display *disp = nv50_display(dev);
920 uint32_t delayed = 0; 926 uint32_t delayed = 0;
921 927
922 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) { 928 while (nv_rd32(device, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
923 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0); 929 uint32_t intr0 = nv_rd32(device, NV50_PDISPLAY_INTR_0);
924 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1); 930 uint32_t intr1 = nv_rd32(device, NV50_PDISPLAY_INTR_1);
925 uint32_t clock; 931 uint32_t clock;
926 932
927 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1); 933 NV_DEBUG(drm, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
928 934
929 if (!intr0 && !(intr1 & ~delayed)) 935 if (!intr0 && !(intr1 & ~delayed))
930 break; 936 break;
@@ -943,21 +949,21 @@ nv50_display_isr(struct drm_device *dev)
943 NV50_PDISPLAY_INTR_1_CLK_UNK20 | 949 NV50_PDISPLAY_INTR_1_CLK_UNK20 |
944 NV50_PDISPLAY_INTR_1_CLK_UNK40)); 950 NV50_PDISPLAY_INTR_1_CLK_UNK40));
945 if (clock) { 951 if (clock) {
946 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0); 952 nv_wr32(device, NV03_PMC_INTR_EN_0, 0);
947 tasklet_schedule(&disp->tasklet); 953 tasklet_schedule(&disp->tasklet);
948 delayed |= clock; 954 delayed |= clock;
949 intr1 &= ~clock; 955 intr1 &= ~clock;
950 } 956 }
951 957
952 if (intr0) { 958 if (intr0) {
953 NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0); 959 NV_ERROR(drm, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
954 nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0); 960 nv_wr32(device, NV50_PDISPLAY_INTR_0, intr0);
955 } 961 }
956 962
957 if (intr1) { 963 if (intr1) {
958 NV_ERROR(dev, 964 NV_ERROR(drm,
959 "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1); 965 "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
960 nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1); 966 nv_wr32(device, NV50_PDISPLAY_INTR_1, intr1);
961 } 967 }
962 } 968 }
963} 969}
diff --git a/drivers/gpu/drm/nouveau/nv50_display.h b/drivers/gpu/drm/nouveau/nv50_display.h
index ef12a7afac9c..973554d8a7a6 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.h
+++ b/drivers/gpu/drm/nouveau/nv50_display.h
@@ -27,12 +27,9 @@
27#ifndef __NV50_DISPLAY_H__ 27#ifndef __NV50_DISPLAY_H__
28#define __NV50_DISPLAY_H__ 28#define __NV50_DISPLAY_H__
29 29
30#include "drmP.h" 30#include "nouveau_display.h"
31#include "drm.h"
32#include "nouveau_drv.h"
33#include "nouveau_dma.h"
34#include "nouveau_reg.h"
35#include "nouveau_crtc.h" 31#include "nouveau_crtc.h"
32#include "nouveau_reg.h"
36#include "nv50_evo.h" 33#include "nv50_evo.h"
37 34
38struct nv50_display_crtc { 35struct nv50_display_crtc {
@@ -64,8 +61,7 @@ struct nv50_display {
64static inline struct nv50_display * 61static inline struct nv50_display *
65nv50_display(struct drm_device *dev) 62nv50_display(struct drm_device *dev)
66{ 63{
67 struct drm_nouveau_private *dev_priv = dev->dev_private; 64 return nouveau_display(dev)->priv;
68 return dev_priv->engine.display.priv;
69} 65}
70 66
71int nv50_display_early_init(struct drm_device *dev); 67int nv50_display_early_init(struct drm_device *dev);
@@ -74,6 +70,7 @@ int nv50_display_create(struct drm_device *dev);
74int nv50_display_init(struct drm_device *dev); 70int nv50_display_init(struct drm_device *dev);
75void nv50_display_fini(struct drm_device *dev); 71void nv50_display_fini(struct drm_device *dev);
76void nv50_display_destroy(struct drm_device *dev); 72void nv50_display_destroy(struct drm_device *dev);
73void nv50_display_intr(struct drm_device *);
77int nv50_crtc_blank(struct nouveau_crtc *, bool blank); 74int nv50_crtc_blank(struct nouveau_crtc *, bool blank);
78int nv50_crtc_set_clock(struct drm_device *, int head, int pclk); 75int nv50_crtc_set_clock(struct drm_device *, int head, int pclk);
79 76
@@ -93,4 +90,17 @@ void nv50_evo_dmaobj_init(struct nouveau_gpuobj *, u32 memtype, u64 base,
93int nv50_evo_dmaobj_new(struct nouveau_channel *, u32 handle, u32 memtype, 90int nv50_evo_dmaobj_new(struct nouveau_channel *, u32 handle, u32 memtype,
94 u64 base, u64 size, struct nouveau_gpuobj **); 91 u64 base, u64 size, struct nouveau_gpuobj **);
95 92
93int nvd0_display_create(struct drm_device *);
94void nvd0_display_destroy(struct drm_device *);
95int nvd0_display_init(struct drm_device *);
96void nvd0_display_fini(struct drm_device *);
97void nvd0_display_intr(struct drm_device *);
98
99void nvd0_display_flip_stop(struct drm_crtc *);
100int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
101 struct nouveau_channel *, u32 swap_interval);
102
103struct nouveau_bo *nv50_display_crtc_sema(struct drm_device *, int head);
104struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int head);
105
96#endif /* __NV50_DISPLAY_H__ */ 106#endif /* __NV50_DISPLAY_H__ */
diff --git a/drivers/gpu/drm/nouveau/nv50_evo.c b/drivers/gpu/drm/nouveau/nv50_evo.c
index d7d8080c6a14..0f534160c021 100644
--- a/drivers/gpu/drm/nouveau/nv50_evo.c
+++ b/drivers/gpu/drm/nouveau/nv50_evo.c
@@ -24,10 +24,15 @@
24 24
25#include "drmP.h" 25#include "drmP.h"
26 26
27#include "nouveau_drv.h" 27#include "nouveau_drm.h"
28#include "nouveau_dma.h" 28#include "nouveau_dma.h"
29#include "nv50_display.h" 29#include "nv50_display.h"
30 30
31#include <core/gpuobj.h>
32
33#include <subdev/timer.h>
34#include <subdev/fb.h>
35
31static u32 36static u32
32nv50_evo_rd32(struct nouveau_object *object, u32 addr) 37nv50_evo_rd32(struct nouveau_object *object, u32 addr)
33{ 38{
@@ -65,15 +70,15 @@ nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 handle, u32 memtype,
65 u64 base, u64 size, struct nouveau_gpuobj **pobj) 70 u64 base, u64 size, struct nouveau_gpuobj **pobj)
66{ 71{
67 struct drm_device *dev = evo->fence; 72 struct drm_device *dev = evo->fence;
68 struct drm_nouveau_private *dev_priv = dev->dev_private; 73 struct nouveau_drm *drm = nouveau_drm(dev);
69 struct nv50_display *disp = nv50_display(dev); 74 struct nv50_display *disp = nv50_display(dev);
70 u32 dmao = disp->dmao; 75 u32 dmao = disp->dmao;
71 u32 hash = disp->hash; 76 u32 hash = disp->hash;
72 u32 flags5; 77 u32 flags5;
73 78
74 if (dev_priv->chipset < 0xc0) { 79 if (nv_device(drm->device)->chipset < 0xc0) {
75 /* not supported on 0x50, specified in format mthd */ 80 /* not supported on 0x50, specified in format mthd */
76 if (dev_priv->chipset == 0x50) 81 if (nv_device(drm->device)->chipset == 0x50)
77 memtype = 0; 82 memtype = 0;
78 flags5 = 0x00010000; 83 flags5 = 0x00010000;
79 } else { 84 } else {
@@ -104,6 +109,7 @@ static int
104nv50_evo_channel_new(struct drm_device *dev, int chid, 109nv50_evo_channel_new(struct drm_device *dev, int chid,
105 struct nouveau_channel **pevo) 110 struct nouveau_channel **pevo)
106{ 111{
112 struct nouveau_drm *drm = nouveau_drm(dev);
107 struct nv50_display *disp = nv50_display(dev); 113 struct nv50_display *disp = nv50_display(dev);
108 struct nouveau_channel *evo; 114 struct nouveau_channel *evo;
109 int ret; 115 int ret;
@@ -113,6 +119,7 @@ nv50_evo_channel_new(struct drm_device *dev, int chid,
113 return -ENOMEM; 119 return -ENOMEM;
114 *pevo = evo; 120 *pevo = evo;
115 121
122 evo->drm = drm;
116 evo->handle = chid; 123 evo->handle = chid;
117 evo->fence = dev; 124 evo->fence = dev;
118 evo->user_get = 4; 125 evo->user_get = 4;
@@ -123,14 +130,14 @@ nv50_evo_channel_new(struct drm_device *dev, int chid,
123 if (ret == 0) 130 if (ret == 0)
124 ret = nouveau_bo_pin(evo->push.buffer, TTM_PL_FLAG_VRAM); 131 ret = nouveau_bo_pin(evo->push.buffer, TTM_PL_FLAG_VRAM);
125 if (ret) { 132 if (ret) {
126 NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret); 133 NV_ERROR(drm, "Error creating EVO DMA push buffer: %d\n", ret);
127 nv50_evo_channel_del(pevo); 134 nv50_evo_channel_del(pevo);
128 return ret; 135 return ret;
129 } 136 }
130 137
131 ret = nouveau_bo_map(evo->push.buffer); 138 ret = nouveau_bo_map(evo->push.buffer);
132 if (ret) { 139 if (ret) {
133 NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret); 140 NV_ERROR(drm, "Error mapping EVO DMA push buffer: %d\n", ret);
134 nv50_evo_channel_del(pevo); 141 nv50_evo_channel_del(pevo);
135 return ret; 142 return ret;
136 } 143 }
@@ -156,39 +163,40 @@ nv50_evo_channel_new(struct drm_device *dev, int chid,
156static int 163static int
157nv50_evo_channel_init(struct nouveau_channel *evo) 164nv50_evo_channel_init(struct nouveau_channel *evo)
158{ 165{
159 struct drm_device *dev = evo->fence; 166 struct nouveau_drm *drm = evo->drm;
167 struct nouveau_device *device = nv_device(drm->device);
160 int id = evo->handle, ret, i; 168 int id = evo->handle, ret, i;
161 u64 pushbuf = evo->push.buffer->bo.offset; 169 u64 pushbuf = evo->push.buffer->bo.offset;
162 u32 tmp; 170 u32 tmp;
163 171
164 tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)); 172 tmp = nv_rd32(device, NV50_PDISPLAY_EVO_CTRL(id));
165 if ((tmp & 0x009f0000) == 0x00020000) 173 if ((tmp & 0x009f0000) == 0x00020000)
166 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x00800000); 174 nv_wr32(device, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x00800000);
167 175
168 tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)); 176 tmp = nv_rd32(device, NV50_PDISPLAY_EVO_CTRL(id));
169 if ((tmp & 0x003f0000) == 0x00030000) 177 if ((tmp & 0x003f0000) == 0x00030000)
170 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x00600000); 178 nv_wr32(device, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x00600000);
171 179
172 /* initialise fifo */ 180 /* initialise fifo */
173 nv_wr32(dev, NV50_PDISPLAY_EVO_DMA_CB(id), pushbuf >> 8 | 181 nv_wr32(device, NV50_PDISPLAY_EVO_DMA_CB(id), pushbuf >> 8 |
174 NV50_PDISPLAY_EVO_DMA_CB_LOCATION_VRAM | 182 NV50_PDISPLAY_EVO_DMA_CB_LOCATION_VRAM |
175 NV50_PDISPLAY_EVO_DMA_CB_VALID); 183 NV50_PDISPLAY_EVO_DMA_CB_VALID);
176 nv_wr32(dev, NV50_PDISPLAY_EVO_UNK2(id), 0x00010000); 184 nv_wr32(device, NV50_PDISPLAY_EVO_UNK2(id), 0x00010000);
177 nv_wr32(dev, NV50_PDISPLAY_EVO_HASH_TAG(id), id); 185 nv_wr32(device, NV50_PDISPLAY_EVO_HASH_TAG(id), id);
178 nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), NV50_PDISPLAY_EVO_CTRL_DMA, 186 nv_mask(device, NV50_PDISPLAY_EVO_CTRL(id), NV50_PDISPLAY_EVO_CTRL_DMA,
179 NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED); 187 NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
180 188
181 nv_wr32(dev, NV50_PDISPLAY_USER_PUT(id), 0x00000000); 189 nv_wr32(device, NV50_PDISPLAY_USER_PUT(id), 0x00000000);
182 nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x01000003 | 190 nv_wr32(device, NV50_PDISPLAY_EVO_CTRL(id), 0x01000003 |
183 NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED); 191 NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
184 if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x80000000, 0x00000000)) { 192 if (!nv_wait(device, NV50_PDISPLAY_EVO_CTRL(id), 0x80000000, 0x00000000)) {
185 NV_ERROR(dev, "EvoCh %d init timeout: 0x%08x\n", id, 193 NV_ERROR(drm, "EvoCh %d init timeout: 0x%08x\n", id,
186 nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id))); 194 nv_rd32(device, NV50_PDISPLAY_EVO_CTRL(id)));
187 return -EBUSY; 195 return -EBUSY;
188 } 196 }
189 197
190 /* enable error reporting on the channel */ 198 /* enable error reporting on the channel */
191 nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << id); 199 nv_mask(device, 0x610028, 0x00000000, 0x00010001 << id);
192 200
193 evo->dma.max = (4096/4) - 2; 201 evo->dma.max = (4096/4) - 2;
194 evo->dma.max &= ~7; 202 evo->dma.max &= ~7;
@@ -209,16 +217,17 @@ nv50_evo_channel_init(struct nouveau_channel *evo)
209static void 217static void
210nv50_evo_channel_fini(struct nouveau_channel *evo) 218nv50_evo_channel_fini(struct nouveau_channel *evo)
211{ 219{
212 struct drm_device *dev = evo->fence; 220 struct nouveau_drm *drm = evo->drm;
221 struct nouveau_device *device = nv_device(drm->device);
213 int id = evo->handle; 222 int id = evo->handle;
214 223
215 nv_mask(dev, 0x610028, 0x00010001 << id, 0x00000000); 224 nv_mask(device, 0x610028, 0x00010001 << id, 0x00000000);
216 nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x00001010, 0x00001000); 225 nv_mask(device, NV50_PDISPLAY_EVO_CTRL(id), 0x00001010, 0x00001000);
217 nv_wr32(dev, NV50_PDISPLAY_INTR_0, (1 << id)); 226 nv_wr32(device, NV50_PDISPLAY_INTR_0, (1 << id));
218 nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x00000003, 0x00000000); 227 nv_mask(device, NV50_PDISPLAY_EVO_CTRL(id), 0x00000003, 0x00000000);
219 if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x001e0000, 0x00000000)) { 228 if (!nv_wait(device, NV50_PDISPLAY_EVO_CTRL(id), 0x001e0000, 0x00000000)) {
220 NV_ERROR(dev, "EvoCh %d takedown timeout: 0x%08x\n", id, 229 NV_ERROR(drm, "EvoCh %d takedown timeout: 0x%08x\n", id,
221 nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id))); 230 nv_rd32(device, NV50_PDISPLAY_EVO_CTRL(id)));
222 } 231 }
223} 232}
224 233
@@ -242,7 +251,8 @@ nv50_evo_destroy(struct drm_device *dev)
242int 251int
243nv50_evo_create(struct drm_device *dev) 252nv50_evo_create(struct drm_device *dev)
244{ 253{
245 struct drm_nouveau_private *dev_priv = dev->dev_private; 254 struct nouveau_drm *drm = nouveau_drm(dev);
255 struct nouveau_fb *pfb = nouveau_fb(drm->device);
246 struct nv50_display *disp = nv50_display(dev); 256 struct nv50_display *disp = nv50_display(dev);
247 struct nouveau_channel *evo; 257 struct nouveau_channel *evo;
248 int ret, i, j; 258 int ret, i, j;
@@ -251,10 +261,10 @@ nv50_evo_create(struct drm_device *dev)
251 * use this also as there's no per-channel support on the 261 * use this also as there's no per-channel support on the
252 * hardware 262 * hardware
253 */ 263 */
254 ret = nouveau_gpuobj_new(dev, NULL, 32768, 65536, 264 ret = nouveau_gpuobj_new(drm->device, NULL, 32768, 65536,
255 NVOBJ_FLAG_ZERO_ALLOC, &disp->ramin); 265 NVOBJ_FLAG_ZERO_ALLOC, &disp->ramin);
256 if (ret) { 266 if (ret) {
257 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret); 267 NV_ERROR(drm, "Error allocating EVO channel memory: %d\n", ret);
258 goto err; 268 goto err;
259 } 269 }
260 270
@@ -276,24 +286,24 @@ nv50_evo_create(struct drm_device *dev)
276 286
277 /* create some default objects for the scanout memtypes we support */ 287 /* create some default objects for the scanout memtypes we support */
278 ret = nv50_evo_dmaobj_new(disp->master, NvEvoVRAM, 0x0000, 288 ret = nv50_evo_dmaobj_new(disp->master, NvEvoVRAM, 0x0000,
279 0, nvfb_vram_size(dev), NULL); 289 0, pfb->ram.size, NULL);
280 if (ret) 290 if (ret)
281 goto err; 291 goto err;
282 292
283 ret = nv50_evo_dmaobj_new(disp->master, NvEvoVRAM_LP, 0x80000000, 293 ret = nv50_evo_dmaobj_new(disp->master, NvEvoVRAM_LP, 0x80000000,
284 0, nvfb_vram_size(dev), NULL); 294 0, pfb->ram.size, NULL);
285 if (ret) 295 if (ret)
286 goto err; 296 goto err;
287 297
288 ret = nv50_evo_dmaobj_new(disp->master, NvEvoFB32, 0x80000000 | 298 ret = nv50_evo_dmaobj_new(disp->master, NvEvoFB32, 0x80000000 |
289 (dev_priv->chipset < 0xc0 ? 0x7a : 0xfe), 299 (nv_device(drm->device)->chipset < 0xc0 ? 0x7a : 0xfe),
290 0, nvfb_vram_size(dev), NULL); 300 0, pfb->ram.size, NULL);
291 if (ret) 301 if (ret)
292 goto err; 302 goto err;
293 303
294 ret = nv50_evo_dmaobj_new(disp->master, NvEvoFB16, 0x80000000 | 304 ret = nv50_evo_dmaobj_new(disp->master, NvEvoFB16, 0x80000000 |
295 (dev_priv->chipset < 0xc0 ? 0x70 : 0xfe), 305 (nv_device(drm->device)->chipset < 0xc0 ? 0x70 : 0xfe),
296 0, nvfb_vram_size(dev), NULL); 306 0, pfb->ram.size, NULL);
297 if (ret) 307 if (ret)
298 goto err; 308 goto err;
299 309
@@ -328,21 +338,21 @@ nv50_evo_create(struct drm_device *dev)
328 goto err; 338 goto err;
329 339
330 ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoVRAM_LP, 0x80000000, 340 ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoVRAM_LP, 0x80000000,
331 0, nvfb_vram_size(dev), NULL); 341 0, pfb->ram.size, NULL);
332 if (ret) 342 if (ret)
333 goto err; 343 goto err;
334 344
335 ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoFB32, 0x80000000 | 345 ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoFB32, 0x80000000 |
336 (dev_priv->chipset < 0xc0 ? 346 (nv_device(drm->device)->chipset < 0xc0 ?
337 0x7a : 0xfe), 347 0x7a : 0xfe),
338 0, nvfb_vram_size(dev), NULL); 348 0, pfb->ram.size, NULL);
339 if (ret) 349 if (ret)
340 goto err; 350 goto err;
341 351
342 ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoFB16, 0x80000000 | 352 ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoFB16, 0x80000000 |
343 (dev_priv->chipset < 0xc0 ? 353 (nv_device(drm->device)->chipset < 0xc0 ?
344 0x70 : 0xfe), 354 0x70 : 0xfe),
345 0, nvfb_vram_size(dev), NULL); 355 0, pfb->ram.size, NULL);
346 if (ret) 356 if (ret)
347 goto err; 357 goto err;
348 358
diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c
index 2028a4447124..52068a0910dc 100644
--- a/drivers/gpu/drm/nouveau/nv50_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c
@@ -30,7 +30,7 @@ int
30nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 30nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
31{ 31{
32 struct nouveau_fbdev *nfbdev = info->par; 32 struct nouveau_fbdev *nfbdev = info->par;
33 struct nouveau_drm *drm = nouveau_newpriv(nfbdev->dev); 33 struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
34 struct nouveau_channel *chan = drm->channel; 34 struct nouveau_channel *chan = drm->channel;
35 int ret; 35 int ret;
36 36
@@ -65,7 +65,7 @@ int
65nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) 65nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
66{ 66{
67 struct nouveau_fbdev *nfbdev = info->par; 67 struct nouveau_fbdev *nfbdev = info->par;
68 struct nouveau_drm *drm = nouveau_newpriv(nfbdev->dev); 68 struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
69 struct nouveau_channel *chan = drm->channel; 69 struct nouveau_channel *chan = drm->channel;
70 int ret; 70 int ret;
71 71
@@ -93,7 +93,7 @@ int
93nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) 93nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
94{ 94{
95 struct nouveau_fbdev *nfbdev = info->par; 95 struct nouveau_fbdev *nfbdev = info->par;
96 struct nouveau_drm *drm = nouveau_newpriv(nfbdev->dev); 96 struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
97 struct nouveau_channel *chan = drm->channel; 97 struct nouveau_channel *chan = drm->channel;
98 uint32_t width, dwords, *data = (uint32_t *)image->data; 98 uint32_t width, dwords, *data = (uint32_t *)image->data;
99 uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel)); 99 uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel));
@@ -152,7 +152,7 @@ nv50_fbcon_accel_init(struct fb_info *info)
152 struct nouveau_fbdev *nfbdev = info->par; 152 struct nouveau_fbdev *nfbdev = info->par;
153 struct nouveau_framebuffer *fb = &nfbdev->nouveau_fb; 153 struct nouveau_framebuffer *fb = &nfbdev->nouveau_fb;
154 struct drm_device *dev = nfbdev->dev; 154 struct drm_device *dev = nfbdev->dev;
155 struct nouveau_drm *drm = nouveau_newpriv(dev); 155 struct nouveau_drm *drm = nouveau_drm(dev);
156 struct nouveau_channel *chan = drm->channel; 156 struct nouveau_channel *chan = drm->channel;
157 struct nouveau_object *object; 157 struct nouveau_object *object;
158 int ret, format; 158 int ret, format;
diff --git a/drivers/gpu/drm/nouveau/nv50_fence.c b/drivers/gpu/drm/nouveau/nv50_fence.c
index e717aaaf62c6..e0763ea88ee2 100644
--- a/drivers/gpu/drm/nouveau/nv50_fence.c
+++ b/drivers/gpu/drm/nouveau/nv50_fence.c
@@ -29,6 +29,8 @@
29#include "nouveau_dma.h" 29#include "nouveau_dma.h"
30#include "nouveau_fence.h" 30#include "nouveau_fence.h"
31 31
32#include "nv50_display.h"
33
32struct nv50_fence_chan { 34struct nv50_fence_chan {
33 struct nouveau_fence_chan base; 35 struct nouveau_fence_chan base;
34}; 36};
@@ -43,6 +45,7 @@ struct nv50_fence_priv {
43static int 45static int
44nv50_fence_context_new(struct nouveau_channel *chan) 46nv50_fence_context_new(struct nouveau_channel *chan)
45{ 47{
48 struct drm_device *dev = chan->drm->dev;
46 struct nv50_fence_priv *priv = chan->drm->fence; 49 struct nv50_fence_priv *priv = chan->drm->fence;
47 struct nv50_fence_chan *fctx; 50 struct nv50_fence_chan *fctx;
48 struct ttm_mem_reg *mem = &priv->bo->bo.mem; 51 struct ttm_mem_reg *mem = &priv->bo->bo.mem;
@@ -66,8 +69,8 @@ nv50_fence_context_new(struct nouveau_channel *chan)
66 &object); 69 &object);
67 70
68 /* dma objects for display sync channel semaphore blocks */ 71 /* dma objects for display sync channel semaphore blocks */
69 for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) { 72 for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) {
70 struct nouveau_bo *bo = nv50sema(chan->drm->dev, i); 73 struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i);
71 74
72 ret = nouveau_object_new(nv_object(chan->cli), chan->handle, 75 ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
73 NvEvoSema0 + i, 0x003d, 76 NvEvoSema0 + i, 0x003d,
diff --git a/drivers/gpu/drm/nouveau/nv50_pm.c b/drivers/gpu/drm/nouveau/nv50_pm.c
index ac0208438ace..0036c8c966de 100644
--- a/drivers/gpu/drm/nouveau/nv50_pm.c
+++ b/drivers/gpu/drm/nouveau/nv50_pm.c
@@ -23,12 +23,19 @@
23 */ 23 */
24 24
25#include "drmP.h" 25#include "drmP.h"
26#include "nouveau_drv.h" 26#include "nouveau_drm.h"
27#include <nouveau_bios.h> 27#include "nouveau_bios.h"
28#include "nouveau_hw.h" 28#include "nouveau_hw.h"
29#include "nouveau_pm.h" 29#include "nouveau_pm.h"
30#include "nouveau_hwsq.h" 30#include "nouveau_hwsq.h"
31 31
32#include "nv50_display.h"
33
34#include <subdev/bios/pll.h>
35#include <subdev/clock.h>
36#include <subdev/timer.h>
37#include <subdev/fb.h>
38
32enum clk_src { 39enum clk_src {
33 clk_src_crystal, 40 clk_src_crystal,
34 clk_src_href, 41 clk_src_href,
@@ -48,19 +55,20 @@ static u32 read_clk(struct drm_device *, enum clk_src);
48static u32 55static u32
49read_div(struct drm_device *dev) 56read_div(struct drm_device *dev)
50{ 57{
51 struct drm_nouveau_private *dev_priv = dev->dev_private; 58 struct nouveau_device *device = nouveau_dev(dev);
59 struct nouveau_drm *drm = nouveau_drm(dev);
52 60
53 switch (dev_priv->chipset) { 61 switch (nv_device(drm->device)->chipset) {
54 case 0x50: /* it exists, but only has bit 31, not the dividers.. */ 62 case 0x50: /* it exists, but only has bit 31, not the dividers.. */
55 case 0x84: 63 case 0x84:
56 case 0x86: 64 case 0x86:
57 case 0x98: 65 case 0x98:
58 case 0xa0: 66 case 0xa0:
59 return nv_rd32(dev, 0x004700); 67 return nv_rd32(device, 0x004700);
60 case 0x92: 68 case 0x92:
61 case 0x94: 69 case 0x94:
62 case 0x96: 70 case 0x96:
63 return nv_rd32(dev, 0x004800); 71 return nv_rd32(device, 0x004800);
64 default: 72 default:
65 return 0x00000000; 73 return 0x00000000;
66 } 74 }
@@ -69,12 +77,13 @@ read_div(struct drm_device *dev)
69static u32 77static u32
70read_pll_src(struct drm_device *dev, u32 base) 78read_pll_src(struct drm_device *dev, u32 base)
71{ 79{
72 struct drm_nouveau_private *dev_priv = dev->dev_private; 80 struct nouveau_device *device = nouveau_dev(dev);
81 struct nouveau_drm *drm = nouveau_drm(dev);
73 u32 coef, ref = read_clk(dev, clk_src_crystal); 82 u32 coef, ref = read_clk(dev, clk_src_crystal);
74 u32 rsel = nv_rd32(dev, 0x00e18c); 83 u32 rsel = nv_rd32(device, 0x00e18c);
75 int P, N, M, id; 84 int P, N, M, id;
76 85
77 switch (dev_priv->chipset) { 86 switch (nv_device(drm->device)->chipset) {
78 case 0x50: 87 case 0x50:
79 case 0xa0: 88 case 0xa0:
80 switch (base) { 89 switch (base) {
@@ -83,11 +92,11 @@ read_pll_src(struct drm_device *dev, u32 base)
83 case 0x4008: id = !!(rsel & 0x00000008); break; 92 case 0x4008: id = !!(rsel & 0x00000008); break;
84 case 0x4030: id = 0; break; 93 case 0x4030: id = 0; break;
85 default: 94 default:
86 NV_ERROR(dev, "ref: bad pll 0x%06x\n", base); 95 NV_ERROR(drm, "ref: bad pll 0x%06x\n", base);
87 return 0; 96 return 0;
88 } 97 }
89 98
90 coef = nv_rd32(dev, 0x00e81c + (id * 0x0c)); 99 coef = nv_rd32(device, 0x00e81c + (id * 0x0c));
91 ref *= (coef & 0x01000000) ? 2 : 4; 100 ref *= (coef & 0x01000000) ? 2 : 4;
92 P = (coef & 0x00070000) >> 16; 101 P = (coef & 0x00070000) >> 16;
93 N = ((coef & 0x0000ff00) >> 8) + 1; 102 N = ((coef & 0x0000ff00) >> 8) + 1;
@@ -96,7 +105,7 @@ read_pll_src(struct drm_device *dev, u32 base)
96 case 0x84: 105 case 0x84:
97 case 0x86: 106 case 0x86:
98 case 0x92: 107 case 0x92:
99 coef = nv_rd32(dev, 0x00e81c); 108 coef = nv_rd32(device, 0x00e81c);
100 P = (coef & 0x00070000) >> 16; 109 P = (coef & 0x00070000) >> 16;
101 N = (coef & 0x0000ff00) >> 8; 110 N = (coef & 0x0000ff00) >> 8;
102 M = (coef & 0x000000ff) >> 0; 111 M = (coef & 0x000000ff) >> 0;
@@ -104,14 +113,14 @@ read_pll_src(struct drm_device *dev, u32 base)
104 case 0x94: 113 case 0x94:
105 case 0x96: 114 case 0x96:
106 case 0x98: 115 case 0x98:
107 rsel = nv_rd32(dev, 0x00c050); 116 rsel = nv_rd32(device, 0x00c050);
108 switch (base) { 117 switch (base) {
109 case 0x4020: rsel = (rsel & 0x00000003) >> 0; break; 118 case 0x4020: rsel = (rsel & 0x00000003) >> 0; break;
110 case 0x4008: rsel = (rsel & 0x0000000c) >> 2; break; 119 case 0x4008: rsel = (rsel & 0x0000000c) >> 2; break;
111 case 0x4028: rsel = (rsel & 0x00001800) >> 11; break; 120 case 0x4028: rsel = (rsel & 0x00001800) >> 11; break;
112 case 0x4030: rsel = 3; break; 121 case 0x4030: rsel = 3; break;
113 default: 122 default:
114 NV_ERROR(dev, "ref: bad pll 0x%06x\n", base); 123 NV_ERROR(drm, "ref: bad pll 0x%06x\n", base);
115 return 0; 124 return 0;
116 } 125 }
117 126
@@ -122,8 +131,8 @@ read_pll_src(struct drm_device *dev, u32 base)
122 case 3: id = 0; break; 131 case 3: id = 0; break;
123 } 132 }
124 133
125 coef = nv_rd32(dev, 0x00e81c + (id * 0x28)); 134 coef = nv_rd32(device, 0x00e81c + (id * 0x28));
126 P = (nv_rd32(dev, 0x00e824 + (id * 0x28)) >> 16) & 7; 135 P = (nv_rd32(device, 0x00e824 + (id * 0x28)) >> 16) & 7;
127 P += (coef & 0x00070000) >> 16; 136 P += (coef & 0x00070000) >> 16;
128 N = (coef & 0x0000ff00) >> 8; 137 N = (coef & 0x0000ff00) >> 8;
129 M = (coef & 0x000000ff) >> 0; 138 M = (coef & 0x000000ff) >> 0;
@@ -140,7 +149,9 @@ read_pll_src(struct drm_device *dev, u32 base)
140static u32 149static u32
141read_pll_ref(struct drm_device *dev, u32 base) 150read_pll_ref(struct drm_device *dev, u32 base)
142{ 151{
143 u32 src, mast = nv_rd32(dev, 0x00c040); 152 struct nouveau_device *device = nouveau_dev(dev);
153 struct nouveau_drm *drm = nouveau_drm(dev);
154 u32 src, mast = nv_rd32(device, 0x00c040);
144 155
145 switch (base) { 156 switch (base) {
146 case 0x004028: 157 case 0x004028:
@@ -158,7 +169,7 @@ read_pll_ref(struct drm_device *dev, u32 base)
158 case 0x00e810: 169 case 0x00e810:
159 return read_clk(dev, clk_src_crystal); 170 return read_clk(dev, clk_src_crystal);
160 default: 171 default:
161 NV_ERROR(dev, "bad pll 0x%06x\n", base); 172 NV_ERROR(drm, "bad pll 0x%06x\n", base);
162 return 0; 173 return 0;
163 } 174 }
164 175
@@ -170,17 +181,18 @@ read_pll_ref(struct drm_device *dev, u32 base)
170static u32 181static u32
171read_pll(struct drm_device *dev, u32 base) 182read_pll(struct drm_device *dev, u32 base)
172{ 183{
173 struct drm_nouveau_private *dev_priv = dev->dev_private; 184 struct nouveau_device *device = nouveau_dev(dev);
174 u32 mast = nv_rd32(dev, 0x00c040); 185 struct nouveau_drm *drm = nouveau_drm(dev);
175 u32 ctrl = nv_rd32(dev, base + 0); 186 u32 mast = nv_rd32(device, 0x00c040);
176 u32 coef = nv_rd32(dev, base + 4); 187 u32 ctrl = nv_rd32(device, base + 0);
188 u32 coef = nv_rd32(device, base + 4);
177 u32 ref = read_pll_ref(dev, base); 189 u32 ref = read_pll_ref(dev, base);
178 u32 clk = 0; 190 u32 clk = 0;
179 int N1, N2, M1, M2; 191 int N1, N2, M1, M2;
180 192
181 if (base == 0x004028 && (mast & 0x00100000)) { 193 if (base == 0x004028 && (mast & 0x00100000)) {
182 /* wtf, appears to only disable post-divider on nva0 */ 194 /* wtf, appears to only disable post-divider on nva0 */
183 if (dev_priv->chipset != 0xa0) 195 if (nv_device(drm->device)->chipset != 0xa0)
184 return read_clk(dev, clk_src_dom6); 196 return read_clk(dev, clk_src_dom6);
185 } 197 }
186 198
@@ -204,13 +216,14 @@ read_pll(struct drm_device *dev, u32 base)
204static u32 216static u32
205read_clk(struct drm_device *dev, enum clk_src src) 217read_clk(struct drm_device *dev, enum clk_src src)
206{ 218{
207 struct drm_nouveau_private *dev_priv = dev->dev_private; 219 struct nouveau_device *device = nouveau_dev(dev);
208 u32 mast = nv_rd32(dev, 0x00c040); 220 struct nouveau_drm *drm = nouveau_drm(dev);
221 u32 mast = nv_rd32(device, 0x00c040);
209 u32 P = 0; 222 u32 P = 0;
210 223
211 switch (src) { 224 switch (src) {
212 case clk_src_crystal: 225 case clk_src_crystal:
213 return dev_priv->crystal; 226 return device->crystal;
214 case clk_src_href: 227 case clk_src_href:
215 return 100000; /* PCIE reference clock */ 228 return 100000; /* PCIE reference clock */
216 case clk_src_hclk: 229 case clk_src_hclk:
@@ -229,7 +242,7 @@ read_clk(struct drm_device *dev, enum clk_src src)
229 break; 242 break;
230 case clk_src_nvclk: 243 case clk_src_nvclk:
231 if (!(mast & 0x00100000)) 244 if (!(mast & 0x00100000))
232 P = (nv_rd32(dev, 0x004028) & 0x00070000) >> 16; 245 P = (nv_rd32(device, 0x004028) & 0x00070000) >> 16;
233 switch (mast & 0x00000003) { 246 switch (mast & 0x00000003) {
234 case 0x00000000: return read_clk(dev, clk_src_crystal) >> P; 247 case 0x00000000: return read_clk(dev, clk_src_crystal) >> P;
235 case 0x00000001: return read_clk(dev, clk_src_dom6); 248 case 0x00000001: return read_clk(dev, clk_src_dom6);
@@ -238,7 +251,7 @@ read_clk(struct drm_device *dev, enum clk_src src)
238 } 251 }
239 break; 252 break;
240 case clk_src_sclk: 253 case clk_src_sclk:
241 P = (nv_rd32(dev, 0x004020) & 0x00070000) >> 16; 254 P = (nv_rd32(device, 0x004020) & 0x00070000) >> 16;
242 switch (mast & 0x00000030) { 255 switch (mast & 0x00000030) {
243 case 0x00000000: 256 case 0x00000000:
244 if (mast & 0x00000080) 257 if (mast & 0x00000080)
@@ -250,8 +263,8 @@ read_clk(struct drm_device *dev, enum clk_src src)
250 } 263 }
251 break; 264 break;
252 case clk_src_mclk: 265 case clk_src_mclk:
253 P = (nv_rd32(dev, 0x004008) & 0x00070000) >> 16; 266 P = (nv_rd32(device, 0x004008) & 0x00070000) >> 16;
254 if (nv_rd32(dev, 0x004008) & 0x00000200) { 267 if (nv_rd32(device, 0x004008) & 0x00000200) {
255 switch (mast & 0x0000c000) { 268 switch (mast & 0x0000c000) {
256 case 0x00000000: 269 case 0x00000000:
257 return read_clk(dev, clk_src_crystal) >> P; 270 return read_clk(dev, clk_src_crystal) >> P;
@@ -265,7 +278,7 @@ read_clk(struct drm_device *dev, enum clk_src src)
265 break; 278 break;
266 case clk_src_vdec: 279 case clk_src_vdec:
267 P = (read_div(dev) & 0x00000700) >> 8; 280 P = (read_div(dev) & 0x00000700) >> 8;
268 switch (dev_priv->chipset) { 281 switch (nv_device(drm->device)->chipset) {
269 case 0x84: 282 case 0x84:
270 case 0x86: 283 case 0x86:
271 case 0x92: 284 case 0x92:
@@ -274,7 +287,7 @@ read_clk(struct drm_device *dev, enum clk_src src)
274 case 0xa0: 287 case 0xa0:
275 switch (mast & 0x00000c00) { 288 switch (mast & 0x00000c00) {
276 case 0x00000000: 289 case 0x00000000:
277 if (dev_priv->chipset == 0xa0) /* wtf?? */ 290 if (nv_device(drm->device)->chipset == 0xa0) /* wtf?? */
278 return read_clk(dev, clk_src_nvclk) >> P; 291 return read_clk(dev, clk_src_nvclk) >> P;
279 return read_clk(dev, clk_src_crystal) >> P; 292 return read_clk(dev, clk_src_crystal) >> P;
280 case 0x00000400: 293 case 0x00000400:
@@ -302,7 +315,7 @@ read_clk(struct drm_device *dev, enum clk_src src)
302 } 315 }
303 break; 316 break;
304 case clk_src_dom6: 317 case clk_src_dom6:
305 switch (dev_priv->chipset) { 318 switch (nv_device(drm->device)->chipset) {
306 case 0x50: 319 case 0x50:
307 case 0xa0: 320 case 0xa0:
308 return read_pll(dev, 0x00e810) >> 2; 321 return read_pll(dev, 0x00e810) >> 2;
@@ -328,22 +341,22 @@ read_clk(struct drm_device *dev, enum clk_src src)
328 break; 341 break;
329 } 342 }
330 343
331 NV_DEBUG(dev, "unknown clock source %d 0x%08x\n", src, mast); 344 NV_DEBUG(drm, "unknown clock source %d 0x%08x\n", src, mast);
332 return 0; 345 return 0;
333} 346}
334 347
335int 348int
336nv50_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl) 349nv50_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl)
337{ 350{
338 struct drm_nouveau_private *dev_priv = dev->dev_private; 351 struct nouveau_drm *drm = nouveau_drm(dev);
339 if (dev_priv->chipset == 0xaa || 352 if (nv_device(drm->device)->chipset == 0xaa ||
340 dev_priv->chipset == 0xac) 353 nv_device(drm->device)->chipset == 0xac)
341 return 0; 354 return 0;
342 355
343 perflvl->core = read_clk(dev, clk_src_nvclk); 356 perflvl->core = read_clk(dev, clk_src_nvclk);
344 perflvl->shader = read_clk(dev, clk_src_sclk); 357 perflvl->shader = read_clk(dev, clk_src_sclk);
345 perflvl->memory = read_clk(dev, clk_src_mclk); 358 perflvl->memory = read_clk(dev, clk_src_mclk);
346 if (dev_priv->chipset != 0x50) { 359 if (nv_device(drm->device)->chipset != 0x50) {
347 perflvl->vdec = read_clk(dev, clk_src_vdec); 360 perflvl->vdec = read_clk(dev, clk_src_vdec);
348 perflvl->dom6 = read_clk(dev, clk_src_dom6); 361 perflvl->dom6 = read_clk(dev, clk_src_dom6);
349 } 362 }
@@ -365,10 +378,13 @@ static u32
365calc_pll(struct drm_device *dev, u32 reg, struct nvbios_pll *pll, 378calc_pll(struct drm_device *dev, u32 reg, struct nvbios_pll *pll,
366 u32 clk, int *N1, int *M1, int *log2P) 379 u32 clk, int *N1, int *M1, int *log2P)
367{ 380{
381 struct nouveau_device *device = nouveau_dev(dev);
382 struct nouveau_bios *bios = nouveau_bios(device);
383 struct nouveau_clock *pclk = nouveau_clock(device);
368 struct nouveau_pll_vals coef; 384 struct nouveau_pll_vals coef;
369 int ret; 385 int ret;
370 386
371 ret = get_pll_limits(dev, reg, pll); 387 ret = nvbios_pll_parse(bios, reg, pll);
372 if (ret) 388 if (ret)
373 return 0; 389 return 0;
374 390
@@ -377,7 +393,7 @@ calc_pll(struct drm_device *dev, u32 reg, struct nvbios_pll *pll,
377 if (!pll->refclk) 393 if (!pll->refclk)
378 return 0; 394 return 0;
379 395
380 ret = nouveau_calc_pll_mnp(dev, pll, clk, &coef); 396 ret = pclk->pll_calc(pclk, pll, clk, &coef);
381 if (ret == 0) 397 if (ret == 0)
382 return 0; 398 return 0;
383 399
@@ -460,26 +476,29 @@ mclk_wait(struct nouveau_mem_exec_func *exec, u32 nsec)
460static u32 476static u32
461mclk_mrg(struct nouveau_mem_exec_func *exec, int mr) 477mclk_mrg(struct nouveau_mem_exec_func *exec, int mr)
462{ 478{
479 struct nouveau_device *device = nouveau_dev(exec->dev);
463 if (mr <= 1) 480 if (mr <= 1)
464 return nv_rd32(exec->dev, 0x1002c0 + ((mr - 0) * 4)); 481 return nv_rd32(device, 0x1002c0 + ((mr - 0) * 4));
465 if (mr <= 3) 482 if (mr <= 3)
466 return nv_rd32(exec->dev, 0x1002e0 + ((mr - 2) * 4)); 483 return nv_rd32(device, 0x1002e0 + ((mr - 2) * 4));
467 return 0; 484 return 0;
468} 485}
469 486
470static void 487static void
471mclk_mrs(struct nouveau_mem_exec_func *exec, int mr, u32 data) 488mclk_mrs(struct nouveau_mem_exec_func *exec, int mr, u32 data)
472{ 489{
490 struct nouveau_device *device = nouveau_dev(exec->dev);
491 struct nouveau_fb *pfb = nouveau_fb(device);
473 struct nv50_pm_state *info = exec->priv; 492 struct nv50_pm_state *info = exec->priv;
474 struct hwsq_ucode *hwsq = &info->mclk_hwsq; 493 struct hwsq_ucode *hwsq = &info->mclk_hwsq;
475 494
476 if (mr <= 1) { 495 if (mr <= 1) {
477 if (nvfb_vram_rank_B(exec->dev)) 496 if (pfb->ram.ranks > 1)
478 hwsq_wr32(hwsq, 0x1002c8 + ((mr - 0) * 4), data); 497 hwsq_wr32(hwsq, 0x1002c8 + ((mr - 0) * 4), data);
479 hwsq_wr32(hwsq, 0x1002c0 + ((mr - 0) * 4), data); 498 hwsq_wr32(hwsq, 0x1002c0 + ((mr - 0) * 4), data);
480 } else 499 } else
481 if (mr <= 3) { 500 if (mr <= 3) {
482 if (nvfb_vram_rank_B(exec->dev)) 501 if (pfb->ram.ranks > 1)
483 hwsq_wr32(hwsq, 0x1002e8 + ((mr - 2) * 4), data); 502 hwsq_wr32(hwsq, 0x1002e8 + ((mr - 2) * 4), data);
484 hwsq_wr32(hwsq, 0x1002e0 + ((mr - 2) * 4), data); 503 hwsq_wr32(hwsq, 0x1002e0 + ((mr - 2) * 4), data);
485 } 504 }
@@ -488,11 +507,12 @@ mclk_mrs(struct nouveau_mem_exec_func *exec, int mr, u32 data)
488static void 507static void
489mclk_clock_set(struct nouveau_mem_exec_func *exec) 508mclk_clock_set(struct nouveau_mem_exec_func *exec)
490{ 509{
510 struct nouveau_device *device = nouveau_dev(exec->dev);
491 struct nv50_pm_state *info = exec->priv; 511 struct nv50_pm_state *info = exec->priv;
492 struct hwsq_ucode *hwsq = &info->mclk_hwsq; 512 struct hwsq_ucode *hwsq = &info->mclk_hwsq;
493 u32 ctrl = nv_rd32(exec->dev, 0x004008); 513 u32 ctrl = nv_rd32(device, 0x004008);
494 514
495 info->mmast = nv_rd32(exec->dev, 0x00c040); 515 info->mmast = nv_rd32(device, 0x00c040);
496 info->mmast &= ~0xc0000000; /* get MCLK_2 from HREF */ 516 info->mmast &= ~0xc0000000; /* get MCLK_2 from HREF */
497 info->mmast |= 0x0000c000; /* use MCLK_2 as MPLL_BYPASS clock */ 517 info->mmast |= 0x0000c000; /* use MCLK_2 as MPLL_BYPASS clock */
498 518
@@ -506,7 +526,7 @@ mclk_clock_set(struct nouveau_mem_exec_func *exec)
506static void 526static void
507mclk_timing_set(struct nouveau_mem_exec_func *exec) 527mclk_timing_set(struct nouveau_mem_exec_func *exec)
508{ 528{
509 struct drm_device *dev = exec->dev; 529 struct nouveau_device *device = nouveau_dev(exec->dev);
510 struct nv50_pm_state *info = exec->priv; 530 struct nv50_pm_state *info = exec->priv;
511 struct nouveau_pm_level *perflvl = info->perflvl; 531 struct nouveau_pm_level *perflvl = info->perflvl;
512 struct hwsq_ucode *hwsq = &info->mclk_hwsq; 532 struct hwsq_ucode *hwsq = &info->mclk_hwsq;
@@ -514,7 +534,7 @@ mclk_timing_set(struct nouveau_mem_exec_func *exec)
514 534
515 for (i = 0; i < 9; i++) { 535 for (i = 0; i < 9; i++) {
516 u32 reg = 0x100220 + (i * 4); 536 u32 reg = 0x100220 + (i * 4);
517 u32 val = nv_rd32(dev, reg); 537 u32 val = nv_rd32(device, reg);
518 if (val != perflvl->timing.reg[i]) 538 if (val != perflvl->timing.reg[i])
519 hwsq_wr32(hwsq, reg, perflvl->timing.reg[i]); 539 hwsq_wr32(hwsq, reg, perflvl->timing.reg[i]);
520 } 540 }
@@ -524,7 +544,8 @@ static int
524calc_mclk(struct drm_device *dev, struct nouveau_pm_level *perflvl, 544calc_mclk(struct drm_device *dev, struct nouveau_pm_level *perflvl,
525 struct nv50_pm_state *info) 545 struct nv50_pm_state *info)
526{ 546{
527 struct drm_nouveau_private *dev_priv = dev->dev_private; 547 struct nouveau_drm *drm = nouveau_drm(dev);
548 struct nouveau_device *device = nouveau_dev(dev);
528 u32 crtc_mask = nv50_display_active_crtcs(dev); 549 u32 crtc_mask = nv50_display_active_crtcs(dev);
529 struct nouveau_mem_exec_func exec = { 550 struct nouveau_mem_exec_func exec = {
530 .dev = dev, 551 .dev = dev,
@@ -545,7 +566,7 @@ calc_mclk(struct drm_device *dev, struct nouveau_pm_level *perflvl,
545 int ret; 566 int ret;
546 567
547 /* use pcie refclock if possible, otherwise use mpll */ 568 /* use pcie refclock if possible, otherwise use mpll */
548 info->mctrl = nv_rd32(dev, 0x004008); 569 info->mctrl = nv_rd32(device, 0x004008);
549 info->mctrl &= ~0x81ff0200; 570 info->mctrl &= ~0x81ff0200;
550 if (clk_same(perflvl->memory, read_clk(dev, clk_src_href))) { 571 if (clk_same(perflvl->memory, read_clk(dev, clk_src_href))) {
551 info->mctrl |= 0x00000200 | (pll.bias_p << 19); 572 info->mctrl |= 0x00000200 | (pll.bias_p << 19);
@@ -565,7 +586,7 @@ calc_mclk(struct drm_device *dev, struct nouveau_pm_level *perflvl,
565 hwsq_op5f(hwsq, crtc_mask, 0x00); /* wait for scanout */ 586 hwsq_op5f(hwsq, crtc_mask, 0x00); /* wait for scanout */
566 hwsq_op5f(hwsq, crtc_mask, 0x01); /* wait for vblank */ 587 hwsq_op5f(hwsq, crtc_mask, 0x01); /* wait for vblank */
567 } 588 }
568 if (dev_priv->chipset >= 0x92) 589 if (nv_device(drm->device)->chipset >= 0x92)
569 hwsq_wr32(hwsq, 0x611200, 0x00003300); /* disable scanout */ 590 hwsq_wr32(hwsq, 0x611200, 0x00003300); /* disable scanout */
570 hwsq_setf(hwsq, 0x10, 0); /* disable bus access */ 591 hwsq_setf(hwsq, 0x10, 0); /* disable bus access */
571 hwsq_op5f(hwsq, 0x00, 0x01); /* no idea :s */ 592 hwsq_op5f(hwsq, 0x00, 0x01); /* no idea :s */
@@ -576,7 +597,7 @@ calc_mclk(struct drm_device *dev, struct nouveau_pm_level *perflvl,
576 597
577 hwsq_setf(hwsq, 0x10, 1); /* enable bus access */ 598 hwsq_setf(hwsq, 0x10, 1); /* enable bus access */
578 hwsq_op5f(hwsq, 0x00, 0x00); /* no idea, reverse of 0x00, 0x01? */ 599 hwsq_op5f(hwsq, 0x00, 0x00); /* no idea, reverse of 0x00, 0x01? */
579 if (dev_priv->chipset >= 0x92) 600 if (nv_device(drm->device)->chipset >= 0x92)
580 hwsq_wr32(hwsq, 0x611200, 0x00003330); /* enable scanout */ 601 hwsq_wr32(hwsq, 0x611200, 0x00003330); /* enable scanout */
581 hwsq_fini(hwsq); 602 hwsq_fini(hwsq);
582 return 0; 603 return 0;
@@ -585,7 +606,8 @@ calc_mclk(struct drm_device *dev, struct nouveau_pm_level *perflvl,
585void * 606void *
586nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl) 607nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
587{ 608{
588 struct drm_nouveau_private *dev_priv = dev->dev_private; 609 struct nouveau_device *device = nouveau_dev(dev);
610 struct nouveau_drm *drm = nouveau_drm(dev);
589 struct nv50_pm_state *info; 611 struct nv50_pm_state *info;
590 struct hwsq_ucode *hwsq; 612 struct hwsq_ucode *hwsq;
591 struct nvbios_pll pll; 613 struct nvbios_pll pll;
@@ -593,8 +615,8 @@ nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
593 int clk, ret = -EINVAL; 615 int clk, ret = -EINVAL;
594 int N, M, P1, P2; 616 int N, M, P1, P2;
595 617
596 if (dev_priv->chipset == 0xaa || 618 if (nv_device(drm->device)->chipset == 0xaa ||
597 dev_priv->chipset == 0xac) 619 nv_device(drm->device)->chipset == 0xac)
598 return ERR_PTR(-ENODEV); 620 return ERR_PTR(-ENODEV);
599 621
600 info = kmalloc(sizeof(*info), GFP_KERNEL); 622 info = kmalloc(sizeof(*info), GFP_KERNEL);
@@ -643,7 +665,7 @@ nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
643 clk = calc_div(perflvl->core, perflvl->vdec, &P1); 665 clk = calc_div(perflvl->core, perflvl->vdec, &P1);
644 666
645 /* see how close we can get using xpll/hclk as a source */ 667 /* see how close we can get using xpll/hclk as a source */
646 if (dev_priv->chipset != 0x98) 668 if (nv_device(drm->device)->chipset != 0x98)
647 out = read_pll(dev, 0x004030); 669 out = read_pll(dev, 0x004030);
648 else 670 else
649 out = read_clk(dev, clk_src_hclkm3d2); 671 out = read_clk(dev, clk_src_hclkm3d2);
@@ -652,7 +674,7 @@ nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
652 /* select whichever gets us closest */ 674 /* select whichever gets us closest */
653 if (abs((int)perflvl->vdec - clk) <= 675 if (abs((int)perflvl->vdec - clk) <=
654 abs((int)perflvl->vdec - out)) { 676 abs((int)perflvl->vdec - out)) {
655 if (dev_priv->chipset != 0x98) 677 if (nv_device(drm->device)->chipset != 0x98)
656 mast |= 0x00000c00; 678 mast |= 0x00000c00;
657 divs |= P1 << 8; 679 divs |= P1 << 8;
658 } else { 680 } else {
@@ -680,7 +702,7 @@ nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
680 } 702 }
681 703
682 /* vdec/dom6: complete switch to new clocks */ 704 /* vdec/dom6: complete switch to new clocks */
683 switch (dev_priv->chipset) { 705 switch (nv_device(drm->device)->chipset) {
684 case 0x92: 706 case 0x92:
685 case 0x94: 707 case 0x94:
686 case 0x96: 708 case 0x96:
@@ -696,7 +718,7 @@ nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
696 /* core/shader: make sure sclk/nvclk are disconnected from their 718 /* core/shader: make sure sclk/nvclk are disconnected from their
697 * PLLs (nvclk to dom6, sclk to hclk) 719 * PLLs (nvclk to dom6, sclk to hclk)
698 */ 720 */
699 if (dev_priv->chipset < 0x92) 721 if (nv_device(drm->device)->chipset < 0x92)
700 mast = (mast & ~0x001000b0) | 0x00100080; 722 mast = (mast & ~0x001000b0) | 0x00100080;
701 else 723 else
702 mast = (mast & ~0x000000b3) | 0x00000081; 724 mast = (mast & ~0x000000b3) | 0x00000081;
@@ -708,7 +730,7 @@ nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
708 if (clk == 0) 730 if (clk == 0)
709 goto error; 731 goto error;
710 732
711 ctrl = nv_rd32(dev, 0x004028) & ~0xc03f0100; 733 ctrl = nv_rd32(device, 0x004028) & ~0xc03f0100;
712 mast &= ~0x00100000; 734 mast &= ~0x00100000;
713 mast |= 3; 735 mast |= 3;
714 736
@@ -721,7 +743,7 @@ nv50_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
721 * cases will be handled by tying to nvclk, but it's possible there's 743 * cases will be handled by tying to nvclk, but it's possible there's
722 * corners 744 * corners
723 */ 745 */
724 ctrl = nv_rd32(dev, 0x004020) & ~0xc03f0100; 746 ctrl = nv_rd32(device, 0x004020) & ~0xc03f0100;
725 747
726 if (P1-- && perflvl->shader == (perflvl->core << 1)) { 748 if (P1-- && perflvl->shader == (perflvl->core << 1)) {
727 hwsq_wr32(hwsq, 0x004020, (P1 << 19) | (P1 << 16) | ctrl); 749 hwsq_wr32(hwsq, 0x004020, (P1 << 19) | (P1 << 16) | ctrl);
@@ -750,11 +772,12 @@ error:
750static int 772static int
751prog_hwsq(struct drm_device *dev, struct hwsq_ucode *hwsq) 773prog_hwsq(struct drm_device *dev, struct hwsq_ucode *hwsq)
752{ 774{
753 struct drm_nouveau_private *dev_priv = dev->dev_private; 775 struct nouveau_device *device = nouveau_dev(dev);
776 struct nouveau_drm *drm = nouveau_drm(dev);
754 u32 hwsq_data, hwsq_kick; 777 u32 hwsq_data, hwsq_kick;
755 int i; 778 int i;
756 779
757 if (dev_priv->chipset < 0x94) { 780 if (nv_device(drm->device)->chipset < 0x94) {
758 hwsq_data = 0x001400; 781 hwsq_data = 0x001400;
759 hwsq_kick = 0x00000003; 782 hwsq_kick = 0x00000003;
760 } else { 783 } else {
@@ -762,22 +785,22 @@ prog_hwsq(struct drm_device *dev, struct hwsq_ucode *hwsq)
762 hwsq_kick = 0x00000001; 785 hwsq_kick = 0x00000001;
763 } 786 }
764 /* upload hwsq ucode */ 787 /* upload hwsq ucode */
765 nv_mask(dev, 0x001098, 0x00000008, 0x00000000); 788 nv_mask(device, 0x001098, 0x00000008, 0x00000000);
766 nv_wr32(dev, 0x001304, 0x00000000); 789 nv_wr32(device, 0x001304, 0x00000000);
767 if (dev_priv->chipset >= 0x92) 790 if (nv_device(drm->device)->chipset >= 0x92)
768 nv_wr32(dev, 0x001318, 0x00000000); 791 nv_wr32(device, 0x001318, 0x00000000);
769 for (i = 0; i < hwsq->len / 4; i++) 792 for (i = 0; i < hwsq->len / 4; i++)
770 nv_wr32(dev, hwsq_data + (i * 4), hwsq->ptr.u32[i]); 793 nv_wr32(device, hwsq_data + (i * 4), hwsq->ptr.u32[i]);
771 nv_mask(dev, 0x001098, 0x00000018, 0x00000018); 794 nv_mask(device, 0x001098, 0x00000018, 0x00000018);
772 795
773 /* launch, and wait for completion */ 796 /* launch, and wait for completion */
774 nv_wr32(dev, 0x00130c, hwsq_kick); 797 nv_wr32(device, 0x00130c, hwsq_kick);
775 if (!nv_wait(dev, 0x001308, 0x00000100, 0x00000000)) { 798 if (!nv_wait(device, 0x001308, 0x00000100, 0x00000000)) {
776 NV_ERROR(dev, "hwsq ucode exec timed out\n"); 799 NV_ERROR(drm, "hwsq ucode exec timed out\n");
777 NV_ERROR(dev, "0x001308: 0x%08x\n", nv_rd32(dev, 0x001308)); 800 NV_ERROR(drm, "0x001308: 0x%08x\n", nv_rd32(device, 0x001308));
778 for (i = 0; i < hwsq->len / 4; i++) { 801 for (i = 0; i < hwsq->len / 4; i++) {
779 NV_ERROR(dev, "0x%06x: 0x%08x\n", 0x1400 + (i * 4), 802 NV_ERROR(drm, "0x%06x: 0x%08x\n", 0x1400 + (i * 4),
780 nv_rd32(dev, 0x001400 + (i * 4))); 803 nv_rd32(device, 0x001400 + (i * 4)));
781 } 804 }
782 805
783 return -EIO; 806 return -EIO;
@@ -789,20 +812,22 @@ prog_hwsq(struct drm_device *dev, struct hwsq_ucode *hwsq)
789int 812int
790nv50_pm_clocks_set(struct drm_device *dev, void *data) 813nv50_pm_clocks_set(struct drm_device *dev, void *data)
791{ 814{
815 struct nouveau_device *device = nouveau_dev(dev);
792 struct nv50_pm_state *info = data; 816 struct nv50_pm_state *info = data;
793 struct bit_entry M; 817 struct bit_entry M;
794 int ret = -EBUSY; 818 int ret = -EBUSY;
795 819
796 /* halt and idle execution engines */ 820 /* halt and idle execution engines */
797 nv_mask(dev, 0x002504, 0x00000001, 0x00000001); 821 nv_mask(device, 0x002504, 0x00000001, 0x00000001);
798 if (!nv_wait(dev, 0x002504, 0x00000010, 0x00000010)) 822 if (!nv_wait(device, 0x002504, 0x00000010, 0x00000010))
799 goto resume; 823 goto resume;
800 if (!nv_wait(dev, 0x00251c, 0x0000003f, 0x0000003f)) 824 if (!nv_wait(device, 0x00251c, 0x0000003f, 0x0000003f))
801 goto resume; 825 goto resume;
802 826
803 /* program memory clock, if necessary - must come before engine clock 827 /* program memory clock, if necessary - must come before engine clock
804 * reprogramming due to how we construct the hwsq scripts in pre() 828 * reprogramming due to how we construct the hwsq scripts in pre()
805 */ 829 */
830#define nouveau_bios_init_exec(a,b) nouveau_bios_run_init_table((a), (b), NULL, 0)
806 if (info->mclk_hwsq.len) { 831 if (info->mclk_hwsq.len) {
807 /* execute some scripts that do ??? from the vbios.. */ 832 /* execute some scripts that do ??? from the vbios.. */
808 if (!bit_table(dev, 'M', &M) && M.version == 1) { 833 if (!bit_table(dev, 'M', &M) && M.version == 1) {
@@ -824,7 +849,7 @@ nv50_pm_clocks_set(struct drm_device *dev, void *data)
824 ret = prog_hwsq(dev, &info->eclk_hwsq); 849 ret = prog_hwsq(dev, &info->eclk_hwsq);
825 850
826resume: 851resume:
827 nv_mask(dev, 0x002504, 0x00000001, 0x00000000); 852 nv_mask(device, 0x002504, 0x00000001, 0x00000000);
828 kfree(info); 853 kfree(info);
829 return ret; 854 return ret;
830} 855}
@@ -832,6 +857,8 @@ resume:
832static int 857static int
833pwm_info(struct drm_device *dev, int *line, int *ctrl, int *indx) 858pwm_info(struct drm_device *dev, int *line, int *ctrl, int *indx)
834{ 859{
860 struct nouveau_drm *drm = nouveau_drm(dev);
861
835 if (*line == 0x04) { 862 if (*line == 0x04) {
836 *ctrl = 0x00e100; 863 *ctrl = 0x00e100;
837 *line = 4; 864 *line = 4;
@@ -847,7 +874,7 @@ pwm_info(struct drm_device *dev, int *line, int *ctrl, int *indx)
847 *line = 0; 874 *line = 0;
848 *indx = 0; 875 *indx = 0;
849 } else { 876 } else {
850 NV_ERROR(dev, "unknown pwm ctrl for gpio %d\n", *line); 877 NV_ERROR(drm, "unknown pwm ctrl for gpio %d\n", *line);
851 return -ENODEV; 878 return -ENODEV;
852 } 879 }
853 880
@@ -857,13 +884,14 @@ pwm_info(struct drm_device *dev, int *line, int *ctrl, int *indx)
857int 884int
858nv50_pm_pwm_get(struct drm_device *dev, int line, u32 *divs, u32 *duty) 885nv50_pm_pwm_get(struct drm_device *dev, int line, u32 *divs, u32 *duty)
859{ 886{
887 struct nouveau_device *device = nouveau_dev(dev);
860 int ctrl, id, ret = pwm_info(dev, &line, &ctrl, &id); 888 int ctrl, id, ret = pwm_info(dev, &line, &ctrl, &id);
861 if (ret) 889 if (ret)
862 return ret; 890 return ret;
863 891
864 if (nv_rd32(dev, ctrl) & (1 << line)) { 892 if (nv_rd32(device, ctrl) & (1 << line)) {
865 *divs = nv_rd32(dev, 0x00e114 + (id * 8)); 893 *divs = nv_rd32(device, 0x00e114 + (id * 8));
866 *duty = nv_rd32(dev, 0x00e118 + (id * 8)); 894 *duty = nv_rd32(device, 0x00e118 + (id * 8));
867 return 0; 895 return 0;
868 } 896 }
869 897
@@ -873,12 +901,13 @@ nv50_pm_pwm_get(struct drm_device *dev, int line, u32 *divs, u32 *duty)
873int 901int
874nv50_pm_pwm_set(struct drm_device *dev, int line, u32 divs, u32 duty) 902nv50_pm_pwm_set(struct drm_device *dev, int line, u32 divs, u32 duty)
875{ 903{
904 struct nouveau_device *device = nouveau_dev(dev);
876 int ctrl, id, ret = pwm_info(dev, &line, &ctrl, &id); 905 int ctrl, id, ret = pwm_info(dev, &line, &ctrl, &id);
877 if (ret) 906 if (ret)
878 return ret; 907 return ret;
879 908
880 nv_mask(dev, ctrl, 0x00010001 << line, 0x00000001 << line); 909 nv_mask(device, ctrl, 0x00010001 << line, 0x00000001 << line);
881 nv_wr32(dev, 0x00e114 + (id * 8), divs); 910 nv_wr32(device, 0x00e114 + (id * 8), divs);
882 nv_wr32(dev, 0x00e118 + (id * 8), duty | 0x80000000); 911 nv_wr32(device, 0x00e118 + (id * 8), duty | 0x80000000);
883 return 0; 912 return 0;
884} 913}
diff --git a/drivers/gpu/drm/nouveau/nv50_sor.c b/drivers/gpu/drm/nouveau/nv50_sor.c
index 2e6d83b37a0f..48644e379e86 100644
--- a/drivers/gpu/drm/nouveau/nv50_sor.c
+++ b/drivers/gpu/drm/nouveau/nv50_sor.c
@@ -29,20 +29,22 @@
29 29
30#define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO) 30#define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
31#include "nouveau_reg.h" 31#include "nouveau_reg.h"
32#include "nouveau_drv.h" 32#include "nouveau_drm.h"
33#include "nouveau_dma.h" 33#include "nouveau_dma.h"
34#include "nouveau_encoder.h" 34#include "nouveau_encoder.h"
35#include "nouveau_connector.h" 35#include "nouveau_connector.h"
36#include "nouveau_crtc.h" 36#include "nouveau_crtc.h"
37#include "nv50_display.h" 37#include "nv50_display.h"
38 38
39#include <subdev/timer.h>
40
39static u32 41static u32
40nv50_sor_dp_lane_map(struct drm_device *dev, struct dcb_output *dcb, u8 lane) 42nv50_sor_dp_lane_map(struct drm_device *dev, struct dcb_output *dcb, u8 lane)
41{ 43{
42 struct drm_nouveau_private *dev_priv = dev->dev_private; 44 struct nouveau_drm *drm = nouveau_drm(dev);
43 static const u8 nvaf[] = { 24, 16, 8, 0 }; /* thanks, apple.. */ 45 static const u8 nvaf[] = { 24, 16, 8, 0 }; /* thanks, apple.. */
44 static const u8 nv50[] = { 16, 8, 0, 24 }; 46 static const u8 nv50[] = { 16, 8, 0, 24 };
45 if (dev_priv->chipset == 0xaf) 47 if (nv_device(drm->device)->chipset == 0xaf)
46 return nvaf[lane]; 48 return nvaf[lane];
47 return nv50[lane]; 49 return nv50[lane];
48} 50}
@@ -50,14 +52,17 @@ nv50_sor_dp_lane_map(struct drm_device *dev, struct dcb_output *dcb, u8 lane)
50static void 52static void
51nv50_sor_dp_train_set(struct drm_device *dev, struct dcb_output *dcb, u8 pattern) 53nv50_sor_dp_train_set(struct drm_device *dev, struct dcb_output *dcb, u8 pattern)
52{ 54{
55 struct nouveau_device *device = nouveau_dev(dev);
53 u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1); 56 u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
54 nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x0f000000, pattern << 24); 57 nv_mask(device, NV50_SOR_DP_CTRL(or, link), 0x0f000000, pattern << 24);
55} 58}
56 59
57static void 60static void
58nv50_sor_dp_train_adj(struct drm_device *dev, struct dcb_output *dcb, 61nv50_sor_dp_train_adj(struct drm_device *dev, struct dcb_output *dcb,
59 u8 lane, u8 swing, u8 preem) 62 u8 lane, u8 swing, u8 preem)
60{ 63{
64 struct nouveau_device *device = nouveau_dev(dev);
65 struct nouveau_drm *drm = nouveau_drm(dev);
61 u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1); 66 u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
62 u32 shift = nv50_sor_dp_lane_map(dev, dcb, lane); 67 u32 shift = nv50_sor_dp_lane_map(dev, dcb, lane);
63 u32 mask = 0x000000ff << shift; 68 u32 mask = 0x000000ff << shift;
@@ -65,7 +70,7 @@ nv50_sor_dp_train_adj(struct drm_device *dev, struct dcb_output *dcb,
65 70
66 table = nouveau_dp_bios_data(dev, dcb, &entry); 71 table = nouveau_dp_bios_data(dev, dcb, &entry);
67 if (!table || (table[0] != 0x20 && table[0] != 0x21)) { 72 if (!table || (table[0] != 0x20 && table[0] != 0x21)) {
68 NV_ERROR(dev, "PDISP: unsupported DP table for chipset\n"); 73 NV_ERROR(drm, "PDISP: unsupported DP table for chipset\n");
69 return; 74 return;
70 } 75 }
71 76
@@ -76,24 +81,26 @@ nv50_sor_dp_train_adj(struct drm_device *dev, struct dcb_output *dcb,
76 return; 81 return;
77 } 82 }
78 83
79 nv_mask(dev, NV50_SOR_DP_UNK118(or, link), mask, config[2] << shift); 84 nv_mask(device, NV50_SOR_DP_UNK118(or, link), mask, config[2] << shift);
80 nv_mask(dev, NV50_SOR_DP_UNK120(or, link), mask, config[3] << shift); 85 nv_mask(device, NV50_SOR_DP_UNK120(or, link), mask, config[3] << shift);
81 nv_mask(dev, NV50_SOR_DP_UNK130(or, link), 0x0000ff00, config[4] << 8); 86 nv_mask(device, NV50_SOR_DP_UNK130(or, link), 0x0000ff00, config[4] << 8);
82} 87}
83 88
84static void 89static void
85nv50_sor_dp_link_set(struct drm_device *dev, struct dcb_output *dcb, int crtc, 90nv50_sor_dp_link_set(struct drm_device *dev, struct dcb_output *dcb, int crtc,
86 int link_nr, u32 link_bw, bool enhframe) 91 int link_nr, u32 link_bw, bool enhframe)
87{ 92{
93 struct nouveau_device *device = nouveau_dev(dev);
94 struct nouveau_drm *drm = nouveau_drm(dev);
88 u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1); 95 u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
89 u32 dpctrl = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link)) & ~0x001f4000; 96 u32 dpctrl = nv_rd32(device, NV50_SOR_DP_CTRL(or, link)) & ~0x001f4000;
90 u32 clksor = nv_rd32(dev, 0x614300 + (or * 0x800)) & ~0x000c0000; 97 u32 clksor = nv_rd32(device, 0x614300 + (or * 0x800)) & ~0x000c0000;
91 u8 *table, *entry, mask; 98 u8 *table, *entry, mask;
92 int i; 99 int i;
93 100
94 table = nouveau_dp_bios_data(dev, dcb, &entry); 101 table = nouveau_dp_bios_data(dev, dcb, &entry);
95 if (!table || (table[0] != 0x20 && table[0] != 0x21)) { 102 if (!table || (table[0] != 0x20 && table[0] != 0x21)) {
96 NV_ERROR(dev, "PDISP: unsupported DP table for chipset\n"); 103 NV_ERROR(drm, "PDISP: unsupported DP table for chipset\n");
97 return; 104 return;
98 } 105 }
99 106
@@ -112,20 +119,21 @@ nv50_sor_dp_link_set(struct drm_device *dev, struct dcb_output *dcb, int crtc,
112 if (link_bw > 162000) 119 if (link_bw > 162000)
113 clksor |= 0x00040000; 120 clksor |= 0x00040000;
114 121
115 nv_wr32(dev, 0x614300 + (or * 0x800), clksor); 122 nv_wr32(device, 0x614300 + (or * 0x800), clksor);
116 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), dpctrl); 123 nv_wr32(device, NV50_SOR_DP_CTRL(or, link), dpctrl);
117 124
118 mask = 0; 125 mask = 0;
119 for (i = 0; i < link_nr; i++) 126 for (i = 0; i < link_nr; i++)
120 mask |= 1 << (nv50_sor_dp_lane_map(dev, dcb, i) >> 3); 127 mask |= 1 << (nv50_sor_dp_lane_map(dev, dcb, i) >> 3);
121 nv_mask(dev, NV50_SOR_DP_UNK130(or, link), 0x0000000f, mask); 128 nv_mask(device, NV50_SOR_DP_UNK130(or, link), 0x0000000f, mask);
122} 129}
123 130
124static void 131static void
125nv50_sor_dp_link_get(struct drm_device *dev, u32 or, u32 link, u32 *nr, u32 *bw) 132nv50_sor_dp_link_get(struct drm_device *dev, u32 or, u32 link, u32 *nr, u32 *bw)
126{ 133{
127 u32 dpctrl = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link)) & 0x000f0000; 134 struct nouveau_device *device = nouveau_dev(dev);
128 u32 clksor = nv_rd32(dev, 0x614300 + (or * 0x800)); 135 u32 dpctrl = nv_rd32(device, NV50_SOR_DP_CTRL(or, link)) & 0x000f0000;
136 u32 clksor = nv_rd32(device, 0x614300 + (or * 0x800));
129 if (clksor & 0x000c0000) 137 if (clksor & 0x000c0000)
130 *bw = 270000; 138 *bw = 270000;
131 else 139 else
@@ -139,6 +147,8 @@ nv50_sor_dp_link_get(struct drm_device *dev, u32 or, u32 link, u32 *nr, u32 *bw)
139void 147void
140nv50_sor_dp_calc_tu(struct drm_device *dev, int or, int link, u32 clk, u32 bpp) 148nv50_sor_dp_calc_tu(struct drm_device *dev, int or, int link, u32 clk, u32 bpp)
141{ 149{
150 struct nouveau_device *device = nouveau_dev(dev);
151 struct nouveau_drm *drm = nouveau_drm(dev);
142 const u32 symbol = 100000; 152 const u32 symbol = 100000;
143 int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0; 153 int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
144 int TU, VTUi, VTUf, VTUa; 154 int TU, VTUi, VTUf, VTUa;
@@ -206,7 +216,7 @@ nv50_sor_dp_calc_tu(struct drm_device *dev, int or, int link, u32 clk, u32 bpp)
206 } 216 }
207 217
208 if (!bestTU) { 218 if (!bestTU) {
209 NV_ERROR(dev, "DP: unable to find suitable config\n"); 219 NV_ERROR(drm, "DP: unable to find suitable config\n");
210 return; 220 return;
211 } 221 }
212 222
@@ -217,8 +227,8 @@ nv50_sor_dp_calc_tu(struct drm_device *dev, int or, int link, u32 clk, u32 bpp)
217 r = do_div(unk, symbol); 227 r = do_div(unk, symbol);
218 unk += 6; 228 unk += 6;
219 229
220 nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x000001fc, bestTU << 2); 230 nv_mask(device, NV50_SOR_DP_CTRL(or, link), 0x000001fc, bestTU << 2);
221 nv_mask(dev, NV50_SOR_DP_SCFG(or, link), 0x010f7f3f, bestVTUa << 24 | 231 nv_mask(device, NV50_SOR_DP_SCFG(or, link), 0x010f7f3f, bestVTUa << 24 |
222 bestVTUf << 16 | 232 bestVTUf << 16 |
223 bestVTUi << 8 | 233 bestVTUi << 8 |
224 unk); 234 unk);
@@ -227,6 +237,7 @@ static void
227nv50_sor_disconnect(struct drm_encoder *encoder) 237nv50_sor_disconnect(struct drm_encoder *encoder)
228{ 238{
229 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 239 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
240 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
230 struct drm_device *dev = encoder->dev; 241 struct drm_device *dev = encoder->dev;
231 struct nouveau_channel *evo = nv50_display(dev)->master; 242 struct nouveau_channel *evo = nv50_display(dev)->master;
232 int ret; 243 int ret;
@@ -235,11 +246,11 @@ nv50_sor_disconnect(struct drm_encoder *encoder)
235 return; 246 return;
236 nv50_crtc_blank(nouveau_crtc(nv_encoder->crtc), true); 247 nv50_crtc_blank(nouveau_crtc(nv_encoder->crtc), true);
237 248
238 NV_DEBUG_KMS(dev, "Disconnecting SOR %d\n", nv_encoder->or); 249 NV_DEBUG(drm, "Disconnecting SOR %d\n", nv_encoder->or);
239 250
240 ret = RING_SPACE(evo, 4); 251 ret = RING_SPACE(evo, 4);
241 if (ret) { 252 if (ret) {
242 NV_ERROR(dev, "no space while disconnecting SOR\n"); 253 NV_ERROR(drm, "no space while disconnecting SOR\n");
243 return; 254 return;
244 } 255 }
245 BEGIN_NV04(evo, 0, NV50_EVO_SOR(nv_encoder->or, MODE_CTRL), 1); 256 BEGIN_NV04(evo, 0, NV50_EVO_SOR(nv_encoder->or, MODE_CTRL), 1);
@@ -256,13 +267,15 @@ nv50_sor_disconnect(struct drm_encoder *encoder)
256static void 267static void
257nv50_sor_dpms(struct drm_encoder *encoder, int mode) 268nv50_sor_dpms(struct drm_encoder *encoder, int mode)
258{ 269{
270 struct nouveau_device *device = nouveau_dev(encoder->dev);
271 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
259 struct drm_device *dev = encoder->dev; 272 struct drm_device *dev = encoder->dev;
260 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 273 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
261 struct drm_encoder *enc; 274 struct drm_encoder *enc;
262 uint32_t val; 275 uint32_t val;
263 int or = nv_encoder->or; 276 int or = nv_encoder->or;
264 277
265 NV_DEBUG_KMS(dev, "or %d type %d mode %d\n", or, nv_encoder->dcb->type, mode); 278 NV_DEBUG(drm, "or %d type %d mode %d\n", or, nv_encoder->dcb->type, mode);
266 279
267 nv_encoder->last_dpms = mode; 280 nv_encoder->last_dpms = mode;
268 list_for_each_entry(enc, &dev->mode_config.encoder_list, head) { 281 list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
@@ -280,27 +293,27 @@ nv50_sor_dpms(struct drm_encoder *encoder, int mode)
280 } 293 }
281 294
282 /* wait for it to be done */ 295 /* wait for it to be done */
283 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_CTRL(or), 296 if (!nv_wait(device, NV50_PDISPLAY_SOR_DPMS_CTRL(or),
284 NV50_PDISPLAY_SOR_DPMS_CTRL_PENDING, 0)) { 297 NV50_PDISPLAY_SOR_DPMS_CTRL_PENDING, 0)) {
285 NV_ERROR(dev, "timeout: SOR_DPMS_CTRL_PENDING(%d) == 0\n", or); 298 NV_ERROR(drm, "timeout: SOR_DPMS_CTRL_PENDING(%d) == 0\n", or);
286 NV_ERROR(dev, "SOR_DPMS_CTRL(%d) = 0x%08x\n", or, 299 NV_ERROR(drm, "SOR_DPMS_CTRL(%d) = 0x%08x\n", or,
287 nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_CTRL(or))); 300 nv_rd32(device, NV50_PDISPLAY_SOR_DPMS_CTRL(or)));
288 } 301 }
289 302
290 val = nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_CTRL(or)); 303 val = nv_rd32(device, NV50_PDISPLAY_SOR_DPMS_CTRL(or));
291 304
292 if (mode == DRM_MODE_DPMS_ON) 305 if (mode == DRM_MODE_DPMS_ON)
293 val |= NV50_PDISPLAY_SOR_DPMS_CTRL_ON; 306 val |= NV50_PDISPLAY_SOR_DPMS_CTRL_ON;
294 else 307 else
295 val &= ~NV50_PDISPLAY_SOR_DPMS_CTRL_ON; 308 val &= ~NV50_PDISPLAY_SOR_DPMS_CTRL_ON;
296 309
297 nv_wr32(dev, NV50_PDISPLAY_SOR_DPMS_CTRL(or), val | 310 nv_wr32(device, NV50_PDISPLAY_SOR_DPMS_CTRL(or), val |
298 NV50_PDISPLAY_SOR_DPMS_CTRL_PENDING); 311 NV50_PDISPLAY_SOR_DPMS_CTRL_PENDING);
299 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(or), 312 if (!nv_wait(device, NV50_PDISPLAY_SOR_DPMS_STATE(or),
300 NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) { 313 NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
301 NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", or); 314 NV_ERROR(drm, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", or);
302 NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", or, 315 NV_ERROR(drm, "SOR_DPMS_STATE(%d) = 0x%08x\n", or,
303 nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(or))); 316 nv_rd32(device, NV50_PDISPLAY_SOR_DPMS_STATE(or)));
304 } 317 }
305 318
306 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) { 319 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
@@ -317,13 +330,15 @@ nv50_sor_dpms(struct drm_encoder *encoder, int mode)
317static void 330static void
318nv50_sor_save(struct drm_encoder *encoder) 331nv50_sor_save(struct drm_encoder *encoder)
319{ 332{
320 NV_ERROR(encoder->dev, "!!\n"); 333 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
334 NV_ERROR(drm, "!!\n");
321} 335}
322 336
323static void 337static void
324nv50_sor_restore(struct drm_encoder *encoder) 338nv50_sor_restore(struct drm_encoder *encoder)
325{ 339{
326 NV_ERROR(encoder->dev, "!!\n"); 340 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
341 NV_ERROR(drm, "!!\n");
327} 342}
328 343
329static bool 344static bool
@@ -331,14 +346,15 @@ nv50_sor_mode_fixup(struct drm_encoder *encoder,
331 const struct drm_display_mode *mode, 346 const struct drm_display_mode *mode,
332 struct drm_display_mode *adjusted_mode) 347 struct drm_display_mode *adjusted_mode)
333{ 348{
349 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
334 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 350 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
335 struct nouveau_connector *connector; 351 struct nouveau_connector *connector;
336 352
337 NV_DEBUG_KMS(encoder->dev, "or %d\n", nv_encoder->or); 353 NV_DEBUG(drm, "or %d\n", nv_encoder->or);
338 354
339 connector = nouveau_encoder_connector_get(nv_encoder); 355 connector = nouveau_encoder_connector_get(nv_encoder);
340 if (!connector) { 356 if (!connector) {
341 NV_ERROR(encoder->dev, "Encoder has no connector\n"); 357 NV_ERROR(drm, "Encoder has no connector\n");
342 return false; 358 return false;
343 } 359 }
344 360
@@ -371,13 +387,13 @@ nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
371{ 387{
372 struct nouveau_channel *evo = nv50_display(encoder->dev)->master; 388 struct nouveau_channel *evo = nv50_display(encoder->dev)->master;
373 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 389 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
374 struct drm_device *dev = encoder->dev; 390 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
375 struct nouveau_crtc *crtc = nouveau_crtc(encoder->crtc); 391 struct nouveau_crtc *crtc = nouveau_crtc(encoder->crtc);
376 struct nouveau_connector *nv_connector; 392 struct nouveau_connector *nv_connector;
377 uint32_t mode_ctl = 0; 393 uint32_t mode_ctl = 0;
378 int ret; 394 int ret;
379 395
380 NV_DEBUG_KMS(dev, "or %d type %d -> crtc %d\n", 396 NV_DEBUG(drm, "or %d type %d -> crtc %d\n",
381 nv_encoder->or, nv_encoder->dcb->type, crtc->index); 397 nv_encoder->or, nv_encoder->dcb->type, crtc->index);
382 nv_encoder->crtc = encoder->crtc; 398 nv_encoder->crtc = encoder->crtc;
383 399
@@ -427,7 +443,7 @@ nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
427 443
428 ret = RING_SPACE(evo, 2); 444 ret = RING_SPACE(evo, 2);
429 if (ret) { 445 if (ret) {
430 NV_ERROR(dev, "no space while connecting SOR\n"); 446 NV_ERROR(drm, "no space while connecting SOR\n");
431 nv_encoder->crtc = NULL; 447 nv_encoder->crtc = NULL;
432 return; 448 return;
433 } 449 }
@@ -458,11 +474,9 @@ static void
458nv50_sor_destroy(struct drm_encoder *encoder) 474nv50_sor_destroy(struct drm_encoder *encoder)
459{ 475{
460 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 476 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
477 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
461 478
462 if (!encoder) 479 NV_DEBUG(drm, "\n");
463 return;
464
465 NV_DEBUG_KMS(encoder->dev, "\n");
466 480
467 drm_encoder_cleanup(encoder); 481 drm_encoder_cleanup(encoder);
468 482
@@ -478,10 +492,11 @@ nv50_sor_create(struct drm_connector *connector, struct dcb_output *entry)
478{ 492{
479 struct nouveau_encoder *nv_encoder = NULL; 493 struct nouveau_encoder *nv_encoder = NULL;
480 struct drm_device *dev = connector->dev; 494 struct drm_device *dev = connector->dev;
495 struct nouveau_drm *drm = nouveau_drm(dev);
481 struct drm_encoder *encoder; 496 struct drm_encoder *encoder;
482 int type; 497 int type;
483 498
484 NV_DEBUG_KMS(dev, "\n"); 499 NV_DEBUG(drm, "\n");
485 500
486 switch (entry->type) { 501 switch (entry->type) {
487 case DCB_OUTPUT_TMDS: 502 case DCB_OUTPUT_TMDS:
diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c
index b0d147a675c4..c686650584b6 100644
--- a/drivers/gpu/drm/nouveau/nv84_fence.c
+++ b/drivers/gpu/drm/nouveau/nv84_fence.c
@@ -31,6 +31,8 @@
31#include "nouveau_dma.h" 31#include "nouveau_dma.h"
32#include "nouveau_fence.h" 32#include "nouveau_fence.h"
33 33
34#include "nv50_display.h"
35
34struct nv84_fence_chan { 36struct nv84_fence_chan {
35 struct nouveau_fence_chan base; 37 struct nouveau_fence_chan base;
36}; 38};
@@ -99,6 +101,7 @@ nv84_fence_context_del(struct nouveau_channel *chan)
99static int 101static int
100nv84_fence_context_new(struct nouveau_channel *chan) 102nv84_fence_context_new(struct nouveau_channel *chan)
101{ 103{
104 struct drm_device *dev = chan->drm->dev;
102 struct nouveau_fifo_chan *fifo = (void *)chan->object; 105 struct nouveau_fifo_chan *fifo = (void *)chan->object;
103 struct nv84_fence_priv *priv = chan->drm->fence; 106 struct nv84_fence_priv *priv = chan->drm->fence;
104 struct nv84_fence_chan *fctx; 107 struct nv84_fence_chan *fctx;
@@ -123,8 +126,8 @@ nv84_fence_context_new(struct nouveau_channel *chan)
123 &object); 126 &object);
124 127
125 /* dma objects for display sync channel semaphore blocks */ 128 /* dma objects for display sync channel semaphore blocks */
126 for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) { 129 for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) {
127 struct nouveau_bo *bo = nv50sema(chan->drm->dev, i); 130 struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i);
128 131
129 ret = nouveau_object_new(nv_object(chan->cli), chan->handle, 132 ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
130 NvEvoSema0 + i, 0x003d, 133 NvEvoSema0 + i, 0x003d,
diff --git a/drivers/gpu/drm/nouveau/nva3_pm.c b/drivers/gpu/drm/nouveau/nva3_pm.c
index 2f7ee50440ae..3f69e46436cf 100644
--- a/drivers/gpu/drm/nouveau/nva3_pm.c
+++ b/drivers/gpu/drm/nouveau/nva3_pm.c
@@ -23,17 +23,24 @@
23 */ 23 */
24 24
25#include "drmP.h" 25#include "drmP.h"
26#include "nouveau_drv.h" 26#include "nouveau_drm.h"
27#include <nouveau_bios.h> 27#include "nouveau_bios.h"
28#include "nouveau_pm.h" 28#include "nouveau_pm.h"
29 29
30#include <subdev/bios/pll.h>
31#include <subdev/bios.h>
32#include <subdev/clock.h>
33#include <subdev/timer.h>
34#include <subdev/fb.h>
35
30static u32 read_clk(struct drm_device *, int, bool); 36static u32 read_clk(struct drm_device *, int, bool);
31static u32 read_pll(struct drm_device *, int, u32); 37static u32 read_pll(struct drm_device *, int, u32);
32 38
33static u32 39static u32
34read_vco(struct drm_device *dev, int clk) 40read_vco(struct drm_device *dev, int clk)
35{ 41{
36 u32 sctl = nv_rd32(dev, 0x4120 + (clk * 4)); 42 struct nouveau_device *device = nouveau_dev(dev);
43 u32 sctl = nv_rd32(device, 0x4120 + (clk * 4));
37 if ((sctl & 0x00000030) != 0x00000030) 44 if ((sctl & 0x00000030) != 0x00000030)
38 return read_pll(dev, 0x41, 0x00e820); 45 return read_pll(dev, 0x41, 0x00e820);
39 return read_pll(dev, 0x42, 0x00e8a0); 46 return read_pll(dev, 0x42, 0x00e8a0);
@@ -42,26 +49,27 @@ read_vco(struct drm_device *dev, int clk)
42static u32 49static u32
43read_clk(struct drm_device *dev, int clk, bool ignore_en) 50read_clk(struct drm_device *dev, int clk, bool ignore_en)
44{ 51{
45 struct drm_nouveau_private *dev_priv = dev->dev_private; 52 struct nouveau_device *device = nouveau_dev(dev);
53 struct nouveau_drm *drm = nouveau_drm(dev);
46 u32 sctl, sdiv, sclk; 54 u32 sctl, sdiv, sclk;
47 55
48 /* refclk for the 0xe8xx plls is a fixed frequency */ 56 /* refclk for the 0xe8xx plls is a fixed frequency */
49 if (clk >= 0x40) { 57 if (clk >= 0x40) {
50 if (dev_priv->chipset == 0xaf) { 58 if (nv_device(drm->device)->chipset == 0xaf) {
51 /* no joke.. seriously.. sigh.. */ 59 /* no joke.. seriously.. sigh.. */
52 return nv_rd32(dev, 0x00471c) * 1000; 60 return nv_rd32(device, 0x00471c) * 1000;
53 } 61 }
54 62
55 return dev_priv->crystal; 63 return device->crystal;
56 } 64 }
57 65
58 sctl = nv_rd32(dev, 0x4120 + (clk * 4)); 66 sctl = nv_rd32(device, 0x4120 + (clk * 4));
59 if (!ignore_en && !(sctl & 0x00000100)) 67 if (!ignore_en && !(sctl & 0x00000100))
60 return 0; 68 return 0;
61 69
62 switch (sctl & 0x00003000) { 70 switch (sctl & 0x00003000) {
63 case 0x00000000: 71 case 0x00000000:
64 return dev_priv->crystal; 72 return device->crystal;
65 case 0x00002000: 73 case 0x00002000:
66 if (sctl & 0x00000040) 74 if (sctl & 0x00000040)
67 return 108000; 75 return 108000;
@@ -78,12 +86,13 @@ read_clk(struct drm_device *dev, int clk, bool ignore_en)
78static u32 86static u32
79read_pll(struct drm_device *dev, int clk, u32 pll) 87read_pll(struct drm_device *dev, int clk, u32 pll)
80{ 88{
81 u32 ctrl = nv_rd32(dev, pll + 0); 89 struct nouveau_device *device = nouveau_dev(dev);
90 u32 ctrl = nv_rd32(device, pll + 0);
82 u32 sclk = 0, P = 1, N = 1, M = 1; 91 u32 sclk = 0, P = 1, N = 1, M = 1;
83 92
84 if (!(ctrl & 0x00000008)) { 93 if (!(ctrl & 0x00000008)) {
85 if (ctrl & 0x00000001) { 94 if (ctrl & 0x00000001) {
86 u32 coef = nv_rd32(dev, pll + 4); 95 u32 coef = nv_rd32(device, pll + 4);
87 M = (coef & 0x000000ff) >> 0; 96 M = (coef & 0x000000ff) >> 0;
88 N = (coef & 0x0000ff00) >> 8; 97 N = (coef & 0x0000ff00) >> 8;
89 P = (coef & 0x003f0000) >> 16; 98 P = (coef & 0x003f0000) >> 16;
@@ -111,6 +120,9 @@ struct creg {
111static int 120static int
112calc_clk(struct drm_device *dev, int clk, u32 pll, u32 khz, struct creg *reg) 121calc_clk(struct drm_device *dev, int clk, u32 pll, u32 khz, struct creg *reg)
113{ 122{
123 struct nouveau_drm *drm = nouveau_drm(dev);
124 struct nouveau_device *device = nouveau_dev(dev);
125 struct nouveau_bios *bios = nouveau_bios(device);
114 struct nvbios_pll limits; 126 struct nvbios_pll limits;
115 u32 oclk, sclk, sdiv; 127 u32 oclk, sclk, sdiv;
116 int P, N, M, diff; 128 int P, N, M, diff;
@@ -119,7 +131,7 @@ calc_clk(struct drm_device *dev, int clk, u32 pll, u32 khz, struct creg *reg)
119 reg->pll = 0; 131 reg->pll = 0;
120 reg->clk = 0; 132 reg->clk = 0;
121 if (!khz) { 133 if (!khz) {
122 NV_DEBUG(dev, "no clock for 0x%04x/0x%02x\n", pll, clk); 134 NV_DEBUG(drm, "no clock for 0x%04x/0x%02x\n", pll, clk);
123 return 0; 135 return 0;
124 } 136 }
125 137
@@ -154,14 +166,14 @@ calc_clk(struct drm_device *dev, int clk, u32 pll, u32 khz, struct creg *reg)
154 } 166 }
155 167
156 if (!pll) { 168 if (!pll) {
157 NV_ERROR(dev, "bad freq %02x: %d %d\n", clk, khz, sclk); 169 NV_ERROR(drm, "bad freq %02x: %d %d\n", clk, khz, sclk);
158 return -ERANGE; 170 return -ERANGE;
159 } 171 }
160 172
161 break; 173 break;
162 } 174 }
163 175
164 ret = get_pll_limits(dev, pll, &limits); 176 ret = nvbios_pll_parse(bios, pll, &limits);
165 if (ret) 177 if (ret)
166 return ret; 178 return ret;
167 179
@@ -171,54 +183,60 @@ calc_clk(struct drm_device *dev, int clk, u32 pll, u32 khz, struct creg *reg)
171 183
172 ret = nva3_calc_pll(dev, &limits, khz, &N, NULL, &M, &P); 184 ret = nva3_calc_pll(dev, &limits, khz, &N, NULL, &M, &P);
173 if (ret >= 0) { 185 if (ret >= 0) {
174 reg->clk = nv_rd32(dev, 0x4120 + (clk * 4)); 186 reg->clk = nv_rd32(device, 0x4120 + (clk * 4));
175 reg->pll = (P << 16) | (N << 8) | M; 187 reg->pll = (P << 16) | (N << 8) | M;
176 } 188 }
189
177 return ret; 190 return ret;
178} 191}
179 192
180static void 193static void
181prog_pll(struct drm_device *dev, int clk, u32 pll, struct creg *reg) 194prog_pll(struct drm_device *dev, int clk, u32 pll, struct creg *reg)
182{ 195{
196 struct nouveau_device *device = nouveau_dev(dev);
197 struct nouveau_drm *drm = nouveau_drm(dev);
183 const u32 src0 = 0x004120 + (clk * 4); 198 const u32 src0 = 0x004120 + (clk * 4);
184 const u32 src1 = 0x004160 + (clk * 4); 199 const u32 src1 = 0x004160 + (clk * 4);
185 const u32 ctrl = pll + 0; 200 const u32 ctrl = pll + 0;
186 const u32 coef = pll + 4; 201 const u32 coef = pll + 4;
187 202
188 if (!reg->clk && !reg->pll) { 203 if (!reg->clk && !reg->pll) {
189 NV_DEBUG(dev, "no clock for %02x\n", clk); 204 NV_DEBUG(drm, "no clock for %02x\n", clk);
190 return; 205 return;
191 } 206 }
192 207
193 if (reg->pll) { 208 if (reg->pll) {
194 nv_mask(dev, src0, 0x00000101, 0x00000101); 209 nv_mask(device, src0, 0x00000101, 0x00000101);
195 nv_wr32(dev, coef, reg->pll); 210 nv_wr32(device, coef, reg->pll);
196 nv_mask(dev, ctrl, 0x00000015, 0x00000015); 211 nv_mask(device, ctrl, 0x00000015, 0x00000015);
197 nv_mask(dev, ctrl, 0x00000010, 0x00000000); 212 nv_mask(device, ctrl, 0x00000010, 0x00000000);
198 nv_wait(dev, ctrl, 0x00020000, 0x00020000); 213 nv_wait(device, ctrl, 0x00020000, 0x00020000);
199 nv_mask(dev, ctrl, 0x00000010, 0x00000010); 214 nv_mask(device, ctrl, 0x00000010, 0x00000010);
200 nv_mask(dev, ctrl, 0x00000008, 0x00000000); 215 nv_mask(device, ctrl, 0x00000008, 0x00000000);
201 nv_mask(dev, src1, 0x00000100, 0x00000000); 216 nv_mask(device, src1, 0x00000100, 0x00000000);
202 nv_mask(dev, src1, 0x00000001, 0x00000000); 217 nv_mask(device, src1, 0x00000001, 0x00000000);
203 } else { 218 } else {
204 nv_mask(dev, src1, 0x003f3141, 0x00000101 | reg->clk); 219 nv_mask(device, src1, 0x003f3141, 0x00000101 | reg->clk);
205 nv_mask(dev, ctrl, 0x00000018, 0x00000018); 220 nv_mask(device, ctrl, 0x00000018, 0x00000018);
206 udelay(20); 221 udelay(20);
207 nv_mask(dev, ctrl, 0x00000001, 0x00000000); 222 nv_mask(device, ctrl, 0x00000001, 0x00000000);
208 nv_mask(dev, src0, 0x00000100, 0x00000000); 223 nv_mask(device, src0, 0x00000100, 0x00000000);
209 nv_mask(dev, src0, 0x00000001, 0x00000000); 224 nv_mask(device, src0, 0x00000001, 0x00000000);
210 } 225 }
211} 226}
212 227
213static void 228static void
214prog_clk(struct drm_device *dev, int clk, struct creg *reg) 229prog_clk(struct drm_device *dev, int clk, struct creg *reg)
215{ 230{
231 struct nouveau_device *device = nouveau_dev(dev);
232 struct nouveau_drm *drm = nouveau_drm(dev);
233
216 if (!reg->clk) { 234 if (!reg->clk) {
217 NV_DEBUG(dev, "no clock for %02x\n", clk); 235 NV_DEBUG(drm, "no clock for %02x\n", clk);
218 return; 236 return;
219 } 237 }
220 238
221 nv_mask(dev, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | reg->clk); 239 nv_mask(device, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | reg->clk);
222} 240}
223 241
224int 242int
@@ -309,10 +327,11 @@ static bool
309nva3_pm_grcp_idle(void *data) 327nva3_pm_grcp_idle(void *data)
310{ 328{
311 struct drm_device *dev = data; 329 struct drm_device *dev = data;
330 struct nouveau_device *device = nouveau_dev(dev);
312 331
313 if (!(nv_rd32(dev, 0x400304) & 0x00000001)) 332 if (!(nv_rd32(device, 0x400304) & 0x00000001))
314 return true; 333 return true;
315 if (nv_rd32(dev, 0x400308) == 0x0050001c) 334 if (nv_rd32(device, 0x400308) == 0x0050001c)
316 return true; 335 return true;
317 return false; 336 return false;
318} 337}
@@ -320,83 +339,91 @@ nva3_pm_grcp_idle(void *data)
320static void 339static void
321mclk_precharge(struct nouveau_mem_exec_func *exec) 340mclk_precharge(struct nouveau_mem_exec_func *exec)
322{ 341{
323 nv_wr32(exec->dev, 0x1002d4, 0x00000001); 342 struct nouveau_device *device = nouveau_dev(exec->dev);
343 nv_wr32(device, 0x1002d4, 0x00000001);
324} 344}
325 345
326static void 346static void
327mclk_refresh(struct nouveau_mem_exec_func *exec) 347mclk_refresh(struct nouveau_mem_exec_func *exec)
328{ 348{
329 nv_wr32(exec->dev, 0x1002d0, 0x00000001); 349 struct nouveau_device *device = nouveau_dev(exec->dev);
350 nv_wr32(device, 0x1002d0, 0x00000001);
330} 351}
331 352
332static void 353static void
333mclk_refresh_auto(struct nouveau_mem_exec_func *exec, bool enable) 354mclk_refresh_auto(struct nouveau_mem_exec_func *exec, bool enable)
334{ 355{
335 nv_wr32(exec->dev, 0x100210, enable ? 0x80000000 : 0x00000000); 356 struct nouveau_device *device = nouveau_dev(exec->dev);
357 nv_wr32(device, 0x100210, enable ? 0x80000000 : 0x00000000);
336} 358}
337 359
338static void 360static void
339mclk_refresh_self(struct nouveau_mem_exec_func *exec, bool enable) 361mclk_refresh_self(struct nouveau_mem_exec_func *exec, bool enable)
340{ 362{
341 nv_wr32(exec->dev, 0x1002dc, enable ? 0x00000001 : 0x00000000); 363 struct nouveau_device *device = nouveau_dev(exec->dev);
364 nv_wr32(device, 0x1002dc, enable ? 0x00000001 : 0x00000000);
342} 365}
343 366
344static void 367static void
345mclk_wait(struct nouveau_mem_exec_func *exec, u32 nsec) 368mclk_wait(struct nouveau_mem_exec_func *exec, u32 nsec)
346{ 369{
347 volatile u32 post = nv_rd32(exec->dev, 0); (void)post; 370 struct nouveau_device *device = nouveau_dev(exec->dev);
371 volatile u32 post = nv_rd32(device, 0); (void)post;
348 udelay((nsec + 500) / 1000); 372 udelay((nsec + 500) / 1000);
349} 373}
350 374
351static u32 375static u32
352mclk_mrg(struct nouveau_mem_exec_func *exec, int mr) 376mclk_mrg(struct nouveau_mem_exec_func *exec, int mr)
353{ 377{
378 struct nouveau_device *device = nouveau_dev(exec->dev);
354 if (mr <= 1) 379 if (mr <= 1)
355 return nv_rd32(exec->dev, 0x1002c0 + ((mr - 0) * 4)); 380 return nv_rd32(device, 0x1002c0 + ((mr - 0) * 4));
356 if (mr <= 3) 381 if (mr <= 3)
357 return nv_rd32(exec->dev, 0x1002e0 + ((mr - 2) * 4)); 382 return nv_rd32(device, 0x1002e0 + ((mr - 2) * 4));
358 return 0; 383 return 0;
359} 384}
360 385
361static void 386static void
362mclk_mrs(struct nouveau_mem_exec_func *exec, int mr, u32 data) 387mclk_mrs(struct nouveau_mem_exec_func *exec, int mr, u32 data)
363{ 388{
389 struct nouveau_device *device = nouveau_dev(exec->dev);
390 struct nouveau_fb *pfb = nouveau_fb(device);
364 if (mr <= 1) { 391 if (mr <= 1) {
365 if (nvfb_vram_rank_B(exec->dev)) 392 if (pfb->ram.ranks > 1)
366 nv_wr32(exec->dev, 0x1002c8 + ((mr - 0) * 4), data); 393 nv_wr32(device, 0x1002c8 + ((mr - 0) * 4), data);
367 nv_wr32(exec->dev, 0x1002c0 + ((mr - 0) * 4), data); 394 nv_wr32(device, 0x1002c0 + ((mr - 0) * 4), data);
368 } else 395 } else
369 if (mr <= 3) { 396 if (mr <= 3) {
370 if (nvfb_vram_rank_B(exec->dev)) 397 if (pfb->ram.ranks > 1)
371 nv_wr32(exec->dev, 0x1002e8 + ((mr - 2) * 4), data); 398 nv_wr32(device, 0x1002e8 + ((mr - 2) * 4), data);
372 nv_wr32(exec->dev, 0x1002e0 + ((mr - 2) * 4), data); 399 nv_wr32(device, 0x1002e0 + ((mr - 2) * 4), data);
373 } 400 }
374} 401}
375 402
376static void 403static void
377mclk_clock_set(struct nouveau_mem_exec_func *exec) 404mclk_clock_set(struct nouveau_mem_exec_func *exec)
378{ 405{
379 struct drm_device *dev = exec->dev; 406 struct nouveau_device *device = nouveau_dev(exec->dev);
380 struct nva3_pm_state *info = exec->priv; 407 struct nva3_pm_state *info = exec->priv;
381 u32 ctrl; 408 u32 ctrl;
382 409
383 ctrl = nv_rd32(dev, 0x004000); 410 ctrl = nv_rd32(device, 0x004000);
384 if (!(ctrl & 0x00000008) && info->mclk.pll) { 411 if (!(ctrl & 0x00000008) && info->mclk.pll) {
385 nv_wr32(dev, 0x004000, (ctrl |= 0x00000008)); 412 nv_wr32(device, 0x004000, (ctrl |= 0x00000008));
386 nv_mask(dev, 0x1110e0, 0x00088000, 0x00088000); 413 nv_mask(device, 0x1110e0, 0x00088000, 0x00088000);
387 nv_wr32(dev, 0x004018, 0x00001000); 414 nv_wr32(device, 0x004018, 0x00001000);
388 nv_wr32(dev, 0x004000, (ctrl &= ~0x00000001)); 415 nv_wr32(device, 0x004000, (ctrl &= ~0x00000001));
389 nv_wr32(dev, 0x004004, info->mclk.pll); 416 nv_wr32(device, 0x004004, info->mclk.pll);
390 nv_wr32(dev, 0x004000, (ctrl |= 0x00000001)); 417 nv_wr32(device, 0x004000, (ctrl |= 0x00000001));
391 udelay(64); 418 udelay(64);
392 nv_wr32(dev, 0x004018, 0x00005000 | info->r004018); 419 nv_wr32(device, 0x004018, 0x00005000 | info->r004018);
393 udelay(20); 420 udelay(20);
394 } else 421 } else
395 if (!info->mclk.pll) { 422 if (!info->mclk.pll) {
396 nv_mask(dev, 0x004168, 0x003f3040, info->mclk.clk); 423 nv_mask(device, 0x004168, 0x003f3040, info->mclk.clk);
397 nv_wr32(dev, 0x004000, (ctrl |= 0x00000008)); 424 nv_wr32(device, 0x004000, (ctrl |= 0x00000008));
398 nv_mask(dev, 0x1110e0, 0x00088000, 0x00088000); 425 nv_mask(device, 0x1110e0, 0x00088000, 0x00088000);
399 nv_wr32(dev, 0x004018, 0x0000d000 | info->r004018); 426 nv_wr32(device, 0x004018, 0x0000d000 | info->r004018);
400 } 427 }
401 428
402 if (info->rammap) { 429 if (info->rammap) {
@@ -408,67 +435,68 @@ mclk_clock_set(struct nouveau_mem_exec_func *exec)
408 (info->ramcfg[3] & 0x0f) << 16 | 435 (info->ramcfg[3] & 0x0f) << 16 |
409 (info->ramcfg[9] & 0x0f) | 436 (info->ramcfg[9] & 0x0f) |
410 0x80000000; 437 0x80000000;
411 nv_wr32(dev, 0x1005a0, unk5a0); 438 nv_wr32(device, 0x1005a0, unk5a0);
412 nv_wr32(dev, 0x1005a4, unk5a4); 439 nv_wr32(device, 0x1005a4, unk5a4);
413 nv_wr32(dev, 0x10f804, unk804); 440 nv_wr32(device, 0x10f804, unk804);
414 nv_mask(dev, 0x10053c, 0x00001000, 0x00000000); 441 nv_mask(device, 0x10053c, 0x00001000, 0x00000000);
415 } else { 442 } else {
416 nv_mask(dev, 0x10053c, 0x00001000, 0x00001000); 443 nv_mask(device, 0x10053c, 0x00001000, 0x00001000);
417 nv_mask(dev, 0x10f804, 0x80000000, 0x00000000); 444 nv_mask(device, 0x10f804, 0x80000000, 0x00000000);
418 nv_mask(dev, 0x100760, 0x22222222, info->r100760); 445 nv_mask(device, 0x100760, 0x22222222, info->r100760);
419 nv_mask(dev, 0x1007a0, 0x22222222, info->r100760); 446 nv_mask(device, 0x1007a0, 0x22222222, info->r100760);
420 nv_mask(dev, 0x1007e0, 0x22222222, info->r100760); 447 nv_mask(device, 0x1007e0, 0x22222222, info->r100760);
421 } 448 }
422 } 449 }
423 450
424 if (info->mclk.pll) { 451 if (info->mclk.pll) {
425 nv_mask(dev, 0x1110e0, 0x00088000, 0x00011000); 452 nv_mask(device, 0x1110e0, 0x00088000, 0x00011000);
426 nv_wr32(dev, 0x004000, (ctrl &= ~0x00000008)); 453 nv_wr32(device, 0x004000, (ctrl &= ~0x00000008));
427 } 454 }
428} 455}
429 456
430static void 457static void
431mclk_timing_set(struct nouveau_mem_exec_func *exec) 458mclk_timing_set(struct nouveau_mem_exec_func *exec)
432{ 459{
433 struct drm_device *dev = exec->dev; 460 struct nouveau_device *device = nouveau_dev(exec->dev);
434 struct nva3_pm_state *info = exec->priv; 461 struct nva3_pm_state *info = exec->priv;
435 struct nouveau_pm_level *perflvl = info->perflvl; 462 struct nouveau_pm_level *perflvl = info->perflvl;
436 int i; 463 int i;
437 464
438 for (i = 0; i < 9; i++) 465 for (i = 0; i < 9; i++)
439 nv_wr32(dev, 0x100220 + (i * 4), perflvl->timing.reg[i]); 466 nv_wr32(device, 0x100220 + (i * 4), perflvl->timing.reg[i]);
440 467
441 if (info->ramcfg) { 468 if (info->ramcfg) {
442 u32 data = (info->ramcfg[2] & 0x08) ? 0x00000000 : 0x00001000; 469 u32 data = (info->ramcfg[2] & 0x08) ? 0x00000000 : 0x00001000;
443 nv_mask(dev, 0x100200, 0x00001000, data); 470 nv_mask(device, 0x100200, 0x00001000, data);
444 } 471 }
445 472
446 if (info->ramcfg) { 473 if (info->ramcfg) {
447 u32 unk714 = nv_rd32(dev, 0x100714) & ~0xf0000010; 474 u32 unk714 = nv_rd32(device, 0x100714) & ~0xf0000010;
448 u32 unk718 = nv_rd32(dev, 0x100718) & ~0x00000100; 475 u32 unk718 = nv_rd32(device, 0x100718) & ~0x00000100;
449 u32 unk71c = nv_rd32(dev, 0x10071c) & ~0x00000100; 476 u32 unk71c = nv_rd32(device, 0x10071c) & ~0x00000100;
450 if ( (info->ramcfg[2] & 0x20)) 477 if ( (info->ramcfg[2] & 0x20))
451 unk714 |= 0xf0000000; 478 unk714 |= 0xf0000000;
452 if (!(info->ramcfg[2] & 0x04)) 479 if (!(info->ramcfg[2] & 0x04))
453 unk714 |= 0x00000010; 480 unk714 |= 0x00000010;
454 nv_wr32(dev, 0x100714, unk714); 481 nv_wr32(device, 0x100714, unk714);
455 482
456 if (info->ramcfg[2] & 0x01) 483 if (info->ramcfg[2] & 0x01)
457 unk71c |= 0x00000100; 484 unk71c |= 0x00000100;
458 nv_wr32(dev, 0x10071c, unk71c); 485 nv_wr32(device, 0x10071c, unk71c);
459 486
460 if (info->ramcfg[2] & 0x02) 487 if (info->ramcfg[2] & 0x02)
461 unk718 |= 0x00000100; 488 unk718 |= 0x00000100;
462 nv_wr32(dev, 0x100718, unk718); 489 nv_wr32(device, 0x100718, unk718);
463 490
464 if (info->ramcfg[2] & 0x10) 491 if (info->ramcfg[2] & 0x10)
465 nv_wr32(dev, 0x111100, 0x48000000); /*XXX*/ 492 nv_wr32(device, 0x111100, 0x48000000); /*XXX*/
466 } 493 }
467} 494}
468 495
469static void 496static void
470prog_mem(struct drm_device *dev, struct nva3_pm_state *info) 497prog_mem(struct drm_device *dev, struct nva3_pm_state *info)
471{ 498{
499 struct nouveau_device *device = nouveau_dev(dev);
472 struct nouveau_mem_exec_func exec = { 500 struct nouveau_mem_exec_func exec = {
473 .dev = dev, 501 .dev = dev,
474 .precharge = mclk_precharge, 502 .precharge = mclk_precharge,
@@ -490,17 +518,17 @@ prog_mem(struct drm_device *dev, struct nva3_pm_state *info)
490 info->r100760 = 0x22222222; 518 info->r100760 = 0x22222222;
491 } 519 }
492 520
493 ctrl = nv_rd32(dev, 0x004000); 521 ctrl = nv_rd32(device, 0x004000);
494 if (ctrl & 0x00000008) { 522 if (ctrl & 0x00000008) {
495 if (info->mclk.pll) { 523 if (info->mclk.pll) {
496 nv_mask(dev, 0x004128, 0x00000101, 0x00000101); 524 nv_mask(device, 0x004128, 0x00000101, 0x00000101);
497 nv_wr32(dev, 0x004004, info->mclk.pll); 525 nv_wr32(device, 0x004004, info->mclk.pll);
498 nv_wr32(dev, 0x004000, (ctrl |= 0x00000001)); 526 nv_wr32(device, 0x004000, (ctrl |= 0x00000001));
499 nv_wr32(dev, 0x004000, (ctrl &= 0xffffffef)); 527 nv_wr32(device, 0x004000, (ctrl &= 0xffffffef));
500 nv_wait(dev, 0x004000, 0x00020000, 0x00020000); 528 nv_wait(device, 0x004000, 0x00020000, 0x00020000);
501 nv_wr32(dev, 0x004000, (ctrl |= 0x00000010)); 529 nv_wr32(device, 0x004000, (ctrl |= 0x00000010));
502 nv_wr32(dev, 0x004018, 0x00005000 | info->r004018); 530 nv_wr32(device, 0x004018, 0x00005000 | info->r004018);
503 nv_wr32(dev, 0x004000, (ctrl |= 0x00000004)); 531 nv_wr32(device, 0x004000, (ctrl |= 0x00000004));
504 } 532 }
505 } else { 533 } else {
506 u32 ssel = 0x00000101; 534 u32 ssel = 0x00000101;
@@ -508,68 +536,67 @@ prog_mem(struct drm_device *dev, struct nva3_pm_state *info)
508 ssel |= info->mclk.clk; 536 ssel |= info->mclk.clk;
509 else 537 else
510 ssel |= 0x00080000; /* 324MHz, shouldn't matter... */ 538 ssel |= 0x00080000; /* 324MHz, shouldn't matter... */
511 nv_mask(dev, 0x004168, 0x003f3141, ctrl); 539 nv_mask(device, 0x004168, 0x003f3141, ctrl);
512 } 540 }
513 541
514 if (info->ramcfg) { 542 if (info->ramcfg) {
515 if (info->ramcfg[2] & 0x10) { 543 if (info->ramcfg[2] & 0x10) {
516 nv_mask(dev, 0x111104, 0x00000600, 0x00000000); 544 nv_mask(device, 0x111104, 0x00000600, 0x00000000);
517 } else { 545 } else {
518 nv_mask(dev, 0x111100, 0x40000000, 0x40000000); 546 nv_mask(device, 0x111100, 0x40000000, 0x40000000);
519 nv_mask(dev, 0x111104, 0x00000180, 0x00000000); 547 nv_mask(device, 0x111104, 0x00000180, 0x00000000);
520 } 548 }
521 } 549 }
522 if (info->rammap && !(info->rammap[4] & 0x02)) 550 if (info->rammap && !(info->rammap[4] & 0x02))
523 nv_mask(dev, 0x100200, 0x00000800, 0x00000000); 551 nv_mask(device, 0x100200, 0x00000800, 0x00000000);
524 nv_wr32(dev, 0x611200, 0x00003300); 552 nv_wr32(device, 0x611200, 0x00003300);
525 if (!(info->ramcfg[2] & 0x10)) 553 if (!(info->ramcfg[2] & 0x10))
526 nv_wr32(dev, 0x111100, 0x4c020000); /*XXX*/ 554 nv_wr32(device, 0x111100, 0x4c020000); /*XXX*/
527 555
528 nouveau_mem_exec(&exec, info->perflvl); 556 nouveau_mem_exec(&exec, info->perflvl);
529 557
530 nv_wr32(dev, 0x611200, 0x00003330); 558 nv_wr32(device, 0x611200, 0x00003330);
531 if (info->rammap && (info->rammap[4] & 0x02)) 559 if (info->rammap && (info->rammap[4] & 0x02))
532 nv_mask(dev, 0x100200, 0x00000800, 0x00000800); 560 nv_mask(device, 0x100200, 0x00000800, 0x00000800);
533 if (info->ramcfg) { 561 if (info->ramcfg) {
534 if (info->ramcfg[2] & 0x10) { 562 if (info->ramcfg[2] & 0x10) {
535 nv_mask(dev, 0x111104, 0x00000180, 0x00000180); 563 nv_mask(device, 0x111104, 0x00000180, 0x00000180);
536 nv_mask(dev, 0x111100, 0x40000000, 0x00000000); 564 nv_mask(device, 0x111100, 0x40000000, 0x00000000);
537 } else { 565 } else {
538 nv_mask(dev, 0x111104, 0x00000600, 0x00000600); 566 nv_mask(device, 0x111104, 0x00000600, 0x00000600);
539 } 567 }
540 } 568 }
541 569
542 if (info->mclk.pll) { 570 if (info->mclk.pll) {
543 nv_mask(dev, 0x004168, 0x00000001, 0x00000000); 571 nv_mask(device, 0x004168, 0x00000001, 0x00000000);
544 nv_mask(dev, 0x004168, 0x00000100, 0x00000000); 572 nv_mask(device, 0x004168, 0x00000100, 0x00000000);
545 } else { 573 } else {
546 nv_mask(dev, 0x004000, 0x00000001, 0x00000000); 574 nv_mask(device, 0x004000, 0x00000001, 0x00000000);
547 nv_mask(dev, 0x004128, 0x00000001, 0x00000000); 575 nv_mask(device, 0x004128, 0x00000001, 0x00000000);
548 nv_mask(dev, 0x004128, 0x00000100, 0x00000000); 576 nv_mask(device, 0x004128, 0x00000100, 0x00000000);
549 } 577 }
550} 578}
551 579
552int 580int
553nva3_pm_clocks_set(struct drm_device *dev, void *pre_state) 581nva3_pm_clocks_set(struct drm_device *dev, void *pre_state)
554{ 582{
555 struct drm_nouveau_private *dev_priv = dev->dev_private; 583 struct nouveau_device *device = nouveau_dev(dev);
584 struct nouveau_drm *drm = nouveau_drm(dev);
556 struct nva3_pm_state *info = pre_state; 585 struct nva3_pm_state *info = pre_state;
557 unsigned long flags;
558 int ret = -EAGAIN; 586 int ret = -EAGAIN;
559 587
560 /* prevent any new grctx switches from starting */ 588 /* prevent any new grctx switches from starting */
561 spin_lock_irqsave(&dev_priv->context_switch_lock, flags); 589 nv_wr32(device, 0x400324, 0x00000000);
562 nv_wr32(dev, 0x400324, 0x00000000); 590 nv_wr32(device, 0x400328, 0x0050001c); /* wait flag 0x1c */
563 nv_wr32(dev, 0x400328, 0x0050001c); /* wait flag 0x1c */
564 /* wait for any pending grctx switches to complete */ 591 /* wait for any pending grctx switches to complete */
565 if (!nv_wait_cb(dev, nva3_pm_grcp_idle, dev)) { 592 if (!nv_wait_cb(device, nva3_pm_grcp_idle, dev)) {
566 NV_ERROR(dev, "pm: ctxprog didn't go idle\n"); 593 NV_ERROR(drm, "pm: ctxprog didn't go idle\n");
567 goto cleanup; 594 goto cleanup;
568 } 595 }
569 /* freeze PFIFO */ 596 /* freeze PFIFO */
570 nv_mask(dev, 0x002504, 0x00000001, 0x00000001); 597 nv_mask(device, 0x002504, 0x00000001, 0x00000001);
571 if (!nv_wait(dev, 0x002504, 0x00000010, 0x00000010)) { 598 if (!nv_wait(device, 0x002504, 0x00000010, 0x00000010)) {
572 NV_ERROR(dev, "pm: fifo didn't go idle\n"); 599 NV_ERROR(drm, "pm: fifo didn't go idle\n");
573 goto cleanup; 600 goto cleanup;
574 } 601 }
575 602
@@ -585,14 +612,13 @@ nva3_pm_clocks_set(struct drm_device *dev, void *pre_state)
585 612
586cleanup: 613cleanup:
587 /* unfreeze PFIFO */ 614 /* unfreeze PFIFO */
588 nv_mask(dev, 0x002504, 0x00000001, 0x00000000); 615 nv_mask(device, 0x002504, 0x00000001, 0x00000000);
589 /* restore ctxprog to normal */ 616 /* restore ctxprog to normal */
590 nv_wr32(dev, 0x400324, 0x00000000); 617 nv_wr32(device, 0x400324, 0x00000000);
591 nv_wr32(dev, 0x400328, 0x0070009c); /* set flag 0x1c */ 618 nv_wr32(device, 0x400328, 0x0070009c); /* set flag 0x1c */
592 /* unblock it if necessary */ 619 /* unblock it if necessary */
593 if (nv_rd32(dev, 0x400308) == 0x0050001c) 620 if (nv_rd32(device, 0x400308) == 0x0050001c)
594 nv_mask(dev, 0x400824, 0x10000000, 0x10000000); 621 nv_mask(device, 0x400824, 0x10000000, 0x10000000);
595 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
596 kfree(info); 622 kfree(info);
597 return ret; 623 return ret;
598} 624}
diff --git a/drivers/gpu/drm/nouveau/nvc0_fbcon.c b/drivers/gpu/drm/nouveau/nvc0_fbcon.c
index cc88f3649909..9dcd30f3e1e0 100644
--- a/drivers/gpu/drm/nouveau/nvc0_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nvc0_fbcon.c
@@ -30,7 +30,7 @@ int
30nvc0_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 30nvc0_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
31{ 31{
32 struct nouveau_fbdev *nfbdev = info->par; 32 struct nouveau_fbdev *nfbdev = info->par;
33 struct nouveau_drm *drm = nouveau_newpriv(nfbdev->dev); 33 struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
34 struct nouveau_channel *chan = drm->channel; 34 struct nouveau_channel *chan = drm->channel;
35 int ret; 35 int ret;
36 36
@@ -65,7 +65,7 @@ int
65nvc0_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) 65nvc0_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
66{ 66{
67 struct nouveau_fbdev *nfbdev = info->par; 67 struct nouveau_fbdev *nfbdev = info->par;
68 struct nouveau_drm *drm = nouveau_newpriv(nfbdev->dev); 68 struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
69 struct nouveau_channel *chan = drm->channel; 69 struct nouveau_channel *chan = drm->channel;
70 int ret; 70 int ret;
71 71
@@ -93,7 +93,7 @@ int
93nvc0_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) 93nvc0_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
94{ 94{
95 struct nouveau_fbdev *nfbdev = info->par; 95 struct nouveau_fbdev *nfbdev = info->par;
96 struct nouveau_drm *drm = nouveau_newpriv(nfbdev->dev); 96 struct nouveau_drm *drm = nouveau_drm(nfbdev->dev);
97 struct nouveau_channel *chan = drm->channel; 97 struct nouveau_channel *chan = drm->channel;
98 uint32_t width, dwords, *data = (uint32_t *)image->data; 98 uint32_t width, dwords, *data = (uint32_t *)image->data;
99 uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel)); 99 uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel));
@@ -152,7 +152,7 @@ nvc0_fbcon_accel_init(struct fb_info *info)
152 struct nouveau_fbdev *nfbdev = info->par; 152 struct nouveau_fbdev *nfbdev = info->par;
153 struct drm_device *dev = nfbdev->dev; 153 struct drm_device *dev = nfbdev->dev;
154 struct nouveau_framebuffer *fb = &nfbdev->nouveau_fb; 154 struct nouveau_framebuffer *fb = &nfbdev->nouveau_fb;
155 struct nouveau_drm *drm = nouveau_newpriv(dev); 155 struct nouveau_drm *drm = nouveau_drm(dev);
156 struct nouveau_channel *chan = drm->channel; 156 struct nouveau_channel *chan = drm->channel;
157 struct nouveau_object *object; 157 struct nouveau_object *object;
158 int ret, format; 158 int ret, format;
diff --git a/drivers/gpu/drm/nouveau/nvc0_fence.c b/drivers/gpu/drm/nouveau/nvc0_fence.c
index ce612ad398ad..53299eac9676 100644
--- a/drivers/gpu/drm/nouveau/nvc0_fence.c
+++ b/drivers/gpu/drm/nouveau/nvc0_fence.c
@@ -32,6 +32,8 @@
32#include "nouveau_dma.h" 32#include "nouveau_dma.h"
33#include "nouveau_fence.h" 33#include "nouveau_fence.h"
34 34
35#include "nv50_display.h"
36
35struct nvc0_fence_priv { 37struct nvc0_fence_priv {
36 struct nouveau_fence_priv base; 38 struct nouveau_fence_priv base;
37 struct nouveau_bo *bo; 39 struct nouveau_bo *bo;
@@ -114,13 +116,13 @@ nvc0_fence_context_del(struct nouveau_channel *chan)
114 116
115 if (nv_device(chan->drm->device)->card_type >= NV_D0) { 117 if (nv_device(chan->drm->device)->card_type >= NV_D0) {
116 for (i = 0; i < dev->mode_config.num_crtc; i++) { 118 for (i = 0; i < dev->mode_config.num_crtc; i++) {
117 struct nouveau_bo *bo = nvd0sema(dev, i); 119 struct nouveau_bo *bo = nvd0_display_crtc_sema(dev, i);
118 nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]); 120 nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]);
119 } 121 }
120 } else 122 } else
121 if (nv_device(chan->drm->device)->card_type >= NV_50) { 123 if (nv_device(chan->drm->device)->card_type >= NV_50) {
122 for (i = 0; i < dev->mode_config.num_crtc; i++) { 124 for (i = 0; i < dev->mode_config.num_crtc; i++) {
123 struct nouveau_bo *bo = nv50sema(dev, i); 125 struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i);
124 nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]); 126 nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]);
125 } 127 }
126 } 128 }
@@ -154,9 +156,9 @@ nvc0_fence_context_new(struct nouveau_channel *chan)
154 for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) { 156 for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) {
155 struct nouveau_bo *bo; 157 struct nouveau_bo *bo;
156 if (nv_device(chan->drm->device)->card_type >= NV_D0) 158 if (nv_device(chan->drm->device)->card_type >= NV_D0)
157 bo = nvd0sema(chan->drm->dev, i); 159 bo = nvd0_display_crtc_sema(chan->drm->dev, i);
158 else 160 else
159 bo = nv50sema(chan->drm->dev, i); 161 bo = nv50_display_crtc_sema(chan->drm->dev, i);
160 162
161 ret = nouveau_bo_vma_add(bo, client->vm, &fctx->dispc_vma[i]); 163 ret = nouveau_bo_vma_add(bo, client->vm, &fctx->dispc_vma[i]);
162 } 164 }
diff --git a/drivers/gpu/drm/nouveau/nvc0_pm.c b/drivers/gpu/drm/nouveau/nvc0_pm.c
index a14711c25176..0d34eb581179 100644
--- a/drivers/gpu/drm/nouveau/nvc0_pm.c
+++ b/drivers/gpu/drm/nouveau/nvc0_pm.c
@@ -22,18 +22,24 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24 24
25#include "drmP.h" 25#include "nouveau_drm.h"
26#include "nouveau_drv.h" 26#include "nouveau_bios.h"
27#include <nouveau_bios.h>
28#include "nouveau_pm.h" 27#include "nouveau_pm.h"
29 28
29#include <subdev/bios/pll.h>
30#include <subdev/bios.h>
31#include <subdev/clock.h>
32#include <subdev/timer.h>
33#include <subdev/fb.h>
34
30static u32 read_div(struct drm_device *, int, u32, u32); 35static u32 read_div(struct drm_device *, int, u32, u32);
31static u32 read_pll(struct drm_device *, u32); 36static u32 read_pll(struct drm_device *, u32);
32 37
33static u32 38static u32
34read_vco(struct drm_device *dev, u32 dsrc) 39read_vco(struct drm_device *dev, u32 dsrc)
35{ 40{
36 u32 ssrc = nv_rd32(dev, dsrc); 41 struct nouveau_device *device = nouveau_dev(dev);
42 u32 ssrc = nv_rd32(device, dsrc);
37 if (!(ssrc & 0x00000100)) 43 if (!(ssrc & 0x00000100))
38 return read_pll(dev, 0x00e800); 44 return read_pll(dev, 0x00e800);
39 return read_pll(dev, 0x00e820); 45 return read_pll(dev, 0x00e820);
@@ -42,8 +48,9 @@ read_vco(struct drm_device *dev, u32 dsrc)
42static u32 48static u32
43read_pll(struct drm_device *dev, u32 pll) 49read_pll(struct drm_device *dev, u32 pll)
44{ 50{
45 u32 ctrl = nv_rd32(dev, pll + 0); 51 struct nouveau_device *device = nouveau_dev(dev);
46 u32 coef = nv_rd32(dev, pll + 4); 52 u32 ctrl = nv_rd32(device, pll + 0);
53 u32 coef = nv_rd32(device, pll + 4);
47 u32 P = (coef & 0x003f0000) >> 16; 54 u32 P = (coef & 0x003f0000) >> 16;
48 u32 N = (coef & 0x0000ff00) >> 8; 55 u32 N = (coef & 0x0000ff00) >> 8;
49 u32 M = (coef & 0x000000ff) >> 0; 56 u32 M = (coef & 0x000000ff) >> 0;
@@ -83,8 +90,9 @@ read_pll(struct drm_device *dev, u32 pll)
83static u32 90static u32
84read_div(struct drm_device *dev, int doff, u32 dsrc, u32 dctl) 91read_div(struct drm_device *dev, int doff, u32 dsrc, u32 dctl)
85{ 92{
86 u32 ssrc = nv_rd32(dev, dsrc + (doff * 4)); 93 struct nouveau_device *device = nouveau_dev(dev);
87 u32 sctl = nv_rd32(dev, dctl + (doff * 4)); 94 u32 ssrc = nv_rd32(device, dsrc + (doff * 4));
95 u32 sctl = nv_rd32(device, dctl + (doff * 4));
88 96
89 switch (ssrc & 0x00000003) { 97 switch (ssrc & 0x00000003) {
90 case 0: 98 case 0:
@@ -109,7 +117,8 @@ read_div(struct drm_device *dev, int doff, u32 dsrc, u32 dctl)
109static u32 117static u32
110read_mem(struct drm_device *dev) 118read_mem(struct drm_device *dev)
111{ 119{
112 u32 ssel = nv_rd32(dev, 0x1373f0); 120 struct nouveau_device *device = nouveau_dev(dev);
121 u32 ssel = nv_rd32(device, 0x1373f0);
113 if (ssel & 0x00000001) 122 if (ssel & 0x00000001)
114 return read_div(dev, 0, 0x137300, 0x137310); 123 return read_div(dev, 0, 0x137300, 0x137310);
115 return read_pll(dev, 0x132000); 124 return read_pll(dev, 0x132000);
@@ -118,8 +127,9 @@ read_mem(struct drm_device *dev)
118static u32 127static u32
119read_clk(struct drm_device *dev, int clk) 128read_clk(struct drm_device *dev, int clk)
120{ 129{
121 u32 sctl = nv_rd32(dev, 0x137250 + (clk * 4)); 130 struct nouveau_device *device = nouveau_dev(dev);
122 u32 ssel = nv_rd32(dev, 0x137100); 131 u32 sctl = nv_rd32(device, 0x137250 + (clk * 4));
132 u32 ssel = nv_rd32(device, 0x137100);
123 u32 sclk, sdiv; 133 u32 sclk, sdiv;
124 134
125 if (ssel & (1 << clk)) { 135 if (ssel & (1 << clk)) {
@@ -212,10 +222,12 @@ calc_src(struct drm_device *dev, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
212static u32 222static u32
213calc_pll(struct drm_device *dev, int clk, u32 freq, u32 *coef) 223calc_pll(struct drm_device *dev, int clk, u32 freq, u32 *coef)
214{ 224{
225 struct nouveau_device *device = nouveau_dev(dev);
226 struct nouveau_bios *bios = nouveau_bios(device);
215 struct nvbios_pll limits; 227 struct nvbios_pll limits;
216 int N, M, P, ret; 228 int N, M, P, ret;
217 229
218 ret = get_pll_limits(dev, 0x137000 + (clk * 0x20), &limits); 230 ret = nvbios_pll_parse(bios, 0x137000 + (clk * 0x20), &limits);
219 if (ret) 231 if (ret)
220 return 0; 232 return 0;
221 233
@@ -308,31 +320,33 @@ calc_clk(struct drm_device *dev, int clk, struct nvc0_pm_clock *info, u32 freq)
308static int 320static int
309calc_mem(struct drm_device *dev, struct nvc0_pm_clock *info, u32 freq) 321calc_mem(struct drm_device *dev, struct nvc0_pm_clock *info, u32 freq)
310{ 322{
323 struct nouveau_device *device = nouveau_dev(dev);
324 struct nouveau_bios *bios = nouveau_bios(device);
311 struct nvbios_pll pll; 325 struct nvbios_pll pll;
312 int N, M, P, ret; 326 int N, M, P, ret;
313 u32 ctrl; 327 u32 ctrl;
314 328
315 /* mclk pll input freq comes from another pll, make sure it's on */ 329 /* mclk pll input freq comes from another pll, make sure it's on */
316 ctrl = nv_rd32(dev, 0x132020); 330 ctrl = nv_rd32(device, 0x132020);
317 if (!(ctrl & 0x00000001)) { 331 if (!(ctrl & 0x00000001)) {
318 /* if not, program it to 567MHz. nfi where this value comes 332 /* if not, program it to 567MHz. nfi where this value comes
319 * from - it looks like it's in the pll limits table for 333 * from - it looks like it's in the pll limits table for
320 * 132000 but the binary driver ignores all my attempts to 334 * 132000 but the binary driver ignores all my attempts to
321 * change this value. 335 * change this value.
322 */ 336 */
323 nv_wr32(dev, 0x137320, 0x00000103); 337 nv_wr32(device, 0x137320, 0x00000103);
324 nv_wr32(dev, 0x137330, 0x81200606); 338 nv_wr32(device, 0x137330, 0x81200606);
325 nv_wait(dev, 0x132020, 0x00010000, 0x00010000); 339 nv_wait(device, 0x132020, 0x00010000, 0x00010000);
326 nv_wr32(dev, 0x132024, 0x0001150f); 340 nv_wr32(device, 0x132024, 0x0001150f);
327 nv_mask(dev, 0x132020, 0x00000001, 0x00000001); 341 nv_mask(device, 0x132020, 0x00000001, 0x00000001);
328 nv_wait(dev, 0x137390, 0x00020000, 0x00020000); 342 nv_wait(device, 0x137390, 0x00020000, 0x00020000);
329 nv_mask(dev, 0x132020, 0x00000004, 0x00000004); 343 nv_mask(device, 0x132020, 0x00000004, 0x00000004);
330 } 344 }
331 345
332 /* for the moment, until the clock tree is better understood, use 346 /* for the moment, until the clock tree is better understood, use
333 * pll mode for all clock frequencies 347 * pll mode for all clock frequencies
334 */ 348 */
335 ret = get_pll_limits(dev, 0x132000, &pll); 349 ret = nvbios_pll_parse(bios, 0x132000, &pll);
336 if (ret == 0) { 350 if (ret == 0) {
337 pll.refclk = read_pll(dev, 0x132020); 351 pll.refclk = read_pll(dev, 0x132020);
338 if (pll.refclk) { 352 if (pll.refclk) {
@@ -350,7 +364,7 @@ calc_mem(struct drm_device *dev, struct nvc0_pm_clock *info, u32 freq)
350void * 364void *
351nvc0_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl) 365nvc0_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
352{ 366{
353 struct drm_nouveau_private *dev_priv = dev->dev_private; 367 struct nouveau_device *device = nouveau_dev(dev);
354 struct nvc0_pm_state *info; 368 struct nvc0_pm_state *info;
355 int ret; 369 int ret;
356 370
@@ -364,7 +378,7 @@ nvc0_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
364 * are always the same freq with the binary driver even when the 378 * are always the same freq with the binary driver even when the
365 * performance table says they should differ. 379 * performance table says they should differ.
366 */ 380 */
367 if (dev_priv->chipset == 0xd9) 381 if (device->chipset == 0xd9)
368 perflvl->rop = 0; 382 perflvl->rop = 0;
369 383
370 if ((ret = calc_clk(dev, 0x00, &info->eng[0x00], perflvl->shader)) || 384 if ((ret = calc_clk(dev, 0x00, &info->eng[0x00], perflvl->shader)) ||
@@ -394,38 +408,40 @@ nvc0_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl)
394static void 408static void
395prog_clk(struct drm_device *dev, int clk, struct nvc0_pm_clock *info) 409prog_clk(struct drm_device *dev, int clk, struct nvc0_pm_clock *info)
396{ 410{
411 struct nouveau_device *device = nouveau_dev(dev);
412
397 /* program dividers at 137160/1371d0 first */ 413 /* program dividers at 137160/1371d0 first */
398 if (clk < 7 && !info->ssel) { 414 if (clk < 7 && !info->ssel) {
399 nv_mask(dev, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv); 415 nv_mask(device, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv);
400 nv_wr32(dev, 0x137160 + (clk * 0x04), info->dsrc); 416 nv_wr32(device, 0x137160 + (clk * 0x04), info->dsrc);
401 } 417 }
402 418
403 /* switch clock to non-pll mode */ 419 /* switch clock to non-pll mode */
404 nv_mask(dev, 0x137100, (1 << clk), 0x00000000); 420 nv_mask(device, 0x137100, (1 << clk), 0x00000000);
405 nv_wait(dev, 0x137100, (1 << clk), 0x00000000); 421 nv_wait(device, 0x137100, (1 << clk), 0x00000000);
406 422
407 /* reprogram pll */ 423 /* reprogram pll */
408 if (clk < 7) { 424 if (clk < 7) {
409 /* make sure it's disabled first... */ 425 /* make sure it's disabled first... */
410 u32 base = 0x137000 + (clk * 0x20); 426 u32 base = 0x137000 + (clk * 0x20);
411 u32 ctrl = nv_rd32(dev, base + 0x00); 427 u32 ctrl = nv_rd32(device, base + 0x00);
412 if (ctrl & 0x00000001) { 428 if (ctrl & 0x00000001) {
413 nv_mask(dev, base + 0x00, 0x00000004, 0x00000000); 429 nv_mask(device, base + 0x00, 0x00000004, 0x00000000);
414 nv_mask(dev, base + 0x00, 0x00000001, 0x00000000); 430 nv_mask(device, base + 0x00, 0x00000001, 0x00000000);
415 } 431 }
416 /* program it to new values, if necessary */ 432 /* program it to new values, if necessary */
417 if (info->ssel) { 433 if (info->ssel) {
418 nv_wr32(dev, base + 0x04, info->coef); 434 nv_wr32(device, base + 0x04, info->coef);
419 nv_mask(dev, base + 0x00, 0x00000001, 0x00000001); 435 nv_mask(device, base + 0x00, 0x00000001, 0x00000001);
420 nv_wait(dev, base + 0x00, 0x00020000, 0x00020000); 436 nv_wait(device, base + 0x00, 0x00020000, 0x00020000);
421 nv_mask(dev, base + 0x00, 0x00020004, 0x00000004); 437 nv_mask(device, base + 0x00, 0x00020004, 0x00000004);
422 } 438 }
423 } 439 }
424 440
425 /* select pll/non-pll mode, and program final clock divider */ 441 /* select pll/non-pll mode, and program final clock divider */
426 nv_mask(dev, 0x137100, (1 << clk), info->ssel); 442 nv_mask(device, 0x137100, (1 << clk), info->ssel);
427 nv_wait(dev, 0x137100, (1 << clk), info->ssel); 443 nv_wait(device, 0x137100, (1 << clk), info->ssel);
428 nv_mask(dev, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv); 444 nv_mask(device, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv);
429} 445}
430 446
431static void 447static void
@@ -441,7 +457,8 @@ mclk_refresh(struct nouveau_mem_exec_func *exec)
441static void 457static void
442mclk_refresh_auto(struct nouveau_mem_exec_func *exec, bool enable) 458mclk_refresh_auto(struct nouveau_mem_exec_func *exec, bool enable)
443{ 459{
444 nv_wr32(exec->dev, 0x10f210, enable ? 0x80000000 : 0x00000000); 460 struct nouveau_device *device = nouveau_dev(exec->dev);
461 nv_wr32(device, 0x10f210, enable ? 0x80000000 : 0x00000000);
445} 462}
446 463
447static void 464static void
@@ -458,81 +475,84 @@ mclk_wait(struct nouveau_mem_exec_func *exec, u32 nsec)
458static u32 475static u32
459mclk_mrg(struct nouveau_mem_exec_func *exec, int mr) 476mclk_mrg(struct nouveau_mem_exec_func *exec, int mr)
460{ 477{
461 struct drm_device *dev = exec->dev; 478 struct nouveau_device *device = nouveau_dev(exec->dev);
462 if (nvfb_vram_type(dev) != NV_MEM_TYPE_GDDR5) { 479 struct nouveau_fb *pfb = nouveau_fb(device);
480 if (pfb->ram.type != NV_MEM_TYPE_GDDR5) {
463 if (mr <= 1) 481 if (mr <= 1)
464 return nv_rd32(dev, 0x10f300 + ((mr - 0) * 4)); 482 return nv_rd32(device, 0x10f300 + ((mr - 0) * 4));
465 return nv_rd32(dev, 0x10f320 + ((mr - 2) * 4)); 483 return nv_rd32(device, 0x10f320 + ((mr - 2) * 4));
466 } else { 484 } else {
467 if (mr == 0) 485 if (mr == 0)
468 return nv_rd32(dev, 0x10f300 + (mr * 4)); 486 return nv_rd32(device, 0x10f300 + (mr * 4));
469 else 487 else
470 if (mr <= 7) 488 if (mr <= 7)
471 return nv_rd32(dev, 0x10f32c + (mr * 4)); 489 return nv_rd32(device, 0x10f32c + (mr * 4));
472 return nv_rd32(dev, 0x10f34c); 490 return nv_rd32(device, 0x10f34c);
473 } 491 }
474} 492}
475 493
476static void 494static void
477mclk_mrs(struct nouveau_mem_exec_func *exec, int mr, u32 data) 495mclk_mrs(struct nouveau_mem_exec_func *exec, int mr, u32 data)
478{ 496{
479 struct drm_device *dev = exec->dev; 497 struct nouveau_device *device = nouveau_dev(exec->dev);
480 if (nvfb_vram_type(dev) != NV_MEM_TYPE_GDDR5) { 498 struct nouveau_fb *pfb = nouveau_fb(device);
499 if (pfb->ram.type != NV_MEM_TYPE_GDDR5) {
481 if (mr <= 1) { 500 if (mr <= 1) {
482 nv_wr32(dev, 0x10f300 + ((mr - 0) * 4), data); 501 nv_wr32(device, 0x10f300 + ((mr - 0) * 4), data);
483 if (nvfb_vram_rank_B(dev)) 502 if (pfb->ram.ranks > 1)
484 nv_wr32(dev, 0x10f308 + ((mr - 0) * 4), data); 503 nv_wr32(device, 0x10f308 + ((mr - 0) * 4), data);
485 } else 504 } else
486 if (mr <= 3) { 505 if (mr <= 3) {
487 nv_wr32(dev, 0x10f320 + ((mr - 2) * 4), data); 506 nv_wr32(device, 0x10f320 + ((mr - 2) * 4), data);
488 if (nvfb_vram_rank_B(dev)) 507 if (pfb->ram.ranks > 1)
489 nv_wr32(dev, 0x10f328 + ((mr - 2) * 4), data); 508 nv_wr32(device, 0x10f328 + ((mr - 2) * 4), data);
490 } 509 }
491 } else { 510 } else {
492 if (mr == 0) nv_wr32(dev, 0x10f300 + (mr * 4), data); 511 if (mr == 0) nv_wr32(device, 0x10f300 + (mr * 4), data);
493 else if (mr <= 7) nv_wr32(dev, 0x10f32c + (mr * 4), data); 512 else if (mr <= 7) nv_wr32(device, 0x10f32c + (mr * 4), data);
494 else if (mr == 15) nv_wr32(dev, 0x10f34c, data); 513 else if (mr == 15) nv_wr32(device, 0x10f34c, data);
495 } 514 }
496} 515}
497 516
498static void 517static void
499mclk_clock_set(struct nouveau_mem_exec_func *exec) 518mclk_clock_set(struct nouveau_mem_exec_func *exec)
500{ 519{
520 struct nouveau_device *device = nouveau_dev(exec->dev);
501 struct nvc0_pm_state *info = exec->priv; 521 struct nvc0_pm_state *info = exec->priv;
502 struct drm_device *dev = exec->dev; 522 u32 ctrl = nv_rd32(device, 0x132000);
503 u32 ctrl = nv_rd32(dev, 0x132000);
504 523
505 nv_wr32(dev, 0x137360, 0x00000001); 524 nv_wr32(device, 0x137360, 0x00000001);
506 nv_wr32(dev, 0x137370, 0x00000000); 525 nv_wr32(device, 0x137370, 0x00000000);
507 nv_wr32(dev, 0x137380, 0x00000000); 526 nv_wr32(device, 0x137380, 0x00000000);
508 if (ctrl & 0x00000001) 527 if (ctrl & 0x00000001)
509 nv_wr32(dev, 0x132000, (ctrl &= ~0x00000001)); 528 nv_wr32(device, 0x132000, (ctrl &= ~0x00000001));
510 529
511 nv_wr32(dev, 0x132004, info->mem.coef); 530 nv_wr32(device, 0x132004, info->mem.coef);
512 nv_wr32(dev, 0x132000, (ctrl |= 0x00000001)); 531 nv_wr32(device, 0x132000, (ctrl |= 0x00000001));
513 nv_wait(dev, 0x137390, 0x00000002, 0x00000002); 532 nv_wait(device, 0x137390, 0x00000002, 0x00000002);
514 nv_wr32(dev, 0x132018, 0x00005000); 533 nv_wr32(device, 0x132018, 0x00005000);
515 534
516 nv_wr32(dev, 0x137370, 0x00000001); 535 nv_wr32(device, 0x137370, 0x00000001);
517 nv_wr32(dev, 0x137380, 0x00000001); 536 nv_wr32(device, 0x137380, 0x00000001);
518 nv_wr32(dev, 0x137360, 0x00000000); 537 nv_wr32(device, 0x137360, 0x00000000);
519} 538}
520 539
521static void 540static void
522mclk_timing_set(struct nouveau_mem_exec_func *exec) 541mclk_timing_set(struct nouveau_mem_exec_func *exec)
523{ 542{
543 struct nouveau_device *device = nouveau_dev(exec->dev);
524 struct nvc0_pm_state *info = exec->priv; 544 struct nvc0_pm_state *info = exec->priv;
525 struct nouveau_pm_level *perflvl = info->perflvl; 545 struct nouveau_pm_level *perflvl = info->perflvl;
526 int i; 546 int i;
527 547
528 for (i = 0; i < 5; i++) 548 for (i = 0; i < 5; i++)
529 nv_wr32(exec->dev, 0x10f290 + (i * 4), perflvl->timing.reg[i]); 549 nv_wr32(device, 0x10f290 + (i * 4), perflvl->timing.reg[i]);
530} 550}
531 551
532static void 552static void
533prog_mem(struct drm_device *dev, struct nvc0_pm_state *info) 553prog_mem(struct drm_device *dev, struct nvc0_pm_state *info)
534{ 554{
535 struct drm_nouveau_private *dev_priv = dev->dev_private; 555 struct nouveau_device *device = nouveau_dev(dev);
536 struct nouveau_mem_exec_func exec = { 556 struct nouveau_mem_exec_func exec = {
537 .dev = dev, 557 .dev = dev,
538 .precharge = mclk_precharge, 558 .precharge = mclk_precharge,
@@ -547,17 +567,17 @@ prog_mem(struct drm_device *dev, struct nvc0_pm_state *info)
547 .priv = info 567 .priv = info
548 }; 568 };
549 569
550 if (dev_priv->chipset < 0xd0) 570 if (device->chipset < 0xd0)
551 nv_wr32(dev, 0x611200, 0x00003300); 571 nv_wr32(device, 0x611200, 0x00003300);
552 else 572 else
553 nv_wr32(dev, 0x62c000, 0x03030000); 573 nv_wr32(device, 0x62c000, 0x03030000);
554 574
555 nouveau_mem_exec(&exec, info->perflvl); 575 nouveau_mem_exec(&exec, info->perflvl);
556 576
557 if (dev_priv->chipset < 0xd0) 577 if (device->chipset < 0xd0)
558 nv_wr32(dev, 0x611200, 0x00003330); 578 nv_wr32(device, 0x611200, 0x00003330);
559 else 579 else
560 nv_wr32(dev, 0x62c000, 0x03030300); 580 nv_wr32(device, 0x62c000, 0x03030300);
561} 581}
562int 582int
563nvc0_pm_clocks_set(struct drm_device *dev, void *data) 583nvc0_pm_clocks_set(struct drm_device *dev, void *data)
diff --git a/drivers/gpu/drm/nouveau/nvd0_display.c b/drivers/gpu/drm/nouveau/nvd0_display.c
index 77d5ce365bb2..37037bc33266 100644
--- a/drivers/gpu/drm/nouveau/nvd0_display.c
+++ b/drivers/gpu/drm/nouveau/nvd0_display.c
@@ -27,14 +27,21 @@
27#include "drmP.h" 27#include "drmP.h"
28#include "drm_crtc_helper.h" 28#include "drm_crtc_helper.h"
29 29
30#include "nouveau_drv.h" 30#include "nouveau_drm.h"
31#include "nouveau_dma.h"
32#include "nouveau_gem.h"
31#include "nouveau_connector.h" 33#include "nouveau_connector.h"
32#include "nouveau_encoder.h" 34#include "nouveau_encoder.h"
33#include "nouveau_crtc.h" 35#include "nouveau_crtc.h"
34#include "nouveau_fb.h"
35#include "nouveau_fence.h" 36#include "nouveau_fence.h"
36#include "nv50_display.h" 37#include "nv50_display.h"
37 38
39#include <core/gpuobj.h>
40
41#include <subdev/timer.h>
42#include <subdev/bar.h>
43#include <subdev/fb.h>
44
38#define EVO_DMA_NR 9 45#define EVO_DMA_NR 9
39 46
40#define EVO_MASTER (0x00) 47#define EVO_MASTER (0x00)
@@ -71,8 +78,7 @@ struct nvd0_display {
71static struct nvd0_display * 78static struct nvd0_display *
72nvd0_display(struct drm_device *dev) 79nvd0_display(struct drm_device *dev)
73{ 80{
74 struct drm_nouveau_private *dev_priv = dev->dev_private; 81 return nouveau_display(dev)->priv;
75 return dev_priv->engine.display.priv;
76} 82}
77 83
78static struct drm_crtc * 84static struct drm_crtc *
@@ -87,28 +93,31 @@ nvd0_display_crtc_get(struct drm_encoder *encoder)
87static inline int 93static inline int
88evo_icmd(struct drm_device *dev, int id, u32 mthd, u32 data) 94evo_icmd(struct drm_device *dev, int id, u32 mthd, u32 data)
89{ 95{
96 struct nouveau_device *device = nouveau_dev(dev);
90 int ret = 0; 97 int ret = 0;
91 nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000001); 98 nv_mask(device, 0x610700 + (id * 0x10), 0x00000001, 0x00000001);
92 nv_wr32(dev, 0x610704 + (id * 0x10), data); 99 nv_wr32(device, 0x610704 + (id * 0x10), data);
93 nv_mask(dev, 0x610704 + (id * 0x10), 0x80000ffc, 0x80000000 | mthd); 100 nv_mask(device, 0x610704 + (id * 0x10), 0x80000ffc, 0x80000000 | mthd);
94 if (!nv_wait(dev, 0x610704 + (id * 0x10), 0x80000000, 0x00000000)) 101 if (!nv_wait(device, 0x610704 + (id * 0x10), 0x80000000, 0x00000000))
95 ret = -EBUSY; 102 ret = -EBUSY;
96 nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000000); 103 nv_mask(device, 0x610700 + (id * 0x10), 0x00000001, 0x00000000);
97 return ret; 104 return ret;
98} 105}
99 106
100static u32 * 107static u32 *
101evo_wait(struct drm_device *dev, int id, int nr) 108evo_wait(struct drm_device *dev, int id, int nr)
102{ 109{
110 struct nouveau_device *device = nouveau_dev(dev);
111 struct nouveau_drm *drm = nouveau_drm(dev);
103 struct nvd0_display *disp = nvd0_display(dev); 112 struct nvd0_display *disp = nvd0_display(dev);
104 u32 put = nv_rd32(dev, 0x640000 + (id * 0x1000)) / 4; 113 u32 put = nv_rd32(device, 0x640000 + (id * 0x1000)) / 4;
105 114
106 if (put + nr >= (PAGE_SIZE / 4)) { 115 if (put + nr >= (PAGE_SIZE / 4)) {
107 disp->evo[id].ptr[put] = 0x20000000; 116 disp->evo[id].ptr[put] = 0x20000000;
108 117
109 nv_wr32(dev, 0x640000 + (id * 0x1000), 0x00000000); 118 nv_wr32(device, 0x640000 + (id * 0x1000), 0x00000000);
110 if (!nv_wait(dev, 0x640004 + (id * 0x1000), ~0, 0x00000000)) { 119 if (!nv_wait(device, 0x640004 + (id * 0x1000), ~0, 0x00000000)) {
111 NV_ERROR(dev, "evo %d dma stalled\n", id); 120 NV_ERROR(drm, "evo %d dma stalled\n", id);
112 return NULL; 121 return NULL;
113 } 122 }
114 123
@@ -121,9 +130,10 @@ evo_wait(struct drm_device *dev, int id, int nr)
121static void 130static void
122evo_kick(u32 *push, struct drm_device *dev, int id) 131evo_kick(u32 *push, struct drm_device *dev, int id)
123{ 132{
133 struct nouveau_device *device = nouveau_dev(dev);
124 struct nvd0_display *disp = nvd0_display(dev); 134 struct nvd0_display *disp = nvd0_display(dev);
125 135
126 nv_wr32(dev, 0x640000 + (id * 0x1000), (push - disp->evo[id].ptr) << 2); 136 nv_wr32(device, 0x640000 + (id * 0x1000), (push - disp->evo[id].ptr) << 2);
127} 137}
128 138
129#define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m)) 139#define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
@@ -132,6 +142,8 @@ evo_kick(u32 *push, struct drm_device *dev, int id)
132static int 142static int
133evo_init_dma(struct drm_device *dev, int ch) 143evo_init_dma(struct drm_device *dev, int ch)
134{ 144{
145 struct nouveau_device *device = nouveau_dev(dev);
146 struct nouveau_drm *drm = nouveau_drm(dev);
135 struct nvd0_display *disp = nvd0_display(dev); 147 struct nvd0_display *disp = nvd0_display(dev);
136 u32 flags; 148 u32 flags;
137 149
@@ -139,68 +151,76 @@ evo_init_dma(struct drm_device *dev, int ch)
139 if (ch == EVO_MASTER) 151 if (ch == EVO_MASTER)
140 flags |= 0x01000000; 152 flags |= 0x01000000;
141 153
142 nv_wr32(dev, 0x610494 + (ch * 0x0010), (disp->evo[ch].handle >> 8) | 3); 154 nv_wr32(device, 0x610494 + (ch * 0x0010), (disp->evo[ch].handle >> 8) | 3);
143 nv_wr32(dev, 0x610498 + (ch * 0x0010), 0x00010000); 155 nv_wr32(device, 0x610498 + (ch * 0x0010), 0x00010000);
144 nv_wr32(dev, 0x61049c + (ch * 0x0010), 0x00000001); 156 nv_wr32(device, 0x61049c + (ch * 0x0010), 0x00000001);
145 nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000010, 0x00000010); 157 nv_mask(device, 0x610490 + (ch * 0x0010), 0x00000010, 0x00000010);
146 nv_wr32(dev, 0x640000 + (ch * 0x1000), 0x00000000); 158 nv_wr32(device, 0x640000 + (ch * 0x1000), 0x00000000);
147 nv_wr32(dev, 0x610490 + (ch * 0x0010), 0x00000013 | flags); 159 nv_wr32(device, 0x610490 + (ch * 0x0010), 0x00000013 | flags);
148 if (!nv_wait(dev, 0x610490 + (ch * 0x0010), 0x80000000, 0x00000000)) { 160 if (!nv_wait(device, 0x610490 + (ch * 0x0010), 0x80000000, 0x00000000)) {
149 NV_ERROR(dev, "PDISP: ch%d 0x%08x\n", ch, 161 NV_ERROR(drm, "PDISP: ch%d 0x%08x\n", ch,
150 nv_rd32(dev, 0x610490 + (ch * 0x0010))); 162 nv_rd32(device, 0x610490 + (ch * 0x0010)));
151 return -EBUSY; 163 return -EBUSY;
152 } 164 }
153 165
154 nv_mask(dev, 0x610090, (1 << ch), (1 << ch)); 166 nv_mask(device, 0x610090, (1 << ch), (1 << ch));
155 nv_mask(dev, 0x6100a0, (1 << ch), (1 << ch)); 167 nv_mask(device, 0x6100a0, (1 << ch), (1 << ch));
156 return 0; 168 return 0;
157} 169}
158 170
159static void 171static void
160evo_fini_dma(struct drm_device *dev, int ch) 172evo_fini_dma(struct drm_device *dev, int ch)
161{ 173{
162 if (!(nv_rd32(dev, 0x610490 + (ch * 0x0010)) & 0x00000010)) 174 struct nouveau_device *device = nouveau_dev(dev);
175
176 if (!(nv_rd32(device, 0x610490 + (ch * 0x0010)) & 0x00000010))
163 return; 177 return;
164 178
165 nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000010, 0x00000000); 179 nv_mask(device, 0x610490 + (ch * 0x0010), 0x00000010, 0x00000000);
166 nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000003, 0x00000000); 180 nv_mask(device, 0x610490 + (ch * 0x0010), 0x00000003, 0x00000000);
167 nv_wait(dev, 0x610490 + (ch * 0x0010), 0x80000000, 0x00000000); 181 nv_wait(device, 0x610490 + (ch * 0x0010), 0x80000000, 0x00000000);
168 nv_mask(dev, 0x610090, (1 << ch), 0x00000000); 182 nv_mask(device, 0x610090, (1 << ch), 0x00000000);
169 nv_mask(dev, 0x6100a0, (1 << ch), 0x00000000); 183 nv_mask(device, 0x6100a0, (1 << ch), 0x00000000);
170} 184}
171 185
172static inline void 186static inline void
173evo_piow(struct drm_device *dev, int ch, u16 mthd, u32 data) 187evo_piow(struct drm_device *dev, int ch, u16 mthd, u32 data)
174{ 188{
175 nv_wr32(dev, 0x640000 + (ch * 0x1000) + mthd, data); 189 struct nouveau_device *device = nouveau_dev(dev);
190 nv_wr32(device, 0x640000 + (ch * 0x1000) + mthd, data);
176} 191}
177 192
178static int 193static int
179evo_init_pio(struct drm_device *dev, int ch) 194evo_init_pio(struct drm_device *dev, int ch)
180{ 195{
181 nv_wr32(dev, 0x610490 + (ch * 0x0010), 0x00000001); 196 struct nouveau_device *device = nouveau_dev(dev);
182 if (!nv_wait(dev, 0x610490 + (ch * 0x0010), 0x00010000, 0x00010000)) { 197 struct nouveau_drm *drm = nouveau_drm(dev);
183 NV_ERROR(dev, "PDISP: ch%d 0x%08x\n", ch, 198
184 nv_rd32(dev, 0x610490 + (ch * 0x0010))); 199 nv_wr32(device, 0x610490 + (ch * 0x0010), 0x00000001);
200 if (!nv_wait(device, 0x610490 + (ch * 0x0010), 0x00010000, 0x00010000)) {
201 NV_ERROR(drm, "PDISP: ch%d 0x%08x\n", ch,
202 nv_rd32(device, 0x610490 + (ch * 0x0010)));
185 return -EBUSY; 203 return -EBUSY;
186 } 204 }
187 205
188 nv_mask(dev, 0x610090, (1 << ch), (1 << ch)); 206 nv_mask(device, 0x610090, (1 << ch), (1 << ch));
189 nv_mask(dev, 0x6100a0, (1 << ch), (1 << ch)); 207 nv_mask(device, 0x6100a0, (1 << ch), (1 << ch));
190 return 0; 208 return 0;
191} 209}
192 210
193static void 211static void
194evo_fini_pio(struct drm_device *dev, int ch) 212evo_fini_pio(struct drm_device *dev, int ch)
195{ 213{
196 if (!(nv_rd32(dev, 0x610490 + (ch * 0x0010)) & 0x00000001)) 214 struct nouveau_device *device = nouveau_dev(dev);
215
216 if (!(nv_rd32(device, 0x610490 + (ch * 0x0010)) & 0x00000001))
197 return; 217 return;
198 218
199 nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000010, 0x00000010); 219 nv_mask(device, 0x610490 + (ch * 0x0010), 0x00000010, 0x00000010);
200 nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000001, 0x00000000); 220 nv_mask(device, 0x610490 + (ch * 0x0010), 0x00000001, 0x00000000);
201 nv_wait(dev, 0x610490 + (ch * 0x0010), 0x00010000, 0x00000000); 221 nv_wait(device, 0x610490 + (ch * 0x0010), 0x00010000, 0x00000000);
202 nv_mask(dev, 0x610090, (1 << ch), 0x00000000); 222 nv_mask(device, 0x610090, (1 << ch), 0x00000000);
203 nv_mask(dev, 0x6100a0, (1 << ch), 0x00000000); 223 nv_mask(device, 0x6100a0, (1 << ch), 0x00000000);
204} 224}
205 225
206static bool 226static bool
@@ -212,6 +232,7 @@ evo_sync_wait(void *data)
212static int 232static int
213evo_sync(struct drm_device *dev, int ch) 233evo_sync(struct drm_device *dev, int ch)
214{ 234{
235 struct nouveau_device *device = nouveau_dev(dev);
215 struct nvd0_display *disp = nvd0_display(dev); 236 struct nvd0_display *disp = nvd0_display(dev);
216 u32 *push = evo_wait(dev, ch, 8); 237 u32 *push = evo_wait(dev, ch, 8);
217 if (push) { 238 if (push) {
@@ -222,7 +243,7 @@ evo_sync(struct drm_device *dev, int ch)
222 evo_data(push, 0x00000000); 243 evo_data(push, 0x00000000);
223 evo_data(push, 0x00000000); 244 evo_data(push, 0x00000000);
224 evo_kick(push, dev, ch); 245 evo_kick(push, dev, ch);
225 if (nv_wait_cb(dev, evo_sync_wait, disp->sync)) 246 if (nv_wait_cb(device, evo_sync_wait, disp->sync))
226 return 0; 247 return 0;
227 } 248 }
228 249
@@ -350,7 +371,7 @@ nvd0_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
350static int 371static int
351nvd0_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update) 372nvd0_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
352{ 373{
353 struct drm_nouveau_private *dev_priv = nv_crtc->base.dev->dev_private; 374 struct nouveau_drm *drm = nouveau_drm(nv_crtc->base.dev);
354 struct drm_device *dev = nv_crtc->base.dev; 375 struct drm_device *dev = nv_crtc->base.dev;
355 struct nouveau_connector *nv_connector; 376 struct nouveau_connector *nv_connector;
356 struct drm_connector *connector; 377 struct drm_connector *connector;
@@ -373,7 +394,7 @@ nvd0_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
373 mode |= nv_connector->dithering_depth; 394 mode |= nv_connector->dithering_depth;
374 } 395 }
375 396
376 if (dev_priv->card_type < NV_E0) 397 if (nv_device(drm->device)->card_type < NV_E0)
377 mthd = 0x0490 + (nv_crtc->index * 0x0300); 398 mthd = 0x0490 + (nv_crtc->index * 0x0300);
378 else 399 else
379 mthd = 0x04a0 + (nv_crtc->index * 0x0300); 400 mthd = 0x04a0 + (nv_crtc->index * 0x0300);
@@ -688,11 +709,12 @@ static int
688nvd0_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 709nvd0_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
689 struct drm_framebuffer *old_fb) 710 struct drm_framebuffer *old_fb)
690{ 711{
712 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
691 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 713 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
692 int ret; 714 int ret;
693 715
694 if (!crtc->fb) { 716 if (!crtc->fb) {
695 NV_DEBUG_KMS(crtc->dev, "No FB bound\n"); 717 NV_DEBUG(drm, "No FB bound\n");
696 return 0; 718 return 0;
697 } 719 }
698 720
@@ -910,6 +932,7 @@ nvd0_dac_dpms(struct drm_encoder *encoder, int mode)
910{ 932{
911 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 933 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
912 struct drm_device *dev = encoder->dev; 934 struct drm_device *dev = encoder->dev;
935 struct nouveau_device *device = nouveau_dev(dev);
913 int or = nv_encoder->or; 936 int or = nv_encoder->or;
914 u32 dpms_ctrl; 937 u32 dpms_ctrl;
915 938
@@ -919,9 +942,9 @@ nvd0_dac_dpms(struct drm_encoder *encoder, int mode)
919 if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF) 942 if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF)
920 dpms_ctrl |= 0x00000004; 943 dpms_ctrl |= 0x00000004;
921 944
922 nv_wait(dev, 0x61a004 + (or * 0x0800), 0x80000000, 0x00000000); 945 nv_wait(device, 0x61a004 + (or * 0x0800), 0x80000000, 0x00000000);
923 nv_mask(dev, 0x61a004 + (or * 0x0800), 0xc000007f, dpms_ctrl); 946 nv_mask(device, 0x61a004 + (or * 0x0800), 0xc000007f, dpms_ctrl);
924 nv_wait(dev, 0x61a004 + (or * 0x0800), 0x80000000, 0x00000000); 947 nv_wait(device, 0x61a004 + (or * 0x0800), 0x80000000, 0x00000000);
925} 948}
926 949
927static bool 950static bool
@@ -1012,18 +1035,19 @@ nvd0_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1012 enum drm_connector_status status = connector_status_disconnected; 1035 enum drm_connector_status status = connector_status_disconnected;
1013 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1036 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1014 struct drm_device *dev = encoder->dev; 1037 struct drm_device *dev = encoder->dev;
1038 struct nouveau_device *device = nouveau_dev(dev);
1015 int or = nv_encoder->or; 1039 int or = nv_encoder->or;
1016 u32 load; 1040 u32 load;
1017 1041
1018 nv_wr32(dev, 0x61a00c + (or * 0x800), 0x00100000); 1042 nv_wr32(device, 0x61a00c + (or * 0x800), 0x00100000);
1019 udelay(9500); 1043 udelay(9500);
1020 nv_wr32(dev, 0x61a00c + (or * 0x800), 0x80000000); 1044 nv_wr32(device, 0x61a00c + (or * 0x800), 0x80000000);
1021 1045
1022 load = nv_rd32(dev, 0x61a00c + (or * 0x800)); 1046 load = nv_rd32(device, 0x61a00c + (or * 0x800));
1023 if ((load & 0x38000000) == 0x38000000) 1047 if ((load & 0x38000000) == 0x38000000)
1024 status = connector_status_connected; 1048 status = connector_status_connected;
1025 1049
1026 nv_wr32(dev, 0x61a00c + (or * 0x800), 0x00000000); 1050 nv_wr32(device, 0x61a00c + (or * 0x800), 0x00000000);
1027 return status; 1051 return status;
1028} 1052}
1029 1053
@@ -1081,24 +1105,25 @@ nvd0_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1081 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1105 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1082 struct nouveau_connector *nv_connector; 1106 struct nouveau_connector *nv_connector;
1083 struct drm_device *dev = encoder->dev; 1107 struct drm_device *dev = encoder->dev;
1108 struct nouveau_device *device = nouveau_dev(dev);
1084 int i, or = nv_encoder->or * 0x30; 1109 int i, or = nv_encoder->or * 0x30;
1085 1110
1086 nv_connector = nouveau_encoder_connector_get(nv_encoder); 1111 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1087 if (!drm_detect_monitor_audio(nv_connector->edid)) 1112 if (!drm_detect_monitor_audio(nv_connector->edid))
1088 return; 1113 return;
1089 1114
1090 nv_mask(dev, 0x10ec10 + or, 0x80000003, 0x80000001); 1115 nv_mask(device, 0x10ec10 + or, 0x80000003, 0x80000001);
1091 1116
1092 drm_edid_to_eld(&nv_connector->base, nv_connector->edid); 1117 drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
1093 if (nv_connector->base.eld[0]) { 1118 if (nv_connector->base.eld[0]) {
1094 u8 *eld = nv_connector->base.eld; 1119 u8 *eld = nv_connector->base.eld;
1095 1120
1096 for (i = 0; i < eld[2] * 4; i++) 1121 for (i = 0; i < eld[2] * 4; i++)
1097 nv_wr32(dev, 0x10ec00 + or, (i << 8) | eld[i]); 1122 nv_wr32(device, 0x10ec00 + or, (i << 8) | eld[i]);
1098 for (i = eld[2] * 4; i < 0x60; i++) 1123 for (i = eld[2] * 4; i < 0x60; i++)
1099 nv_wr32(dev, 0x10ec00 + or, (i << 8) | 0x00); 1124 nv_wr32(device, 0x10ec00 + or, (i << 8) | 0x00);
1100 1125
1101 nv_mask(dev, 0x10ec10 + or, 0x80000002, 0x80000002); 1126 nv_mask(device, 0x10ec10 + or, 0x80000002, 0x80000002);
1102 } 1127 }
1103} 1128}
1104 1129
@@ -1107,9 +1132,10 @@ nvd0_audio_disconnect(struct drm_encoder *encoder)
1107{ 1132{
1108 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1133 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1109 struct drm_device *dev = encoder->dev; 1134 struct drm_device *dev = encoder->dev;
1135 struct nouveau_device *device = nouveau_dev(dev);
1110 int or = nv_encoder->or * 0x30; 1136 int or = nv_encoder->or * 0x30;
1111 1137
1112 nv_mask(dev, 0x10ec10 + or, 0x80000003, 0x80000000); 1138 nv_mask(device, 0x10ec10 + or, 0x80000003, 0x80000000);
1113} 1139}
1114 1140
1115/****************************************************************************** 1141/******************************************************************************
@@ -1122,6 +1148,7 @@ nvd0_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1122 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1148 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1123 struct nouveau_connector *nv_connector; 1149 struct nouveau_connector *nv_connector;
1124 struct drm_device *dev = encoder->dev; 1150 struct drm_device *dev = encoder->dev;
1151 struct nouveau_device *device = nouveau_dev(dev);
1125 int head = nv_crtc->index * 0x800; 1152 int head = nv_crtc->index * 0x800;
1126 u32 rekey = 56; /* binary driver, and tegra constant */ 1153 u32 rekey = 56; /* binary driver, and tegra constant */
1127 u32 max_ac_packet; 1154 u32 max_ac_packet;
@@ -1136,25 +1163,25 @@ nvd0_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1136 max_ac_packet /= 32; 1163 max_ac_packet /= 32;
1137 1164
1138 /* AVI InfoFrame */ 1165 /* AVI InfoFrame */
1139 nv_mask(dev, 0x616714 + head, 0x00000001, 0x00000000); 1166 nv_mask(device, 0x616714 + head, 0x00000001, 0x00000000);
1140 nv_wr32(dev, 0x61671c + head, 0x000d0282); 1167 nv_wr32(device, 0x61671c + head, 0x000d0282);
1141 nv_wr32(dev, 0x616720 + head, 0x0000006f); 1168 nv_wr32(device, 0x616720 + head, 0x0000006f);
1142 nv_wr32(dev, 0x616724 + head, 0x00000000); 1169 nv_wr32(device, 0x616724 + head, 0x00000000);
1143 nv_wr32(dev, 0x616728 + head, 0x00000000); 1170 nv_wr32(device, 0x616728 + head, 0x00000000);
1144 nv_wr32(dev, 0x61672c + head, 0x00000000); 1171 nv_wr32(device, 0x61672c + head, 0x00000000);
1145 nv_mask(dev, 0x616714 + head, 0x00000001, 0x00000001); 1172 nv_mask(device, 0x616714 + head, 0x00000001, 0x00000001);
1146 1173
1147 /* ??? InfoFrame? */ 1174 /* ??? InfoFrame? */
1148 nv_mask(dev, 0x6167a4 + head, 0x00000001, 0x00000000); 1175 nv_mask(device, 0x6167a4 + head, 0x00000001, 0x00000000);
1149 nv_wr32(dev, 0x6167ac + head, 0x00000010); 1176 nv_wr32(device, 0x6167ac + head, 0x00000010);
1150 nv_mask(dev, 0x6167a4 + head, 0x00000001, 0x00000001); 1177 nv_mask(device, 0x6167a4 + head, 0x00000001, 0x00000001);
1151 1178
1152 /* HDMI_CTRL */ 1179 /* HDMI_CTRL */
1153 nv_mask(dev, 0x616798 + head, 0x401f007f, 0x40000000 | rekey | 1180 nv_mask(device, 0x616798 + head, 0x401f007f, 0x40000000 | rekey |
1154 max_ac_packet << 16); 1181 max_ac_packet << 16);
1155 1182
1156 /* NFI, audio doesn't work without it though.. */ 1183 /* NFI, audio doesn't work without it though.. */
1157 nv_mask(dev, 0x616548 + head, 0x00000070, 0x00000000); 1184 nv_mask(device, 0x616548 + head, 0x00000070, 0x00000000);
1158 1185
1159 nvd0_audio_mode_set(encoder, mode); 1186 nvd0_audio_mode_set(encoder, mode);
1160} 1187}
@@ -1165,13 +1192,14 @@ nvd0_hdmi_disconnect(struct drm_encoder *encoder)
1165 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1192 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1166 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); 1193 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1167 struct drm_device *dev = encoder->dev; 1194 struct drm_device *dev = encoder->dev;
1195 struct nouveau_device *device = nouveau_dev(dev);
1168 int head = nv_crtc->index * 0x800; 1196 int head = nv_crtc->index * 0x800;
1169 1197
1170 nvd0_audio_disconnect(encoder); 1198 nvd0_audio_disconnect(encoder);
1171 1199
1172 nv_mask(dev, 0x616798 + head, 0x40000000, 0x00000000); 1200 nv_mask(device, 0x616798 + head, 0x40000000, 0x00000000);
1173 nv_mask(dev, 0x6167a4 + head, 0x00000001, 0x00000000); 1201 nv_mask(device, 0x6167a4 + head, 0x00000001, 0x00000000);
1174 nv_mask(dev, 0x616714 + head, 0x00000001, 0x00000000); 1202 nv_mask(device, 0x616714 + head, 0x00000001, 0x00000000);
1175} 1203}
1176 1204
1177/****************************************************************************** 1205/******************************************************************************
@@ -1187,15 +1215,18 @@ nvd0_sor_dp_lane_map(struct drm_device *dev, struct dcb_output *dcb, u8 lane)
1187static void 1215static void
1188nvd0_sor_dp_train_set(struct drm_device *dev, struct dcb_output *dcb, u8 pattern) 1216nvd0_sor_dp_train_set(struct drm_device *dev, struct dcb_output *dcb, u8 pattern)
1189{ 1217{
1218 struct nouveau_device *device = nouveau_dev(dev);
1190 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1); 1219 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
1191 const u32 loff = (or * 0x800) + (link * 0x80); 1220 const u32 loff = (or * 0x800) + (link * 0x80);
1192 nv_mask(dev, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern); 1221 nv_mask(device, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern);
1193} 1222}
1194 1223
1195static void 1224static void
1196nvd0_sor_dp_train_adj(struct drm_device *dev, struct dcb_output *dcb, 1225nvd0_sor_dp_train_adj(struct drm_device *dev, struct dcb_output *dcb,
1197 u8 lane, u8 swing, u8 preem) 1226 u8 lane, u8 swing, u8 preem)
1198{ 1227{
1228 struct nouveau_device *device = nouveau_dev(dev);
1229 struct nouveau_drm *drm = nouveau_drm(dev);
1199 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1); 1230 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
1200 const u32 loff = (or * 0x800) + (link * 0x80); 1231 const u32 loff = (or * 0x800) + (link * 0x80);
1201 u32 shift = nvd0_sor_dp_lane_map(dev, dcb, lane); 1232 u32 shift = nvd0_sor_dp_lane_map(dev, dcb, lane);
@@ -1223,25 +1254,26 @@ nvd0_sor_dp_train_adj(struct drm_device *dev, struct dcb_output *dcb,
1223 } 1254 }
1224 1255
1225 if (!config) { 1256 if (!config) {
1226 NV_ERROR(dev, "PDISP: unsupported DP table for chipset\n"); 1257 NV_ERROR(drm, "PDISP: unsupported DP table for chipset\n");
1227 return; 1258 return;
1228 } 1259 }
1229 1260
1230 nv_mask(dev, 0x61c118 + loff, mask, config[1] << shift); 1261 nv_mask(device, 0x61c118 + loff, mask, config[1] << shift);
1231 nv_mask(dev, 0x61c120 + loff, mask, config[2] << shift); 1262 nv_mask(device, 0x61c120 + loff, mask, config[2] << shift);
1232 nv_mask(dev, 0x61c130 + loff, 0x0000ff00, config[3] << 8); 1263 nv_mask(device, 0x61c130 + loff, 0x0000ff00, config[3] << 8);
1233 nv_mask(dev, 0x61c13c + loff, 0x00000000, 0x00000000); 1264 nv_mask(device, 0x61c13c + loff, 0x00000000, 0x00000000);
1234} 1265}
1235 1266
1236static void 1267static void
1237nvd0_sor_dp_link_set(struct drm_device *dev, struct dcb_output *dcb, int crtc, 1268nvd0_sor_dp_link_set(struct drm_device *dev, struct dcb_output *dcb, int crtc,
1238 int link_nr, u32 link_bw, bool enhframe) 1269 int link_nr, u32 link_bw, bool enhframe)
1239{ 1270{
1271 struct nouveau_device *device = nouveau_dev(dev);
1240 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1); 1272 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
1241 const u32 loff = (or * 0x800) + (link * 0x80); 1273 const u32 loff = (or * 0x800) + (link * 0x80);
1242 const u32 soff = (or * 0x800); 1274 const u32 soff = (or * 0x800);
1243 u32 dpctrl = nv_rd32(dev, 0x61c10c + loff) & ~0x001f4000; 1275 u32 dpctrl = nv_rd32(device, 0x61c10c + loff) & ~0x001f4000;
1244 u32 clksor = nv_rd32(dev, 0x612300 + soff) & ~0x007c0000; 1276 u32 clksor = nv_rd32(device, 0x612300 + soff) & ~0x007c0000;
1245 u32 script = 0x0000, lane_mask = 0; 1277 u32 script = 0x0000, lane_mask = 0;
1246 u8 *table, *entry; 1278 u8 *table, *entry;
1247 int i; 1279 int i;
@@ -1271,20 +1303,21 @@ nvd0_sor_dp_link_set(struct drm_device *dev, struct dcb_output *dcb, int crtc,
1271 for (i = 0; i < link_nr; i++) 1303 for (i = 0; i < link_nr; i++)
1272 lane_mask |= 1 << (nvd0_sor_dp_lane_map(dev, dcb, i) >> 3); 1304 lane_mask |= 1 << (nvd0_sor_dp_lane_map(dev, dcb, i) >> 3);
1273 1305
1274 nv_wr32(dev, 0x612300 + soff, clksor); 1306 nv_wr32(device, 0x612300 + soff, clksor);
1275 nv_wr32(dev, 0x61c10c + loff, dpctrl); 1307 nv_wr32(device, 0x61c10c + loff, dpctrl);
1276 nv_mask(dev, 0x61c130 + loff, 0x0000000f, lane_mask); 1308 nv_mask(device, 0x61c130 + loff, 0x0000000f, lane_mask);
1277} 1309}
1278 1310
1279static void 1311static void
1280nvd0_sor_dp_link_get(struct drm_device *dev, struct dcb_output *dcb, 1312nvd0_sor_dp_link_get(struct drm_device *dev, struct dcb_output *dcb,
1281 u32 *link_nr, u32 *link_bw) 1313 u32 *link_nr, u32 *link_bw)
1282{ 1314{
1315 struct nouveau_device *device = nouveau_dev(dev);
1283 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1); 1316 const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
1284 const u32 loff = (or * 0x800) + (link * 0x80); 1317 const u32 loff = (or * 0x800) + (link * 0x80);
1285 const u32 soff = (or * 0x800); 1318 const u32 soff = (or * 0x800);
1286 u32 dpctrl = nv_rd32(dev, 0x61c10c + loff) & 0x000f0000; 1319 u32 dpctrl = nv_rd32(device, 0x61c10c + loff) & 0x000f0000;
1287 u32 clksor = nv_rd32(dev, 0x612300 + soff); 1320 u32 clksor = nv_rd32(device, 0x612300 + soff);
1288 1321
1289 if (dpctrl > 0x00030000) *link_nr = 4; 1322 if (dpctrl > 0x00030000) *link_nr = 4;
1290 else if (dpctrl > 0x00010000) *link_nr = 2; 1323 else if (dpctrl > 0x00010000) *link_nr = 2;
@@ -1298,6 +1331,7 @@ static void
1298nvd0_sor_dp_calc_tu(struct drm_device *dev, struct dcb_output *dcb, 1331nvd0_sor_dp_calc_tu(struct drm_device *dev, struct dcb_output *dcb,
1299 u32 crtc, u32 datarate) 1332 u32 crtc, u32 datarate)
1300{ 1333{
1334 struct nouveau_device *device = nouveau_dev(dev);
1301 const u32 symbol = 100000; 1335 const u32 symbol = 100000;
1302 const u32 TU = 64; 1336 const u32 TU = 64;
1303 u32 link_nr, link_bw; 1337 u32 link_nr, link_bw;
@@ -1317,7 +1351,7 @@ nvd0_sor_dp_calc_tu(struct drm_device *dev, struct dcb_output *dcb,
1317 value += 5; 1351 value += 5;
1318 value |= 0x08000000; 1352 value |= 0x08000000;
1319 1353
1320 nv_wr32(dev, 0x616610 + (crtc * 0x800), value); 1354 nv_wr32(device, 0x616610 + (crtc * 0x800), value);
1321} 1355}
1322 1356
1323static void 1357static void
@@ -1325,6 +1359,7 @@ nvd0_sor_dpms(struct drm_encoder *encoder, int mode)
1325{ 1359{
1326 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1360 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1327 struct drm_device *dev = encoder->dev; 1361 struct drm_device *dev = encoder->dev;
1362 struct nouveau_device *device = nouveau_dev(dev);
1328 struct drm_encoder *partner; 1363 struct drm_encoder *partner;
1329 int or = nv_encoder->or; 1364 int or = nv_encoder->or;
1330 u32 dpms_ctrl; 1365 u32 dpms_ctrl;
@@ -1348,10 +1383,10 @@ nvd0_sor_dpms(struct drm_encoder *encoder, int mode)
1348 dpms_ctrl = (mode == DRM_MODE_DPMS_ON); 1383 dpms_ctrl = (mode == DRM_MODE_DPMS_ON);
1349 dpms_ctrl |= 0x80000000; 1384 dpms_ctrl |= 0x80000000;
1350 1385
1351 nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000); 1386 nv_wait(device, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000);
1352 nv_mask(dev, 0x61c004 + (or * 0x0800), 0x80000001, dpms_ctrl); 1387 nv_mask(device, 0x61c004 + (or * 0x0800), 0x80000001, dpms_ctrl);
1353 nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000); 1388 nv_wait(device, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000);
1354 nv_wait(dev, 0x61c030 + (or * 0x0800), 0x10000000, 0x00000000); 1389 nv_wait(device, 0x61c030 + (or * 0x0800), 0x10000000, 0x00000000);
1355 1390
1356 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) { 1391 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
1357 struct dp_train_func func = { 1392 struct dp_train_func func = {
@@ -1428,11 +1463,11 @@ nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1428 struct drm_display_mode *mode) 1463 struct drm_display_mode *mode)
1429{ 1464{
1430 struct drm_device *dev = encoder->dev; 1465 struct drm_device *dev = encoder->dev;
1431 struct drm_nouveau_private *dev_priv = dev->dev_private; 1466 struct nouveau_drm *drm = nouveau_drm(dev);
1432 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 1467 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1433 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); 1468 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1434 struct nouveau_connector *nv_connector; 1469 struct nouveau_connector *nv_connector;
1435 struct nvbios *bios = &dev_priv->vbios; 1470 struct nvbios *bios = &drm->vbios;
1436 u32 mode_ctrl = (1 << nv_crtc->index); 1471 u32 mode_ctrl = (1 << nv_crtc->index);
1437 u32 syncs, magic, *push; 1472 u32 syncs, magic, *push;
1438 u32 or_config; 1473 u32 or_config;
@@ -1587,7 +1622,7 @@ nvd0_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1587static struct dcb_output * 1622static struct dcb_output *
1588lookup_dcb(struct drm_device *dev, int id, u32 mc) 1623lookup_dcb(struct drm_device *dev, int id, u32 mc)
1589{ 1624{
1590 struct drm_nouveau_private *dev_priv = dev->dev_private; 1625 struct nouveau_drm *drm = nouveau_drm(dev);
1591 int type, or, i, link = -1; 1626 int type, or, i, link = -1;
1592 1627
1593 if (id < 4) { 1628 if (id < 4) {
@@ -1602,32 +1637,33 @@ lookup_dcb(struct drm_device *dev, int id, u32 mc)
1602 case 0x00000800: link = 0; type = DCB_OUTPUT_DP; break; 1637 case 0x00000800: link = 0; type = DCB_OUTPUT_DP; break;
1603 case 0x00000900: link = 1; type = DCB_OUTPUT_DP; break; 1638 case 0x00000900: link = 1; type = DCB_OUTPUT_DP; break;
1604 default: 1639 default:
1605 NV_ERROR(dev, "PDISP: unknown SOR mc 0x%08x\n", mc); 1640 NV_ERROR(drm, "PDISP: unknown SOR mc 0x%08x\n", mc);
1606 return NULL; 1641 return NULL;
1607 } 1642 }
1608 1643
1609 or = id - 4; 1644 or = id - 4;
1610 } 1645 }
1611 1646
1612 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) { 1647 for (i = 0; i < drm->vbios.dcb.entries; i++) {
1613 struct dcb_output *dcb = &dev_priv->vbios.dcb.entry[i]; 1648 struct dcb_output *dcb = &drm->vbios.dcb.entry[i];
1614 if (dcb->type == type && (dcb->or & (1 << or)) && 1649 if (dcb->type == type && (dcb->or & (1 << or)) &&
1615 (link < 0 || link == !(dcb->sorconf.link & 1))) 1650 (link < 0 || link == !(dcb->sorconf.link & 1)))
1616 return dcb; 1651 return dcb;
1617 } 1652 }
1618 1653
1619 NV_ERROR(dev, "PDISP: DCB for %d/0x%08x not found\n", id, mc); 1654 NV_ERROR(drm, "PDISP: DCB for %d/0x%08x not found\n", id, mc);
1620 return NULL; 1655 return NULL;
1621} 1656}
1622 1657
1623static void 1658static void
1624nvd0_display_unk1_handler(struct drm_device *dev, u32 crtc, u32 mask) 1659nvd0_display_unk1_handler(struct drm_device *dev, u32 crtc, u32 mask)
1625{ 1660{
1661 struct nouveau_device *device = nouveau_dev(dev);
1626 struct dcb_output *dcb; 1662 struct dcb_output *dcb;
1627 int i; 1663 int i;
1628 1664
1629 for (i = 0; mask && i < 8; i++) { 1665 for (i = 0; mask && i < 8; i++) {
1630 u32 mcc = nv_rd32(dev, 0x640180 + (i * 0x20)); 1666 u32 mcc = nv_rd32(device, 0x640180 + (i * 0x20));
1631 if (!(mcc & (1 << crtc))) 1667 if (!(mcc & (1 << crtc)))
1632 continue; 1668 continue;
1633 1669
@@ -1638,20 +1674,22 @@ nvd0_display_unk1_handler(struct drm_device *dev, u32 crtc, u32 mask)
1638 nouveau_bios_run_display_table(dev, 0x0000, -1, dcb, crtc); 1674 nouveau_bios_run_display_table(dev, 0x0000, -1, dcb, crtc);
1639 } 1675 }
1640 1676
1641 nv_wr32(dev, 0x6101d4, 0x00000000); 1677 nv_wr32(device, 0x6101d4, 0x00000000);
1642 nv_wr32(dev, 0x6109d4, 0x00000000); 1678 nv_wr32(device, 0x6109d4, 0x00000000);
1643 nv_wr32(dev, 0x6101d0, 0x80000000); 1679 nv_wr32(device, 0x6101d0, 0x80000000);
1644} 1680}
1645 1681
1646static void 1682static void
1647nvd0_display_unk2_handler(struct drm_device *dev, u32 crtc, u32 mask) 1683nvd0_display_unk2_handler(struct drm_device *dev, u32 crtc, u32 mask)
1648{ 1684{
1685 struct nouveau_device *device = nouveau_dev(dev);
1686 struct nouveau_drm *drm = nouveau_drm(dev);
1649 struct dcb_output *dcb; 1687 struct dcb_output *dcb;
1650 u32 or, tmp, pclk; 1688 u32 or, tmp, pclk;
1651 int i; 1689 int i;
1652 1690
1653 for (i = 0; mask && i < 8; i++) { 1691 for (i = 0; mask && i < 8; i++) {
1654 u32 mcc = nv_rd32(dev, 0x640180 + (i * 0x20)); 1692 u32 mcc = nv_rd32(device, 0x640180 + (i * 0x20));
1655 if (!(mcc & (1 << crtc))) 1693 if (!(mcc & (1 << crtc)))
1656 continue; 1694 continue;
1657 1695
@@ -1662,16 +1700,16 @@ nvd0_display_unk2_handler(struct drm_device *dev, u32 crtc, u32 mask)
1662 nouveau_bios_run_display_table(dev, 0x0000, -2, dcb, crtc); 1700 nouveau_bios_run_display_table(dev, 0x0000, -2, dcb, crtc);
1663 } 1701 }
1664 1702
1665 pclk = nv_rd32(dev, 0x660450 + (crtc * 0x300)) / 1000; 1703 pclk = nv_rd32(device, 0x660450 + (crtc * 0x300)) / 1000;
1666 NV_DEBUG_KMS(dev, "PDISP: crtc %d pclk %d mask 0x%08x\n", 1704 NV_DEBUG(drm, "PDISP: crtc %d pclk %d mask 0x%08x\n",
1667 crtc, pclk, mask); 1705 crtc, pclk, mask);
1668 if (pclk && (mask & 0x00010000)) { 1706 if (pclk && (mask & 0x00010000)) {
1669 nv50_crtc_set_clock(dev, crtc, pclk); 1707 nv50_crtc_set_clock(dev, crtc, pclk);
1670 } 1708 }
1671 1709
1672 for (i = 0; mask && i < 8; i++) { 1710 for (i = 0; mask && i < 8; i++) {
1673 u32 mcp = nv_rd32(dev, 0x660180 + (i * 0x20)); 1711 u32 mcp = nv_rd32(device, 0x660180 + (i * 0x20));
1674 u32 cfg = nv_rd32(dev, 0x660184 + (i * 0x20)); 1712 u32 cfg = nv_rd32(device, 0x660184 + (i * 0x20));
1675 if (!(mcp & (1 << crtc))) 1713 if (!(mcp & (1 << crtc)))
1676 continue; 1714 continue;
1677 1715
@@ -1682,10 +1720,10 @@ nvd0_display_unk2_handler(struct drm_device *dev, u32 crtc, u32 mask)
1682 1720
1683 nouveau_bios_run_display_table(dev, cfg, pclk, dcb, crtc); 1721 nouveau_bios_run_display_table(dev, cfg, pclk, dcb, crtc);
1684 1722
1685 nv_wr32(dev, 0x612200 + (crtc * 0x800), 0x00000000); 1723 nv_wr32(device, 0x612200 + (crtc * 0x800), 0x00000000);
1686 switch (dcb->type) { 1724 switch (dcb->type) {
1687 case DCB_OUTPUT_ANALOG: 1725 case DCB_OUTPUT_ANALOG:
1688 nv_wr32(dev, 0x612280 + (or * 0x800), 0x00000000); 1726 nv_wr32(device, 0x612280 + (or * 0x800), 0x00000000);
1689 break; 1727 break;
1690 case DCB_OUTPUT_TMDS: 1728 case DCB_OUTPUT_TMDS:
1691 case DCB_OUTPUT_LVDS: 1729 case DCB_OUTPUT_LVDS:
@@ -1695,7 +1733,7 @@ nvd0_display_unk2_handler(struct drm_device *dev, u32 crtc, u32 mask)
1695 else 1733 else
1696 tmp = 0x00000000; 1734 tmp = 0x00000000;
1697 1735
1698 nv_mask(dev, 0x612300 + (or * 0x800), 0x00000707, tmp); 1736 nv_mask(device, 0x612300 + (or * 0x800), 0x00000707, tmp);
1699 break; 1737 break;
1700 default: 1738 default:
1701 break; 1739 break;
@@ -1704,22 +1742,23 @@ nvd0_display_unk2_handler(struct drm_device *dev, u32 crtc, u32 mask)
1704 break; 1742 break;
1705 } 1743 }
1706 1744
1707 nv_wr32(dev, 0x6101d4, 0x00000000); 1745 nv_wr32(device, 0x6101d4, 0x00000000);
1708 nv_wr32(dev, 0x6109d4, 0x00000000); 1746 nv_wr32(device, 0x6109d4, 0x00000000);
1709 nv_wr32(dev, 0x6101d0, 0x80000000); 1747 nv_wr32(device, 0x6101d0, 0x80000000);
1710} 1748}
1711 1749
1712static void 1750static void
1713nvd0_display_unk4_handler(struct drm_device *dev, u32 crtc, u32 mask) 1751nvd0_display_unk4_handler(struct drm_device *dev, u32 crtc, u32 mask)
1714{ 1752{
1753 struct nouveau_device *device = nouveau_dev(dev);
1715 struct dcb_output *dcb; 1754 struct dcb_output *dcb;
1716 int pclk, i; 1755 int pclk, i;
1717 1756
1718 pclk = nv_rd32(dev, 0x660450 + (crtc * 0x300)) / 1000; 1757 pclk = nv_rd32(device, 0x660450 + (crtc * 0x300)) / 1000;
1719 1758
1720 for (i = 0; mask && i < 8; i++) { 1759 for (i = 0; mask && i < 8; i++) {
1721 u32 mcp = nv_rd32(dev, 0x660180 + (i * 0x20)); 1760 u32 mcp = nv_rd32(device, 0x660180 + (i * 0x20));
1722 u32 cfg = nv_rd32(dev, 0x660184 + (i * 0x20)); 1761 u32 cfg = nv_rd32(device, 0x660184 + (i * 0x20));
1723 if (!(mcp & (1 << crtc))) 1762 if (!(mcp & (1 << crtc)))
1724 continue; 1763 continue;
1725 1764
@@ -1730,34 +1769,36 @@ nvd0_display_unk4_handler(struct drm_device *dev, u32 crtc, u32 mask)
1730 nouveau_bios_run_display_table(dev, cfg, -pclk, dcb, crtc); 1769 nouveau_bios_run_display_table(dev, cfg, -pclk, dcb, crtc);
1731 } 1770 }
1732 1771
1733 nv_wr32(dev, 0x6101d4, 0x00000000); 1772 nv_wr32(device, 0x6101d4, 0x00000000);
1734 nv_wr32(dev, 0x6109d4, 0x00000000); 1773 nv_wr32(device, 0x6109d4, 0x00000000);
1735 nv_wr32(dev, 0x6101d0, 0x80000000); 1774 nv_wr32(device, 0x6101d0, 0x80000000);
1736} 1775}
1737 1776
1738static void 1777static void
1739nvd0_display_bh(unsigned long data) 1778nvd0_display_bh(unsigned long data)
1740{ 1779{
1741 struct drm_device *dev = (struct drm_device *)data; 1780 struct drm_device *dev = (struct drm_device *)data;
1781 struct nouveau_device *device = nouveau_dev(dev);
1782 struct nouveau_drm *drm = nouveau_drm(dev);
1742 struct nvd0_display *disp = nvd0_display(dev); 1783 struct nvd0_display *disp = nvd0_display(dev);
1743 u32 mask = 0, crtc = ~0; 1784 u32 mask = 0, crtc = ~0;
1744 int i; 1785 int i;
1745 1786
1746 if (drm_debug & (DRM_UT_DRIVER | DRM_UT_KMS)) { 1787 if (drm_debug & (DRM_UT_DRIVER | DRM_UT_KMS)) {
1747 NV_INFO(dev, "PDISP: modeset req %d\n", disp->modeset); 1788 NV_INFO(drm, "PDISP: modeset req %d\n", disp->modeset);
1748 NV_INFO(dev, " STAT: 0x%08x 0x%08x 0x%08x\n", 1789 NV_INFO(drm, " STAT: 0x%08x 0x%08x 0x%08x\n",
1749 nv_rd32(dev, 0x6101d0), 1790 nv_rd32(device, 0x6101d0),
1750 nv_rd32(dev, 0x6101d4), nv_rd32(dev, 0x6109d4)); 1791 nv_rd32(device, 0x6101d4), nv_rd32(device, 0x6109d4));
1751 for (i = 0; i < 8; i++) { 1792 for (i = 0; i < 8; i++) {
1752 NV_INFO(dev, " %s%d: 0x%08x 0x%08x\n", 1793 NV_INFO(drm, " %s%d: 0x%08x 0x%08x\n",
1753 i < 4 ? "DAC" : "SOR", i, 1794 i < 4 ? "DAC" : "SOR", i,
1754 nv_rd32(dev, 0x640180 + (i * 0x20)), 1795 nv_rd32(device, 0x640180 + (i * 0x20)),
1755 nv_rd32(dev, 0x660180 + (i * 0x20))); 1796 nv_rd32(device, 0x660180 + (i * 0x20)));
1756 } 1797 }
1757 } 1798 }
1758 1799
1759 while (!mask && ++crtc < dev->mode_config.num_crtc) 1800 while (!mask && ++crtc < dev->mode_config.num_crtc)
1760 mask = nv_rd32(dev, 0x6101d4 + (crtc * 0x800)); 1801 mask = nv_rd32(device, 0x6101d4 + (crtc * 0x800));
1761 1802
1762 if (disp->modeset & 0x00000001) 1803 if (disp->modeset & 0x00000001)
1763 nvd0_display_unk1_handler(dev, crtc, mask); 1804 nvd0_display_unk1_handler(dev, crtc, mask);
@@ -1767,51 +1808,52 @@ nvd0_display_bh(unsigned long data)
1767 nvd0_display_unk4_handler(dev, crtc, mask); 1808 nvd0_display_unk4_handler(dev, crtc, mask);
1768} 1809}
1769 1810
1770static void 1811void
1771nvd0_display_intr(struct drm_device *dev) 1812nvd0_display_intr(struct drm_device *dev)
1772{ 1813{
1773 struct nvd0_display *disp = nvd0_display(dev); 1814 struct nvd0_display *disp = nvd0_display(dev);
1774 u32 intr = nv_rd32(dev, 0x610088); 1815 struct nouveau_device *device = nouveau_dev(dev);
1775 int i; 1816 struct nouveau_drm *drm = nouveau_drm(dev);
1817 u32 intr = nv_rd32(device, 0x610088);
1776 1818
1777 if (intr & 0x00000001) { 1819 if (intr & 0x00000001) {
1778 u32 stat = nv_rd32(dev, 0x61008c); 1820 u32 stat = nv_rd32(device, 0x61008c);
1779 nv_wr32(dev, 0x61008c, stat); 1821 nv_wr32(device, 0x61008c, stat);
1780 intr &= ~0x00000001; 1822 intr &= ~0x00000001;
1781 } 1823 }
1782 1824
1783 if (intr & 0x00000002) { 1825 if (intr & 0x00000002) {
1784 u32 stat = nv_rd32(dev, 0x61009c); 1826 u32 stat = nv_rd32(device, 0x61009c);
1785 int chid = ffs(stat) - 1; 1827 int chid = ffs(stat) - 1;
1786 if (chid >= 0) { 1828 if (chid >= 0) {
1787 u32 mthd = nv_rd32(dev, 0x6101f0 + (chid * 12)); 1829 u32 mthd = nv_rd32(device, 0x6101f0 + (chid * 12));
1788 u32 data = nv_rd32(dev, 0x6101f4 + (chid * 12)); 1830 u32 data = nv_rd32(device, 0x6101f4 + (chid * 12));
1789 u32 unkn = nv_rd32(dev, 0x6101f8 + (chid * 12)); 1831 u32 unkn = nv_rd32(device, 0x6101f8 + (chid * 12));
1790 1832
1791 NV_INFO(dev, "EvoCh: chid %d mthd 0x%04x data 0x%08x " 1833 NV_INFO(drm, "EvoCh: chid %d mthd 0x%04x data 0x%08x "
1792 "0x%08x 0x%08x\n", 1834 "0x%08x 0x%08x\n",
1793 chid, (mthd & 0x0000ffc), data, mthd, unkn); 1835 chid, (mthd & 0x0000ffc), data, mthd, unkn);
1794 nv_wr32(dev, 0x61009c, (1 << chid)); 1836 nv_wr32(device, 0x61009c, (1 << chid));
1795 nv_wr32(dev, 0x6101f0 + (chid * 12), 0x90000000); 1837 nv_wr32(device, 0x6101f0 + (chid * 12), 0x90000000);
1796 } 1838 }
1797 1839
1798 intr &= ~0x00000002; 1840 intr &= ~0x00000002;
1799 } 1841 }
1800 1842
1801 if (intr & 0x00100000) { 1843 if (intr & 0x00100000) {
1802 u32 stat = nv_rd32(dev, 0x6100ac); 1844 u32 stat = nv_rd32(device, 0x6100ac);
1803 1845
1804 if (stat & 0x00000007) { 1846 if (stat & 0x00000007) {
1805 disp->modeset = stat; 1847 disp->modeset = stat;
1806 tasklet_schedule(&disp->tasklet); 1848 tasklet_schedule(&disp->tasklet);
1807 1849
1808 nv_wr32(dev, 0x6100ac, (stat & 0x00000007)); 1850 nv_wr32(device, 0x6100ac, (stat & 0x00000007));
1809 stat &= ~0x00000007; 1851 stat &= ~0x00000007;
1810 } 1852 }
1811 1853
1812 if (stat) { 1854 if (stat) {
1813 NV_INFO(dev, "PDISP: unknown intr24 0x%08x\n", stat); 1855 NV_INFO(drm, "PDISP: unknown intr24 0x%08x\n", stat);
1814 nv_wr32(dev, 0x6100ac, stat); 1856 nv_wr32(device, 0x6100ac, stat);
1815 } 1857 }
1816 1858
1817 intr &= ~0x00100000; 1859 intr &= ~0x00100000;
@@ -1819,7 +1861,7 @@ nvd0_display_intr(struct drm_device *dev)
1819 1861
1820 intr &= ~0x0f000000; /* vblank, handled in core */ 1862 intr &= ~0x0f000000; /* vblank, handled in core */
1821 if (intr) 1863 if (intr)
1822 NV_INFO(dev, "PDISP: unknown intr 0x%08x\n", intr); 1864 NV_INFO(drm, "PDISP: unknown intr 0x%08x\n", intr);
1823} 1865}
1824 1866
1825/****************************************************************************** 1867/******************************************************************************
@@ -1846,15 +1888,17 @@ int
1846nvd0_display_init(struct drm_device *dev) 1888nvd0_display_init(struct drm_device *dev)
1847{ 1889{
1848 struct nvd0_display *disp = nvd0_display(dev); 1890 struct nvd0_display *disp = nvd0_display(dev);
1891 struct nouveau_device *device = nouveau_dev(dev);
1892 struct nouveau_drm *drm = nouveau_drm(dev);
1849 int ret, i; 1893 int ret, i;
1850 u32 *push; 1894 u32 *push;
1851 1895
1852 if (nv_rd32(dev, 0x6100ac) & 0x00000100) { 1896 if (nv_rd32(device, 0x6100ac) & 0x00000100) {
1853 nv_wr32(dev, 0x6100ac, 0x00000100); 1897 nv_wr32(device, 0x6100ac, 0x00000100);
1854 nv_mask(dev, 0x6194e8, 0x00000001, 0x00000000); 1898 nv_mask(device, 0x6194e8, 0x00000001, 0x00000000);
1855 if (!nv_wait(dev, 0x6194e8, 0x00000002, 0x00000000)) { 1899 if (!nv_wait(device, 0x6194e8, 0x00000002, 0x00000000)) {
1856 NV_ERROR(dev, "PDISP: 0x6194e8 0x%08x\n", 1900 NV_ERROR(drm, "PDISP: 0x6194e8 0x%08x\n",
1857 nv_rd32(dev, 0x6194e8)); 1901 nv_rd32(device, 0x6194e8));
1858 return -EBUSY; 1902 return -EBUSY;
1859 } 1903 }
1860 } 1904 }
@@ -1863,27 +1907,27 @@ nvd0_display_init(struct drm_device *dev)
1863 * work at all unless you do the SOR part below. 1907 * work at all unless you do the SOR part below.
1864 */ 1908 */
1865 for (i = 0; i < 3; i++) { 1909 for (i = 0; i < 3; i++) {
1866 u32 dac = nv_rd32(dev, 0x61a000 + (i * 0x800)); 1910 u32 dac = nv_rd32(device, 0x61a000 + (i * 0x800));
1867 nv_wr32(dev, 0x6101c0 + (i * 0x800), dac); 1911 nv_wr32(device, 0x6101c0 + (i * 0x800), dac);
1868 } 1912 }
1869 1913
1870 for (i = 0; i < 4; i++) { 1914 for (i = 0; i < 4; i++) {
1871 u32 sor = nv_rd32(dev, 0x61c000 + (i * 0x800)); 1915 u32 sor = nv_rd32(device, 0x61c000 + (i * 0x800));
1872 nv_wr32(dev, 0x6301c4 + (i * 0x800), sor); 1916 nv_wr32(device, 0x6301c4 + (i * 0x800), sor);
1873 } 1917 }
1874 1918
1875 for (i = 0; i < dev->mode_config.num_crtc; i++) { 1919 for (i = 0; i < dev->mode_config.num_crtc; i++) {
1876 u32 crtc0 = nv_rd32(dev, 0x616104 + (i * 0x800)); 1920 u32 crtc0 = nv_rd32(device, 0x616104 + (i * 0x800));
1877 u32 crtc1 = nv_rd32(dev, 0x616108 + (i * 0x800)); 1921 u32 crtc1 = nv_rd32(device, 0x616108 + (i * 0x800));
1878 u32 crtc2 = nv_rd32(dev, 0x61610c + (i * 0x800)); 1922 u32 crtc2 = nv_rd32(device, 0x61610c + (i * 0x800));
1879 nv_wr32(dev, 0x6101b4 + (i * 0x800), crtc0); 1923 nv_wr32(device, 0x6101b4 + (i * 0x800), crtc0);
1880 nv_wr32(dev, 0x6101b8 + (i * 0x800), crtc1); 1924 nv_wr32(device, 0x6101b8 + (i * 0x800), crtc1);
1881 nv_wr32(dev, 0x6101bc + (i * 0x800), crtc2); 1925 nv_wr32(device, 0x6101bc + (i * 0x800), crtc2);
1882 } 1926 }
1883 1927
1884 /* point at our hash table / objects, enable interrupts */ 1928 /* point at our hash table / objects, enable interrupts */
1885 nv_wr32(dev, 0x610010, (disp->mem->addr >> 8) | 9); 1929 nv_wr32(device, 0x610010, (disp->mem->addr >> 8) | 9);
1886 nv_mask(dev, 0x6100b0, 0x00000307, 0x00000307); 1930 nv_mask(device, 0x6100b0, 0x00000307, 0x00000307);
1887 1931
1888 /* init master */ 1932 /* init master */
1889 ret = evo_init_dma(dev, EVO_MASTER); 1933 ret = evo_init_dma(dev, EVO_MASTER);
@@ -1923,7 +1967,6 @@ error:
1923void 1967void
1924nvd0_display_destroy(struct drm_device *dev) 1968nvd0_display_destroy(struct drm_device *dev)
1925{ 1969{
1926 struct drm_nouveau_private *dev_priv = dev->dev_private;
1927 struct nvd0_display *disp = nvd0_display(dev); 1970 struct nvd0_display *disp = nvd0_display(dev);
1928 struct pci_dev *pdev = dev->pdev; 1971 struct pci_dev *pdev = dev->pdev;
1929 int i; 1972 int i;
@@ -1936,17 +1979,19 @@ nvd0_display_destroy(struct drm_device *dev)
1936 nouveau_gpuobj_ref(NULL, &disp->mem); 1979 nouveau_gpuobj_ref(NULL, &disp->mem);
1937 nouveau_bo_unmap(disp->sync); 1980 nouveau_bo_unmap(disp->sync);
1938 nouveau_bo_ref(NULL, &disp->sync); 1981 nouveau_bo_ref(NULL, &disp->sync);
1939 nouveau_irq_unregister(dev, 26);
1940 1982
1941 dev_priv->engine.display.priv = NULL; 1983 nouveau_display(dev)->priv = NULL;
1942 kfree(disp); 1984 kfree(disp);
1943} 1985}
1944 1986
1945int 1987int
1946nvd0_display_create(struct drm_device *dev) 1988nvd0_display_create(struct drm_device *dev)
1947{ 1989{
1948 struct drm_nouveau_private *dev_priv = dev->dev_private; 1990 struct nouveau_device *device = nouveau_dev(dev);
1949 struct dcb_table *dcb = &dev_priv->vbios.dcb; 1991 struct nouveau_drm *drm = nouveau_drm(dev);
1992 struct nouveau_bar *bar = nouveau_bar(device);
1993 struct nouveau_fb *pfb = nouveau_fb(device);
1994 struct dcb_table *dcb = &drm->vbios.dcb;
1950 struct drm_connector *connector, *tmp; 1995 struct drm_connector *connector, *tmp;
1951 struct pci_dev *pdev = dev->pdev; 1996 struct pci_dev *pdev = dev->pdev;
1952 struct nvd0_display *disp; 1997 struct nvd0_display *disp;
@@ -1956,10 +2001,14 @@ nvd0_display_create(struct drm_device *dev)
1956 disp = kzalloc(sizeof(*disp), GFP_KERNEL); 2001 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
1957 if (!disp) 2002 if (!disp)
1958 return -ENOMEM; 2003 return -ENOMEM;
1959 dev_priv->engine.display.priv = disp; 2004
2005 nouveau_display(dev)->priv = disp;
2006 nouveau_display(dev)->dtor = nvd0_display_destroy;
2007 nouveau_display(dev)->init = nvd0_display_init;
2008 nouveau_display(dev)->fini = nvd0_display_fini;
1960 2009
1961 /* create crtc objects to represent the hw heads */ 2010 /* create crtc objects to represent the hw heads */
1962 crtcs = nv_rd32(dev, 0x022448); 2011 crtcs = nv_rd32(device, 0x022448);
1963 for (i = 0; i < crtcs; i++) { 2012 for (i = 0; i < crtcs; i++) {
1964 ret = nvd0_crtc_create(dev, i); 2013 ret = nvd0_crtc_create(dev, i);
1965 if (ret) 2014 if (ret)
@@ -1973,7 +2022,7 @@ nvd0_display_create(struct drm_device *dev)
1973 continue; 2022 continue;
1974 2023
1975 if (dcbe->location != DCB_LOC_ON_CHIP) { 2024 if (dcbe->location != DCB_LOC_ON_CHIP) {
1976 NV_WARN(dev, "skipping off-chip encoder %d/%d\n", 2025 NV_WARN(drm, "skipping off-chip encoder %d/%d\n",
1977 dcbe->type, ffs(dcbe->or) - 1); 2026 dcbe->type, ffs(dcbe->or) - 1);
1978 continue; 2027 continue;
1979 } 2028 }
@@ -1988,7 +2037,7 @@ nvd0_display_create(struct drm_device *dev)
1988 nvd0_dac_create(connector, dcbe); 2037 nvd0_dac_create(connector, dcbe);
1989 break; 2038 break;
1990 default: 2039 default:
1991 NV_WARN(dev, "skipping unsupported encoder %d/%d\n", 2040 NV_WARN(drm, "skipping unsupported encoder %d/%d\n",
1992 dcbe->type, ffs(dcbe->or) - 1); 2041 dcbe->type, ffs(dcbe->or) - 1);
1993 continue; 2042 continue;
1994 } 2043 }
@@ -1999,14 +2048,13 @@ nvd0_display_create(struct drm_device *dev)
1999 if (connector->encoder_ids[0]) 2048 if (connector->encoder_ids[0])
2000 continue; 2049 continue;
2001 2050
2002 NV_WARN(dev, "%s has no encoders, removing\n", 2051 NV_WARN(drm, "%s has no encoders, removing\n",
2003 drm_get_connector_name(connector)); 2052 drm_get_connector_name(connector));
2004 connector->funcs->destroy(connector); 2053 connector->funcs->destroy(connector);
2005 } 2054 }
2006 2055
2007 /* setup interrupt handling */ 2056 /* setup interrupt handling */
2008 tasklet_init(&disp->tasklet, nvd0_display_bh, (unsigned long)dev); 2057 tasklet_init(&disp->tasklet, nvd0_display_bh, (unsigned long)dev);
2009 nouveau_irq_register(dev, 26, nvd0_display_intr);
2010 2058
2011 /* small shared memory area we use for notifiers and semaphores */ 2059 /* small shared memory area we use for notifiers and semaphores */
2012 ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, 2060 ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
@@ -2023,7 +2071,7 @@ nvd0_display_create(struct drm_device *dev)
2023 goto out; 2071 goto out;
2024 2072
2025 /* hash table and dma objects for the memory areas we care about */ 2073 /* hash table and dma objects for the memory areas we care about */
2026 ret = nouveau_gpuobj_new(dev, NULL, 0x4000, 0x10000, 2074 ret = nouveau_gpuobj_new(nv_object(device), NULL, 0x4000, 0x10000,
2027 NVOBJ_FLAG_ZERO_ALLOC, &disp->mem); 2075 NVOBJ_FLAG_ZERO_ALLOC, &disp->mem);
2028 if (ret) 2076 if (ret)
2029 goto out; 2077 goto out;
@@ -2055,7 +2103,7 @@ nvd0_display_create(struct drm_device *dev)
2055 2103
2056 nv_wo32(disp->mem, dmao + 0x20, 0x00000049); 2104 nv_wo32(disp->mem, dmao + 0x20, 0x00000049);
2057 nv_wo32(disp->mem, dmao + 0x24, 0x00000000); 2105 nv_wo32(disp->mem, dmao + 0x24, 0x00000000);
2058 nv_wo32(disp->mem, dmao + 0x28, (nvfb_vram_size(dev) - 1) >> 8); 2106 nv_wo32(disp->mem, dmao + 0x28, (pfb->ram.size - 1) >> 8);
2059 nv_wo32(disp->mem, dmao + 0x2c, 0x00000000); 2107 nv_wo32(disp->mem, dmao + 0x2c, 0x00000000);
2060 nv_wo32(disp->mem, dmao + 0x30, 0x00000000); 2108 nv_wo32(disp->mem, dmao + 0x30, 0x00000000);
2061 nv_wo32(disp->mem, dmao + 0x34, 0x00000000); 2109 nv_wo32(disp->mem, dmao + 0x34, 0x00000000);
@@ -2065,7 +2113,7 @@ nvd0_display_create(struct drm_device *dev)
2065 2113
2066 nv_wo32(disp->mem, dmao + 0x40, 0x00000009); 2114 nv_wo32(disp->mem, dmao + 0x40, 0x00000009);
2067 nv_wo32(disp->mem, dmao + 0x44, 0x00000000); 2115 nv_wo32(disp->mem, dmao + 0x44, 0x00000000);
2068 nv_wo32(disp->mem, dmao + 0x48, (nvfb_vram_size(dev) - 1) >> 8); 2116 nv_wo32(disp->mem, dmao + 0x48, (pfb->ram.size - 1) >> 8);
2069 nv_wo32(disp->mem, dmao + 0x4c, 0x00000000); 2117 nv_wo32(disp->mem, dmao + 0x4c, 0x00000000);
2070 nv_wo32(disp->mem, dmao + 0x50, 0x00000000); 2118 nv_wo32(disp->mem, dmao + 0x50, 0x00000000);
2071 nv_wo32(disp->mem, dmao + 0x54, 0x00000000); 2119 nv_wo32(disp->mem, dmao + 0x54, 0x00000000);
@@ -2075,7 +2123,7 @@ nvd0_display_create(struct drm_device *dev)
2075 2123
2076 nv_wo32(disp->mem, dmao + 0x60, 0x0fe00009); 2124 nv_wo32(disp->mem, dmao + 0x60, 0x0fe00009);
2077 nv_wo32(disp->mem, dmao + 0x64, 0x00000000); 2125 nv_wo32(disp->mem, dmao + 0x64, 0x00000000);
2078 nv_wo32(disp->mem, dmao + 0x68, (nvfb_vram_size(dev) - 1) >> 8); 2126 nv_wo32(disp->mem, dmao + 0x68, (pfb->ram.size - 1) >> 8);
2079 nv_wo32(disp->mem, dmao + 0x6c, 0x00000000); 2127 nv_wo32(disp->mem, dmao + 0x6c, 0x00000000);
2080 nv_wo32(disp->mem, dmao + 0x70, 0x00000000); 2128 nv_wo32(disp->mem, dmao + 0x70, 0x00000000);
2081 nv_wo32(disp->mem, dmao + 0x74, 0x00000000); 2129 nv_wo32(disp->mem, dmao + 0x74, 0x00000000);
@@ -2084,7 +2132,7 @@ nvd0_display_create(struct drm_device *dev)
2084 ((dmao + 0x60) << 9)); 2132 ((dmao + 0x60) << 9));
2085 } 2133 }
2086 2134
2087 nvimem_flush(dev); 2135 bar->flush(bar);
2088 2136
2089out: 2137out:
2090 if (ret) 2138 if (ret)
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 14:55:24 -0500