drm/nouveau: port remainder of drm code, and rip out compat layer

v2: Ben Skeggs <bskeggs@redhat.com>
- fill in nouveau_pm.dev to prevent oops
- fix ppc issues (build + OF shadow)

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

1 files changed, 50 insertions, 38 deletions

diff --git a/drivers/gpu/drm/nouveau/nouveau_hw.h b/drivers/gpu/drm/nouveau/nouveau_hw.h
index b1c22b788be8..ba8fc0f9e0db 100644
--- a/drivers/gpu/drm/nouveau/nouveau_hw.h
+++ b/drivers/gpu/drm/nouveau/nouveau_hw.h
@@ -24,7 +24,6 @@
 #define __NOUVEAU_HW_H__
 
 #include "drmP.h"
-#include "nouveau_drv.h"
 #include "nv04_display.h"
 
 #include <subdev/bios/pll.h>
@@ -60,37 +59,41 @@ extern void nouveau_calc_arb(struct drm_device *, int vclk, int bpp,
 static inline uint32_t NVReadCRTC(struct drm_device *dev,
                                         int head, uint32_t reg)
 {
+        struct nouveau_device *device = nouveau_dev(dev);
         uint32_t val;
         if (head)
                 reg += NV_PCRTC0_SIZE;
-        val = nv_rd32(dev, reg);
+        val = nv_rd32(device, reg);
         return val;
 }
 
 static inline void NVWriteCRTC(struct drm_device *dev,
                                         int head, uint32_t reg, uint32_t val)
 {
+        struct nouveau_device *device = nouveau_dev(dev);
         if (head)
                 reg += NV_PCRTC0_SIZE;
-        nv_wr32(dev, reg, val);
+        nv_wr32(device, reg, val);
 }
 
 static inline uint32_t NVReadRAMDAC(struct drm_device *dev,
                                         int head, uint32_t reg)
 {
+        struct nouveau_device *device = nouveau_dev(dev);
         uint32_t val;
         if (head)
                 reg += NV_PRAMDAC0_SIZE;
-        val = nv_rd32(dev, reg);
+        val = nv_rd32(device, reg);
         return val;
 }
 
 static inline void NVWriteRAMDAC(struct drm_device *dev,
                                         int head, uint32_t reg, uint32_t val)
 {
+        struct nouveau_device *device = nouveau_dev(dev);
         if (head)
                 reg += NV_PRAMDAC0_SIZE;
-        nv_wr32(dev, reg, val);
+        nv_wr32(device, reg, val);
 }
 
 static inline uint8_t nv_read_tmds(struct drm_device *dev,
@@ -116,16 +119,18 @@ static inline void nv_write_tmds(struct drm_device *dev,
 static inline void NVWriteVgaCrtc(struct drm_device *dev,
                                         int head, uint8_t index, uint8_t value)
 {
-        nv_wr08(dev, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
-        nv_wr08(dev, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value);
+        struct nouveau_device *device = nouveau_dev(dev);
+        nv_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
+        nv_wr08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value);
 }
 
 static inline uint8_t NVReadVgaCrtc(struct drm_device *dev,
                                         int head, uint8_t index)
 {
+        struct nouveau_device *device = nouveau_dev(dev);
         uint8_t val;
-        nv_wr08(dev, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
-        val = nv_rd08(dev, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE);
+        nv_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
+        val = nv_rd08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE);
         return val;
 }
 
@@ -159,68 +164,74 @@ static inline uint8_t NVReadVgaCrtc5758(struct drm_device *dev, int head, uint8_
 static inline uint8_t NVReadPRMVIO(struct drm_device *dev,
                                         int head, uint32_t reg)
 {
-        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_device *device = nouveau_dev(dev);
+        struct nouveau_drm *drm = nouveau_drm(dev);
         uint8_t val;
 
         /* Only NV4x have two pvio ranges; other twoHeads cards MUST call
          * NVSetOwner for the relevant head to be programmed */
-        if (head && dev_priv->card_type == NV_40)
+        if (head && nv_device(drm->device)->card_type == NV_40)
                 reg += NV_PRMVIO_SIZE;
 
-        val = nv_rd08(dev, reg);
+        val = nv_rd08(device, reg);
         return val;
 }
 
 static inline void NVWritePRMVIO(struct drm_device *dev,
                                         int head, uint32_t reg, uint8_t value)
 {
-        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_device *device = nouveau_dev(dev);
+        struct nouveau_drm *drm = nouveau_drm(dev);
 
         /* Only NV4x have two pvio ranges; other twoHeads cards MUST call
          * NVSetOwner for the relevant head to be programmed */
-        if (head && dev_priv->card_type == NV_40)
+        if (head && nv_device(drm->device)->card_type == NV_40)
                 reg += NV_PRMVIO_SIZE;
 
-        nv_wr08(dev, reg, value);
+        nv_wr08(device, reg, value);
 }
 
 static inline void NVSetEnablePalette(struct drm_device *dev, int head, bool enable)
 {
-        nv_rd08(dev, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
-        nv_wr08(dev, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20);
+        struct nouveau_device *device = nouveau_dev(dev);
+        nv_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
+        nv_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20);
 }
 
 static inline bool NVGetEnablePalette(struct drm_device *dev, int head)
 {
-        nv_rd08(dev, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
-        return !(nv_rd08(dev, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20);
+        struct nouveau_device *device = nouveau_dev(dev);
+        nv_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
+        return !(nv_rd08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20);
 }
 
 static inline void NVWriteVgaAttr(struct drm_device *dev,
                                         int head, uint8_t index, uint8_t value)
 {
+        struct nouveau_device *device = nouveau_dev(dev);
         if (NVGetEnablePalette(dev, head))
                 index &= ~0x20;
         else
                 index |= 0x20;
 
-        nv_rd08(dev, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
-        nv_wr08(dev, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
-        nv_wr08(dev, NV_PRMCIO_AR__WRITE + head * NV_PRMCIO_SIZE, value);
+        nv_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
+        nv_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
+        nv_wr08(device, NV_PRMCIO_AR__WRITE + head * NV_PRMCIO_SIZE, value);
 }
 
 static inline uint8_t NVReadVgaAttr(struct drm_device *dev,
                                         int head, uint8_t index)
 {
+        struct nouveau_device *device = nouveau_dev(dev);
         uint8_t val;
         if (NVGetEnablePalette(dev, head))
                 index &= ~0x20;
         else
                 index |= 0x20;
 
-        nv_rd08(dev, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
-        nv_wr08(dev, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
-        val = nv_rd08(dev, NV_PRMCIO_AR__READ + head * NV_PRMCIO_SIZE);
+        nv_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
+        nv_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
+        val = nv_rd08(device, NV_PRMCIO_AR__READ + head * NV_PRMCIO_SIZE);
         return val;
 }
 
@@ -247,10 +258,11 @@ static inline void NVVgaProtect(struct drm_device *dev, int head, bool protect)
 static inline bool
 nv_heads_tied(struct drm_device *dev)
 {
-        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_device *device = nouveau_dev(dev);
+        struct nouveau_drm *drm = nouveau_drm(dev);
 
-        if (dev_priv->chipset == 0x11)
-                return !!(nv_rd32(dev, NV_PBUS_DEBUG_1) & (1 << 28));
+        if (nv_device(drm->device)->chipset == 0x11)
+                return !!(nv_rd32(device, NV_PBUS_DEBUG_1) & (1 << 28));
 
         return NVReadVgaCrtc(dev, 0, NV_CIO_CRE_44) & 0x4;
 }
@@ -299,13 +311,13 @@ nv_lock_vga_crtc_shadow(struct drm_device *dev, int head, int lock)
 static inline bool
 NVLockVgaCrtcs(struct drm_device *dev, bool lock)
 {
-        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_drm *drm = nouveau_drm(dev);
         bool waslocked = !NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX);
 
         NVWriteVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX,
                        lock ? NV_CIO_SR_LOCK_VALUE : NV_CIO_SR_UNLOCK_RW_VALUE);
         /* NV11 has independently lockable extended crtcs, except when tied */
-        if (dev_priv->chipset == 0x11 && !nv_heads_tied(dev))
+        if (nv_device(drm->device)->chipset == 0x11 && !nv_heads_tied(dev))
                 NVWriteVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX,
                                lock ? NV_CIO_SR_LOCK_VALUE :
                                       NV_CIO_SR_UNLOCK_RW_VALUE);
@@ -320,9 +332,9 @@ NVLockVgaCrtcs(struct drm_device *dev, bool lock)
 
 static inline int nv_cursor_width(struct drm_device *dev)
 {
-        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_drm *drm = nouveau_drm(dev);
 
-        return dev_priv->card_type >= NV_10 ? NV10_CURSOR_SIZE : NV04_CURSOR_SIZE;
+        return nv_device(drm->device)->card_type >= NV_10 ? NV10_CURSOR_SIZE : NV04_CURSOR_SIZE;
 }
 
 static inline void
@@ -340,11 +352,11 @@ nv_fix_nv40_hw_cursor(struct drm_device *dev, int head)
 static inline void
 nv_set_crtc_base(struct drm_device *dev, int head, uint32_t offset)
 {
-        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_drm *drm = nouveau_drm(dev);
 
         NVWriteCRTC(dev, head, NV_PCRTC_START, offset);
 
-        if (dev_priv->card_type == NV_04) {
+        if (nv_device(drm->device)->card_type == NV_04) {
                 /*
                  * Hilarious, the 24th bit doesn't want to stick to
                  * PCRTC_START...
@@ -359,7 +371,7 @@ nv_set_crtc_base(struct drm_device *dev, int head, uint32_t offset)
 static inline void
 nv_show_cursor(struct drm_device *dev, int head, bool show)
 {
-        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_drm *drm = nouveau_drm(dev);
         uint8_t *curctl1 =
                 &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];
 
@@ -369,14 +381,14 @@ nv_show_cursor(struct drm_device *dev, int head, bool show)
                 *curctl1 &= ~MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE);
         NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, *curctl1);
 
-        if (dev_priv->card_type == NV_40)
+        if (nv_device(drm->device)->card_type == NV_40)
                 nv_fix_nv40_hw_cursor(dev, head);
 }
 
 static inline uint32_t
 nv_pitch_align(struct drm_device *dev, uint32_t width, int bpp)
 {
-        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_drm *drm = nouveau_drm(dev);
         int mask;
 
         if (bpp == 15)
@@ -385,7 +397,7 @@ nv_pitch_align(struct drm_device *dev, uint32_t width, int bpp)
                 bpp = 8;
 
         /* Alignment requirements taken from the Haiku driver */
-        if (dev_priv->card_type == NV_04)
+        if (nv_device(drm->device)->card_type == NV_04)
                 mask = 128 / bpp - 1;
         else
                 mask = 512 / bpp - 1;