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authorBen Skeggs <bskeggs@redhat.com>2015-01-14 00:09:19 -0500
committerBen Skeggs <bskeggs@redhat.com>2015-01-21 21:17:57 -0500
commit42594600095f03244a674fecdd2b5f6da2441180 (patch)
treec6f555f7fc6174e63d83c860f4798289d5aa52de /drivers/gpu/drm/nouveau/include
parentd7e5fcd2e7455094d6f8326b00f70864a700017a (diff)
drm/nouveau/mmu: namespace + nvidia gpu names (no binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/include')
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/core/os.h1
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h1
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h161
3 files changed, 67 insertions, 96 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
index 7894ff57514b..423086564735 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
@@ -240,5 +240,6 @@
240#define nvc0_pte_storage_type_map gf100_pte_storage_type_map 240#define nvc0_pte_storage_type_map gf100_pte_storage_type_map
241#define nouveau_fuse nvkm_fuse 241#define nouveau_fuse nvkm_fuse
242#define nouveau_mc nvkm_mc 242#define nouveau_mc nvkm_mc
243#define nouveau_mmu nvkm_mmu
243 244
244#endif 245#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
index 639d0fd64cad..92cfcf5ae9d4 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
@@ -1,5 +1,6 @@
1#ifndef __NVKM_CE_H__ 1#ifndef __NVKM_CE_H__
2#define __NVKM_CE_H__ 2#define __NVKM_CE_H__
3#include <core/engine.h>
3 4
4void nva3_ce_intr(struct nouveau_subdev *); 5void nva3_ce_intr(struct nouveau_subdev *);
5 6
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
index 2c3b29967ea4..3a5368776c31 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
@@ -1,72 +1,44 @@
1/* 1#ifndef __NVKM_MMU_H__
2 * Copyright 2010 Red Hat Inc. 2#define __NVKM_MMU_H__
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#ifndef __NOUVEAU_MMU_H__
26#define __NOUVEAU_MMU_H__
27
28#include <core/object.h>
29#include <core/subdev.h> 3#include <core/subdev.h>
30#include <core/device.h>
31#include <core/mm.h> 4#include <core/mm.h>
5struct nvkm_device;
6struct nvkm_mem;
32 7
33struct nouveau_vm_pgt { 8struct nvkm_vm_pgt {
34 struct nouveau_gpuobj *obj[2]; 9 struct nvkm_gpuobj *obj[2];
35 u32 refcount[2]; 10 u32 refcount[2];
36}; 11};
37 12
38struct nouveau_vm_pgd { 13struct nvkm_vm_pgd {
39 struct list_head head; 14 struct list_head head;
40 struct nouveau_gpuobj *obj; 15 struct nvkm_gpuobj *obj;
41}; 16};
42 17
43struct nouveau_gpuobj; 18struct nvkm_vma {
44struct nouveau_mem;
45
46struct nouveau_vma {
47 struct list_head head; 19 struct list_head head;
48 int refcount; 20 int refcount;
49 struct nouveau_vm *vm; 21 struct nvkm_vm *vm;
50 struct nouveau_mm_node *node; 22 struct nvkm_mm_node *node;
51 u64 offset; 23 u64 offset;
52 u32 access; 24 u32 access;
53}; 25};
54 26
55struct nouveau_vm { 27struct nvkm_vm {
56 struct nouveau_mmu *mmu; 28 struct nvkm_mmu *mmu;
57 struct nouveau_mm mm; 29 struct nvkm_mm mm;
58 struct kref refcount; 30 struct kref refcount;
59 31
60 struct list_head pgd_list; 32 struct list_head pgd_list;
61 atomic_t engref[NVDEV_SUBDEV_NR]; 33 atomic_t engref[NVDEV_SUBDEV_NR];
62 34
63 struct nouveau_vm_pgt *pgt; 35 struct nvkm_vm_pgt *pgt;
64 u32 fpde; 36 u32 fpde;
65 u32 lpde; 37 u32 lpde;
66}; 38};
67 39
68struct nouveau_mmu { 40struct nvkm_mmu {
69 struct nouveau_subdev base; 41 struct nvkm_subdev base;
70 42
71 u64 limit; 43 u64 limit;
72 u8 dma_bits; 44 u8 dma_bits;
@@ -74,62 +46,59 @@ struct nouveau_mmu {
74 u8 spg_shift; 46 u8 spg_shift;
75 u8 lpg_shift; 47 u8 lpg_shift;
76 48
77 int (*create)(struct nouveau_mmu *, u64 offset, u64 length, 49 int (*create)(struct nvkm_mmu *, u64 offset, u64 length,
78 u64 mm_offset, struct nouveau_vm **); 50 u64 mm_offset, struct nvkm_vm **);
79 51
80 void (*map_pgt)(struct nouveau_gpuobj *pgd, u32 pde, 52 void (*map_pgt)(struct nvkm_gpuobj *pgd, u32 pde,
81 struct nouveau_gpuobj *pgt[2]); 53 struct nvkm_gpuobj *pgt[2]);
82 void (*map)(struct nouveau_vma *, struct nouveau_gpuobj *, 54 void (*map)(struct nvkm_vma *, struct nvkm_gpuobj *,
83 struct nouveau_mem *, u32 pte, u32 cnt, 55 struct nvkm_mem *, u32 pte, u32 cnt,
84 u64 phys, u64 delta); 56 u64 phys, u64 delta);
85 void (*map_sg)(struct nouveau_vma *, struct nouveau_gpuobj *, 57 void (*map_sg)(struct nvkm_vma *, struct nvkm_gpuobj *,
86 struct nouveau_mem *, u32 pte, u32 cnt, dma_addr_t *); 58 struct nvkm_mem *, u32 pte, u32 cnt, dma_addr_t *);
87 void (*unmap)(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt); 59 void (*unmap)(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt);
88 void (*flush)(struct nouveau_vm *); 60 void (*flush)(struct nvkm_vm *);
89}; 61};
90 62
91static inline struct nouveau_mmu * 63static inline struct nvkm_mmu *
92nouveau_mmu(void *obj) 64nvkm_mmu(void *obj)
93{ 65{
94 return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_MMU); 66 return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MMU);
95} 67}
96 68
97#define nouveau_mmu_create(p,e,o,i,f,d) \ 69#define nvkm_mmu_create(p,e,o,i,f,d) \
98 nouveau_subdev_create((p), (e), (o), 0, (i), (f), (d)) 70 nvkm_subdev_create((p), (e), (o), 0, (i), (f), (d))
99#define nouveau_mmu_destroy(p) \ 71#define nvkm_mmu_destroy(p) \
100 nouveau_subdev_destroy(&(p)->base) 72 nvkm_subdev_destroy(&(p)->base)
101#define nouveau_mmu_init(p) \ 73#define nvkm_mmu_init(p) \
102 nouveau_subdev_init(&(p)->base) 74 nvkm_subdev_init(&(p)->base)
103#define nouveau_mmu_fini(p,s) \ 75#define nvkm_mmu_fini(p,s) \
104 nouveau_subdev_fini(&(p)->base, (s)) 76 nvkm_subdev_fini(&(p)->base, (s))
105 77
106#define _nouveau_mmu_dtor _nouveau_subdev_dtor 78#define _nvkm_mmu_dtor _nvkm_subdev_dtor
107#define _nouveau_mmu_init _nouveau_subdev_init 79#define _nvkm_mmu_init _nvkm_subdev_init
108#define _nouveau_mmu_fini _nouveau_subdev_fini 80#define _nvkm_mmu_fini _nvkm_subdev_fini
109 81
110extern struct nouveau_oclass nv04_mmu_oclass; 82extern struct nvkm_oclass nv04_mmu_oclass;
111extern struct nouveau_oclass nv41_mmu_oclass; 83extern struct nvkm_oclass nv41_mmu_oclass;
112extern struct nouveau_oclass nv44_mmu_oclass; 84extern struct nvkm_oclass nv44_mmu_oclass;
113extern struct nouveau_oclass nv50_mmu_oclass; 85extern struct nvkm_oclass nv50_mmu_oclass;
114extern struct nouveau_oclass nvc0_mmu_oclass; 86extern struct nvkm_oclass gf100_mmu_oclass;
115 87
116int nv04_vm_create(struct nouveau_mmu *, u64, u64, u64, 88int nv04_vm_create(struct nvkm_mmu *, u64, u64, u64,
117 struct nouveau_vm **); 89 struct nvkm_vm **);
118void nv04_mmu_dtor(struct nouveau_object *); 90void nv04_mmu_dtor(struct nvkm_object *);
119 91
120/* nouveau_vm.c */ 92int nvkm_vm_create(struct nvkm_mmu *, u64 offset, u64 length, u64 mm_offset,
121int nouveau_vm_create(struct nouveau_mmu *, u64 offset, u64 length, 93 u32 block, struct nvkm_vm **);
122 u64 mm_offset, u32 block, struct nouveau_vm **); 94int nvkm_vm_new(struct nvkm_device *, u64 offset, u64 length, u64 mm_offset,
123int nouveau_vm_new(struct nouveau_device *, u64 offset, u64 length, 95 struct nvkm_vm **);
124 u64 mm_offset, struct nouveau_vm **); 96int nvkm_vm_ref(struct nvkm_vm *, struct nvkm_vm **, struct nvkm_gpuobj *pgd);
125int nouveau_vm_ref(struct nouveau_vm *, struct nouveau_vm **, 97int nvkm_vm_get(struct nvkm_vm *, u64 size, u32 page_shift, u32 access,
126 struct nouveau_gpuobj *pgd); 98 struct nvkm_vma *);
127int nouveau_vm_get(struct nouveau_vm *, u64 size, u32 page_shift, 99void nvkm_vm_put(struct nvkm_vma *);
128 u32 access, struct nouveau_vma *); 100void nvkm_vm_map(struct nvkm_vma *, struct nvkm_mem *);
129void nouveau_vm_put(struct nouveau_vma *); 101void nvkm_vm_map_at(struct nvkm_vma *, u64 offset, struct nvkm_mem *);
130void nouveau_vm_map(struct nouveau_vma *, struct nouveau_mem *); 102void nvkm_vm_unmap(struct nvkm_vma *);
131void nouveau_vm_map_at(struct nouveau_vma *, u64 offset, struct nouveau_mem *); 103void nvkm_vm_unmap_at(struct nvkm_vma *, u64 offset, u64 length);
132void nouveau_vm_unmap(struct nouveau_vma *);
133void nouveau_vm_unmap_at(struct nouveau_vma *, u64 offset, u64 length);
134
135#endif 104#endif