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authorBen Skeggs <bskeggs@redhat.com>2015-01-14 00:09:19 -0500
committerBen Skeggs <bskeggs@redhat.com>2015-01-21 21:17:57 -0500
commit42594600095f03244a674fecdd2b5f6da2441180 (patch)
treec6f555f7fc6174e63d83c860f4798289d5aa52de
parentd7e5fcd2e7455094d6f8326b00f70864a700017a (diff)
drm/nouveau/mmu: namespace + nvidia gpu names (no binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/core/os.h1
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h1
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h161
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/core/engctx.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c4
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c18
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c16
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c1
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild2
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c169
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c (renamed from drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nvc0.c)92
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c56
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h6
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c56
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c60
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c64
29 files changed, 351 insertions, 374 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
index 7894ff57514b..423086564735 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
@@ -240,5 +240,6 @@
240#define nvc0_pte_storage_type_map gf100_pte_storage_type_map 240#define nvc0_pte_storage_type_map gf100_pte_storage_type_map
241#define nouveau_fuse nvkm_fuse 241#define nouveau_fuse nvkm_fuse
242#define nouveau_mc nvkm_mc 242#define nouveau_mc nvkm_mc
243#define nouveau_mmu nvkm_mmu
243 244
244#endif 245#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
index 639d0fd64cad..92cfcf5ae9d4 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h
@@ -1,5 +1,6 @@
1#ifndef __NVKM_CE_H__ 1#ifndef __NVKM_CE_H__
2#define __NVKM_CE_H__ 2#define __NVKM_CE_H__
3#include <core/engine.h>
3 4
4void nva3_ce_intr(struct nouveau_subdev *); 5void nva3_ce_intr(struct nouveau_subdev *);
5 6
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
index 2c3b29967ea4..3a5368776c31 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h
@@ -1,72 +1,44 @@
1/* 1#ifndef __NVKM_MMU_H__
2 * Copyright 2010 Red Hat Inc. 2#define __NVKM_MMU_H__
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#ifndef __NOUVEAU_MMU_H__
26#define __NOUVEAU_MMU_H__
27
28#include <core/object.h>
29#include <core/subdev.h> 3#include <core/subdev.h>
30#include <core/device.h>
31#include <core/mm.h> 4#include <core/mm.h>
5struct nvkm_device;
6struct nvkm_mem;
32 7
33struct nouveau_vm_pgt { 8struct nvkm_vm_pgt {
34 struct nouveau_gpuobj *obj[2]; 9 struct nvkm_gpuobj *obj[2];
35 u32 refcount[2]; 10 u32 refcount[2];
36}; 11};
37 12
38struct nouveau_vm_pgd { 13struct nvkm_vm_pgd {
39 struct list_head head; 14 struct list_head head;
40 struct nouveau_gpuobj *obj; 15 struct nvkm_gpuobj *obj;
41}; 16};
42 17
43struct nouveau_gpuobj; 18struct nvkm_vma {
44struct nouveau_mem;
45
46struct nouveau_vma {
47 struct list_head head; 19 struct list_head head;
48 int refcount; 20 int refcount;
49 struct nouveau_vm *vm; 21 struct nvkm_vm *vm;
50 struct nouveau_mm_node *node; 22 struct nvkm_mm_node *node;
51 u64 offset; 23 u64 offset;
52 u32 access; 24 u32 access;
53}; 25};
54 26
55struct nouveau_vm { 27struct nvkm_vm {
56 struct nouveau_mmu *mmu; 28 struct nvkm_mmu *mmu;
57 struct nouveau_mm mm; 29 struct nvkm_mm mm;
58 struct kref refcount; 30 struct kref refcount;
59 31
60 struct list_head pgd_list; 32 struct list_head pgd_list;
61 atomic_t engref[NVDEV_SUBDEV_NR]; 33 atomic_t engref[NVDEV_SUBDEV_NR];
62 34
63 struct nouveau_vm_pgt *pgt; 35 struct nvkm_vm_pgt *pgt;
64 u32 fpde; 36 u32 fpde;
65 u32 lpde; 37 u32 lpde;
66}; 38};
67 39
68struct nouveau_mmu { 40struct nvkm_mmu {
69 struct nouveau_subdev base; 41 struct nvkm_subdev base;
70 42
71 u64 limit; 43 u64 limit;
72 u8 dma_bits; 44 u8 dma_bits;
@@ -74,62 +46,59 @@ struct nouveau_mmu {
74 u8 spg_shift; 46 u8 spg_shift;
75 u8 lpg_shift; 47 u8 lpg_shift;
76 48
77 int (*create)(struct nouveau_mmu *, u64 offset, u64 length, 49 int (*create)(struct nvkm_mmu *, u64 offset, u64 length,
78 u64 mm_offset, struct nouveau_vm **); 50 u64 mm_offset, struct nvkm_vm **);
79 51
80 void (*map_pgt)(struct nouveau_gpuobj *pgd, u32 pde, 52 void (*map_pgt)(struct nvkm_gpuobj *pgd, u32 pde,
81 struct nouveau_gpuobj *pgt[2]); 53 struct nvkm_gpuobj *pgt[2]);
82 void (*map)(struct nouveau_vma *, struct nouveau_gpuobj *, 54 void (*map)(struct nvkm_vma *, struct nvkm_gpuobj *,
83 struct nouveau_mem *, u32 pte, u32 cnt, 55 struct nvkm_mem *, u32 pte, u32 cnt,
84 u64 phys, u64 delta); 56 u64 phys, u64 delta);
85 void (*map_sg)(struct nouveau_vma *, struct nouveau_gpuobj *, 57 void (*map_sg)(struct nvkm_vma *, struct nvkm_gpuobj *,
86 struct nouveau_mem *, u32 pte, u32 cnt, dma_addr_t *); 58 struct nvkm_mem *, u32 pte, u32 cnt, dma_addr_t *);
87 void (*unmap)(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt); 59 void (*unmap)(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt);
88 void (*flush)(struct nouveau_vm *); 60 void (*flush)(struct nvkm_vm *);
89}; 61};
90 62
91static inline struct nouveau_mmu * 63static inline struct nvkm_mmu *
92nouveau_mmu(void *obj) 64nvkm_mmu(void *obj)
93{ 65{
94 return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_MMU); 66 return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MMU);
95} 67}
96 68
97#define nouveau_mmu_create(p,e,o,i,f,d) \ 69#define nvkm_mmu_create(p,e,o,i,f,d) \
98 nouveau_subdev_create((p), (e), (o), 0, (i), (f), (d)) 70 nvkm_subdev_create((p), (e), (o), 0, (i), (f), (d))
99#define nouveau_mmu_destroy(p) \ 71#define nvkm_mmu_destroy(p) \
100 nouveau_subdev_destroy(&(p)->base) 72 nvkm_subdev_destroy(&(p)->base)
101#define nouveau_mmu_init(p) \ 73#define nvkm_mmu_init(p) \
102 nouveau_subdev_init(&(p)->base) 74 nvkm_subdev_init(&(p)->base)
103#define nouveau_mmu_fini(p,s) \ 75#define nvkm_mmu_fini(p,s) \
104 nouveau_subdev_fini(&(p)->base, (s)) 76 nvkm_subdev_fini(&(p)->base, (s))
105 77
106#define _nouveau_mmu_dtor _nouveau_subdev_dtor 78#define _nvkm_mmu_dtor _nvkm_subdev_dtor
107#define _nouveau_mmu_init _nouveau_subdev_init 79#define _nvkm_mmu_init _nvkm_subdev_init
108#define _nouveau_mmu_fini _nouveau_subdev_fini 80#define _nvkm_mmu_fini _nvkm_subdev_fini
109 81
110extern struct nouveau_oclass nv04_mmu_oclass; 82extern struct nvkm_oclass nv04_mmu_oclass;
111extern struct nouveau_oclass nv41_mmu_oclass; 83extern struct nvkm_oclass nv41_mmu_oclass;
112extern struct nouveau_oclass nv44_mmu_oclass; 84extern struct nvkm_oclass nv44_mmu_oclass;
113extern struct nouveau_oclass nv50_mmu_oclass; 85extern struct nvkm_oclass nv50_mmu_oclass;
114extern struct nouveau_oclass nvc0_mmu_oclass; 86extern struct nvkm_oclass gf100_mmu_oclass;
115 87
116int nv04_vm_create(struct nouveau_mmu *, u64, u64, u64, 88int nv04_vm_create(struct nvkm_mmu *, u64, u64, u64,
117 struct nouveau_vm **); 89 struct nvkm_vm **);
118void nv04_mmu_dtor(struct nouveau_object *); 90void nv04_mmu_dtor(struct nvkm_object *);
119 91
120/* nouveau_vm.c */ 92int nvkm_vm_create(struct nvkm_mmu *, u64 offset, u64 length, u64 mm_offset,
121int nouveau_vm_create(struct nouveau_mmu *, u64 offset, u64 length, 93 u32 block, struct nvkm_vm **);
122 u64 mm_offset, u32 block, struct nouveau_vm **); 94int nvkm_vm_new(struct nvkm_device *, u64 offset, u64 length, u64 mm_offset,
123int nouveau_vm_new(struct nouveau_device *, u64 offset, u64 length, 95 struct nvkm_vm **);
124 u64 mm_offset, struct nouveau_vm **); 96int nvkm_vm_ref(struct nvkm_vm *, struct nvkm_vm **, struct nvkm_gpuobj *pgd);
125int nouveau_vm_ref(struct nouveau_vm *, struct nouveau_vm **, 97int nvkm_vm_get(struct nvkm_vm *, u64 size, u32 page_shift, u32 access,
126 struct nouveau_gpuobj *pgd); 98 struct nvkm_vma *);
127int nouveau_vm_get(struct nouveau_vm *, u64 size, u32 page_shift, 99void nvkm_vm_put(struct nvkm_vma *);
128 u32 access, struct nouveau_vma *); 100void nvkm_vm_map(struct nvkm_vma *, struct nvkm_mem *);
129void nouveau_vm_put(struct nouveau_vma *); 101void nvkm_vm_map_at(struct nvkm_vma *, u64 offset, struct nvkm_mem *);
130void nouveau_vm_map(struct nouveau_vma *, struct nouveau_mem *); 102void nvkm_vm_unmap(struct nvkm_vma *);
131void nouveau_vm_map_at(struct nouveau_vma *, u64 offset, struct nouveau_mem *); 103void nvkm_vm_unmap_at(struct nvkm_vma *, u64 offset, u64 length);
132void nouveau_vm_unmap(struct nouveau_vma *);
133void nouveau_vm_unmap_at(struct nouveau_vma *, u64 offset, u64 length);
134
135#endif 104#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/engctx.c b/drivers/gpu/drm/nouveau/nvkm/core/engctx.c
index a9df07a90f9b..fb2acbca75d9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/engctx.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/engctx.c
@@ -22,6 +22,7 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24#include <core/engctx.h> 24#include <core/engctx.h>
25#include <core/engine.h>
25#include <core/client.h> 26#include <core/client.h>
26 27
27static inline int 28static inline int
diff --git a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
index 0c5cb55fc617..2eba801aae6f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
+++ b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c
@@ -22,6 +22,7 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24#include <core/gpuobj.h> 24#include <core/gpuobj.h>
25#include <core/engine.h>
25 26
26#include <subdev/instmem.h> 27#include <subdev/instmem.h>
27#include <subdev/bar.h> 28#include <subdev/bar.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c
index b193b5f4037a..b14617ac5abe 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c
@@ -30,6 +30,7 @@
30#include <subdev/mmu.h> 30#include <subdev/mmu.h>
31 31
32#include <core/client.h> 32#include <core/client.h>
33#include <core/device.h>
33#include <core/enum.h> 34#include <core/enum.h>
34 35
35 36
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 165271cf9959..adf9c27a88b6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -76,7 +76,7 @@ gm100_identify(struct nouveau_device *device)
76 device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; 76 device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
77 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; 77 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
78 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 78 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
79 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; 79 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
80 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; 80 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
81 device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; 81 device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
82 82
@@ -120,7 +120,7 @@ gm100_identify(struct nouveau_device *device)
120 device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; 120 device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
121 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; 121 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
122 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 122 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
123 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; 123 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
124 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; 124 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
125 device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; 125 device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
126#if 0 126#if 0
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 2363a583fc3c..6cd796c33ba0 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -76,7 +76,7 @@ nvc0_identify(struct nouveau_device *device)
76 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; 76 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
77 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; 77 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
78 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 78 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
79 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; 79 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
80 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; 80 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
81 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; 81 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
82 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 82 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -109,7 +109,7 @@ nvc0_identify(struct nouveau_device *device)
109 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; 109 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
110 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; 110 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
111 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 111 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
112 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; 112 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
113 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; 113 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
114 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; 114 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
115 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 115 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -142,7 +142,7 @@ nvc0_identify(struct nouveau_device *device)
142 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; 142 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
143 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; 143 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
144 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 144 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
145 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; 145 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
146 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; 146 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
147 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; 147 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
148 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 148 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -174,7 +174,7 @@ nvc0_identify(struct nouveau_device *device)
174 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; 174 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
175 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; 175 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
176 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 176 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
177 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; 177 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
178 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; 178 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
179 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; 179 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
180 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 180 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -207,7 +207,7 @@ nvc0_identify(struct nouveau_device *device)
207 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; 207 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
208 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; 208 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
209 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 209 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
210 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; 210 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
211 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; 211 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
212 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; 212 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
213 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 213 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -239,7 +239,7 @@ nvc0_identify(struct nouveau_device *device)
239 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; 239 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
240 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; 240 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
241 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 241 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
242 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; 242 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
243 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; 243 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
244 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; 244 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
245 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 245 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -271,7 +271,7 @@ nvc0_identify(struct nouveau_device *device)
271 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; 271 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
272 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; 272 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
273 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 273 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
274 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; 274 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
275 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; 275 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
276 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; 276 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
277 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 277 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -304,7 +304,7 @@ nvc0_identify(struct nouveau_device *device)
304 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; 304 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
305 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; 305 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
306 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 306 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
307 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; 307 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
308 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; 308 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
309 device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; 309 device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
310 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 310 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -336,7 +336,7 @@ nvc0_identify(struct nouveau_device *device)
336 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; 336 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
337 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; 337 device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
338 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 338 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
339 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; 339 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
340 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; 340 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
341 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; 341 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
342 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; 342 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index 9ade56294c38..64aee47dee89 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -76,7 +76,7 @@ nve0_identify(struct nouveau_device *device)
76 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; 76 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
77 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; 77 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
78 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 78 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
79 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; 79 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
80 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; 80 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
81 device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; 81 device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
82 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 82 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -110,7 +110,7 @@ nve0_identify(struct nouveau_device *device)
110 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; 110 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
111 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; 111 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
112 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 112 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
113 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; 113 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
114 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; 114 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
115 device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; 115 device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
116 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 116 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -144,7 +144,7 @@ nve0_identify(struct nouveau_device *device)
144 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; 144 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
145 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; 145 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
146 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 146 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
147 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; 147 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
148 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; 148 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
149 device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; 149 device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
150 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 150 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -172,7 +172,7 @@ nve0_identify(struct nouveau_device *device)
172 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; 172 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
173 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass; 173 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass;
174 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 174 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
175 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; 175 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
176 device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass; 176 device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass;
177 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; 177 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
178 device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; 178 device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
@@ -200,7 +200,7 @@ nve0_identify(struct nouveau_device *device)
200 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; 200 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
201 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; 201 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
202 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 202 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
203 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; 203 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
204 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; 204 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
205 device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; 205 device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
206 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 206 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -234,7 +234,7 @@ nve0_identify(struct nouveau_device *device)
234 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; 234 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
235 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; 235 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
236 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 236 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
237 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; 237 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
238 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; 238 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
239 device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; 239 device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
240 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 240 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -268,7 +268,7 @@ nve0_identify(struct nouveau_device *device)
268 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; 268 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
269 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; 269 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
270 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 270 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
271 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; 271 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
272 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; 272 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
273 device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; 273 device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
274 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 274 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@@ -301,7 +301,7 @@ nve0_identify(struct nouveau_device *device)
301 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; 301 device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
302 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; 302 device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
303 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; 303 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
304 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; 304 device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
305 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; 305 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
306 device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; 306 device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass;
307 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; 307 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c
index e1500f77a56a..741f4a7cc0b1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c
@@ -24,6 +24,7 @@
24 24
25#include <core/object.h> 25#include <core/object.h>
26#include <core/client.h> 26#include <core/client.h>
27#include <core/device.h>
27#include <nvif/unpack.h> 28#include <nvif/unpack.h>
28#include <nvif/class.h> 29#include <nvif/class.h>
29 30
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
index 604cb5286632..be0293476279 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c
@@ -23,6 +23,7 @@
23 */ 23 */
24 24
25#include <core/client.h> 25#include <core/client.h>
26#include <core/device.h>
26#include <nvif/unpack.h> 27#include <nvif/unpack.h>
27#include <nvif/class.h> 28#include <nvif/class.h>
28#include <core/engctx.h> 29#include <core/engctx.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
index 8b7d879a7fa1..2798d26a8ca3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
@@ -20,6 +20,7 @@
20 * OTHER DEALINGS IN THE SOFTWARE. 20 * OTHER DEALINGS IN THE SOFTWARE.
21 */ 21 */
22 22
23#include <core/device.h>
23#include <core/gpuobj.h> 24#include <core/gpuobj.h>
24 25
25#define CP_FLAG_CLEAR 0 26#define CP_FLAG_CLEAR 0
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
index 9cc5c25f571b..6b3341f9a3f4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
@@ -23,6 +23,7 @@
23 */ 23 */
24 24
25#include <core/client.h> 25#include <core/client.h>
26#include <core/device.h>
26#include <core/os.h> 27#include <core/os.h>
27#include <core/handle.h> 28#include <core/handle.h>
28 29
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
index 3995d2cf0668..cea90df533d9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c
@@ -20,6 +20,7 @@
20 * OTHER DEALINGS IN THE SOFTWARE. 20 * OTHER DEALINGS IN THE SOFTWARE.
21 */ 21 */
22#include <engine/xtensa.h> 22#include <engine/xtensa.h>
23#include <core/device.h>
23 24
24#include <core/engctx.h> 25#include <core/engctx.h>
25 26
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
index 4c6d238dd3da..12a1aebd9a96 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c
@@ -23,6 +23,7 @@
23 */ 23 */
24#include "priv.h" 24#include "priv.h"
25 25
26#include <core/device.h>
26#include <core/gpuobj.h> 27#include <core/gpuobj.h>
27#include <subdev/fb.h> 28#include <subdev/fb.h>
28#include <subdev/mmu.h> 29#include <subdev/mmu.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c
index 5a6c2b7a6ef1..d51aa0237baf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c
@@ -23,6 +23,8 @@
23 */ 23 */
24#include "gf100.h" 24#include "gf100.h"
25 25
26#include <core/device.h>
27
26extern const u8 gf100_pte_storage_type_map[256]; 28extern const u8 gf100_pte_storage_type_map[256];
27 29
28bool 30bool
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c
index 6c0b82f35d94..09ebb9477e00 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c
@@ -25,6 +25,8 @@
25 */ 25 */
26#include "nv04.h" 26#include "nv04.h"
27 27
28#include <core/device.h>
29
28void 30void
29nv30_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch, 31nv30_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch,
30 u32 flags, struct nvkm_fb_tile *tile) 32 u32 flags, struct nvkm_fb_tile *tile)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
index 48fd5a5bcd3c..0480ce52aa06 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
@@ -24,6 +24,7 @@
24#include "nv50.h" 24#include "nv50.h"
25 25
26#include <core/client.h> 26#include <core/client.h>
27#include <core/device.h>
27#include <core/engctx.h> 28#include <core/engctx.h>
28#include <core/enum.h> 29#include <core/enum.h>
29 30
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c
index 6cf526b4a12f..5f30db140b47 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c
@@ -21,6 +21,8 @@
21 */ 21 */
22#include "priv.h" 22#include "priv.h"
23 23
24#include <core/device.h>
25
24struct gk20a_mem { 26struct gk20a_mem {
25 struct nvkm_mem base; 27 struct nvkm_mem base;
26 void *cpuaddr; 28 void *cpuaddr;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c
index 8bb7e432ad04..fbae05db4ffd 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c
@@ -23,6 +23,8 @@
23 */ 23 */
24#include "priv.h" 24#include "priv.h"
25 25
26#include <core/device.h>
27
26static int 28static int
27nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, 29nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
28 struct nvkm_oclass *oclass, void *data, u32 size, 30 struct nvkm_oclass *oclass, void *data, u32 size,
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
index 14f5ba5eefde..d2c81dd635dc 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
@@ -24,6 +24,7 @@
24#include "nv50.h" 24#include "nv50.h"
25#include "ramseq.h" 25#include "ramseq.h"
26 26
27#include <core/device.h>
27#include <core/option.h> 28#include <core/option.h>
28#include <subdev/bios.h> 29#include <subdev/bios.h>
29#include <subdev/bios/perf.h> 30#include <subdev/bios/perf.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild
index 729e27f2cbd4..012c9db687b2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild
@@ -3,4 +3,4 @@ nvkm-y += nvkm/subdev/mmu/nv04.o
3nvkm-y += nvkm/subdev/mmu/nv41.o 3nvkm-y += nvkm/subdev/mmu/nv41.o
4nvkm-y += nvkm/subdev/mmu/nv44.o 4nvkm-y += nvkm/subdev/mmu/nv44.o
5nvkm-y += nvkm/subdev/mmu/nv50.o 5nvkm-y += nvkm/subdev/mmu/nv50.o
6nvkm-y += nvkm/subdev/mmu/nvc0.o 6nvkm-y += nvkm/subdev/mmu/gf100.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c
index e3cb186c440b..277b6ec04e24 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c
@@ -21,19 +21,17 @@
21 * 21 *
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24#include <subdev/mmu.h>
25#include <subdev/fb.h>
24 26
25#include <core/gpuobj.h> 27#include <core/gpuobj.h>
26#include <core/mm.h>
27
28#include <subdev/fb.h>
29#include <subdev/mmu.h>
30 28
31void 29void
32nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node) 30nvkm_vm_map_at(struct nvkm_vma *vma, u64 delta, struct nvkm_mem *node)
33{ 31{
34 struct nouveau_vm *vm = vma->vm; 32 struct nvkm_vm *vm = vma->vm;
35 struct nouveau_mmu *mmu = vm->mmu; 33 struct nvkm_mmu *mmu = vm->mmu;
36 struct nouveau_mm_node *r; 34 struct nvkm_mm_node *r;
37 int big = vma->node->type != mmu->spg_shift; 35 int big = vma->node->type != mmu->spg_shift;
38 u32 offset = vma->node->offset + (delta >> 12); 36 u32 offset = vma->node->offset + (delta >> 12);
39 u32 bits = vma->node->type - 12; 37 u32 bits = vma->node->type - 12;
@@ -48,7 +46,7 @@ nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node)
48 u32 num = r->length >> bits; 46 u32 num = r->length >> bits;
49 47
50 while (num) { 48 while (num) {
51 struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; 49 struct nvkm_gpuobj *pgt = vm->pgt[pde].obj[big];
52 50
53 end = (pte + num); 51 end = (pte + num);
54 if (unlikely(end >= max)) 52 if (unlikely(end >= max))
@@ -73,11 +71,11 @@ nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node)
73} 71}
74 72
75static void 73static void
76nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length, 74nvkm_vm_map_sg_table(struct nvkm_vma *vma, u64 delta, u64 length,
77 struct nouveau_mem *mem) 75 struct nvkm_mem *mem)
78{ 76{
79 struct nouveau_vm *vm = vma->vm; 77 struct nvkm_vm *vm = vma->vm;
80 struct nouveau_mmu *mmu = vm->mmu; 78 struct nvkm_mmu *mmu = vm->mmu;
81 int big = vma->node->type != mmu->spg_shift; 79 int big = vma->node->type != mmu->spg_shift;
82 u32 offset = vma->node->offset + (delta >> 12); 80 u32 offset = vma->node->offset + (delta >> 12);
83 u32 bits = vma->node->type - 12; 81 u32 bits = vma->node->type - 12;
@@ -91,7 +89,7 @@ nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length,
91 struct scatterlist *sg; 89 struct scatterlist *sg;
92 90
93 for_each_sg(mem->sg->sgl, sg, mem->sg->nents, i) { 91 for_each_sg(mem->sg->sgl, sg, mem->sg->nents, i) {
94 struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; 92 struct nvkm_gpuobj *pgt = vm->pgt[pde].obj[big];
95 sglen = sg_dma_len(sg) >> PAGE_SHIFT; 93 sglen = sg_dma_len(sg) >> PAGE_SHIFT;
96 94
97 end = pte + sglen; 95 end = pte + sglen;
@@ -131,11 +129,11 @@ finish:
131} 129}
132 130
133static void 131static void
134nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length, 132nvkm_vm_map_sg(struct nvkm_vma *vma, u64 delta, u64 length,
135 struct nouveau_mem *mem) 133 struct nvkm_mem *mem)
136{ 134{
137 struct nouveau_vm *vm = vma->vm; 135 struct nvkm_vm *vm = vma->vm;
138 struct nouveau_mmu *mmu = vm->mmu; 136 struct nvkm_mmu *mmu = vm->mmu;
139 dma_addr_t *list = mem->pages; 137 dma_addr_t *list = mem->pages;
140 int big = vma->node->type != mmu->spg_shift; 138 int big = vma->node->type != mmu->spg_shift;
141 u32 offset = vma->node->offset + (delta >> 12); 139 u32 offset = vma->node->offset + (delta >> 12);
@@ -147,7 +145,7 @@ nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length,
147 u32 end, len; 145 u32 end, len;
148 146
149 while (num) { 147 while (num) {
150 struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; 148 struct nvkm_gpuobj *pgt = vm->pgt[pde].obj[big];
151 149
152 end = (pte + num); 150 end = (pte + num);
153 if (unlikely(end >= max)) 151 if (unlikely(end >= max))
@@ -169,22 +167,22 @@ nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length,
169} 167}
170 168
171void 169void
172nouveau_vm_map(struct nouveau_vma *vma, struct nouveau_mem *node) 170nvkm_vm_map(struct nvkm_vma *vma, struct nvkm_mem *node)
173{ 171{
174 if (node->sg) 172 if (node->sg)
175 nouveau_vm_map_sg_table(vma, 0, node->size << 12, node); 173 nvkm_vm_map_sg_table(vma, 0, node->size << 12, node);
176 else 174 else
177 if (node->pages) 175 if (node->pages)
178 nouveau_vm_map_sg(vma, 0, node->size << 12, node); 176 nvkm_vm_map_sg(vma, 0, node->size << 12, node);
179 else 177 else
180 nouveau_vm_map_at(vma, 0, node); 178 nvkm_vm_map_at(vma, 0, node);
181} 179}
182 180
183void 181void
184nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length) 182nvkm_vm_unmap_at(struct nvkm_vma *vma, u64 delta, u64 length)
185{ 183{
186 struct nouveau_vm *vm = vma->vm; 184 struct nvkm_vm *vm = vma->vm;
187 struct nouveau_mmu *mmu = vm->mmu; 185 struct nvkm_mmu *mmu = vm->mmu;
188 int big = vma->node->type != mmu->spg_shift; 186 int big = vma->node->type != mmu->spg_shift;
189 u32 offset = vma->node->offset + (delta >> 12); 187 u32 offset = vma->node->offset + (delta >> 12);
190 u32 bits = vma->node->type - 12; 188 u32 bits = vma->node->type - 12;
@@ -195,7 +193,7 @@ nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length)
195 u32 end, len; 193 u32 end, len;
196 194
197 while (num) { 195 while (num) {
198 struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; 196 struct nvkm_gpuobj *pgt = vm->pgt[pde].obj[big];
199 197
200 end = (pte + num); 198 end = (pte + num);
201 if (unlikely(end >= max)) 199 if (unlikely(end >= max))
@@ -216,18 +214,18 @@ nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length)
216} 214}
217 215
218void 216void
219nouveau_vm_unmap(struct nouveau_vma *vma) 217nvkm_vm_unmap(struct nvkm_vma *vma)
220{ 218{
221 nouveau_vm_unmap_at(vma, 0, (u64)vma->node->length << 12); 219 nvkm_vm_unmap_at(vma, 0, (u64)vma->node->length << 12);
222} 220}
223 221
224static void 222static void
225nouveau_vm_unmap_pgt(struct nouveau_vm *vm, int big, u32 fpde, u32 lpde) 223nvkm_vm_unmap_pgt(struct nvkm_vm *vm, int big, u32 fpde, u32 lpde)
226{ 224{
227 struct nouveau_mmu *mmu = vm->mmu; 225 struct nvkm_mmu *mmu = vm->mmu;
228 struct nouveau_vm_pgd *vpgd; 226 struct nvkm_vm_pgd *vpgd;
229 struct nouveau_vm_pgt *vpgt; 227 struct nvkm_vm_pgt *vpgt;
230 struct nouveau_gpuobj *pgt; 228 struct nvkm_gpuobj *pgt;
231 u32 pde; 229 u32 pde;
232 230
233 for (pde = fpde; pde <= lpde; pde++) { 231 for (pde = fpde; pde <= lpde; pde++) {
@@ -243,18 +241,18 @@ nouveau_vm_unmap_pgt(struct nouveau_vm *vm, int big, u32 fpde, u32 lpde)
243 } 241 }
244 242
245 mutex_unlock(&nv_subdev(mmu)->mutex); 243 mutex_unlock(&nv_subdev(mmu)->mutex);
246 nouveau_gpuobj_ref(NULL, &pgt); 244 nvkm_gpuobj_ref(NULL, &pgt);
247 mutex_lock(&nv_subdev(mmu)->mutex); 245 mutex_lock(&nv_subdev(mmu)->mutex);
248 } 246 }
249} 247}
250 248
251static int 249static int
252nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type) 250nvkm_vm_map_pgt(struct nvkm_vm *vm, u32 pde, u32 type)
253{ 251{
254 struct nouveau_mmu *mmu = vm->mmu; 252 struct nvkm_mmu *mmu = vm->mmu;
255 struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde]; 253 struct nvkm_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde];
256 struct nouveau_vm_pgd *vpgd; 254 struct nvkm_vm_pgd *vpgd;
257 struct nouveau_gpuobj *pgt; 255 struct nvkm_gpuobj *pgt;
258 int big = (type != mmu->spg_shift); 256 int big = (type != mmu->spg_shift);
259 u32 pgt_size; 257 u32 pgt_size;
260 int ret; 258 int ret;
@@ -263,8 +261,8 @@ nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type)
263 pgt_size *= 8; 261 pgt_size *= 8;
264 262
265 mutex_unlock(&nv_subdev(mmu)->mutex); 263 mutex_unlock(&nv_subdev(mmu)->mutex);
266 ret = nouveau_gpuobj_new(nv_object(vm->mmu), NULL, pgt_size, 0x1000, 264 ret = nvkm_gpuobj_new(nv_object(vm->mmu), NULL, pgt_size, 0x1000,
267 NVOBJ_FLAG_ZERO_ALLOC, &pgt); 265 NVOBJ_FLAG_ZERO_ALLOC, &pgt);
268 mutex_lock(&nv_subdev(mmu)->mutex); 266 mutex_lock(&nv_subdev(mmu)->mutex);
269 if (unlikely(ret)) 267 if (unlikely(ret))
270 return ret; 268 return ret;
@@ -272,7 +270,7 @@ nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type)
272 /* someone beat us to filling the PDE while we didn't have the lock */ 270 /* someone beat us to filling the PDE while we didn't have the lock */
273 if (unlikely(vpgt->refcount[big]++)) { 271 if (unlikely(vpgt->refcount[big]++)) {
274 mutex_unlock(&nv_subdev(mmu)->mutex); 272 mutex_unlock(&nv_subdev(mmu)->mutex);
275 nouveau_gpuobj_ref(NULL, &pgt); 273 nvkm_gpuobj_ref(NULL, &pgt);
276 mutex_lock(&nv_subdev(mmu)->mutex); 274 mutex_lock(&nv_subdev(mmu)->mutex);
277 return 0; 275 return 0;
278 } 276 }
@@ -286,18 +284,18 @@ nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type)
286} 284}
287 285
288int 286int
289nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift, 287nvkm_vm_get(struct nvkm_vm *vm, u64 size, u32 page_shift, u32 access,
290 u32 access, struct nouveau_vma *vma) 288 struct nvkm_vma *vma)
291{ 289{
292 struct nouveau_mmu *mmu = vm->mmu; 290 struct nvkm_mmu *mmu = vm->mmu;
293 u32 align = (1 << page_shift) >> 12; 291 u32 align = (1 << page_shift) >> 12;
294 u32 msize = size >> 12; 292 u32 msize = size >> 12;
295 u32 fpde, lpde, pde; 293 u32 fpde, lpde, pde;
296 int ret; 294 int ret;
297 295
298 mutex_lock(&nv_subdev(mmu)->mutex); 296 mutex_lock(&nv_subdev(mmu)->mutex);
299 ret = nouveau_mm_head(&vm->mm, 0, page_shift, msize, msize, align, 297 ret = nvkm_mm_head(&vm->mm, 0, page_shift, msize, msize, align,
300 &vma->node); 298 &vma->node);
301 if (unlikely(ret != 0)) { 299 if (unlikely(ret != 0)) {
302 mutex_unlock(&nv_subdev(mmu)->mutex); 300 mutex_unlock(&nv_subdev(mmu)->mutex);
303 return ret; 301 return ret;
@@ -307,7 +305,7 @@ nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift,
307 lpde = (vma->node->offset + vma->node->length - 1) >> mmu->pgt_bits; 305 lpde = (vma->node->offset + vma->node->length - 1) >> mmu->pgt_bits;
308 306
309 for (pde = fpde; pde <= lpde; pde++) { 307 for (pde = fpde; pde <= lpde; pde++) {
310 struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde]; 308 struct nvkm_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde];
311 int big = (vma->node->type != mmu->spg_shift); 309 int big = (vma->node->type != mmu->spg_shift);
312 310
313 if (likely(vpgt->refcount[big])) { 311 if (likely(vpgt->refcount[big])) {
@@ -315,11 +313,11 @@ nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift,
315 continue; 313 continue;
316 } 314 }
317 315
318 ret = nouveau_vm_map_pgt(vm, pde, vma->node->type); 316 ret = nvkm_vm_map_pgt(vm, pde, vma->node->type);
319 if (ret) { 317 if (ret) {
320 if (pde != fpde) 318 if (pde != fpde)
321 nouveau_vm_unmap_pgt(vm, big, fpde, pde - 1); 319 nvkm_vm_unmap_pgt(vm, big, fpde, pde - 1);
322 nouveau_mm_free(&vm->mm, &vma->node); 320 nvkm_mm_free(&vm->mm, &vma->node);
323 mutex_unlock(&nv_subdev(mmu)->mutex); 321 mutex_unlock(&nv_subdev(mmu)->mutex);
324 return ret; 322 return ret;
325 } 323 }
@@ -327,17 +325,17 @@ nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift,
327 mutex_unlock(&nv_subdev(mmu)->mutex); 325 mutex_unlock(&nv_subdev(mmu)->mutex);
328 326
329 vma->vm = NULL; 327 vma->vm = NULL;
330 nouveau_vm_ref(vm, &vma->vm, NULL); 328 nvkm_vm_ref(vm, &vma->vm, NULL);
331 vma->offset = (u64)vma->node->offset << 12; 329 vma->offset = (u64)vma->node->offset << 12;
332 vma->access = access; 330 vma->access = access;
333 return 0; 331 return 0;
334} 332}
335 333
336void 334void
337nouveau_vm_put(struct nouveau_vma *vma) 335nvkm_vm_put(struct nvkm_vma *vma)
338{ 336{
339 struct nouveau_vm *vm = vma->vm; 337 struct nvkm_vm *vm = vma->vm;
340 struct nouveau_mmu *mmu = vm->mmu; 338 struct nvkm_mmu *mmu = vm->mmu;
341 u32 fpde, lpde; 339 u32 fpde, lpde;
342 340
343 if (unlikely(vma->node == NULL)) 341 if (unlikely(vma->node == NULL))
@@ -346,18 +344,18 @@ nouveau_vm_put(struct nouveau_vma *vma)
346 lpde = (vma->node->offset + vma->node->length - 1) >> mmu->pgt_bits; 344 lpde = (vma->node->offset + vma->node->length - 1) >> mmu->pgt_bits;
347 345
348 mutex_lock(&nv_subdev(mmu)->mutex); 346 mutex_lock(&nv_subdev(mmu)->mutex);
349 nouveau_vm_unmap_pgt(vm, vma->node->type != mmu->spg_shift, fpde, lpde); 347 nvkm_vm_unmap_pgt(vm, vma->node->type != mmu->spg_shift, fpde, lpde);
350 nouveau_mm_free(&vm->mm, &vma->node); 348 nvkm_mm_free(&vm->mm, &vma->node);
351 mutex_unlock(&nv_subdev(mmu)->mutex); 349 mutex_unlock(&nv_subdev(mmu)->mutex);
352 350
353 nouveau_vm_ref(NULL, &vma->vm, NULL); 351 nvkm_vm_ref(NULL, &vma->vm, NULL);
354} 352}
355 353
356int 354int
357nouveau_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, 355nvkm_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mm_offset,
358 u64 mm_offset, u32 block, struct nouveau_vm **pvm) 356 u32 block, struct nvkm_vm **pvm)
359{ 357{
360 struct nouveau_vm *vm; 358 struct nvkm_vm *vm;
361 u64 mm_length = (offset + length) - mm_offset; 359 u64 mm_length = (offset + length) - mm_offset;
362 int ret; 360 int ret;
363 361
@@ -377,8 +375,8 @@ nouveau_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length,
377 return -ENOMEM; 375 return -ENOMEM;
378 } 376 }
379 377
380 ret = nouveau_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12, 378 ret = nvkm_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12,
381 block >> 12); 379 block >> 12);
382 if (ret) { 380 if (ret) {
383 vfree(vm->pgt); 381 vfree(vm->pgt);
384 kfree(vm); 382 kfree(vm);
@@ -391,18 +389,18 @@ nouveau_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length,
391} 389}
392 390
393int 391int
394nouveau_vm_new(struct nouveau_device *device, u64 offset, u64 length, 392nvkm_vm_new(struct nvkm_device *device, u64 offset, u64 length, u64 mm_offset,
395 u64 mm_offset, struct nouveau_vm **pvm) 393 struct nvkm_vm **pvm)
396{ 394{
397 struct nouveau_mmu *mmu = nouveau_mmu(device); 395 struct nvkm_mmu *mmu = nvkm_mmu(device);
398 return mmu->create(mmu, offset, length, mm_offset, pvm); 396 return mmu->create(mmu, offset, length, mm_offset, pvm);
399} 397}
400 398
401static int 399static int
402nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd) 400nvkm_vm_link(struct nvkm_vm *vm, struct nvkm_gpuobj *pgd)
403{ 401{
404 struct nouveau_mmu *mmu = vm->mmu; 402 struct nvkm_mmu *mmu = vm->mmu;
405 struct nouveau_vm_pgd *vpgd; 403 struct nvkm_vm_pgd *vpgd;
406 int i; 404 int i;
407 405
408 if (!pgd) 406 if (!pgd)
@@ -412,7 +410,7 @@ nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd)
412 if (!vpgd) 410 if (!vpgd)
413 return -ENOMEM; 411 return -ENOMEM;
414 412
415 nouveau_gpuobj_ref(pgd, &vpgd->obj); 413 nvkm_gpuobj_ref(pgd, &vpgd->obj);
416 414
417 mutex_lock(&nv_subdev(mmu)->mutex); 415 mutex_lock(&nv_subdev(mmu)->mutex);
418 for (i = vm->fpde; i <= vm->lpde; i++) 416 for (i = vm->fpde; i <= vm->lpde; i++)
@@ -423,11 +421,11 @@ nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd)
423} 421}
424 422
425static void 423static void
426nouveau_vm_unlink(struct nouveau_vm *vm, struct nouveau_gpuobj *mpgd) 424nvkm_vm_unlink(struct nvkm_vm *vm, struct nvkm_gpuobj *mpgd)
427{ 425{
428 struct nouveau_mmu *mmu = vm->mmu; 426 struct nvkm_mmu *mmu = vm->mmu;
429 struct nouveau_vm_pgd *vpgd, *tmp; 427 struct nvkm_vm_pgd *vpgd, *tmp;
430 struct nouveau_gpuobj *pgd = NULL; 428 struct nvkm_gpuobj *pgd = NULL;
431 429
432 if (!mpgd) 430 if (!mpgd)
433 return; 431 return;
@@ -443,30 +441,29 @@ nouveau_vm_unlink(struct nouveau_vm *vm, struct nouveau_gpuobj *mpgd)
443 } 441 }
444 mutex_unlock(&nv_subdev(mmu)->mutex); 442 mutex_unlock(&nv_subdev(mmu)->mutex);
445 443
446 nouveau_gpuobj_ref(NULL, &pgd); 444 nvkm_gpuobj_ref(NULL, &pgd);
447} 445}
448 446
449static void 447static void
450nouveau_vm_del(struct kref *kref) 448nvkm_vm_del(struct kref *kref)
451{ 449{
452 struct nouveau_vm *vm = container_of(kref, typeof(*vm), refcount); 450 struct nvkm_vm *vm = container_of(kref, typeof(*vm), refcount);
453 struct nouveau_vm_pgd *vpgd, *tmp; 451 struct nvkm_vm_pgd *vpgd, *tmp;
454 452
455 list_for_each_entry_safe(vpgd, tmp, &vm->pgd_list, head) { 453 list_for_each_entry_safe(vpgd, tmp, &vm->pgd_list, head) {
456 nouveau_vm_unlink(vm, vpgd->obj); 454 nvkm_vm_unlink(vm, vpgd->obj);
457 } 455 }
458 456
459 nouveau_mm_fini(&vm->mm); 457 nvkm_mm_fini(&vm->mm);
460 vfree(vm->pgt); 458 vfree(vm->pgt);
461 kfree(vm); 459 kfree(vm);
462} 460}
463 461
464int 462int
465nouveau_vm_ref(struct nouveau_vm *ref, struct nouveau_vm **ptr, 463nvkm_vm_ref(struct nvkm_vm *ref, struct nvkm_vm **ptr, struct nvkm_gpuobj *pgd)
466 struct nouveau_gpuobj *pgd)
467{ 464{
468 if (ref) { 465 if (ref) {
469 int ret = nouveau_vm_link(ref, pgd); 466 int ret = nvkm_vm_link(ref, pgd);
470 if (ret) 467 if (ret)
471 return ret; 468 return ret;
472 469
@@ -474,8 +471,8 @@ nouveau_vm_ref(struct nouveau_vm *ref, struct nouveau_vm **ptr,
474 } 471 }
475 472
476 if (*ptr) { 473 if (*ptr) {
477 nouveau_vm_unlink(*ptr, pgd); 474 nvkm_vm_unlink(*ptr, pgd);
478 kref_put(&(*ptr)->refcount, nouveau_vm_del); 475 kref_put(&(*ptr)->refcount, nvkm_vm_del);
479 } 476 }
480 477
481 *ptr = ref; 478 *ptr = ref;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c
index bd695c59aac7..294cda37f068 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c
@@ -21,25 +21,23 @@
21 * 21 *
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24
25#include <core/device.h>
26#include <core/gpuobj.h>
27
28#include <subdev/timer.h>
29#include <subdev/fb.h>
30#include <subdev/mmu.h> 24#include <subdev/mmu.h>
31#include <subdev/ltc.h>
32#include <subdev/bar.h> 25#include <subdev/bar.h>
26#include <subdev/fb.h>
27#include <subdev/ltc.h>
28#include <subdev/timer.h>
33 29
34struct nvc0_mmu_priv { 30#include <core/gpuobj.h>
35 struct nouveau_mmu base; 31
32struct gf100_mmu_priv {
33 struct nvkm_mmu base;
36}; 34};
37 35
38 36
39/* Map from compressed to corresponding uncompressed storage type. 37/* Map from compressed to corresponding uncompressed storage type.
40 * The value 0xff represents an invalid storage type. 38 * The value 0xff represents an invalid storage type.
41 */ 39 */
42const u8 nvc0_pte_storage_type_map[256] = 40const u8 gf100_pte_storage_type_map[256] =
43{ 41{
44 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0xff, 0x01, /* 0x00 */ 42 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0xff, 0x01, /* 0x00 */
45 0x01, 0x01, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 43 0x01, 0x01, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff,
@@ -77,8 +75,7 @@ const u8 nvc0_pte_storage_type_map[256] =
77 75
78 76
79static void 77static void
80nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index, 78gf100_vm_map_pgt(struct nvkm_gpuobj *pgd, u32 index, struct nvkm_gpuobj *pgt[2])
81 struct nouveau_gpuobj *pgt[2])
82{ 79{
83 u32 pde[2] = { 0, 0 }; 80 u32 pde[2] = { 0, 0 };
84 81
@@ -92,7 +89,7 @@ nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index,
92} 89}
93 90
94static inline u64 91static inline u64
95nvc0_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) 92gf100_vm_addr(struct nvkm_vma *vma, u64 phys, u32 memtype, u32 target)
96{ 93{
97 phys >>= 8; 94 phys >>= 8;
98 95
@@ -102,21 +99,20 @@ nvc0_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target)
102 99
103 phys |= ((u64)target << 32); 100 phys |= ((u64)target << 32);
104 phys |= ((u64)memtype << 36); 101 phys |= ((u64)memtype << 36);
105
106 return phys; 102 return phys;
107} 103}
108 104
109static void 105static void
110nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, 106gf100_vm_map(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
111 struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) 107 struct nvkm_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)
112{ 108{
113 u64 next = 1 << (vma->node->type - 8); 109 u64 next = 1 << (vma->node->type - 8);
114 110
115 phys = nvc0_vm_addr(vma, phys, mem->memtype, 0); 111 phys = gf100_vm_addr(vma, phys, mem->memtype, 0);
116 pte <<= 3; 112 pte <<= 3;
117 113
118 if (mem->tag) { 114 if (mem->tag) {
119 struct nouveau_ltc *ltc = nouveau_ltc(vma->vm->mmu); 115 struct nvkm_ltc *ltc = nvkm_ltc(vma->vm->mmu);
120 u32 tag = mem->tag->offset + (delta >> 17); 116 u32 tag = mem->tag->offset + (delta >> 17);
121 phys |= (u64)tag << (32 + 12); 117 phys |= (u64)tag << (32 + 12);
122 next |= (u64)1 << (32 + 12); 118 next |= (u64)1 << (32 + 12);
@@ -132,16 +128,16 @@ nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
132} 128}
133 129
134static void 130static void
135nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, 131gf100_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
136 struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) 132 struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
137{ 133{
138 u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 7 : 5; 134 u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 7 : 5;
139 /* compressed storage types are invalid for system memory */ 135 /* compressed storage types are invalid for system memory */
140 u32 memtype = nvc0_pte_storage_type_map[mem->memtype & 0xff]; 136 u32 memtype = gf100_pte_storage_type_map[mem->memtype & 0xff];
141 137
142 pte <<= 3; 138 pte <<= 3;
143 while (cnt--) { 139 while (cnt--) {
144 u64 phys = nvc0_vm_addr(vma, *list++, memtype, target); 140 u64 phys = gf100_vm_addr(vma, *list++, memtype, target);
145 nv_wo32(pgt, pte + 0, lower_32_bits(phys)); 141 nv_wo32(pgt, pte + 0, lower_32_bits(phys));
146 nv_wo32(pgt, pte + 4, upper_32_bits(phys)); 142 nv_wo32(pgt, pte + 4, upper_32_bits(phys));
147 pte += 8; 143 pte += 8;
@@ -149,7 +145,7 @@ nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
149} 145}
150 146
151static void 147static void
152nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) 148gf100_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)
153{ 149{
154 pte <<= 3; 150 pte <<= 3;
155 while (cnt--) { 151 while (cnt--) {
@@ -160,11 +156,11 @@ nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
160} 156}
161 157
162static void 158static void
163nvc0_vm_flush(struct nouveau_vm *vm) 159gf100_vm_flush(struct nvkm_vm *vm)
164{ 160{
165 struct nvc0_mmu_priv *priv = (void *)vm->mmu; 161 struct gf100_mmu_priv *priv = (void *)vm->mmu;
166 struct nouveau_bar *bar = nouveau_bar(priv); 162 struct nvkm_bar *bar = nvkm_bar(priv);
167 struct nouveau_vm_pgd *vpgd; 163 struct nvkm_vm_pgd *vpgd;
168 u32 type; 164 u32 type;
169 165
170 bar->flush(bar); 166 bar->flush(bar);
@@ -196,21 +192,21 @@ nvc0_vm_flush(struct nouveau_vm *vm)
196} 192}
197 193
198static int 194static int
199nvc0_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, 195gf100_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mm_offset,
200 u64 mm_offset, struct nouveau_vm **pvm) 196 struct nvkm_vm **pvm)
201{ 197{
202 return nouveau_vm_create(mmu, offset, length, mm_offset, 4096, pvm); 198 return nvkm_vm_create(mmu, offset, length, mm_offset, 4096, pvm);
203} 199}
204 200
205static int 201static int
206nvc0_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 202gf100_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
207 struct nouveau_oclass *oclass, void *data, u32 size, 203 struct nvkm_oclass *oclass, void *data, u32 size,
208 struct nouveau_object **pobject) 204 struct nvkm_object **pobject)
209{ 205{
210 struct nvc0_mmu_priv *priv; 206 struct gf100_mmu_priv *priv;
211 int ret; 207 int ret;
212 208
213 ret = nouveau_mmu_create(parent, engine, oclass, "VM", "vm", &priv); 209 ret = nvkm_mmu_create(parent, engine, oclass, "VM", "vm", &priv);
214 *pobject = nv_object(priv); 210 *pobject = nv_object(priv);
215 if (ret) 211 if (ret)
216 return ret; 212 return ret;
@@ -220,22 +216,22 @@ nvc0_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
220 priv->base.pgt_bits = 27 - 12; 216 priv->base.pgt_bits = 27 - 12;
221 priv->base.spg_shift = 12; 217 priv->base.spg_shift = 12;
222 priv->base.lpg_shift = 17; 218 priv->base.lpg_shift = 17;
223 priv->base.create = nvc0_vm_create; 219 priv->base.create = gf100_vm_create;
224 priv->base.map_pgt = nvc0_vm_map_pgt; 220 priv->base.map_pgt = gf100_vm_map_pgt;
225 priv->base.map = nvc0_vm_map; 221 priv->base.map = gf100_vm_map;
226 priv->base.map_sg = nvc0_vm_map_sg; 222 priv->base.map_sg = gf100_vm_map_sg;
227 priv->base.unmap = nvc0_vm_unmap; 223 priv->base.unmap = gf100_vm_unmap;
228 priv->base.flush = nvc0_vm_flush; 224 priv->base.flush = gf100_vm_flush;
229 return 0; 225 return 0;
230} 226}
231 227
232struct nouveau_oclass 228struct nvkm_oclass
233nvc0_mmu_oclass = { 229gf100_mmu_oclass = {
234 .handle = NV_SUBDEV(MMU, 0xc0), 230 .handle = NV_SUBDEV(MMU, 0xc0),
235 .ofuncs = &(struct nouveau_ofuncs) { 231 .ofuncs = &(struct nvkm_ofuncs) {
236 .ctor = nvc0_mmu_ctor, 232 .ctor = gf100_mmu_ctor,
237 .dtor = _nouveau_mmu_dtor, 233 .dtor = _nvkm_mmu_dtor,
238 .init = _nouveau_mmu_init, 234 .init = _nvkm_mmu_init,
239 .fini = _nouveau_mmu_fini, 235 .fini = _nvkm_mmu_fini,
240 }, 236 },
241}; 237};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c
index a317d8f13570..fe93ea2711c9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c
@@ -21,11 +21,11 @@
21 * 21 *
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24#include "nv04.h"
24 25
26#include <core/device.h>
25#include <core/gpuobj.h> 27#include <core/gpuobj.h>
26 28
27#include "nv04.h"
28
29#define NV04_PDMA_SIZE (128 * 1024 * 1024) 29#define NV04_PDMA_SIZE (128 * 1024 * 1024)
30#define NV04_PDMA_PAGE ( 4 * 1024) 30#define NV04_PDMA_PAGE ( 4 * 1024)
31 31
@@ -34,8 +34,8 @@
34 ******************************************************************************/ 34 ******************************************************************************/
35 35
36static void 36static void
37nv04_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, 37nv04_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
38 struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) 38 struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
39{ 39{
40 pte = 0x00008 + (pte * 4); 40 pte = 0x00008 + (pte * 4);
41 while (cnt) { 41 while (cnt) {
@@ -51,7 +51,7 @@ nv04_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
51} 51}
52 52
53static void 53static void
54nv04_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) 54nv04_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)
55{ 55{
56 pte = 0x00008 + (pte * 4); 56 pte = 0x00008 + (pte * 4);
57 while (cnt--) { 57 while (cnt--) {
@@ -61,7 +61,7 @@ nv04_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
61} 61}
62 62
63static void 63static void
64nv04_vm_flush(struct nouveau_vm *vm) 64nv04_vm_flush(struct nvkm_vm *vm)
65{ 65{
66} 66}
67 67
@@ -70,8 +70,8 @@ nv04_vm_flush(struct nouveau_vm *vm)
70 ******************************************************************************/ 70 ******************************************************************************/
71 71
72int 72int
73nv04_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, u64 mmstart, 73nv04_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mmstart,
74 struct nouveau_vm **pvm) 74 struct nvkm_vm **pvm)
75{ 75{
76 return -EINVAL; 76 return -EINVAL;
77} 77}
@@ -81,16 +81,16 @@ nv04_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, u64 mmstart,
81 ******************************************************************************/ 81 ******************************************************************************/
82 82
83static int 83static int
84nv04_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 84nv04_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
85 struct nouveau_oclass *oclass, void *data, u32 size, 85 struct nvkm_oclass *oclass, void *data, u32 size,
86 struct nouveau_object **pobject) 86 struct nvkm_object **pobject)
87{ 87{
88 struct nv04_mmu_priv *priv; 88 struct nv04_mmu_priv *priv;
89 struct nouveau_gpuobj *dma; 89 struct nvkm_gpuobj *dma;
90 int ret; 90 int ret;
91 91
92 ret = nouveau_mmu_create(parent, engine, oclass, "PCIGART", 92 ret = nvkm_mmu_create(parent, engine, oclass, "PCIGART",
93 "pcigart", &priv); 93 "pcigart", &priv);
94 *pobject = nv_object(priv); 94 *pobject = nv_object(priv);
95 if (ret) 95 if (ret)
96 return ret; 96 return ret;
@@ -105,15 +105,15 @@ nv04_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
105 priv->base.unmap = nv04_vm_unmap; 105 priv->base.unmap = nv04_vm_unmap;
106 priv->base.flush = nv04_vm_flush; 106 priv->base.flush = nv04_vm_flush;
107 107
108 ret = nouveau_vm_create(&priv->base, 0, NV04_PDMA_SIZE, 0, 4096, 108 ret = nvkm_vm_create(&priv->base, 0, NV04_PDMA_SIZE, 0, 4096,
109 &priv->vm); 109 &priv->vm);
110 if (ret) 110 if (ret)
111 return ret; 111 return ret;
112 112
113 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 113 ret = nvkm_gpuobj_new(nv_object(priv), NULL,
114 (NV04_PDMA_SIZE / NV04_PDMA_PAGE) * 4 + 114 (NV04_PDMA_SIZE / NV04_PDMA_PAGE) * 4 + 8,
115 8, 16, NVOBJ_FLAG_ZERO_ALLOC, 115 16, NVOBJ_FLAG_ZERO_ALLOC,
116 &priv->vm->pgt[0].obj[0]); 116 &priv->vm->pgt[0].obj[0]);
117 dma = priv->vm->pgt[0].obj[0]; 117 dma = priv->vm->pgt[0].obj[0];
118 priv->vm->pgt[0].refcount[0] = 1; 118 priv->vm->pgt[0].refcount[0] = 1;
119 if (ret) 119 if (ret)
@@ -125,27 +125,27 @@ nv04_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
125} 125}
126 126
127void 127void
128nv04_mmu_dtor(struct nouveau_object *object) 128nv04_mmu_dtor(struct nvkm_object *object)
129{ 129{
130 struct nv04_mmu_priv *priv = (void *)object; 130 struct nv04_mmu_priv *priv = (void *)object;
131 if (priv->vm) { 131 if (priv->vm) {
132 nouveau_gpuobj_ref(NULL, &priv->vm->pgt[0].obj[0]); 132 nvkm_gpuobj_ref(NULL, &priv->vm->pgt[0].obj[0]);
133 nouveau_vm_ref(NULL, &priv->vm, NULL); 133 nvkm_vm_ref(NULL, &priv->vm, NULL);
134 } 134 }
135 if (priv->nullp) { 135 if (priv->nullp) {
136 pci_free_consistent(nv_device(priv)->pdev, 16 * 1024, 136 pci_free_consistent(nv_device(priv)->pdev, 16 * 1024,
137 priv->nullp, priv->null); 137 priv->nullp, priv->null);
138 } 138 }
139 nouveau_mmu_destroy(&priv->base); 139 nvkm_mmu_destroy(&priv->base);
140} 140}
141 141
142struct nouveau_oclass 142struct nvkm_oclass
143nv04_mmu_oclass = { 143nv04_mmu_oclass = {
144 .handle = NV_SUBDEV(MMU, 0x04), 144 .handle = NV_SUBDEV(MMU, 0x04),
145 .ofuncs = &(struct nouveau_ofuncs) { 145 .ofuncs = &(struct nvkm_ofuncs) {
146 .ctor = nv04_mmu_ctor, 146 .ctor = nv04_mmu_ctor,
147 .dtor = nv04_mmu_dtor, 147 .dtor = nv04_mmu_dtor,
148 .init = _nouveau_mmu_init, 148 .init = _nvkm_mmu_init,
149 .fini = _nouveau_mmu_fini, 149 .fini = _nvkm_mmu_fini,
150 }, 150 },
151}; 151};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h
index 919b254ef6a1..7bf6f4b38f1d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h
@@ -4,8 +4,8 @@
4#include <subdev/mmu.h> 4#include <subdev/mmu.h>
5 5
6struct nv04_mmu_priv { 6struct nv04_mmu_priv {
7 struct nouveau_mmu base; 7 struct nvkm_mmu base;
8 struct nouveau_vm *vm; 8 struct nvkm_vm *vm;
9 dma_addr_t null; 9 dma_addr_t null;
10 void *nullp; 10 void *nullp;
11}; 11};
@@ -13,7 +13,7 @@ struct nv04_mmu_priv {
13static inline struct nv04_mmu_priv * 13static inline struct nv04_mmu_priv *
14nv04_mmu(void *obj) 14nv04_mmu(void *obj)
15{ 15{
16 return (void *)nouveau_mmu(obj); 16 return (void *)nvkm_mmu(obj);
17} 17}
18 18
19#endif 19#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c
index 61af036f1252..61ee3ab11660 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c
@@ -21,14 +21,12 @@
21 * 21 *
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24#include "nv04.h"
24 25
26#include <core/device.h>
25#include <core/gpuobj.h> 27#include <core/gpuobj.h>
26#include <core/option.h> 28#include <core/option.h>
27
28#include <subdev/timer.h> 29#include <subdev/timer.h>
29#include <subdev/mmu.h>
30
31#include "nv04.h"
32 30
33#define NV41_GART_SIZE (512 * 1024 * 1024) 31#define NV41_GART_SIZE (512 * 1024 * 1024)
34#define NV41_GART_PAGE ( 4 * 1024) 32#define NV41_GART_PAGE ( 4 * 1024)
@@ -38,8 +36,8 @@
38 ******************************************************************************/ 36 ******************************************************************************/
39 37
40static void 38static void
41nv41_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, 39nv41_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
42 struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) 40 struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
43{ 41{
44 pte = pte * 4; 42 pte = pte * 4;
45 while (cnt) { 43 while (cnt) {
@@ -55,7 +53,7 @@ nv41_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
55} 53}
56 54
57static void 55static void
58nv41_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) 56nv41_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)
59{ 57{
60 pte = pte * 4; 58 pte = pte * 4;
61 while (cnt--) { 59 while (cnt--) {
@@ -65,7 +63,7 @@ nv41_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
65} 63}
66 64
67static void 65static void
68nv41_vm_flush(struct nouveau_vm *vm) 66nv41_vm_flush(struct nvkm_vm *vm)
69{ 67{
70 struct nv04_mmu_priv *priv = (void *)vm->mmu; 68 struct nv04_mmu_priv *priv = (void *)vm->mmu;
71 69
@@ -84,22 +82,22 @@ nv41_vm_flush(struct nouveau_vm *vm)
84 ******************************************************************************/ 82 ******************************************************************************/
85 83
86static int 84static int
87nv41_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 85nv41_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
88 struct nouveau_oclass *oclass, void *data, u32 size, 86 struct nvkm_oclass *oclass, void *data, u32 size,
89 struct nouveau_object **pobject) 87 struct nvkm_object **pobject)
90{ 88{
91 struct nouveau_device *device = nv_device(parent); 89 struct nvkm_device *device = nv_device(parent);
92 struct nv04_mmu_priv *priv; 90 struct nv04_mmu_priv *priv;
93 int ret; 91 int ret;
94 92
95 if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) || 93 if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
96 !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) { 94 !nvkm_boolopt(device->cfgopt, "NvPCIE", true)) {
97 return nouveau_object_ctor(parent, engine, &nv04_mmu_oclass, 95 return nvkm_object_ctor(parent, engine, &nv04_mmu_oclass,
98 data, size, pobject); 96 data, size, pobject);
99 } 97 }
100 98
101 ret = nouveau_mmu_create(parent, engine, oclass, "PCIEGART", 99 ret = nvkm_mmu_create(parent, engine, oclass, "PCIEGART",
102 "pciegart", &priv); 100 "pciegart", &priv);
103 *pobject = nv_object(priv); 101 *pobject = nv_object(priv);
104 if (ret) 102 if (ret)
105 return ret; 103 return ret;
@@ -114,15 +112,15 @@ nv41_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
114 priv->base.unmap = nv41_vm_unmap; 112 priv->base.unmap = nv41_vm_unmap;
115 priv->base.flush = nv41_vm_flush; 113 priv->base.flush = nv41_vm_flush;
116 114
117 ret = nouveau_vm_create(&priv->base, 0, NV41_GART_SIZE, 0, 4096, 115 ret = nvkm_vm_create(&priv->base, 0, NV41_GART_SIZE, 0, 4096,
118 &priv->vm); 116 &priv->vm);
119 if (ret) 117 if (ret)
120 return ret; 118 return ret;
121 119
122 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 120 ret = nvkm_gpuobj_new(nv_object(priv), NULL,
123 (NV41_GART_SIZE / NV41_GART_PAGE) * 4, 121 (NV41_GART_SIZE / NV41_GART_PAGE) * 4, 16,
124 16, NVOBJ_FLAG_ZERO_ALLOC, 122 NVOBJ_FLAG_ZERO_ALLOC,
125 &priv->vm->pgt[0].obj[0]); 123 &priv->vm->pgt[0].obj[0]);
126 priv->vm->pgt[0].refcount[0] = 1; 124 priv->vm->pgt[0].refcount[0] = 1;
127 if (ret) 125 if (ret)
128 return ret; 126 return ret;
@@ -131,13 +129,13 @@ nv41_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
131} 129}
132 130
133static int 131static int
134nv41_mmu_init(struct nouveau_object *object) 132nv41_mmu_init(struct nvkm_object *object)
135{ 133{
136 struct nv04_mmu_priv *priv = (void *)object; 134 struct nv04_mmu_priv *priv = (void *)object;
137 struct nouveau_gpuobj *dma = priv->vm->pgt[0].obj[0]; 135 struct nvkm_gpuobj *dma = priv->vm->pgt[0].obj[0];
138 int ret; 136 int ret;
139 137
140 ret = nouveau_mmu_init(&priv->base); 138 ret = nvkm_mmu_init(&priv->base);
141 if (ret) 139 if (ret)
142 return ret; 140 return ret;
143 141
@@ -147,13 +145,13 @@ nv41_mmu_init(struct nouveau_object *object)
147 return 0; 145 return 0;
148} 146}
149 147
150struct nouveau_oclass 148struct nvkm_oclass
151nv41_mmu_oclass = { 149nv41_mmu_oclass = {
152 .handle = NV_SUBDEV(MMU, 0x41), 150 .handle = NV_SUBDEV(MMU, 0x41),
153 .ofuncs = &(struct nouveau_ofuncs) { 151 .ofuncs = &(struct nvkm_ofuncs) {
154 .ctor = nv41_mmu_ctor, 152 .ctor = nv41_mmu_ctor,
155 .dtor = nv04_mmu_dtor, 153 .dtor = nv04_mmu_dtor,
156 .init = nv41_mmu_init, 154 .init = nv41_mmu_init,
157 .fini = _nouveau_mmu_fini, 155 .fini = _nvkm_mmu_fini,
158 }, 156 },
159}; 157};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c
index f5319e3e7fe5..b90ded1887aa 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c
@@ -21,14 +21,12 @@
21 * 21 *
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24#include "nv04.h"
24 25
26#include <core/device.h>
25#include <core/gpuobj.h> 27#include <core/gpuobj.h>
26#include <core/option.h> 28#include <core/option.h>
27
28#include <subdev/timer.h> 29#include <subdev/timer.h>
29#include <subdev/mmu.h>
30
31#include "nv04.h"
32 30
33#define NV44_GART_SIZE (512 * 1024 * 1024) 31#define NV44_GART_SIZE (512 * 1024 * 1024)
34#define NV44_GART_PAGE ( 4 * 1024) 32#define NV44_GART_PAGE ( 4 * 1024)
@@ -38,7 +36,7 @@
38 ******************************************************************************/ 36 ******************************************************************************/
39 37
40static void 38static void
41nv44_vm_fill(struct nouveau_gpuobj *pgt, dma_addr_t null, 39nv44_vm_fill(struct nvkm_gpuobj *pgt, dma_addr_t null,
42 dma_addr_t *list, u32 pte, u32 cnt) 40 dma_addr_t *list, u32 pte, u32 cnt)
43{ 41{
44 u32 base = (pte << 2) & ~0x0000000f; 42 u32 base = (pte << 2) & ~0x0000000f;
@@ -84,8 +82,8 @@ nv44_vm_fill(struct nouveau_gpuobj *pgt, dma_addr_t null,
84} 82}
85 83
86static void 84static void
87nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, 85nv44_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
88 struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) 86 struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
89{ 87{
90 struct nv04_mmu_priv *priv = (void *)vma->vm->mmu; 88 struct nv04_mmu_priv *priv = (void *)vma->vm->mmu;
91 u32 tmp[4]; 89 u32 tmp[4];
@@ -115,9 +113,9 @@ nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
115} 113}
116 114
117static void 115static void
118nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) 116nv44_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)
119{ 117{
120 struct nv04_mmu_priv *priv = (void *)nouveau_mmu(pgt); 118 struct nv04_mmu_priv *priv = (void *)nvkm_mmu(pgt);
121 119
122 if (pte & 3) { 120 if (pte & 3) {
123 u32 max = 4 - (pte & 3); 121 u32 max = 4 - (pte & 3);
@@ -140,7 +138,7 @@ nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
140} 138}
141 139
142static void 140static void
143nv44_vm_flush(struct nouveau_vm *vm) 141nv44_vm_flush(struct nvkm_vm *vm)
144{ 142{
145 struct nv04_mmu_priv *priv = (void *)vm->mmu; 143 struct nv04_mmu_priv *priv = (void *)vm->mmu;
146 nv_wr32(priv, 0x100814, priv->base.limit - NV44_GART_PAGE); 144 nv_wr32(priv, 0x100814, priv->base.limit - NV44_GART_PAGE);
@@ -155,22 +153,22 @@ nv44_vm_flush(struct nouveau_vm *vm)
155 ******************************************************************************/ 153 ******************************************************************************/
156 154
157static int 155static int
158nv44_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 156nv44_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
159 struct nouveau_oclass *oclass, void *data, u32 size, 157 struct nvkm_oclass *oclass, void *data, u32 size,
160 struct nouveau_object **pobject) 158 struct nvkm_object **pobject)
161{ 159{
162 struct nouveau_device *device = nv_device(parent); 160 struct nvkm_device *device = nv_device(parent);
163 struct nv04_mmu_priv *priv; 161 struct nv04_mmu_priv *priv;
164 int ret; 162 int ret;
165 163
166 if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) || 164 if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
167 !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) { 165 !nvkm_boolopt(device->cfgopt, "NvPCIE", true)) {
168 return nouveau_object_ctor(parent, engine, &nv04_mmu_oclass, 166 return nvkm_object_ctor(parent, engine, &nv04_mmu_oclass,
169 data, size, pobject); 167 data, size, pobject);
170 } 168 }
171 169
172 ret = nouveau_mmu_create(parent, engine, oclass, "PCIEGART", 170 ret = nvkm_mmu_create(parent, engine, oclass, "PCIEGART",
173 "pciegart", &priv); 171 "pciegart", &priv);
174 *pobject = nv_object(priv); 172 *pobject = nv_object(priv);
175 if (ret) 173 if (ret)
176 return ret; 174 return ret;
@@ -191,15 +189,15 @@ nv44_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
191 return -ENOMEM; 189 return -ENOMEM;
192 } 190 }
193 191
194 ret = nouveau_vm_create(&priv->base, 0, NV44_GART_SIZE, 0, 4096, 192 ret = nvkm_vm_create(&priv->base, 0, NV44_GART_SIZE, 0, 4096,
195 &priv->vm); 193 &priv->vm);
196 if (ret) 194 if (ret)
197 return ret; 195 return ret;
198 196
199 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 197 ret = nvkm_gpuobj_new(nv_object(priv), NULL,
200 (NV44_GART_SIZE / NV44_GART_PAGE) * 4, 198 (NV44_GART_SIZE / NV44_GART_PAGE) * 4,
201 512 * 1024, NVOBJ_FLAG_ZERO_ALLOC, 199 512 * 1024, NVOBJ_FLAG_ZERO_ALLOC,
202 &priv->vm->pgt[0].obj[0]); 200 &priv->vm->pgt[0].obj[0]);
203 priv->vm->pgt[0].refcount[0] = 1; 201 priv->vm->pgt[0].refcount[0] = 1;
204 if (ret) 202 if (ret)
205 return ret; 203 return ret;
@@ -208,14 +206,14 @@ nv44_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
208} 206}
209 207
210static int 208static int
211nv44_mmu_init(struct nouveau_object *object) 209nv44_mmu_init(struct nvkm_object *object)
212{ 210{
213 struct nv04_mmu_priv *priv = (void *)object; 211 struct nv04_mmu_priv *priv = (void *)object;
214 struct nouveau_gpuobj *gart = priv->vm->pgt[0].obj[0]; 212 struct nvkm_gpuobj *gart = priv->vm->pgt[0].obj[0];
215 u32 addr; 213 u32 addr;
216 int ret; 214 int ret;
217 215
218 ret = nouveau_mmu_init(&priv->base); 216 ret = nvkm_mmu_init(&priv->base);
219 if (ret) 217 if (ret)
220 return ret; 218 return ret;
221 219
@@ -237,13 +235,13 @@ nv44_mmu_init(struct nouveau_object *object)
237 return 0; 235 return 0;
238} 236}
239 237
240struct nouveau_oclass 238struct nvkm_oclass
241nv44_mmu_oclass = { 239nv44_mmu_oclass = {
242 .handle = NV_SUBDEV(MMU, 0x44), 240 .handle = NV_SUBDEV(MMU, 0x44),
243 .ofuncs = &(struct nouveau_ofuncs) { 241 .ofuncs = &(struct nvkm_ofuncs) {
244 .ctor = nv44_mmu_ctor, 242 .ctor = nv44_mmu_ctor,
245 .dtor = nv04_mmu_dtor, 243 .dtor = nv04_mmu_dtor,
246 .init = nv44_mmu_init, 244 .init = nv44_mmu_init,
247 .fini = _nouveau_mmu_fini, 245 .fini = _nvkm_mmu_fini,
248 }, 246 },
249}; 247};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
index 70e1a140e7a3..b83550fa7f96 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
@@ -21,22 +21,20 @@
21 * 21 *
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24#include <subdev/mmu.h>
25#include <subdev/bar.h>
26#include <subdev/fb.h>
27#include <subdev/timer.h>
24 28
25#include <core/device.h> 29#include <core/engine.h>
26#include <core/gpuobj.h> 30#include <core/gpuobj.h>
27 31
28#include <subdev/timer.h>
29#include <subdev/fb.h>
30#include <subdev/bar.h>
31#include <subdev/mmu.h>
32
33struct nv50_mmu_priv { 32struct nv50_mmu_priv {
34 struct nouveau_mmu base; 33 struct nvkm_mmu base;
35}; 34};
36 35
37static void 36static void
38nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde, 37nv50_vm_map_pgt(struct nvkm_gpuobj *pgd, u32 pde, struct nvkm_gpuobj *pgt[2])
39 struct nouveau_gpuobj *pgt[2])
40{ 38{
41 u64 phys = 0xdeadcafe00000000ULL; 39 u64 phys = 0xdeadcafe00000000ULL;
42 u32 coverage = 0; 40 u32 coverage = 0;
@@ -64,7 +62,7 @@ nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
64} 62}
65 63
66static inline u64 64static inline u64
67vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) 65vm_addr(struct nvkm_vma *vma, u64 phys, u32 memtype, u32 target)
68{ 66{
69 phys |= 1; /* present */ 67 phys |= 1; /* present */
70 phys |= (u64)memtype << 40; 68 phys |= (u64)memtype << 40;
@@ -77,8 +75,8 @@ vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target)
77} 75}
78 76
79static void 77static void
80nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, 78nv50_vm_map(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
81 struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) 79 struct nvkm_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)
82{ 80{
83 u32 comp = (mem->memtype & 0x180) >> 7; 81 u32 comp = (mem->memtype & 0x180) >> 7;
84 u32 block, target; 82 u32 block, target;
@@ -86,8 +84,8 @@ nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
86 84
87 /* IGPs don't have real VRAM, re-target to stolen system memory */ 85 /* IGPs don't have real VRAM, re-target to stolen system memory */
88 target = 0; 86 target = 0;
89 if (nouveau_fb(vma->vm->mmu)->ram->stolen) { 87 if (nvkm_fb(vma->vm->mmu)->ram->stolen) {
90 phys += nouveau_fb(vma->vm->mmu)->ram->stolen; 88 phys += nvkm_fb(vma->vm->mmu)->ram->stolen;
91 target = 3; 89 target = 3;
92 } 90 }
93 91
@@ -124,8 +122,8 @@ nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
124} 122}
125 123
126static void 124static void
127nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, 125nv50_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
128 struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) 126 struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
129{ 127{
130 u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 3 : 2; 128 u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 3 : 2;
131 pte <<= 3; 129 pte <<= 3;
@@ -138,7 +136,7 @@ nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
138} 136}
139 137
140static void 138static void
141nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) 139nv50_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)
142{ 140{
143 pte <<= 3; 141 pte <<= 3;
144 while (cnt--) { 142 while (cnt--) {
@@ -149,11 +147,11 @@ nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
149} 147}
150 148
151static void 149static void
152nv50_vm_flush(struct nouveau_vm *vm) 150nv50_vm_flush(struct nvkm_vm *vm)
153{ 151{
154 struct nv50_mmu_priv *priv = (void *)vm->mmu; 152 struct nv50_mmu_priv *priv = (void *)vm->mmu;
155 struct nouveau_bar *bar = nouveau_bar(priv); 153 struct nvkm_bar *bar = nvkm_bar(priv);
156 struct nouveau_engine *engine; 154 struct nvkm_engine *engine;
157 int i, vme; 155 int i, vme;
158 156
159 bar->flush(bar); 157 bar->flush(bar);
@@ -164,7 +162,7 @@ nv50_vm_flush(struct nouveau_vm *vm)
164 continue; 162 continue;
165 163
166 /* unfortunate hw bug workaround... */ 164 /* unfortunate hw bug workaround... */
167 engine = nouveau_engine(priv, i); 165 engine = nvkm_engine(priv, i);
168 if (engine && engine->tlb_flush) { 166 if (engine && engine->tlb_flush) {
169 engine->tlb_flush(engine); 167 engine->tlb_flush(engine);
170 continue; 168 continue;
@@ -194,25 +192,25 @@ nv50_vm_flush(struct nouveau_vm *vm)
194} 192}
195 193
196static int 194static int
197nv50_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, 195nv50_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length,
198 u64 mm_offset, struct nouveau_vm **pvm) 196 u64 mm_offset, struct nvkm_vm **pvm)
199{ 197{
200 u32 block = (1 << (mmu->pgt_bits + 12)); 198 u32 block = (1 << (mmu->pgt_bits + 12));
201 if (block > length) 199 if (block > length)
202 block = length; 200 block = length;
203 201
204 return nouveau_vm_create(mmu, offset, length, mm_offset, block, pvm); 202 return nvkm_vm_create(mmu, offset, length, mm_offset, block, pvm);
205} 203}
206 204
207static int 205static int
208nv50_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, 206nv50_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
209 struct nouveau_oclass *oclass, void *data, u32 size, 207 struct nvkm_oclass *oclass, void *data, u32 size,
210 struct nouveau_object **pobject) 208 struct nvkm_object **pobject)
211{ 209{
212 struct nv50_mmu_priv *priv; 210 struct nv50_mmu_priv *priv;
213 int ret; 211 int ret;
214 212
215 ret = nouveau_mmu_create(parent, engine, oclass, "VM", "vm", &priv); 213 ret = nvkm_mmu_create(parent, engine, oclass, "VM", "vm", &priv);
216 *pobject = nv_object(priv); 214 *pobject = nv_object(priv);
217 if (ret) 215 if (ret)
218 return ret; 216 return ret;
@@ -231,13 +229,13 @@ nv50_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
231 return 0; 229 return 0;
232} 230}
233 231
234struct nouveau_oclass 232struct nvkm_oclass
235nv50_mmu_oclass = { 233nv50_mmu_oclass = {
236 .handle = NV_SUBDEV(MMU, 0x50), 234 .handle = NV_SUBDEV(MMU, 0x50),
237 .ofuncs = &(struct nouveau_ofuncs) { 235 .ofuncs = &(struct nvkm_ofuncs) {
238 .ctor = nv50_mmu_ctor, 236 .ctor = nv50_mmu_ctor,
239 .dtor = _nouveau_mmu_dtor, 237 .dtor = _nvkm_mmu_dtor,
240 .init = _nouveau_mmu_init, 238 .init = _nvkm_mmu_init,
241 .fini = _nouveau_mmu_fini, 239 .fini = _nvkm_mmu_fini,
242 }, 240 },
243}; 241};
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-18 14:43:54 -0400