diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2015-01-14 00:08:21 -0500 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2015-01-21 21:17:56 -0500 |
commit | d7e5fcd2e7455094d6f8326b00f70864a700017a (patch) | |
tree | 1a7f69ffb6e3e4038664430a708f323aaf50a520 | |
parent | 2799bba69a1caf54889035ed63247d09c4a2fc84 (diff) |
drm/nouveau/mc: namespace + nvidia gpu names (no binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
20 files changed, 192 insertions, 208 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h index 58f8d8bf2f8e..7894ff57514b 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h | |||
@@ -239,5 +239,6 @@ | |||
239 | #define nouveau_fb_tile nvkm_fb_tile | 239 | #define nouveau_fb_tile nvkm_fb_tile |
240 | #define nvc0_pte_storage_type_map gf100_pte_storage_type_map | 240 | #define nvc0_pte_storage_type_map gf100_pte_storage_type_map |
241 | #define nouveau_fuse nvkm_fuse | 241 | #define nouveau_fuse nvkm_fuse |
242 | #define nouveau_mc nvkm_mc | ||
242 | 243 | ||
243 | #endif | 244 | #endif |
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h index f37fd1a50077..cd5d29fc0565 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h | |||
@@ -28,5 +28,4 @@ nvkm_ltc(void *obj) | |||
28 | extern struct nvkm_oclass *gf100_ltc_oclass; | 28 | extern struct nvkm_oclass *gf100_ltc_oclass; |
29 | extern struct nvkm_oclass *gk104_ltc_oclass; | 29 | extern struct nvkm_oclass *gk104_ltc_oclass; |
30 | extern struct nvkm_oclass *gm107_ltc_oclass; | 30 | extern struct nvkm_oclass *gm107_ltc_oclass; |
31 | |||
32 | #endif | 31 | #endif |
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h index af7926f3a93d..055bea7702a1 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h | |||
@@ -1,31 +1,28 @@ | |||
1 | #ifndef __NOUVEAU_MC_H__ | 1 | #ifndef __NVKM_MC_H__ |
2 | #define __NOUVEAU_MC_H__ | 2 | #define __NVKM_MC_H__ |
3 | |||
4 | #include <core/subdev.h> | 3 | #include <core/subdev.h> |
5 | #include <core/device.h> | ||
6 | 4 | ||
7 | struct nouveau_mc { | 5 | struct nvkm_mc { |
8 | struct nouveau_subdev base; | 6 | struct nvkm_subdev base; |
9 | bool use_msi; | 7 | bool use_msi; |
10 | unsigned int irq; | 8 | unsigned int irq; |
11 | void (*unk260)(struct nouveau_mc *, u32); | 9 | void (*unk260)(struct nvkm_mc *, u32); |
12 | }; | 10 | }; |
13 | 11 | ||
14 | static inline struct nouveau_mc * | 12 | static inline struct nvkm_mc * |
15 | nouveau_mc(void *obj) | 13 | nvkm_mc(void *obj) |
16 | { | 14 | { |
17 | return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_MC); | 15 | return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MC); |
18 | } | 16 | } |
19 | 17 | ||
20 | extern struct nouveau_oclass *nv04_mc_oclass; | 18 | extern struct nvkm_oclass *nv04_mc_oclass; |
21 | extern struct nouveau_oclass *nv40_mc_oclass; | 19 | extern struct nvkm_oclass *nv40_mc_oclass; |
22 | extern struct nouveau_oclass *nv44_mc_oclass; | 20 | extern struct nvkm_oclass *nv44_mc_oclass; |
23 | extern struct nouveau_oclass *nv4c_mc_oclass; | 21 | extern struct nvkm_oclass *nv4c_mc_oclass; |
24 | extern struct nouveau_oclass *nv50_mc_oclass; | 22 | extern struct nvkm_oclass *nv50_mc_oclass; |
25 | extern struct nouveau_oclass *nv94_mc_oclass; | 23 | extern struct nvkm_oclass *g94_mc_oclass; |
26 | extern struct nouveau_oclass *nv98_mc_oclass; | 24 | extern struct nvkm_oclass *g98_mc_oclass; |
27 | extern struct nouveau_oclass *nvc0_mc_oclass; | 25 | extern struct nvkm_oclass *gf100_mc_oclass; |
28 | extern struct nouveau_oclass *nvc3_mc_oclass; | 26 | extern struct nvkm_oclass *gf106_mc_oclass; |
29 | extern struct nouveau_oclass *gk20a_mc_oclass; | 27 | extern struct nvkm_oclass *gk20a_mc_oclass; |
30 | |||
31 | #endif | 28 | #endif |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index 579829a39e25..6183cc372d17 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c | |||
@@ -184,7 +184,7 @@ nv50_identify(struct nouveau_device *device) | |||
184 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; | 184 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
185 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 185 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
186 | device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass; | 186 | device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass; |
187 | device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; | 187 | device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass; |
188 | device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; | 188 | device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; |
189 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 189 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
190 | device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; | 190 | device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; |
@@ -213,7 +213,7 @@ nv50_identify(struct nouveau_device *device) | |||
213 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; | 213 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
214 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 214 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
215 | device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass; | 215 | device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass; |
216 | device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; | 216 | device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass; |
217 | device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; | 217 | device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; |
218 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 218 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
219 | device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; | 219 | device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; |
@@ -242,7 +242,7 @@ nv50_identify(struct nouveau_device *device) | |||
242 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; | 242 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
243 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 243 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
244 | device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass; | 244 | device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass; |
245 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; | 245 | device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; |
246 | device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; | 246 | device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; |
247 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 247 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
248 | device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; | 248 | device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; |
@@ -271,7 +271,7 @@ nv50_identify(struct nouveau_device *device) | |||
271 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; | 271 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
272 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 272 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
273 | device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass; | 273 | device->oclass[NVDEV_SUBDEV_DEVINIT] = g84_devinit_oclass; |
274 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; | 274 | device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; |
275 | device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; | 275 | device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; |
276 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 276 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
277 | device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; | 277 | device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; |
@@ -300,7 +300,7 @@ nv50_identify(struct nouveau_device *device) | |||
300 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; | 300 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
301 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 301 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
302 | device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass; | 302 | device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass; |
303 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; | 303 | device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; |
304 | device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; | 304 | device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; |
305 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 305 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
306 | device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass; | 306 | device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass; |
@@ -329,7 +329,7 @@ nv50_identify(struct nouveau_device *device) | |||
329 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; | 329 | device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; |
330 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 330 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
331 | device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass; | 331 | device->oclass[NVDEV_SUBDEV_DEVINIT] = g98_devinit_oclass; |
332 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; | 332 | device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; |
333 | device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; | 333 | device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; |
334 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 334 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
335 | device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass; | 335 | device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass; |
@@ -358,7 +358,7 @@ nv50_identify(struct nouveau_device *device) | |||
358 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; | 358 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
359 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 359 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
360 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass; | 360 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass; |
361 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; | 361 | device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; |
362 | device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; | 362 | device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; |
363 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 363 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
364 | device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass; | 364 | device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass; |
@@ -389,7 +389,7 @@ nv50_identify(struct nouveau_device *device) | |||
389 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; | 389 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
390 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 390 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
391 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass; | 391 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass; |
392 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; | 392 | device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; |
393 | device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; | 393 | device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; |
394 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 394 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
395 | device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass; | 395 | device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass; |
@@ -419,7 +419,7 @@ nv50_identify(struct nouveau_device *device) | |||
419 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; | 419 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
420 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 420 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
421 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass; | 421 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gt215_devinit_oclass; |
422 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; | 422 | device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; |
423 | device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; | 423 | device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; |
424 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 424 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
425 | device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass; | 425 | device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass; |
@@ -449,7 +449,7 @@ nv50_identify(struct nouveau_device *device) | |||
449 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; | 449 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
450 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 450 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
451 | device->oclass[NVDEV_SUBDEV_DEVINIT] = mcp89_devinit_oclass; | 451 | device->oclass[NVDEV_SUBDEV_DEVINIT] = mcp89_devinit_oclass; |
452 | device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; | 452 | device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; |
453 | device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; | 453 | device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; |
454 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 454 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
455 | device->oclass[NVDEV_SUBDEV_FB ] = mcp89_fb_oclass; | 455 | device->oclass[NVDEV_SUBDEV_FB ] = mcp89_fb_oclass; |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c index fbe552e825b8..2363a583fc3c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c | |||
@@ -69,7 +69,7 @@ nvc0_identify(struct nouveau_device *device) | |||
69 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; | 69 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
70 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 70 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
71 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; | 71 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; |
72 | device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; | 72 | device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; |
73 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; | 73 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; |
74 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 74 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
75 | device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; | 75 | device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; |
@@ -102,7 +102,7 @@ nvc0_identify(struct nouveau_device *device) | |||
102 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; | 102 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
103 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 103 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
104 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; | 104 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; |
105 | device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; | 105 | device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; |
106 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; | 106 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; |
107 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 107 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
108 | device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; | 108 | device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; |
@@ -135,7 +135,7 @@ nvc0_identify(struct nouveau_device *device) | |||
135 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; | 135 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
136 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 136 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
137 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; | 137 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; |
138 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; | 138 | device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; |
139 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; | 139 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; |
140 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 140 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
141 | device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; | 141 | device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; |
@@ -167,7 +167,7 @@ nvc0_identify(struct nouveau_device *device) | |||
167 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; | 167 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
168 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 168 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
169 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; | 169 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; |
170 | device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; | 170 | device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; |
171 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; | 171 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; |
172 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 172 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
173 | device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; | 173 | device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; |
@@ -200,7 +200,7 @@ nvc0_identify(struct nouveau_device *device) | |||
200 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; | 200 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
201 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 201 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
202 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; | 202 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; |
203 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; | 203 | device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; |
204 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; | 204 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; |
205 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 205 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
206 | device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; | 206 | device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; |
@@ -232,7 +232,7 @@ nvc0_identify(struct nouveau_device *device) | |||
232 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; | 232 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
233 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 233 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
234 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; | 234 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; |
235 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; | 235 | device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; |
236 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; | 236 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; |
237 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 237 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
238 | device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; | 238 | device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; |
@@ -264,7 +264,7 @@ nvc0_identify(struct nouveau_device *device) | |||
264 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; | 264 | device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; |
265 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 265 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
266 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; | 266 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; |
267 | device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; | 267 | device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; |
268 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; | 268 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; |
269 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 269 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
270 | device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; | 270 | device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; |
@@ -297,7 +297,7 @@ nvc0_identify(struct nouveau_device *device) | |||
297 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; | 297 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
298 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 298 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
299 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; | 299 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; |
300 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; | 300 | device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; |
301 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; | 301 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; |
302 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 302 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
303 | device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; | 303 | device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; |
@@ -329,7 +329,7 @@ nvc0_identify(struct nouveau_device *device) | |||
329 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; | 329 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
330 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 330 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
331 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; | 331 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; |
332 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; | 332 | device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; |
333 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; | 333 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; |
334 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 334 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
335 | device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; | 335 | device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; |
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c index a9b5aa3d9ed1..9ade56294c38 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c | |||
@@ -69,7 +69,7 @@ nve0_identify(struct nouveau_device *device) | |||
69 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; | 69 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
70 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 70 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
71 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; | 71 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; |
72 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; | 72 | device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; |
73 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; | 73 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; |
74 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 74 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
75 | device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; | 75 | device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; |
@@ -103,7 +103,7 @@ nve0_identify(struct nouveau_device *device) | |||
103 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; | 103 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
104 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 104 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
105 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; | 105 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; |
106 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; | 106 | device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; |
107 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; | 107 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; |
108 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 108 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
109 | device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; | 109 | device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; |
@@ -137,7 +137,7 @@ nve0_identify(struct nouveau_device *device) | |||
137 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; | 137 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
138 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 138 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
139 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; | 139 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; |
140 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; | 140 | device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; |
141 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; | 141 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; |
142 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 142 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
143 | device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; | 143 | device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; |
@@ -193,7 +193,7 @@ nve0_identify(struct nouveau_device *device) | |||
193 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; | 193 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
194 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 194 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
195 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; | 195 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; |
196 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; | 196 | device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; |
197 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; | 197 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; |
198 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 198 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
199 | device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; | 199 | device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; |
@@ -227,7 +227,7 @@ nve0_identify(struct nouveau_device *device) | |||
227 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; | 227 | device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; |
228 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; | 228 | device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; |
229 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; | 229 | device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass; |
230 | device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; | 230 | device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; |
231 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; | 231 | device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; |
232 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; | 232 | device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; |
233 | device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; | 233 | device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; |
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild index 24b589b5001a..721643f04bb5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/Kbuild | |||
@@ -4,8 +4,8 @@ nvkm-y += nvkm/subdev/mc/nv40.o | |||
4 | nvkm-y += nvkm/subdev/mc/nv44.o | 4 | nvkm-y += nvkm/subdev/mc/nv44.o |
5 | nvkm-y += nvkm/subdev/mc/nv4c.o | 5 | nvkm-y += nvkm/subdev/mc/nv4c.o |
6 | nvkm-y += nvkm/subdev/mc/nv50.o | 6 | nvkm-y += nvkm/subdev/mc/nv50.o |
7 | nvkm-y += nvkm/subdev/mc/nv94.o | 7 | nvkm-y += nvkm/subdev/mc/g94.o |
8 | nvkm-y += nvkm/subdev/mc/nv98.o | 8 | nvkm-y += nvkm/subdev/mc/g98.o |
9 | nvkm-y += nvkm/subdev/mc/nvc0.o | 9 | nvkm-y += nvkm/subdev/mc/gf100.o |
10 | nvkm-y += nvkm/subdev/mc/nvc3.o | 10 | nvkm-y += nvkm/subdev/mc/gf106.o |
11 | nvkm-y += nvkm/subdev/mc/gk20a.o | 11 | nvkm-y += nvkm/subdev/mc/gk20a.o |
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c index 25e3b9644a3f..5b051a26653e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c | |||
@@ -21,20 +21,21 @@ | |||
21 | * | 21 | * |
22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
23 | */ | 23 | */ |
24 | |||
25 | #include "priv.h" | 24 | #include "priv.h" |
25 | |||
26 | #include <core/device.h> | ||
26 | #include <core/option.h> | 27 | #include <core/option.h> |
27 | 28 | ||
28 | static inline void | 29 | static inline void |
29 | nouveau_mc_unk260(struct nouveau_mc *pmc, u32 data) | 30 | nvkm_mc_unk260(struct nvkm_mc *pmc, u32 data) |
30 | { | 31 | { |
31 | const struct nouveau_mc_oclass *impl = (void *)nv_oclass(pmc); | 32 | const struct nvkm_mc_oclass *impl = (void *)nv_oclass(pmc); |
32 | if (impl->unk260) | 33 | if (impl->unk260) |
33 | impl->unk260(pmc, data); | 34 | impl->unk260(pmc, data); |
34 | } | 35 | } |
35 | 36 | ||
36 | static inline u32 | 37 | static inline u32 |
37 | nouveau_mc_intr_mask(struct nouveau_mc *pmc) | 38 | nvkm_mc_intr_mask(struct nvkm_mc *pmc) |
38 | { | 39 | { |
39 | u32 intr = nv_rd32(pmc, 0x000100); | 40 | u32 intr = nv_rd32(pmc, 0x000100); |
40 | if (intr == 0xffffffff) /* likely fallen off the bus */ | 41 | if (intr == 0xffffffff) /* likely fallen off the bus */ |
@@ -43,25 +44,25 @@ nouveau_mc_intr_mask(struct nouveau_mc *pmc) | |||
43 | } | 44 | } |
44 | 45 | ||
45 | static irqreturn_t | 46 | static irqreturn_t |
46 | nouveau_mc_intr(int irq, void *arg) | 47 | nvkm_mc_intr(int irq, void *arg) |
47 | { | 48 | { |
48 | struct nouveau_mc *pmc = arg; | 49 | struct nvkm_mc *pmc = arg; |
49 | const struct nouveau_mc_oclass *oclass = (void *)nv_object(pmc)->oclass; | 50 | const struct nvkm_mc_oclass *oclass = (void *)nv_object(pmc)->oclass; |
50 | const struct nouveau_mc_intr *map = oclass->intr; | 51 | const struct nvkm_mc_intr *map = oclass->intr; |
51 | struct nouveau_subdev *unit; | 52 | struct nvkm_subdev *unit; |
52 | u32 intr; | 53 | u32 intr; |
53 | 54 | ||
54 | nv_wr32(pmc, 0x000140, 0x00000000); | 55 | nv_wr32(pmc, 0x000140, 0x00000000); |
55 | nv_rd32(pmc, 0x000140); | 56 | nv_rd32(pmc, 0x000140); |
56 | intr = nouveau_mc_intr_mask(pmc); | 57 | intr = nvkm_mc_intr_mask(pmc); |
57 | if (pmc->use_msi) | 58 | if (pmc->use_msi) |
58 | oclass->msi_rearm(pmc); | 59 | oclass->msi_rearm(pmc); |
59 | 60 | ||
60 | if (intr) { | 61 | if (intr) { |
61 | u32 stat = intr = nouveau_mc_intr_mask(pmc); | 62 | u32 stat = intr = nvkm_mc_intr_mask(pmc); |
62 | while (map->stat) { | 63 | while (map->stat) { |
63 | if (intr & map->stat) { | 64 | if (intr & map->stat) { |
64 | unit = nouveau_subdev(pmc, map->unit); | 65 | unit = nvkm_subdev(pmc, map->unit); |
65 | if (unit && unit->intr) | 66 | if (unit && unit->intr) |
66 | unit->intr(unit); | 67 | unit->intr(unit); |
67 | stat &= ~map->stat; | 68 | stat &= ~map->stat; |
@@ -78,18 +79,18 @@ nouveau_mc_intr(int irq, void *arg) | |||
78 | } | 79 | } |
79 | 80 | ||
80 | int | 81 | int |
81 | _nouveau_mc_fini(struct nouveau_object *object, bool suspend) | 82 | _nvkm_mc_fini(struct nvkm_object *object, bool suspend) |
82 | { | 83 | { |
83 | struct nouveau_mc *pmc = (void *)object; | 84 | struct nvkm_mc *pmc = (void *)object; |
84 | nv_wr32(pmc, 0x000140, 0x00000000); | 85 | nv_wr32(pmc, 0x000140, 0x00000000); |
85 | return nouveau_subdev_fini(&pmc->base, suspend); | 86 | return nvkm_subdev_fini(&pmc->base, suspend); |
86 | } | 87 | } |
87 | 88 | ||
88 | int | 89 | int |
89 | _nouveau_mc_init(struct nouveau_object *object) | 90 | _nvkm_mc_init(struct nvkm_object *object) |
90 | { | 91 | { |
91 | struct nouveau_mc *pmc = (void *)object; | 92 | struct nvkm_mc *pmc = (void *)object; |
92 | int ret = nouveau_subdev_init(&pmc->base); | 93 | int ret = nvkm_subdev_init(&pmc->base); |
93 | if (ret) | 94 | if (ret) |
94 | return ret; | 95 | return ret; |
95 | nv_wr32(pmc, 0x000140, 0x00000001); | 96 | nv_wr32(pmc, 0x000140, 0x00000001); |
@@ -97,32 +98,32 @@ _nouveau_mc_init(struct nouveau_object *object) | |||
97 | } | 98 | } |
98 | 99 | ||
99 | void | 100 | void |
100 | _nouveau_mc_dtor(struct nouveau_object *object) | 101 | _nvkm_mc_dtor(struct nvkm_object *object) |
101 | { | 102 | { |
102 | struct nouveau_device *device = nv_device(object); | 103 | struct nvkm_device *device = nv_device(object); |
103 | struct nouveau_mc *pmc = (void *)object; | 104 | struct nvkm_mc *pmc = (void *)object; |
104 | free_irq(pmc->irq, pmc); | 105 | free_irq(pmc->irq, pmc); |
105 | if (pmc->use_msi) | 106 | if (pmc->use_msi) |
106 | pci_disable_msi(device->pdev); | 107 | pci_disable_msi(device->pdev); |
107 | nouveau_subdev_destroy(&pmc->base); | 108 | nvkm_subdev_destroy(&pmc->base); |
108 | } | 109 | } |
109 | 110 | ||
110 | int | 111 | int |
111 | nouveau_mc_create_(struct nouveau_object *parent, struct nouveau_object *engine, | 112 | nvkm_mc_create_(struct nvkm_object *parent, struct nvkm_object *engine, |
112 | struct nouveau_oclass *bclass, int length, void **pobject) | 113 | struct nvkm_oclass *bclass, int length, void **pobject) |
113 | { | 114 | { |
114 | const struct nouveau_mc_oclass *oclass = (void *)bclass; | 115 | const struct nvkm_mc_oclass *oclass = (void *)bclass; |
115 | struct nouveau_device *device = nv_device(parent); | 116 | struct nvkm_device *device = nv_device(parent); |
116 | struct nouveau_mc *pmc; | 117 | struct nvkm_mc *pmc; |
117 | int ret; | 118 | int ret; |
118 | 119 | ||
119 | ret = nouveau_subdev_create_(parent, engine, bclass, 0, "PMC", | 120 | ret = nvkm_subdev_create_(parent, engine, bclass, 0, "PMC", |
120 | "master", length, pobject); | 121 | "master", length, pobject); |
121 | pmc = *pobject; | 122 | pmc = *pobject; |
122 | if (ret) | 123 | if (ret) |
123 | return ret; | 124 | return ret; |
124 | 125 | ||
125 | pmc->unk260 = nouveau_mc_unk260; | 126 | pmc->unk260 = nvkm_mc_unk260; |
126 | 127 | ||
127 | if (nv_device_is_pci(device)) { | 128 | if (nv_device_is_pci(device)) { |
128 | switch (device->pdev->device & 0x0ff0) { | 129 | switch (device->pdev->device & 0x0ff0) { |
@@ -141,8 +142,8 @@ nouveau_mc_create_(struct nouveau_object *parent, struct nouveau_object *engine, | |||
141 | } | 142 | } |
142 | } | 143 | } |
143 | 144 | ||
144 | pmc->use_msi = nouveau_boolopt(device->cfgopt, "NvMSI", | 145 | pmc->use_msi = nvkm_boolopt(device->cfgopt, "NvMSI", |
145 | pmc->use_msi); | 146 | pmc->use_msi); |
146 | 147 | ||
147 | if (pmc->use_msi && oclass->msi_rearm) { | 148 | if (pmc->use_msi && oclass->msi_rearm) { |
148 | pmc->use_msi = pci_enable_msi(device->pdev) == 0; | 149 | pmc->use_msi = pci_enable_msi(device->pdev) == 0; |
@@ -160,9 +161,7 @@ nouveau_mc_create_(struct nouveau_object *parent, struct nouveau_object *engine, | |||
160 | return ret; | 161 | return ret; |
161 | pmc->irq = ret; | 162 | pmc->irq = ret; |
162 | 163 | ||
163 | ret = request_irq(pmc->irq, nouveau_mc_intr, IRQF_SHARED, "nouveau", | 164 | ret = request_irq(pmc->irq, nvkm_mc_intr, IRQF_SHARED, "nvkm", pmc); |
164 | pmc); | ||
165 | |||
166 | if (ret < 0) | 165 | if (ret < 0) |
167 | return ret; | 166 | return ret; |
168 | 167 | ||
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g94.c index 5f4541105e73..f042e7d8321d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv94.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g94.c | |||
@@ -21,17 +21,16 @@ | |||
21 | * | 21 | * |
22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
23 | */ | 23 | */ |
24 | |||
25 | #include "nv04.h" | 24 | #include "nv04.h" |
26 | 25 | ||
27 | struct nouveau_oclass * | 26 | struct nvkm_oclass * |
28 | nv94_mc_oclass = &(struct nouveau_mc_oclass) { | 27 | g94_mc_oclass = &(struct nvkm_mc_oclass) { |
29 | .base.handle = NV_SUBDEV(MC, 0x94), | 28 | .base.handle = NV_SUBDEV(MC, 0x94), |
30 | .base.ofuncs = &(struct nouveau_ofuncs) { | 29 | .base.ofuncs = &(struct nvkm_ofuncs) { |
31 | .ctor = nv04_mc_ctor, | 30 | .ctor = nv04_mc_ctor, |
32 | .dtor = _nouveau_mc_dtor, | 31 | .dtor = _nvkm_mc_dtor, |
33 | .init = nv50_mc_init, | 32 | .init = nv50_mc_init, |
34 | .fini = _nouveau_mc_fini, | 33 | .fini = _nvkm_mc_fini, |
35 | }, | 34 | }, |
36 | .intr = nv50_mc_intr, | 35 | .intr = nv50_mc_intr, |
37 | .msi_rearm = nv40_mc_msi_rearm, | 36 | .msi_rearm = nv40_mc_msi_rearm, |
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c index 49de0cf57359..8ab7f1272a14 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c | |||
@@ -21,11 +21,10 @@ | |||
21 | * | 21 | * |
22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
23 | */ | 23 | */ |
24 | |||
25 | #include "nv04.h" | 24 | #include "nv04.h" |
26 | 25 | ||
27 | static const struct nouveau_mc_intr | 26 | static const struct nvkm_mc_intr |
28 | nv98_mc_intr[] = { | 27 | g98_mc_intr[] = { |
29 | { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work */ | 28 | { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work */ |
30 | { 0x00000001, NVDEV_ENGINE_MSPPP }, | 29 | { 0x00000001, NVDEV_ENGINE_MSPPP }, |
31 | { 0x00000100, NVDEV_ENGINE_FIFO }, | 30 | { 0x00000100, NVDEV_ENGINE_FIFO }, |
@@ -45,15 +44,15 @@ nv98_mc_intr[] = { | |||
45 | {}, | 44 | {}, |
46 | }; | 45 | }; |
47 | 46 | ||
48 | struct nouveau_oclass * | 47 | struct nvkm_oclass * |
49 | nv98_mc_oclass = &(struct nouveau_mc_oclass) { | 48 | g98_mc_oclass = &(struct nvkm_mc_oclass) { |
50 | .base.handle = NV_SUBDEV(MC, 0x98), | 49 | .base.handle = NV_SUBDEV(MC, 0x98), |
51 | .base.ofuncs = &(struct nouveau_ofuncs) { | 50 | .base.ofuncs = &(struct nvkm_ofuncs) { |
52 | .ctor = nv04_mc_ctor, | 51 | .ctor = nv04_mc_ctor, |
53 | .dtor = _nouveau_mc_dtor, | 52 | .dtor = _nvkm_mc_dtor, |
54 | .init = nv50_mc_init, | 53 | .init = nv50_mc_init, |
55 | .fini = _nouveau_mc_fini, | 54 | .fini = _nvkm_mc_fini, |
56 | }, | 55 | }, |
57 | .intr = nv98_mc_intr, | 56 | .intr = g98_mc_intr, |
58 | .msi_rearm = nv40_mc_msi_rearm, | 57 | .msi_rearm = nv40_mc_msi_rearm, |
59 | }.base; | 58 | }.base; |
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c index a52687a883f0..2425984b045e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c | |||
@@ -21,11 +21,10 @@ | |||
21 | * | 21 | * |
22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
23 | */ | 23 | */ |
24 | |||
25 | #include "nv04.h" | 24 | #include "nv04.h" |
26 | 25 | ||
27 | const struct nouveau_mc_intr | 26 | const struct nvkm_mc_intr |
28 | nvc0_mc_intr[] = { | 27 | gf100_mc_intr[] = { |
29 | { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work. */ | 28 | { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work. */ |
30 | { 0x00000001, NVDEV_ENGINE_MSPPP }, | 29 | { 0x00000001, NVDEV_ENGINE_MSPPP }, |
31 | { 0x00000020, NVDEV_ENGINE_CE0 }, | 30 | { 0x00000020, NVDEV_ENGINE_CE0 }, |
@@ -50,28 +49,28 @@ nvc0_mc_intr[] = { | |||
50 | }; | 49 | }; |
51 | 50 | ||
52 | static void | 51 | static void |
53 | nvc0_mc_msi_rearm(struct nouveau_mc *pmc) | 52 | gf100_mc_msi_rearm(struct nvkm_mc *pmc) |
54 | { | 53 | { |
55 | struct nv04_mc_priv *priv = (void *)pmc; | 54 | struct nv04_mc_priv *priv = (void *)pmc; |
56 | nv_wr32(priv, 0x088704, 0x00000000); | 55 | nv_wr32(priv, 0x088704, 0x00000000); |
57 | } | 56 | } |
58 | 57 | ||
59 | void | 58 | void |
60 | nvc0_mc_unk260(struct nouveau_mc *pmc, u32 data) | 59 | gf100_mc_unk260(struct nvkm_mc *pmc, u32 data) |
61 | { | 60 | { |
62 | nv_wr32(pmc, 0x000260, data); | 61 | nv_wr32(pmc, 0x000260, data); |
63 | } | 62 | } |
64 | 63 | ||
65 | struct nouveau_oclass * | 64 | struct nvkm_oclass * |
66 | nvc0_mc_oclass = &(struct nouveau_mc_oclass) { | 65 | gf100_mc_oclass = &(struct nvkm_mc_oclass) { |
67 | .base.handle = NV_SUBDEV(MC, 0xc0), | 66 | .base.handle = NV_SUBDEV(MC, 0xc0), |
68 | .base.ofuncs = &(struct nouveau_ofuncs) { | 67 | .base.ofuncs = &(struct nvkm_ofuncs) { |
69 | .ctor = nv04_mc_ctor, | 68 | .ctor = nv04_mc_ctor, |
70 | .dtor = _nouveau_mc_dtor, | 69 | .dtor = _nvkm_mc_dtor, |
71 | .init = nv50_mc_init, | 70 | .init = nv50_mc_init, |
72 | .fini = _nouveau_mc_fini, | 71 | .fini = _nvkm_mc_fini, |
73 | }, | 72 | }, |
74 | .intr = nvc0_mc_intr, | 73 | .intr = gf100_mc_intr, |
75 | .msi_rearm = nvc0_mc_msi_rearm, | 74 | .msi_rearm = gf100_mc_msi_rearm, |
76 | .unk260 = nvc0_mc_unk260, | 75 | .unk260 = gf100_mc_unk260, |
77 | }.base; | 76 | }.base; |
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf106.c index 68b5f61aadb5..8d2a8f457778 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc3.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf106.c | |||
@@ -21,19 +21,18 @@ | |||
21 | * | 21 | * |
22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
23 | */ | 23 | */ |
24 | |||
25 | #include "nv04.h" | 24 | #include "nv04.h" |
26 | 25 | ||
27 | struct nouveau_oclass * | 26 | struct nvkm_oclass * |
28 | nvc3_mc_oclass = &(struct nouveau_mc_oclass) { | 27 | gf106_mc_oclass = &(struct nvkm_mc_oclass) { |
29 | .base.handle = NV_SUBDEV(MC, 0xc3), | 28 | .base.handle = NV_SUBDEV(MC, 0xc3), |
30 | .base.ofuncs = &(struct nouveau_ofuncs) { | 29 | .base.ofuncs = &(struct nvkm_ofuncs) { |
31 | .ctor = nv04_mc_ctor, | 30 | .ctor = nv04_mc_ctor, |
32 | .dtor = _nouveau_mc_dtor, | 31 | .dtor = _nvkm_mc_dtor, |
33 | .init = nv50_mc_init, | 32 | .init = nv50_mc_init, |
34 | .fini = _nouveau_mc_fini, | 33 | .fini = _nvkm_mc_fini, |
35 | }, | 34 | }, |
36 | .intr = nvc0_mc_intr, | 35 | .intr = gf100_mc_intr, |
37 | .msi_rearm = nv40_mc_msi_rearm, | 36 | .msi_rearm = nv40_mc_msi_rearm, |
38 | .unk260 = nvc0_mc_unk260, | 37 | .unk260 = gf100_mc_unk260, |
39 | }.base; | 38 | }.base; |
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c index b8d6cb435d0a..43b27742956d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c | |||
@@ -21,18 +21,17 @@ | |||
21 | * | 21 | * |
22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
23 | */ | 23 | */ |
24 | |||
25 | #include "nv04.h" | 24 | #include "nv04.h" |
26 | 25 | ||
27 | struct nouveau_oclass * | 26 | struct nvkm_oclass * |
28 | gk20a_mc_oclass = &(struct nouveau_mc_oclass) { | 27 | gk20a_mc_oclass = &(struct nvkm_mc_oclass) { |
29 | .base.handle = NV_SUBDEV(MC, 0xea), | 28 | .base.handle = NV_SUBDEV(MC, 0xea), |
30 | .base.ofuncs = &(struct nouveau_ofuncs) { | 29 | .base.ofuncs = &(struct nvkm_ofuncs) { |
31 | .ctor = nv04_mc_ctor, | 30 | .ctor = nv04_mc_ctor, |
32 | .dtor = _nouveau_mc_dtor, | 31 | .dtor = _nvkm_mc_dtor, |
33 | .init = nv50_mc_init, | 32 | .init = nv50_mc_init, |
34 | .fini = _nouveau_mc_fini, | 33 | .fini = _nvkm_mc_fini, |
35 | }, | 34 | }, |
36 | .intr = nvc0_mc_intr, | 35 | .intr = gf100_mc_intr, |
37 | .msi_rearm = nv40_mc_msi_rearm, | 36 | .msi_rearm = nv40_mc_msi_rearm, |
38 | }.base; | 37 | }.base; |
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c index 2d787e4dfefa..32713827b4dc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c | |||
@@ -21,10 +21,9 @@ | |||
21 | * | 21 | * |
22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
23 | */ | 23 | */ |
24 | |||
25 | #include "nv04.h" | 24 | #include "nv04.h" |
26 | 25 | ||
27 | const struct nouveau_mc_intr | 26 | const struct nvkm_mc_intr |
28 | nv04_mc_intr[] = { | 27 | nv04_mc_intr[] = { |
29 | { 0x00000001, NVDEV_ENGINE_MPEG }, /* NV17- MPEG/ME */ | 28 | { 0x00000001, NVDEV_ENGINE_MPEG }, /* NV17- MPEG/ME */ |
30 | { 0x00000100, NVDEV_ENGINE_FIFO }, | 29 | { 0x00000100, NVDEV_ENGINE_FIFO }, |
@@ -40,25 +39,25 @@ nv04_mc_intr[] = { | |||
40 | }; | 39 | }; |
41 | 40 | ||
42 | int | 41 | int |
43 | nv04_mc_init(struct nouveau_object *object) | 42 | nv04_mc_init(struct nvkm_object *object) |
44 | { | 43 | { |
45 | struct nv04_mc_priv *priv = (void *)object; | 44 | struct nv04_mc_priv *priv = (void *)object; |
46 | 45 | ||
47 | nv_wr32(priv, 0x000200, 0xffffffff); /* everything enabled */ | 46 | nv_wr32(priv, 0x000200, 0xffffffff); /* everything enabled */ |
48 | nv_wr32(priv, 0x001850, 0x00000001); /* disable rom access */ | 47 | nv_wr32(priv, 0x001850, 0x00000001); /* disable rom access */ |
49 | 48 | ||
50 | return nouveau_mc_init(&priv->base); | 49 | return nvkm_mc_init(&priv->base); |
51 | } | 50 | } |
52 | 51 | ||
53 | int | 52 | int |
54 | nv04_mc_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | 53 | nv04_mc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
55 | struct nouveau_oclass *oclass, void *data, u32 size, | 54 | struct nvkm_oclass *oclass, void *data, u32 size, |
56 | struct nouveau_object **pobject) | 55 | struct nvkm_object **pobject) |
57 | { | 56 | { |
58 | struct nv04_mc_priv *priv; | 57 | struct nv04_mc_priv *priv; |
59 | int ret; | 58 | int ret; |
60 | 59 | ||
61 | ret = nouveau_mc_create(parent, engine, oclass, &priv); | 60 | ret = nvkm_mc_create(parent, engine, oclass, &priv); |
62 | *pobject = nv_object(priv); | 61 | *pobject = nv_object(priv); |
63 | if (ret) | 62 | if (ret) |
64 | return ret; | 63 | return ret; |
@@ -66,14 +65,14 @@ nv04_mc_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
66 | return 0; | 65 | return 0; |
67 | } | 66 | } |
68 | 67 | ||
69 | struct nouveau_oclass * | 68 | struct nvkm_oclass * |
70 | nv04_mc_oclass = &(struct nouveau_mc_oclass) { | 69 | nv04_mc_oclass = &(struct nvkm_mc_oclass) { |
71 | .base.handle = NV_SUBDEV(MC, 0x04), | 70 | .base.handle = NV_SUBDEV(MC, 0x04), |
72 | .base.ofuncs = &(struct nouveau_ofuncs) { | 71 | .base.ofuncs = &(struct nvkm_ofuncs) { |
73 | .ctor = nv04_mc_ctor, | 72 | .ctor = nv04_mc_ctor, |
74 | .dtor = _nouveau_mc_dtor, | 73 | .dtor = _nvkm_mc_dtor, |
75 | .init = nv04_mc_init, | 74 | .init = nv04_mc_init, |
76 | .fini = _nouveau_mc_fini, | 75 | .fini = _nvkm_mc_fini, |
77 | }, | 76 | }, |
78 | .intr = nv04_mc_intr, | 77 | .intr = nv04_mc_intr, |
79 | }.base; | 78 | }.base; |
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.h index 4d9ea46c47c2..411de3d08ab6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.h | |||
@@ -1,22 +1,20 @@ | |||
1 | #ifndef __NVKM_MC_NV04_H__ | 1 | #ifndef __NVKM_MC_NV04_H__ |
2 | #define __NVKM_MC_NV04_H__ | 2 | #define __NVKM_MC_NV04_H__ |
3 | |||
4 | #include "priv.h" | 3 | #include "priv.h" |
5 | 4 | ||
6 | struct nv04_mc_priv { | 5 | struct nv04_mc_priv { |
7 | struct nouveau_mc base; | 6 | struct nvkm_mc base; |
8 | }; | 7 | }; |
9 | 8 | ||
10 | int nv04_mc_ctor(struct nouveau_object *, struct nouveau_object *, | 9 | int nv04_mc_ctor(struct nvkm_object *, struct nvkm_object *, |
11 | struct nouveau_oclass *, void *, u32, | 10 | struct nvkm_oclass *, void *, u32, |
12 | struct nouveau_object **); | 11 | struct nvkm_object **); |
13 | |||
14 | extern const struct nouveau_mc_intr nv04_mc_intr[]; | ||
15 | int nv04_mc_init(struct nouveau_object *); | ||
16 | void nv40_mc_msi_rearm(struct nouveau_mc *); | ||
17 | int nv44_mc_init(struct nouveau_object *object); | ||
18 | int nv50_mc_init(struct nouveau_object *); | ||
19 | extern const struct nouveau_mc_intr nv50_mc_intr[]; | ||
20 | extern const struct nouveau_mc_intr nvc0_mc_intr[]; | ||
21 | 12 | ||
13 | extern const struct nvkm_mc_intr nv04_mc_intr[]; | ||
14 | int nv04_mc_init(struct nvkm_object *); | ||
15 | void nv40_mc_msi_rearm(struct nvkm_mc *); | ||
16 | int nv44_mc_init(struct nvkm_object *object); | ||
17 | int nv50_mc_init(struct nvkm_object *); | ||
18 | extern const struct nvkm_mc_intr nv50_mc_intr[]; | ||
19 | extern const struct nvkm_mc_intr gf100_mc_intr[]; | ||
22 | #endif | 20 | #endif |
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv40.c index 5b1faecfed2d..b7613059da08 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv40.c | |||
@@ -21,24 +21,23 @@ | |||
21 | * | 21 | * |
22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
23 | */ | 23 | */ |
24 | |||
25 | #include "nv04.h" | 24 | #include "nv04.h" |
26 | 25 | ||
27 | void | 26 | void |
28 | nv40_mc_msi_rearm(struct nouveau_mc *pmc) | 27 | nv40_mc_msi_rearm(struct nvkm_mc *pmc) |
29 | { | 28 | { |
30 | struct nv04_mc_priv *priv = (void *)pmc; | 29 | struct nv04_mc_priv *priv = (void *)pmc; |
31 | nv_wr08(priv, 0x088068, 0xff); | 30 | nv_wr08(priv, 0x088068, 0xff); |
32 | } | 31 | } |
33 | 32 | ||
34 | struct nouveau_oclass * | 33 | struct nvkm_oclass * |
35 | nv40_mc_oclass = &(struct nouveau_mc_oclass) { | 34 | nv40_mc_oclass = &(struct nvkm_mc_oclass) { |
36 | .base.handle = NV_SUBDEV(MC, 0x40), | 35 | .base.handle = NV_SUBDEV(MC, 0x40), |
37 | .base.ofuncs = &(struct nouveau_ofuncs) { | 36 | .base.ofuncs = &(struct nvkm_ofuncs) { |
38 | .ctor = nv04_mc_ctor, | 37 | .ctor = nv04_mc_ctor, |
39 | .dtor = _nouveau_mc_dtor, | 38 | .dtor = _nvkm_mc_dtor, |
40 | .init = nv04_mc_init, | 39 | .init = nv04_mc_init, |
41 | .fini = _nouveau_mc_fini, | 40 | .fini = _nvkm_mc_fini, |
42 | }, | 41 | }, |
43 | .intr = nv04_mc_intr, | 42 | .intr = nv04_mc_intr, |
44 | .msi_rearm = nv40_mc_msi_rearm, | 43 | .msi_rearm = nv40_mc_msi_rearm, |
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c index cc4d0d2d886e..2c7f7c701a2b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c | |||
@@ -21,11 +21,10 @@ | |||
21 | * | 21 | * |
22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
23 | */ | 23 | */ |
24 | |||
25 | #include "nv04.h" | 24 | #include "nv04.h" |
26 | 25 | ||
27 | int | 26 | int |
28 | nv44_mc_init(struct nouveau_object *object) | 27 | nv44_mc_init(struct nvkm_object *object) |
29 | { | 28 | { |
30 | struct nv04_mc_priv *priv = (void *)object; | 29 | struct nv04_mc_priv *priv = (void *)object; |
31 | u32 tmp = nv_rd32(priv, 0x10020c); | 30 | u32 tmp = nv_rd32(priv, 0x10020c); |
@@ -37,17 +36,17 @@ nv44_mc_init(struct nouveau_object *object) | |||
37 | nv_wr32(priv, 0x001708, 0); | 36 | nv_wr32(priv, 0x001708, 0); |
38 | nv_wr32(priv, 0x00170c, tmp); | 37 | nv_wr32(priv, 0x00170c, tmp); |
39 | 38 | ||
40 | return nouveau_mc_init(&priv->base); | 39 | return nvkm_mc_init(&priv->base); |
41 | } | 40 | } |
42 | 41 | ||
43 | struct nouveau_oclass * | 42 | struct nvkm_oclass * |
44 | nv44_mc_oclass = &(struct nouveau_mc_oclass) { | 43 | nv44_mc_oclass = &(struct nvkm_mc_oclass) { |
45 | .base.handle = NV_SUBDEV(MC, 0x44), | 44 | .base.handle = NV_SUBDEV(MC, 0x44), |
46 | .base.ofuncs = &(struct nouveau_ofuncs) { | 45 | .base.ofuncs = &(struct nvkm_ofuncs) { |
47 | .ctor = nv04_mc_ctor, | 46 | .ctor = nv04_mc_ctor, |
48 | .dtor = _nouveau_mc_dtor, | 47 | .dtor = _nvkm_mc_dtor, |
49 | .init = nv44_mc_init, | 48 | .init = nv44_mc_init, |
50 | .fini = _nouveau_mc_fini, | 49 | .fini = _nvkm_mc_fini, |
51 | }, | 50 | }, |
52 | .intr = nv04_mc_intr, | 51 | .intr = nv04_mc_intr, |
53 | .msi_rearm = nv40_mc_msi_rearm, | 52 | .msi_rearm = nv40_mc_msi_rearm, |
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv4c.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv4c.c index 165401c4045c..c0aac7e20d45 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv4c.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv4c.c | |||
@@ -21,17 +21,16 @@ | |||
21 | * | 21 | * |
22 | * Authors: Ilia Mirkin | 22 | * Authors: Ilia Mirkin |
23 | */ | 23 | */ |
24 | |||
25 | #include "nv04.h" | 24 | #include "nv04.h" |
26 | 25 | ||
27 | struct nouveau_oclass * | 26 | struct nvkm_oclass * |
28 | nv4c_mc_oclass = &(struct nouveau_mc_oclass) { | 27 | nv4c_mc_oclass = &(struct nvkm_mc_oclass) { |
29 | .base.handle = NV_SUBDEV(MC, 0x4c), | 28 | .base.handle = NV_SUBDEV(MC, 0x4c), |
30 | .base.ofuncs = &(struct nouveau_ofuncs) { | 29 | .base.ofuncs = &(struct nvkm_ofuncs) { |
31 | .ctor = nv04_mc_ctor, | 30 | .ctor = nv04_mc_ctor, |
32 | .dtor = _nouveau_mc_dtor, | 31 | .dtor = _nvkm_mc_dtor, |
33 | .init = nv44_mc_init, | 32 | .init = nv44_mc_init, |
34 | .fini = _nouveau_mc_fini, | 33 | .fini = _nvkm_mc_fini, |
35 | }, | 34 | }, |
36 | .intr = nv04_mc_intr, | 35 | .intr = nv04_mc_intr, |
37 | }.base; | 36 | }.base; |
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c index 9100f2875636..40e3019e1fde 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c | |||
@@ -21,10 +21,11 @@ | |||
21 | * | 21 | * |
22 | * Authors: Ben Skeggs | 22 | * Authors: Ben Skeggs |
23 | */ | 23 | */ |
24 | |||
25 | #include "nv04.h" | 24 | #include "nv04.h" |
26 | 25 | ||
27 | const struct nouveau_mc_intr | 26 | #include <core/device.h> |
27 | |||
28 | const struct nvkm_mc_intr | ||
28 | nv50_mc_intr[] = { | 29 | nv50_mc_intr[] = { |
29 | { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP before FIFO, so pageflip-timestamping works! */ | 30 | { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP before FIFO, so pageflip-timestamping works! */ |
30 | { 0x00000001, NVDEV_ENGINE_MPEG }, | 31 | { 0x00000001, NVDEV_ENGINE_MPEG }, |
@@ -43,28 +44,28 @@ nv50_mc_intr[] = { | |||
43 | }; | 44 | }; |
44 | 45 | ||
45 | static void | 46 | static void |
46 | nv50_mc_msi_rearm(struct nouveau_mc *pmc) | 47 | nv50_mc_msi_rearm(struct nvkm_mc *pmc) |
47 | { | 48 | { |
48 | struct nouveau_device *device = nv_device(pmc); | 49 | struct nvkm_device *device = nv_device(pmc); |
49 | pci_write_config_byte(device->pdev, 0x68, 0xff); | 50 | pci_write_config_byte(device->pdev, 0x68, 0xff); |
50 | } | 51 | } |
51 | 52 | ||
52 | int | 53 | int |
53 | nv50_mc_init(struct nouveau_object *object) | 54 | nv50_mc_init(struct nvkm_object *object) |
54 | { | 55 | { |
55 | struct nv04_mc_priv *priv = (void *)object; | 56 | struct nv04_mc_priv *priv = (void *)object; |
56 | nv_wr32(priv, 0x000200, 0xffffffff); /* everything on */ | 57 | nv_wr32(priv, 0x000200, 0xffffffff); /* everything on */ |
57 | return nouveau_mc_init(&priv->base); | 58 | return nvkm_mc_init(&priv->base); |
58 | } | 59 | } |
59 | 60 | ||
60 | struct nouveau_oclass * | 61 | struct nvkm_oclass * |
61 | nv50_mc_oclass = &(struct nouveau_mc_oclass) { | 62 | nv50_mc_oclass = &(struct nvkm_mc_oclass) { |
62 | .base.handle = NV_SUBDEV(MC, 0x50), | 63 | .base.handle = NV_SUBDEV(MC, 0x50), |
63 | .base.ofuncs = &(struct nouveau_ofuncs) { | 64 | .base.ofuncs = &(struct nvkm_ofuncs) { |
64 | .ctor = nv04_mc_ctor, | 65 | .ctor = nv04_mc_ctor, |
65 | .dtor = _nouveau_mc_dtor, | 66 | .dtor = _nvkm_mc_dtor, |
66 | .init = nv50_mc_init, | 67 | .init = nv50_mc_init, |
67 | .fini = _nouveau_mc_fini, | 68 | .fini = _nvkm_mc_fini, |
68 | }, | 69 | }, |
69 | .intr = nv50_mc_intr, | 70 | .intr = nv50_mc_intr, |
70 | .msi_rearm = nv50_mc_msi_rearm, | 71 | .msi_rearm = nv50_mc_msi_rearm, |
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h index 911e66392587..d2cad07afd1a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h | |||
@@ -1,38 +1,36 @@ | |||
1 | #ifndef __NVKM_MC_PRIV_H__ | 1 | #ifndef __NVKM_MC_PRIV_H__ |
2 | #define __NVKM_MC_PRIV_H__ | 2 | #define __NVKM_MC_PRIV_H__ |
3 | |||
4 | #include <subdev/mc.h> | 3 | #include <subdev/mc.h> |
5 | 4 | ||
6 | #define nouveau_mc_create(p,e,o,d) \ | 5 | #define nvkm_mc_create(p,e,o,d) \ |
7 | nouveau_mc_create_((p), (e), (o), sizeof(**d), (void **)d) | 6 | nvkm_mc_create_((p), (e), (o), sizeof(**d), (void **)d) |
8 | #define nouveau_mc_destroy(p) ({ \ | 7 | #define nvkm_mc_destroy(p) ({ \ |
9 | struct nouveau_mc *pmc = (p); _nouveau_mc_dtor(nv_object(pmc)); \ | 8 | struct nvkm_mc *pmc = (p); _nvkm_mc_dtor(nv_object(pmc)); \ |
10 | }) | 9 | }) |
11 | #define nouveau_mc_init(p) ({ \ | 10 | #define nvkm_mc_init(p) ({ \ |
12 | struct nouveau_mc *pmc = (p); _nouveau_mc_init(nv_object(pmc)); \ | 11 | struct nvkm_mc *pmc = (p); _nvkm_mc_init(nv_object(pmc)); \ |
13 | }) | 12 | }) |
14 | #define nouveau_mc_fini(p,s) ({ \ | 13 | #define nvkm_mc_fini(p,s) ({ \ |
15 | struct nouveau_mc *pmc = (p); _nouveau_mc_fini(nv_object(pmc), (s)); \ | 14 | struct nvkm_mc *pmc = (p); _nvkm_mc_fini(nv_object(pmc), (s)); \ |
16 | }) | 15 | }) |
17 | 16 | ||
18 | int nouveau_mc_create_(struct nouveau_object *, struct nouveau_object *, | 17 | int nvkm_mc_create_(struct nvkm_object *, struct nvkm_object *, |
19 | struct nouveau_oclass *, int, void **); | 18 | struct nvkm_oclass *, int, void **); |
20 | void _nouveau_mc_dtor(struct nouveau_object *); | 19 | void _nvkm_mc_dtor(struct nvkm_object *); |
21 | int _nouveau_mc_init(struct nouveau_object *); | 20 | int _nvkm_mc_init(struct nvkm_object *); |
22 | int _nouveau_mc_fini(struct nouveau_object *, bool); | 21 | int _nvkm_mc_fini(struct nvkm_object *, bool); |
23 | 22 | ||
24 | struct nouveau_mc_intr { | 23 | struct nvkm_mc_intr { |
25 | u32 stat; | 24 | u32 stat; |
26 | u32 unit; | 25 | u32 unit; |
27 | }; | 26 | }; |
28 | 27 | ||
29 | struct nouveau_mc_oclass { | 28 | struct nvkm_mc_oclass { |
30 | struct nouveau_oclass base; | 29 | struct nvkm_oclass base; |
31 | const struct nouveau_mc_intr *intr; | 30 | const struct nvkm_mc_intr *intr; |
32 | void (*msi_rearm)(struct nouveau_mc *); | 31 | void (*msi_rearm)(struct nvkm_mc *); |
33 | void (*unk260)(struct nouveau_mc *, u32); | 32 | void (*unk260)(struct nvkm_mc *, u32); |
34 | }; | 33 | }; |
35 | 34 | ||
36 | void nvc0_mc_unk260(struct nouveau_mc *, u32); | 35 | void gf100_mc_unk260(struct nvkm_mc *, u32); |
37 | |||
38 | #endif | 36 | #endif |