drm/msm: add register definitions for gpu

Generated from rnndb files in:

https://github.com/freedreno/envytools

Keep this split out as a separate commit to make it easier to review the
actual driver.

Signed-off-by: Rob Clark <robdclark@gmail.com>

4 files changed, 4317 insertions, 0 deletions

diff --git a/drivers/gpu/drm/msm/adreno/a2xx.xml.h b/drivers/gpu/drm/msm/adreno/a2xx.xml.h
new file mode 100644
index 000000000000..35463864b959
--- /dev/null
+++ b/drivers/gpu/drm/msm/adreno/a2xx.xml.h
@@ -0,0 +1,1438 @@
+#ifndef A2XX_XML
+#define A2XX_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml              (    327 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
+- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml           (  30005 bytes, from 2013-07-19 21:30:48)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml       (   8983 bytes, from 2013-07-24 01:38:36)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml          (   9712 bytes, from 2013-05-26 15:22:37)
+- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml           (  51415 bytes, from 2013-08-03 14:26:05)
+
+Copyright (C) 2013 by the following authors:
+- Rob Clark <robdclark@gmail.com> (robclark)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+enum a2xx_rb_dither_type {
+        DITHER_PIXEL = 0,
+        DITHER_SUBPIXEL = 1,
+};
+
+enum a2xx_colorformatx {
+        COLORX_4_4_4_4 = 0,
+        COLORX_1_5_5_5 = 1,
+        COLORX_5_6_5 = 2,
+        COLORX_8 = 3,
+        COLORX_8_8 = 4,
+        COLORX_8_8_8_8 = 5,
+        COLORX_S8_8_8_8 = 6,
+        COLORX_16_FLOAT = 7,
+        COLORX_16_16_FLOAT = 8,
+        COLORX_16_16_16_16_FLOAT = 9,
+        COLORX_32_FLOAT = 10,
+        COLORX_32_32_FLOAT = 11,
+        COLORX_32_32_32_32_FLOAT = 12,
+        COLORX_2_3_3 = 13,
+        COLORX_8_8_8 = 14,
+};
+
+enum a2xx_sq_surfaceformat {
+        FMT_1_REVERSE = 0,
+        FMT_1 = 1,
+        FMT_8 = 2,
+        FMT_1_5_5_5 = 3,
+        FMT_5_6_5 = 4,
+        FMT_6_5_5 = 5,
+        FMT_8_8_8_8 = 6,
+        FMT_2_10_10_10 = 7,
+        FMT_8_A = 8,
+        FMT_8_B = 9,
+        FMT_8_8 = 10,
+        FMT_Cr_Y1_Cb_Y0 = 11,
+        FMT_Y1_Cr_Y0_Cb = 12,
+        FMT_5_5_5_1 = 13,
+        FMT_8_8_8_8_A = 14,
+        FMT_4_4_4_4 = 15,
+        FMT_10_11_11 = 16,
+        FMT_11_11_10 = 17,
+        FMT_DXT1 = 18,
+        FMT_DXT2_3 = 19,
+        FMT_DXT4_5 = 20,
+        FMT_24_8 = 22,
+        FMT_24_8_FLOAT = 23,
+        FMT_16 = 24,
+        FMT_16_16 = 25,
+        FMT_16_16_16_16 = 26,
+        FMT_16_EXPAND = 27,
+        FMT_16_16_EXPAND = 28,
+        FMT_16_16_16_16_EXPAND = 29,
+        FMT_16_FLOAT = 30,
+        FMT_16_16_FLOAT = 31,
+        FMT_16_16_16_16_FLOAT = 32,
+        FMT_32 = 33,
+        FMT_32_32 = 34,
+        FMT_32_32_32_32 = 35,
+        FMT_32_FLOAT = 36,
+        FMT_32_32_FLOAT = 37,
+        FMT_32_32_32_32_FLOAT = 38,
+        FMT_32_AS_8 = 39,
+        FMT_32_AS_8_8 = 40,
+        FMT_16_MPEG = 41,
+        FMT_16_16_MPEG = 42,
+        FMT_8_INTERLACED = 43,
+        FMT_32_AS_8_INTERLACED = 44,
+        FMT_32_AS_8_8_INTERLACED = 45,
+        FMT_16_INTERLACED = 46,
+        FMT_16_MPEG_INTERLACED = 47,
+        FMT_16_16_MPEG_INTERLACED = 48,
+        FMT_DXN = 49,
+        FMT_8_8_8_8_AS_16_16_16_16 = 50,
+        FMT_DXT1_AS_16_16_16_16 = 51,
+        FMT_DXT2_3_AS_16_16_16_16 = 52,
+        FMT_DXT4_5_AS_16_16_16_16 = 53,
+        FMT_2_10_10_10_AS_16_16_16_16 = 54,
+        FMT_10_11_11_AS_16_16_16_16 = 55,
+        FMT_11_11_10_AS_16_16_16_16 = 56,
+        FMT_32_32_32_FLOAT = 57,
+        FMT_DXT3A = 58,
+        FMT_DXT5A = 59,
+        FMT_CTX1 = 60,
+        FMT_DXT3A_AS_1_1_1_1 = 61,
+};
+
+enum a2xx_sq_ps_vtx_mode {
+        POSITION_1_VECTOR = 0,
+        POSITION_2_VECTORS_UNUSED = 1,
+        POSITION_2_VECTORS_SPRITE = 2,
+        POSITION_2_VECTORS_EDGE = 3,
+        POSITION_2_VECTORS_KILL = 4,
+        POSITION_2_VECTORS_SPRITE_KILL = 5,
+        POSITION_2_VECTORS_EDGE_KILL = 6,
+        MULTIPASS = 7,
+};
+
+enum a2xx_sq_sample_cntl {
+        CENTROIDS_ONLY = 0,
+        CENTERS_ONLY = 1,
+        CENTROIDS_AND_CENTERS = 2,
+};
+
+enum a2xx_dx_clip_space {
+        DXCLIP_OPENGL = 0,
+        DXCLIP_DIRECTX = 1,
+};
+
+enum a2xx_pa_su_sc_polymode {
+        POLY_DISABLED = 0,
+        POLY_DUALMODE = 1,
+};
+
+enum a2xx_rb_edram_mode {
+        EDRAM_NOP = 0,
+        COLOR_DEPTH = 4,
+        DEPTH_ONLY = 5,
+        EDRAM_COPY = 6,
+};
+
+enum a2xx_pa_sc_pattern_bit_order {
+        LITTLE = 0,
+        BIG = 1,
+};
+
+enum a2xx_pa_sc_auto_reset_cntl {
+        NEVER = 0,
+        EACH_PRIMITIVE = 1,
+        EACH_PACKET = 2,
+};
+
+enum a2xx_pa_pixcenter {
+        PIXCENTER_D3D = 0,
+        PIXCENTER_OGL = 1,
+};
+
+enum a2xx_pa_roundmode {
+        TRUNCATE = 0,
+        ROUND = 1,
+        ROUNDTOEVEN = 2,
+        ROUNDTOODD = 3,
+};
+
+enum a2xx_pa_quantmode {
+        ONE_SIXTEENTH = 0,
+        ONE_EIGTH = 1,
+        ONE_QUARTER = 2,
+        ONE_HALF = 3,
+        ONE = 4,
+};
+
+enum a2xx_rb_copy_sample_select {
+        SAMPLE_0 = 0,
+        SAMPLE_1 = 1,
+        SAMPLE_2 = 2,
+        SAMPLE_3 = 3,
+        SAMPLE_01 = 4,
+        SAMPLE_23 = 5,
+        SAMPLE_0123 = 6,
+};
+
+enum sq_tex_clamp {
+        SQ_TEX_WRAP = 0,
+        SQ_TEX_MIRROR = 1,
+        SQ_TEX_CLAMP_LAST_TEXEL = 2,
+        SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3,
+        SQ_TEX_CLAMP_HALF_BORDER = 4,
+        SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5,
+        SQ_TEX_CLAMP_BORDER = 6,
+        SQ_TEX_MIRROR_ONCE_BORDER = 7,
+};
+
+enum sq_tex_swiz {
+        SQ_TEX_X = 0,
+        SQ_TEX_Y = 1,
+        SQ_TEX_Z = 2,
+        SQ_TEX_W = 3,
+        SQ_TEX_ZERO = 4,
+        SQ_TEX_ONE = 5,
+};
+
+enum sq_tex_filter {
+        SQ_TEX_FILTER_POINT = 0,
+        SQ_TEX_FILTER_BILINEAR = 1,
+        SQ_TEX_FILTER_BICUBIC = 2,
+};
+
+#define REG_A2XX_RBBM_PATCH_RELEASE                             0x00000001
+
+#define REG_A2XX_RBBM_CNTL                                      0x0000003b
+
+#define REG_A2XX_RBBM_SOFT_RESET                                0x0000003c
+
+#define REG_A2XX_CP_PFP_UCODE_ADDR                              0x000000c0
+
+#define REG_A2XX_CP_PFP_UCODE_DATA                              0x000000c1
+
+#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT                       0x00000395
+
+#define REG_A2XX_RBBM_PERFCOUNTER1_LO                           0x00000397
+
+#define REG_A2XX_RBBM_PERFCOUNTER1_HI                           0x00000398
+
+#define REG_A2XX_RBBM_DEBUG                                     0x0000039b
+
+#define REG_A2XX_RBBM_PM_OVERRIDE1                              0x0000039c
+
+#define REG_A2XX_RBBM_PM_OVERRIDE2                              0x0000039d
+
+#define REG_A2XX_RBBM_DEBUG_OUT                                 0x000003a0
+
+#define REG_A2XX_RBBM_DEBUG_CNTL                                0x000003a1
+
+#define REG_A2XX_RBBM_READ_ERROR                                0x000003b3
+
+#define REG_A2XX_RBBM_INT_CNTL                                  0x000003b4
+
+#define REG_A2XX_RBBM_INT_STATUS                                0x000003b5
+
+#define REG_A2XX_RBBM_INT_ACK                                   0x000003b6
+
+#define REG_A2XX_MASTER_INT_SIGNAL                              0x000003b7
+
+#define REG_A2XX_RBBM_PERIPHID1                                 0x000003f9
+
+#define REG_A2XX_RBBM_PERIPHID2                                 0x000003fa
+
+#define REG_A2XX_CP_PERFMON_CNTL                                0x00000444
+
+#define REG_A2XX_CP_PERFCOUNTER_SELECT                          0x00000445
+
+#define REG_A2XX_CP_PERFCOUNTER_LO                              0x00000446
+
+#define REG_A2XX_CP_PERFCOUNTER_HI                              0x00000447
+
+#define REG_A2XX_CP_ST_BASE                                     0x0000044d
+
+#define REG_A2XX_CP_ST_BUFSZ                                    0x0000044e
+
+#define REG_A2XX_CP_IB1_BASE                                    0x00000458
+
+#define REG_A2XX_CP_IB1_BUFSZ                                   0x00000459
+
+#define REG_A2XX_CP_IB2_BASE                                    0x0000045a
+
+#define REG_A2XX_CP_IB2_BUFSZ                                   0x0000045b
+
+#define REG_A2XX_CP_STAT                                        0x0000047f
+
+#define REG_A2XX_RBBM_STATUS                                    0x000005d0
+#define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK                    0x0000001f
+#define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT                   0
+static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val)
+{
+        return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK;
+}
+#define A2XX_RBBM_STATUS_TC_BUSY                                0x00000020
+#define A2XX_RBBM_STATUS_HIRQ_PENDING                           0x00000100
+#define A2XX_RBBM_STATUS_CPRQ_PENDING                           0x00000200
+#define A2XX_RBBM_STATUS_CFRQ_PENDING                           0x00000400
+#define A2XX_RBBM_STATUS_PFRQ_PENDING                           0x00000800
+#define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA                        0x00001000
+#define A2XX_RBBM_STATUS_RBBM_WU_BUSY                           0x00004000
+#define A2XX_RBBM_STATUS_CP_NRT_BUSY                            0x00010000
+#define A2XX_RBBM_STATUS_MH_BUSY                                0x00040000
+#define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY                      0x00080000
+#define A2XX_RBBM_STATUS_SX_BUSY                                0x00200000
+#define A2XX_RBBM_STATUS_TPC_BUSY                               0x00400000
+#define A2XX_RBBM_STATUS_SC_CNTX_BUSY                           0x01000000
+#define A2XX_RBBM_STATUS_PA_BUSY                                0x02000000
+#define A2XX_RBBM_STATUS_VGT_BUSY                               0x04000000
+#define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY                         0x08000000
+#define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY                          0x10000000
+#define A2XX_RBBM_STATUS_RB_CNTX_BUSY                           0x40000000
+#define A2XX_RBBM_STATUS_GUI_ACTIVE                             0x80000000
+
+#define REG_A2XX_A220_VSC_BIN_SIZE                              0x00000c01
+#define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK                      0x0000001f
+#define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT                     0
+static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val)
+{
+        return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK;
+}
+#define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK                     0x000003e0
+#define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT                    5
+static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val)
+{
+        return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK;
+}
+
+static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
+
+static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
+
+static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; }
+
+static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }
+
+#define REG_A2XX_PC_DEBUG_CNTL                                  0x00000c38
+
+#define REG_A2XX_PC_DEBUG_DATA                                  0x00000c39
+
+#define REG_A2XX_PA_SC_VIZ_QUERY_STATUS                         0x00000c44
+
+#define REG_A2XX_GRAS_DEBUG_CNTL                                0x00000c80
+
+#define REG_A2XX_PA_SU_DEBUG_CNTL                               0x00000c80
+
+#define REG_A2XX_GRAS_DEBUG_DATA                                0x00000c81
+
+#define REG_A2XX_PA_SU_DEBUG_DATA                               0x00000c81
+
+#define REG_A2XX_PA_SU_FACE_DATA                                0x00000c86
+
+#define REG_A2XX_SQ_GPR_MANAGEMENT                              0x00000d00
+
+#define REG_A2XX_SQ_FLOW_CONTROL                                0x00000d01
+
+#define REG_A2XX_SQ_INST_STORE_MANAGMENT                        0x00000d02
+
+#define REG_A2XX_SQ_DEBUG_MISC                                  0x00000d05
+
+#define REG_A2XX_SQ_INT_CNTL                                    0x00000d34
+
+#define REG_A2XX_SQ_INT_STATUS                                  0x00000d35
+
+#define REG_A2XX_SQ_INT_ACK                                     0x00000d36
+
+#define REG_A2XX_SQ_DEBUG_INPUT_FSM                             0x00000dae
+
+#define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM                         0x00000daf
+
+#define REG_A2XX_SQ_DEBUG_TP_FSM                                0x00000db0
+
+#define REG_A2XX_SQ_DEBUG_FSM_ALU_0                             0x00000db1
+
+#define REG_A2XX_SQ_DEBUG_FSM_ALU_1                             0x00000db2
+
+#define REG_A2XX_SQ_DEBUG_EXP_ALLOC                             0x00000db3
+
+#define REG_A2XX_SQ_DEBUG_PTR_BUFF                              0x00000db4
+
+#define REG_A2XX_SQ_DEBUG_GPR_VTX                               0x00000db5
+
+#define REG_A2XX_SQ_DEBUG_GPR_PIX                               0x00000db6
+
+#define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL                         0x00000db7
+
+#define REG_A2XX_SQ_DEBUG_VTX_TB_0                              0x00000db8
+
+#define REG_A2XX_SQ_DEBUG_VTX_TB_1                              0x00000db9
+
+#define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG                     0x00000dba
+
+#define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM                      0x00000dbb
+
+#define REG_A2XX_SQ_DEBUG_PIX_TB_0                              0x00000dbc
+
+#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0                   0x00000dbd
+
+#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1                   0x00000dbe
+
+#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2                   0x00000dbf
+
+#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3                   0x00000dc0
+
+#define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM                      0x00000dc1
+
+#define REG_A2XX_TC_CNTL_STATUS                                 0x00000e00
+#define A2XX_TC_CNTL_STATUS_L2_INVALIDATE                       0x00000001
+
+#define REG_A2XX_TP0_CHICKEN                                    0x00000e1e
+
+#define REG_A2XX_RB_BC_CONTROL                                  0x00000f01
+#define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE             0x00000001
+#define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK           0x00000006
+#define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT          1
+static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val)
+{
+        return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK;
+}
+#define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM                    0x00000008
+#define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH       0x00000010
+#define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP            0x00000020
+#define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP            0x00000040
+#define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE                   0x00000080
+#define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK              0x00001f00
+#define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT             8
+static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val)
+{
+        return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK;
+}
+#define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE                    0x00004000
+#define A2XX_RB_BC_CONTROL_CRC_MODE                             0x00008000
+#define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS              0x00010000
+#define A2XX_RB_BC_CONTROL_DISABLE_ACCUM                        0x00020000
+#define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK               0x003c0000
+#define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT              18
+static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val)
+{
+        return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK;
+}
+#define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE            0x00400000
+#define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK          0x07800000
+#define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT         23
+static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val)
+{
+        return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK;
+}
+#define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK      0x18000000
+#define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT     27
+static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val)
+{
+        return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK;
+}
+#define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE        0x20000000
+#define A2XX_RB_BC_CONTROL_CRC_SYSTEM                           0x40000000
+#define A2XX_RB_BC_CONTROL_RESERVED6                            0x80000000
+
+#define REG_A2XX_RB_EDRAM_INFO                                  0x00000f02
+
+#define REG_A2XX_RB_DEBUG_CNTL                                  0x00000f26
+
+#define REG_A2XX_RB_DEBUG_DATA                                  0x00000f27
+
+#define REG_A2XX_RB_SURFACE_INFO                                0x00002000
+
+#define REG_A2XX_RB_COLOR_INFO                                  0x00002001
+#define A2XX_RB_COLOR_INFO_FORMAT__MASK                         0x0000000f
+#define A2XX_RB_COLOR_INFO_FORMAT__SHIFT                        0
+static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val)
+{
+        return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK;
+}
+#define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK                     0x00000030
+#define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT                    4
+static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val)
+{
+        return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK;
+}
+#define A2XX_RB_COLOR_INFO_LINEAR                               0x00000040
+#define A2XX_RB_COLOR_INFO_ENDIAN__MASK                         0x00000180
+#define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT                        7
+static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val)
+{
+        return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK;
+}
+#define A2XX_RB_COLOR_INFO_SWAP__MASK                           0x00000600
+#define A2XX_RB_COLOR_INFO_SWAP__SHIFT                          9
+static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val)
+{
+        return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK;
+}
+#define A2XX_RB_COLOR_INFO_BASE__MASK                           0xfffff000
+#define A2XX_RB_COLOR_INFO_BASE__SHIFT                          12
+static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val)
+{
+        return ((val >> 10) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK;
+}
+
+#define REG_A2XX_RB_DEPTH_INFO                                  0x00002002
+#define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK                   0x00000001
+#define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT                  0
+static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val)
+{
+        return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
+}
+#define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK                     0xfffff000
+#define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT                    12
+static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
+{
+        return ((val >> 10) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
+}
+
+#define REG_A2XX_A225_RB_COLOR_INFO3                            0x00002005
+
+#define REG_A2XX_COHER_DEST_BASE_0                              0x00002006
+
+#define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL                        0x0000200e
+#define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE      0x80000000
+#define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK                    0x00007fff
+#define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT                   0
+static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
+{
+        return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK;
+}
+#define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK                    0x7fff0000
+#define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT                   16
+static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
+{
+        return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK;
+}
+
+#define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR                        0x0000200f
+#define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE      0x80000000
+#define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK                    0x00007fff
+#define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT                   0
+static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
+{
+        return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK;
+}
+#define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK                    0x7fff0000
+#define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT                   16
+static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
+{
+        return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK;
+}
+
+#define REG_A2XX_PA_SC_WINDOW_OFFSET                            0x00002080
+#define A2XX_PA_SC_WINDOW_OFFSET_X__MASK                        0x00007fff
+#define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT                       0
+static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val)
+{
+        return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK;
+}
+#define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK                        0x7fff0000
+#define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT                       16
+static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val)
+{
+        return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK;
+}
+#define A2XX_PA_SC_WINDOW_OFFSET_DISABLE                        0x80000000
+
+#define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL                        0x00002081
+#define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE      0x80000000
+#define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK                    0x00007fff
+#define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT                   0
+static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
+{
+        return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK;
+}
+#define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK                    0x7fff0000
+#define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT                   16
+static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
+{
+        return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK;
+}
+
+#define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR                        0x00002082
+#define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE      0x80000000
+#define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK                    0x00007fff
+#define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT                   0
+static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
+{
+        return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK;
+}
+#define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK                    0x7fff0000
+#define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT                   16
+static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
+{
+        return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK;
+}
+
+#define REG_A2XX_UNKNOWN_2010                                   0x00002010
+
+#define REG_A2XX_VGT_MAX_VTX_INDX                               0x00002100
+
+#define REG_A2XX_VGT_MIN_VTX_INDX                               0x00002101
+
+#define REG_A2XX_VGT_INDX_OFFSET                                0x00002102
+
+#define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX               0x00002103
+
+#define REG_A2XX_RB_COLOR_MASK                                  0x00002104
+#define A2XX_RB_COLOR_MASK_WRITE_RED                            0x00000001
+#define A2XX_RB_COLOR_MASK_WRITE_GREEN                          0x00000002
+#define A2XX_RB_COLOR_MASK_WRITE_BLUE                           0x00000004
+#define A2XX_RB_COLOR_MASK_WRITE_ALPHA                          0x00000008
+
+#define REG_A2XX_RB_BLEND_RED                                   0x00002105
+
+#define REG_A2XX_RB_BLEND_GREEN                                 0x00002106
+
+#define REG_A2XX_RB_BLEND_BLUE                                  0x00002107
+
+#define REG_A2XX_RB_BLEND_ALPHA                                 0x00002108
+
+#define REG_A2XX_RB_FOG_COLOR                                   0x00002109
+
+#define REG_A2XX_RB_STENCILREFMASK_BF                           0x0000210c
+#define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK              0x000000ff
+#define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT             0
+static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
+{
+        return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
+}
+#define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK             0x0000ff00
+#define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT            8
+static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
+{
+        return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
+}
+#define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK        0x00ff0000
+#define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT       16
+static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
+{
+        return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
+}
+
+#define REG_A2XX_RB_STENCILREFMASK                              0x0000210d
+#define A2XX_RB_STENCILREFMASK_STENCILREF__MASK                 0x000000ff
+#define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT                0
+static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
+{
+        return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK;
+}
+#define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK                0x0000ff00
+#define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT               8
+static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
+{
+        return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK;
+}
+#define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK           0x00ff0000
+#define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT          16
+static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
+{
+        return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
+}
+
+#define REG_A2XX_RB_ALPHA_REF                                   0x0000210e
+
+#define REG_A2XX_PA_CL_VPORT_XSCALE                             0x0000210f
+#define A2XX_PA_CL_VPORT_XSCALE__MASK                           0xffffffff
+#define A2XX_PA_CL_VPORT_XSCALE__SHIFT                          0
+static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val)
+{
+        return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK;
+}
+
+#define REG_A2XX_PA_CL_VPORT_XOFFSET                            0x00002110
+#define A2XX_PA_CL_VPORT_XOFFSET__MASK                          0xffffffff
+#define A2XX_PA_CL_VPORT_XOFFSET__SHIFT                         0
+static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val)
+{
+        return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK;
+}
+
+#define REG_A2XX_PA_CL_VPORT_YSCALE                             0x00002111
+#define A2XX_PA_CL_VPORT_YSCALE__MASK                           0xffffffff
+#define A2XX_PA_CL_VPORT_YSCALE__SHIFT                          0
+static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val)
+{
+        return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK;
+}
+
+#define REG_A2XX_PA_CL_VPORT_YOFFSET                            0x00002112
+#define A2XX_PA_CL_VPORT_YOFFSET__MASK                          0xffffffff
+#define A2XX_PA_CL_VPORT_YOFFSET__SHIFT                         0
+static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val)
+{
+        return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK;
+}
+
+#define REG_A2XX_PA_CL_VPORT_ZSCALE                             0x00002113
+#define A2XX_PA_CL_VPORT_ZSCALE__MASK                           0xffffffff
+#define A2XX_PA_CL_VPORT_ZSCALE__SHIFT                          0
+static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val)
+{
+        return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK;
+}
+
+#define REG_A2XX_PA_CL_VPORT_ZOFFSET                            0x00002114
+#define A2XX_PA_CL_VPORT_ZOFFSET__MASK                          0xffffffff
+#define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT                         0
+static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val)
+{
+        return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK;
+}
+
+#define REG_A2XX_SQ_PROGRAM_CNTL                                0x00002180
+#define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK                      0x000000ff
+#define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT                     0
+static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val)
+{
+        return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK;
+}
+#define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK                      0x0000ff00
+#define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT                     8
+static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val)
+{
+        return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK;
+}
+#define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE                        0x00010000
+#define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE                        0x00020000
+#define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN                          0x00040000
+#define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX                      0x00080000
+#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK              0x00f00000
+#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT             20
+static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val)
+{
+        return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK;
+}
+#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK               0x07000000
+#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT              24
+static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val)
+{
+        return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK;
+}
+#define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK               0x78000000
+#define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT              27
+static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val)
+{
+        return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK;
+}
+#define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX                      0x80000000
+
+#define REG_A2XX_SQ_CONTEXT_MISC                                0x00002181
+#define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE                 0x00000001
+#define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY                0x00000002
+#define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK               0x0000000c
+#define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT              2
+static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val)
+{
+        return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK;
+}
+#define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK                0x0000ff00
+#define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT               8
+static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val)
+{
+        return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK;
+}
+#define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF                    0x00010000
+#define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE                     0x00020000
+#define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL                       0x00040000
+
+#define REG_A2XX_SQ_INTERPOLATOR_CNTL                           0x00002182
+
+#define REG_A2XX_SQ_WRAPPING_0                                  0x00002183
+
+#define REG_A2XX_SQ_WRAPPING_1                                  0x00002184
+
+#define REG_A2XX_SQ_PS_PROGRAM                                  0x000021f6
+
+#define REG_A2XX_SQ_VS_PROGRAM                                  0x000021f7
+
+#define REG_A2XX_RB_DEPTHCONTROL                                0x00002200
+#define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE                     0x00000001
+#define A2XX_RB_DEPTHCONTROL_Z_ENABLE                           0x00000002
+#define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE                     0x00000004
+#define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE                     0x00000008
+#define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK                        0x00000070
+#define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT                       4
+static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val)
+{
+        return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK;
+}
+#define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE                    0x00000080
+#define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK                  0x00000700
+#define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT                 8
+static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val)
+{
+        return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK;
+}
+#define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK                  0x00003800
+#define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT                 11
+static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val)
+{
+        return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK;
+}
+#define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK                 0x0001c000
+#define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT                14
+static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val)
+{
+        return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK;
+}
+#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK                 0x000e0000
+#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT                17
+static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val)
+{
+        return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK;
+}
+#define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK               0x00700000
+#define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT              20
+static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val)
+{
+        return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK;
+}
+#define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK               0x03800000
+#define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT              23
+static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val)
+{
+        return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK;
+}
+#define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK              0x1c000000
+#define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT             26
+static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val)
+{
+        return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK;
+}
+#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK              0xe0000000
+#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT             29
+static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val)
+{
+        return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK;
+}
+
+#define REG_A2XX_RB_BLEND_CONTROL                               0x00002201
+#define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK              0x0000001f
+#define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT             0
+static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val)
+{
+        return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK;
+}
+#define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK              0x000000e0
+#define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT             5
+static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum adreno_rb_blend_opcode val)
+{
+        return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK;
+}
+#define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK             0x00001f00
+#define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT            8
+static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val)
+{
+        return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK;
+}
+#define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK              0x001f0000
+#define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT             16
+static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val)
+{
+        return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK;
+}
+#define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK              0x00e00000
+#define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT             21
+static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum adreno_rb_blend_opcode val)
+{
+        return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK;
+}
+#define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK             0x1f000000
+#define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT            24
+static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val)
+{
+        return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK;
+}
+#define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE                0x20000000
+#define A2XX_RB_BLEND_CONTROL_BLEND_FORCE                       0x40000000
+
+#define REG_A2XX_RB_COLORCONTROL                                0x00002202
+#define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK                   0x00000007
+#define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT                  0
+static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val)
+{
+        return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK;
+}
+#define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE                  0x00000008
+#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE               0x00000010
+#define A2XX_RB_COLORCONTROL_BLEND_DISABLE                      0x00000020
+#define A2XX_RB_COLORCONTROL_VOB_ENABLE                         0x00000040
+#define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG                     0x00000080
+#define A2XX_RB_COLORCONTROL_ROP_CODE__MASK                     0x00000f00
+#define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT                    8
+static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val)
+{
+        return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK;
+}
+#define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK                  0x00003000
+#define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT                 12
+static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val)
+{
+        return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK;
+}
+#define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK                  0x0000c000
+#define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT                 14
+static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val)
+{
+        return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK;
+}
+#define A2XX_RB_COLORCONTROL_PIXEL_FOG                          0x00010000
+#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK        0x03000000
+#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT       24
+static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val)
+{
+        return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK;
+}
+#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK        0x0c000000
+#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT       26
+static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val)
+{
+        return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK;
+}
+#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK        0x30000000
+#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT       28
+static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val)
+{
+        return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK;
+}
+#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK        0xc0000000
+#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT       30
+static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val)
+{
+        return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK;
+}
+
+#define REG_A2XX_VGT_CURRENT_BIN_ID_MAX                         0x00002203
+#define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK                0x00000007
+#define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT               0
+static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val)
+{
+        return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK;
+}
+#define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK                   0x00000038
+#define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT                  3
+static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val)
+{
+        return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK;
+}
+#define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK       0x000001c0
+#define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT      6
+static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val)
+{
+        return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK;
+}
+
+#define REG_A2XX_PA_CL_CLIP_CNTL                                0x00002204
+#define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE                       0x00010000
+#define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA             0x00040000
+#define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK            0x00080000
+#define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT           19
+static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val)
+{
+        return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK;
+}
+#define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT                0x00100000
+#define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR                        0x00200000
+#define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN                      0x00400000
+#define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN                       0x00800000
+#define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN                       0x01000000
+
+#define REG_A2XX_PA_SU_SC_MODE_CNTL                             0x00002205
+#define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT                      0x00000001
+#define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK                       0x00000002
+#define A2XX_PA_SU_SC_MODE_CNTL_FACE                            0x00000004
+#define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK                  0x00000018
+#define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT                 3
+static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val)
+{
+        return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK;
+}
+#define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK               0x000000e0
+#define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT              5
+static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
+{
+        return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK;
+}
+#define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK                0x00000700
+#define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT               8
+static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
+{
+        return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK;
+}
+#define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE        0x00000800
+#define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE         0x00001000
+#define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE         0x00002000
+#define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE                     0x00008000
+#define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE        0x00010000
+#define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE             0x00040000
+#define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST              0x00080000
+#define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS                  0x00100000
+#define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA               0x00200000
+#define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE               0x00800000
+#define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI            0x02000000
+#define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE        0x04000000
+#define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS                0x10000000
+#define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS              0x20000000
+#define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE                0x40000000
+#define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE               0x80000000
+
+#define REG_A2XX_PA_CL_VTE_CNTL                                 0x00002206
+#define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA                   0x00000001
+#define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA                  0x00000002
+#define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA                   0x00000004
+#define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA                  0x00000008
+#define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA                   0x00000010
+#define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA                  0x00000020
+#define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT                          0x00000100
+#define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT                           0x00000200
+#define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT                          0x00000400
+#define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF                     0x00000800
+
+#define REG_A2XX_VGT_CURRENT_BIN_ID_MIN                         0x00002207
+#define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK                0x00000007
+#define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT               0
+static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val)
+{
+        return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK;
+}
+#define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK                   0x00000038
+#define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT                  3
+static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val)
+{
+        return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK;
+}
+#define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK       0x000001c0
+#define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT      6
+static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val)
+{
+        return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK;
+}
+
+#define REG_A2XX_RB_MODECONTROL                                 0x00002208
+#define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK                    0x00000007
+#define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT                   0
+static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val)
+{
+        return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK;
+}
+
+#define REG_A2XX_A220_RB_LRZ_VSC_CONTROL                        0x00002209
+
+#define REG_A2XX_RB_SAMPLE_POS                                  0x0000220a
+
+#define REG_A2XX_CLEAR_COLOR                                    0x0000220b
+#define A2XX_CLEAR_COLOR_RED__MASK                              0x000000ff
+#define A2XX_CLEAR_COLOR_RED__SHIFT                             0
+static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val)
+{
+        return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK;
+}
+#define A2XX_CLEAR_COLOR_GREEN__MASK                            0x0000ff00
+#define A2XX_CLEAR_COLOR_GREEN__SHIFT                           8
+static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val)
+{
+        return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK;
+}
+#define A2XX_CLEAR_COLOR_BLUE__MASK                             0x00ff0000
+#define A2XX_CLEAR_COLOR_BLUE__SHIFT                            16
+static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val)
+{
+        return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK;
+}
+#define A2XX_CLEAR_COLOR_ALPHA__MASK                            0xff000000
+#define A2XX_CLEAR_COLOR_ALPHA__SHIFT                           24
+static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val)
+{
+        return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK;
+}
+
+#define REG_A2XX_A220_GRAS_CONTROL                              0x00002210
+
+#define REG_A2XX_PA_SU_POINT_SIZE                               0x00002280
+#define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK                      0x0000ffff
+#define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT                     0
+static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val)
+{
+        return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK;
+}
+#define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK                       0xffff0000
+#define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT                      16
+static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val)
+{
+        return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK;
+}
+
+#define REG_A2XX_PA_SU_POINT_MINMAX                             0x00002281
+#define A2XX_PA_SU_POINT_MINMAX_MIN__MASK                       0x0000ffff
+#define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT                      0
+static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val)
+{
+        return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK;
+}
+#define A2XX_PA_SU_POINT_MINMAX_MAX__MASK                       0xffff0000
+#define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT                      16
+static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val)
+{
+        return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK;
+}
+
+#define REG_A2XX_PA_SU_LINE_CNTL                                0x00002282
+#define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK                        0x0000ffff
+#define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT                       0
+static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val)
+{
+        return ((((uint32_t)(val * 8.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK;
+}
+
+#define REG_A2XX_PA_SC_LINE_STIPPLE                             0x00002283
+#define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK              0x0000ffff
+#define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT             0
+static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val)
+{
+        return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK;
+}
+#define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK              0x00ff0000
+#define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT             16
+static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val)
+{
+        return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK;
+}
+#define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK         0x10000000
+#define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT        28
+static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val)
+{
+        return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK;
+}
+#define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK           0x60000000
+#define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT          29
+static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val)
+{
+        return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK;
+}
+
+#define REG_A2XX_PA_SC_VIZ_QUERY                                0x00002293
+
+#define REG_A2XX_VGT_ENHANCE                                    0x00002294
+
+#define REG_A2XX_PA_SC_LINE_CNTL                                0x00002300
+#define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK                    0x0000ffff
+#define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT                   0
+static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val)
+{
+        return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK;
+}
+#define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL                      0x00000100
+#define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH                  0x00000200
+#define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL                         0x00000400
+
+#define REG_A2XX_PA_SC_AA_CONFIG                                0x00002301
+
+#define REG_A2XX_PA_SU_VTX_CNTL                                 0x00002302
+#define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK                    0x00000001
+#define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT                   0
+static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val)
+{
+        return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK;
+}
+#define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK                    0x00000006
+#define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT                   1
+static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val)
+{
+        return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK;
+}
+#define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK                    0x00000380
+#define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT                   7
+static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val)
+{
+        return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK;
+}
+
+#define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ                         0x00002303
+#define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK                       0xffffffff
+#define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT                      0
+static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val)
+{
+        return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK;
+}
+
+#define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ                         0x00002304
+#define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK                       0xffffffff
+#define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT                      0
+static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val)
+{
+        return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK;
+}
+
+#define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ                         0x00002305
+#define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK                       0xffffffff
+#define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT                      0
+static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val)
+{
+        return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK;
+}
+
+#define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ                         0x00002306
+#define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK                       0xffffffff
+#define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT                      0
+static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val)
+{
+        return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK;
+}
+
+#define REG_A2XX_SQ_VS_CONST                                    0x00002307
+#define A2XX_SQ_VS_CONST_BASE__MASK                             0x000001ff
+#define A2XX_SQ_VS_CONST_BASE__SHIFT                            0
+static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val)
+{
+        return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK;
+}
+#define A2XX_SQ_VS_CONST_SIZE__MASK                             0x001ff000
+#define A2XX_SQ_VS_CONST_SIZE__SHIFT                            12
+static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val)
+{
+        return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK;
+}
+
+#define REG_A2XX_SQ_PS_CONST                                    0x00002308
+#define A2XX_SQ_PS_CONST_BASE__MASK                             0x000001ff
+#define A2XX_SQ_PS_CONST_BASE__SHIFT                            0
+static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val)
+{
+        return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK;
+}
+#define A2XX_SQ_PS_CONST_SIZE__MASK                             0x001ff000
+#define A2XX_SQ_PS_CONST_SIZE__SHIFT                            12
+static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val)
+{
+        return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK;
+}
+
+#define REG_A2XX_SQ_DEBUG_MISC_0                                0x00002309
+
+#define REG_A2XX_SQ_DEBUG_MISC_1                                0x0000230a
+
+#define REG_A2XX_PA_SC_AA_MASK                                  0x00002312
+
+#define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL                    0x00002316
+
+#define REG_A2XX_VGT_OUT_DEALLOC_CNTL                           0x00002317
+
+#define REG_A2XX_RB_COPY_CONTROL                                0x00002318
+#define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK           0x00000007
+#define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT          0
+static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val)
+{
+        return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK;
+}
+#define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE                 0x00000008
+#define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK                   0x000000f0
+#define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT                  4
+static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val)
+{
+        return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK;
+}
+
+#define REG_A2XX_RB_COPY_DEST_BASE                              0x00002319
+
+#define REG_A2XX_RB_COPY_DEST_PITCH                             0x0000231a
+#define A2XX_RB_COPY_DEST_PITCH__MASK                           0xffffffff
+#define A2XX_RB_COPY_DEST_PITCH__SHIFT                          0
+static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val)
+{
+        return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK;
+}
+
+#define REG_A2XX_RB_COPY_DEST_INFO                              0x0000231b
+#define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK                0x00000007
+#define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT               0
+static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val)
+{
+        return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK;
+}
+#define A2XX_RB_COPY_DEST_INFO_LINEAR                           0x00000008
+#define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK                     0x000000f0
+#define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT                    4
+static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val)
+{
+        return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK;
+}
+#define A2XX_RB_COPY_DEST_INFO_SWAP__MASK                       0x00000300
+#define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT                      8
+static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val)
+{
+        return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK;
+}
+#define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK                0x00000c00
+#define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT               10
+static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
+{
+        return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
+}
+#define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK                0x00003000
+#define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT               12
+static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val)
+{
+        return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK;
+}
+#define A2XX_RB_COPY_DEST_INFO_WRITE_RED                        0x00004000
+#define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN                      0x00008000
+#define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE                       0x00010000
+#define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA                      0x00020000
+
+#define REG_A2XX_RB_COPY_DEST_OFFSET                            0x0000231c
+#define A2XX_RB_COPY_DEST_OFFSET_X__MASK                        0x00001fff
+#define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT                       0
+static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val)
+{
+        return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK;
+}
+#define A2XX_RB_COPY_DEST_OFFSET_Y__MASK                        0x03ffe000
+#define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT                       13
+static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val)
+{
+        return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK;
+}
+
+#define REG_A2XX_RB_DEPTH_CLEAR                                 0x0000231d
+
+#define REG_A2XX_RB_SAMPLE_COUNT_CTL                            0x00002324
+
+#define REG_A2XX_RB_COLOR_DEST_MASK                             0x00002326
+
+#define REG_A2XX_A225_GRAS_UCP0X                                0x00002340
+
+#define REG_A2XX_A225_GRAS_UCP5W                                0x00002357
+
+#define REG_A2XX_A225_GRAS_UCP_ENABLED                          0x00002360
+
+#define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE                  0x00002380
+
+#define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET                  0x00002383
+
+#define REG_A2XX_SQ_CONSTANT_0                                  0x00004000
+
+#define REG_A2XX_SQ_FETCH_0                                     0x00004800
+
+#define REG_A2XX_SQ_CF_BOOLEANS                                 0x00004900
+
+#define REG_A2XX_SQ_CF_LOOP                                     0x00004908
+
+#define REG_A2XX_COHER_SIZE_PM4                                 0x00000a29
+
+#define REG_A2XX_COHER_BASE_PM4                                 0x00000a2a
+
+#define REG_A2XX_COHER_STATUS_PM4                               0x00000a2b
+
+#define REG_A2XX_SQ_TEX_0                                       0x00000000
+#define A2XX_SQ_TEX_0_CLAMP_X__MASK                             0x00001c00
+#define A2XX_SQ_TEX_0_CLAMP_X__SHIFT                            10
+static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val)
+{
+        return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK;
+}
+#define A2XX_SQ_TEX_0_CLAMP_Y__MASK                             0x0000e000
+#define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT                            13
+static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val)
+{
+        return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK;
+}
+#define A2XX_SQ_TEX_0_CLAMP_Z__MASK                             0x00070000
+#define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT                            16
+static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val)
+{
+        return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK;
+}
+#define A2XX_SQ_TEX_0_PITCH__MASK                               0xffc00000
+#define A2XX_SQ_TEX_0_PITCH__SHIFT                              22
+static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val)
+{
+        return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK;
+}
+
+#define REG_A2XX_SQ_TEX_1                                       0x00000001
+
+#define REG_A2XX_SQ_TEX_2                                       0x00000002
+#define A2XX_SQ_TEX_2_WIDTH__MASK                               0x00001fff
+#define A2XX_SQ_TEX_2_WIDTH__SHIFT                              0
+static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val)
+{
+        return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK;
+}
+#define A2XX_SQ_TEX_2_HEIGHT__MASK                              0x03ffe000
+#define A2XX_SQ_TEX_2_HEIGHT__SHIFT                             13
+static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val)
+{
+        return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK;
+}
+
+#define REG_A2XX_SQ_TEX_3                                       0x00000003
+#define A2XX_SQ_TEX_3_SWIZ_X__MASK                              0x0000000e
+#define A2XX_SQ_TEX_3_SWIZ_X__SHIFT                             1
+static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val)
+{
+        return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK;
+}
+#define A2XX_SQ_TEX_3_SWIZ_Y__MASK                              0x00000070
+#define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT                             4
+static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val)
+{
+        return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK;
+}
+#define A2XX_SQ_TEX_3_SWIZ_Z__MASK                              0x00000380
+#define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT                             7
+static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val)
+{
+        return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK;
+}
+#define A2XX_SQ_TEX_3_SWIZ_W__MASK                              0x00001c00
+#define A2XX_SQ_TEX_3_SWIZ_W__SHIFT                             10
+static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val)
+{
+        return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK;
+}
+#define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK                       0x00180000
+#define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT                      19
+static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val)
+{
+        return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK;
+}
+#define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK                       0x00600000
+#define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT                      21
+static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val)
+{
+        return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK;
+}
+
+
+#endif /* A2XX_XML */
diff --git a/drivers/gpu/drm/msm/adreno/a3xx.xml.h b/drivers/gpu/drm/msm/adreno/a3xx.xml.h
new file mode 100644
index 000000000000..d183516067b4
--- /dev/null
+++ b/drivers/gpu/drm/msm/adreno/a3xx.xml.h
@@ -0,0 +1,2193 @@
+#ifndef A3XX_XML
+#define A3XX_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml              (    327 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
+- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml           (  30005 bytes, from 2013-07-19 21:30:48)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml       (   8983 bytes, from 2013-07-24 01:38:36)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml          (   9712 bytes, from 2013-05-26 15:22:37)
+- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml           (  51415 bytes, from 2013-08-03 14:26:05)
+
+Copyright (C) 2013 by the following authors:
+- Rob Clark <robdclark@gmail.com> (robclark)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+enum a3xx_render_mode {
+        RB_RENDERING_PASS = 0,
+        RB_TILING_PASS = 1,
+        RB_RESOLVE_PASS = 2,
+};
+
+enum a3xx_tile_mode {
+        LINEAR = 0,
+        TILE_32X32 = 2,
+};
+
+enum a3xx_threadmode {
+        MULTI = 0,
+        SINGLE = 1,
+};
+
+enum a3xx_instrbuffermode {
+        BUFFER = 1,
+};
+
+enum a3xx_threadsize {
+        TWO_QUADS = 0,
+        FOUR_QUADS = 1,
+};
+
+enum a3xx_state_block_id {
+        HLSQ_BLOCK_ID_TP_TEX = 2,
+        HLSQ_BLOCK_ID_TP_MIPMAP = 3,
+        HLSQ_BLOCK_ID_SP_VS = 4,
+        HLSQ_BLOCK_ID_SP_FS = 6,
+};
+
+enum a3xx_cache_opcode {
+        INVALIDATE = 1,
+};
+
+enum a3xx_vtx_fmt {
+        VFMT_FLOAT_32 = 0,
+        VFMT_FLOAT_32_32 = 1,
+        VFMT_FLOAT_32_32_32 = 2,
+        VFMT_FLOAT_32_32_32_32 = 3,
+        VFMT_FLOAT_16 = 4,
+        VFMT_FLOAT_16_16 = 5,
+        VFMT_FLOAT_16_16_16 = 6,
+        VFMT_FLOAT_16_16_16_16 = 7,
+        VFMT_FIXED_32 = 8,
+        VFMT_FIXED_32_32 = 9,
+        VFMT_FIXED_32_32_32 = 10,
+        VFMT_FIXED_32_32_32_32 = 11,
+        VFMT_SHORT_16 = 16,
+        VFMT_SHORT_16_16 = 17,
+        VFMT_SHORT_16_16_16 = 18,
+        VFMT_SHORT_16_16_16_16 = 19,
+        VFMT_USHORT_16 = 20,
+        VFMT_USHORT_16_16 = 21,
+        VFMT_USHORT_16_16_16 = 22,
+        VFMT_USHORT_16_16_16_16 = 23,
+        VFMT_NORM_SHORT_16 = 24,
+        VFMT_NORM_SHORT_16_16 = 25,
+        VFMT_NORM_SHORT_16_16_16 = 26,
+        VFMT_NORM_SHORT_16_16_16_16 = 27,
+        VFMT_NORM_USHORT_16 = 28,
+        VFMT_NORM_USHORT_16_16 = 29,
+        VFMT_NORM_USHORT_16_16_16 = 30,
+        VFMT_NORM_USHORT_16_16_16_16 = 31,
+        VFMT_UBYTE_8 = 40,
+        VFMT_UBYTE_8_8 = 41,
+        VFMT_UBYTE_8_8_8 = 42,
+        VFMT_UBYTE_8_8_8_8 = 43,
+        VFMT_NORM_UBYTE_8 = 44,
+        VFMT_NORM_UBYTE_8_8 = 45,
+        VFMT_NORM_UBYTE_8_8_8 = 46,
+        VFMT_NORM_UBYTE_8_8_8_8 = 47,
+        VFMT_BYTE_8 = 48,
+        VFMT_BYTE_8_8 = 49,
+        VFMT_BYTE_8_8_8 = 50,
+        VFMT_BYTE_8_8_8_8 = 51,
+        VFMT_NORM_BYTE_8 = 52,
+        VFMT_NORM_BYTE_8_8 = 53,
+        VFMT_NORM_BYTE_8_8_8 = 54,
+        VFMT_NORM_BYTE_8_8_8_8 = 55,
+        VFMT_UINT_10_10_10_2 = 60,
+        VFMT_NORM_UINT_10_10_10_2 = 61,
+        VFMT_INT_10_10_10_2 = 62,
+        VFMT_NORM_INT_10_10_10_2 = 63,
+};
+
+enum a3xx_tex_fmt {
+        TFMT_NORM_USHORT_565 = 4,
+        TFMT_NORM_USHORT_5551 = 6,
+        TFMT_NORM_USHORT_4444 = 7,
+        TFMT_NORM_UINT_X8Z24 = 10,
+        TFMT_NORM_UINT_NV12_UV_TILED = 17,
+        TFMT_NORM_UINT_NV12_Y_TILED = 19,
+        TFMT_NORM_UINT_NV12_UV = 21,
+        TFMT_NORM_UINT_NV12_Y = 23,
+        TFMT_NORM_UINT_I420_Y = 24,
+        TFMT_NORM_UINT_I420_U = 26,
+        TFMT_NORM_UINT_I420_V = 27,
+        TFMT_NORM_UINT_2_10_10_10 = 41,
+        TFMT_NORM_UINT_A8 = 44,
+        TFMT_NORM_UINT_L8_A8 = 47,
+        TFMT_NORM_UINT_8 = 48,
+        TFMT_NORM_UINT_8_8 = 49,
+        TFMT_NORM_UINT_8_8_8 = 50,
+        TFMT_NORM_UINT_8_8_8_8 = 51,
+        TFMT_FLOAT_16 = 64,
+        TFMT_FLOAT_16_16 = 65,
+        TFMT_FLOAT_16_16_16_16 = 67,
+        TFMT_FLOAT_32 = 84,
+        TFMT_FLOAT_32_32 = 85,
+        TFMT_FLOAT_32_32_32_32 = 87,
+};
+
+enum a3xx_tex_fetchsize {
+        TFETCH_DISABLE = 0,
+        TFETCH_1_BYTE = 1,
+        TFETCH_2_BYTE = 2,
+        TFETCH_4_BYTE = 3,
+        TFETCH_8_BYTE = 4,
+        TFETCH_16_BYTE = 5,
+};
+
+enum a3xx_color_fmt {
+        RB_R8G8B8_UNORM = 4,
+        RB_R8G8B8A8_UNORM = 8,
+        RB_Z16_UNORM = 12,
+        RB_A8_UNORM = 20,
+};
+
+enum a3xx_color_swap {
+        WZYX = 0,
+        WXYZ = 1,
+        ZYXW = 2,
+        XYZW = 3,
+};
+
+enum a3xx_msaa_samples {
+        MSAA_ONE = 0,
+        MSAA_TWO = 1,
+        MSAA_FOUR = 2,
+};
+
+enum a3xx_sp_perfcounter_select {
+        SP_FS_CFLOW_INSTRUCTIONS = 12,
+        SP_FS_FULL_ALU_INSTRUCTIONS = 14,
+        SP0_ICL1_MISSES = 26,
+        SP_ALU_ACTIVE_CYCLES = 29,
+};
+
+enum adreno_rb_copy_control_mode {
+        RB_COPY_RESOLVE = 1,
+        RB_COPY_DEPTH_STENCIL = 5,
+};
+
+enum a3xx_tex_filter {
+        A3XX_TEX_NEAREST = 0,
+        A3XX_TEX_LINEAR = 1,
+};
+
+enum a3xx_tex_clamp {
+        A3XX_TEX_REPEAT = 0,
+        A3XX_TEX_CLAMP_TO_EDGE = 1,
+        A3XX_TEX_MIRROR_REPEAT = 2,
+        A3XX_TEX_CLAMP_NONE = 3,
+};
+
+enum a3xx_tex_swiz {
+        A3XX_TEX_X = 0,
+        A3XX_TEX_Y = 1,
+        A3XX_TEX_Z = 2,
+        A3XX_TEX_W = 3,
+        A3XX_TEX_ZERO = 4,
+        A3XX_TEX_ONE = 5,
+};
+
+enum a3xx_tex_type {
+        A3XX_TEX_1D = 0,
+        A3XX_TEX_2D = 1,
+        A3XX_TEX_CUBE = 2,
+        A3XX_TEX_3D = 3,
+};
+
+#define A3XX_INT0_RBBM_GPU_IDLE                                 0x00000001
+#define A3XX_INT0_RBBM_AHB_ERROR                                0x00000002
+#define A3XX_INT0_RBBM_REG_TIMEOUT                              0x00000004
+#define A3XX_INT0_RBBM_ME_MS_TIMEOUT                            0x00000008
+#define A3XX_INT0_RBBM_PFP_MS_TIMEOUT                           0x00000010
+#define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW                         0x00000020
+#define A3XX_INT0_VFD_ERROR                                     0x00000040
+#define A3XX_INT0_CP_SW_INT                                     0x00000080
+#define A3XX_INT0_CP_T0_PACKET_IN_IB                            0x00000100
+#define A3XX_INT0_CP_OPCODE_ERROR                               0x00000200
+#define A3XX_INT0_CP_RESERVED_BIT_ERROR                         0x00000400
+#define A3XX_INT0_CP_HW_FAULT                                   0x00000800
+#define A3XX_INT0_CP_DMA                                        0x00001000
+#define A3XX_INT0_CP_IB2_INT                                    0x00002000
+#define A3XX_INT0_CP_IB1_INT                                    0x00004000
+#define A3XX_INT0_CP_RB_INT                                     0x00008000
+#define A3XX_INT0_CP_REG_PROTECT_FAULT                          0x00010000
+#define A3XX_INT0_CP_RB_DONE_TS                                 0x00020000
+#define A3XX_INT0_CP_VS_DONE_TS                                 0x00040000
+#define A3XX_INT0_CP_PS_DONE_TS                                 0x00080000
+#define A3XX_INT0_CACHE_FLUSH_TS                                0x00100000
+#define A3XX_INT0_CP_AHB_ERROR_HALT                             0x00200000
+#define A3XX_INT0_MISC_HANG_DETECT                              0x01000000
+#define A3XX_INT0_UCHE_OOB_ACCESS                               0x02000000
+#define REG_A3XX_RBBM_HW_VERSION                                0x00000000
+
+#define REG_A3XX_RBBM_HW_RELEASE                                0x00000001
+
+#define REG_A3XX_RBBM_HW_CONFIGURATION                          0x00000002
+
+#define REG_A3XX_RBBM_CLOCK_CTL                                 0x00000010
+
+#define REG_A3XX_RBBM_SP_HYST_CNT                               0x00000012
+
+#define REG_A3XX_RBBM_SW_RESET_CMD                              0x00000018
+
+#define REG_A3XX_RBBM_AHB_CTL0                                  0x00000020
+
+#define REG_A3XX_RBBM_AHB_CTL1                                  0x00000021
+
+#define REG_A3XX_RBBM_AHB_CMD                                   0x00000022
+
+#define REG_A3XX_RBBM_AHB_ERROR_STATUS                          0x00000027
+
+#define REG_A3XX_RBBM_GPR0_CTL                                  0x0000002e
+
+#define REG_A3XX_RBBM_STATUS                                    0x00000030
+#define A3XX_RBBM_STATUS_HI_BUSY                                0x00000001
+#define A3XX_RBBM_STATUS_CP_ME_BUSY                             0x00000002
+#define A3XX_RBBM_STATUS_CP_PFP_BUSY                            0x00000004
+#define A3XX_RBBM_STATUS_CP_NRT_BUSY                            0x00004000
+#define A3XX_RBBM_STATUS_VBIF_BUSY                              0x00008000
+#define A3XX_RBBM_STATUS_TSE_BUSY                               0x00010000
+#define A3XX_RBBM_STATUS_RAS_BUSY                               0x00020000
+#define A3XX_RBBM_STATUS_RB_BUSY                                0x00040000
+#define A3XX_RBBM_STATUS_PC_DCALL_BUSY                          0x00080000
+#define A3XX_RBBM_STATUS_PC_VSD_BUSY                            0x00100000
+#define A3XX_RBBM_STATUS_VFD_BUSY                               0x00200000
+#define A3XX_RBBM_STATUS_VPC_BUSY                               0x00400000
+#define A3XX_RBBM_STATUS_UCHE_BUSY                              0x00800000
+#define A3XX_RBBM_STATUS_SP_BUSY                                0x01000000
+#define A3XX_RBBM_STATUS_TPL1_BUSY                              0x02000000
+#define A3XX_RBBM_STATUS_MARB_BUSY                              0x04000000
+#define A3XX_RBBM_STATUS_VSC_BUSY                               0x08000000
+#define A3XX_RBBM_STATUS_ARB_BUSY                               0x10000000
+#define A3XX_RBBM_STATUS_HLSQ_BUSY                              0x20000000
+#define A3XX_RBBM_STATUS_GPU_BUSY_NOHC                          0x40000000
+#define A3XX_RBBM_STATUS_GPU_BUSY                               0x80000000
+
+#define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL                      0x00000033
+
+#define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL                    0x00000050
+
+#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0                  0x00000051
+
+#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1                  0x00000054
+
+#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2                  0x00000057
+
+#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3                  0x0000005a
+
+#define REG_A3XX_RBBM_INT_CLEAR_CMD                             0x00000061
+
+#define REG_A3XX_RBBM_INT_0_MASK                                0x00000063
+
+#define REG_A3XX_RBBM_INT_0_STATUS                              0x00000064
+
+#define REG_A3XX_RBBM_PERFCTR_CTL                               0x00000080
+
+#define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0                         0x00000081
+
+#define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1                         0x00000082
+
+#define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO                     0x00000084
+
+#define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI                     0x00000085
+
+#define REG_A3XX_RBBM_PERFCOUNTER0_SELECT                       0x00000086
+
+#define REG_A3XX_RBBM_PERFCOUNTER1_SELECT                       0x00000087
+
+#define REG_A3XX_RBBM_GPU_BUSY_MASKED                           0x00000088
+
+#define REG_A3XX_RBBM_PERFCTR_CP_0_LO                           0x00000090
+
+#define REG_A3XX_RBBM_PERFCTR_CP_0_HI                           0x00000091
+
+#define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO                         0x00000092
+
+#define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI                         0x00000093
+
+#define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO                         0x00000094
+
+#define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI                         0x00000095
+
+#define REG_A3XX_RBBM_PERFCTR_PC_0_LO                           0x00000096
+
+#define REG_A3XX_RBBM_PERFCTR_PC_0_HI                           0x00000097
+
+#define REG_A3XX_RBBM_PERFCTR_PC_1_LO                           0x00000098
+
+#define REG_A3XX_RBBM_PERFCTR_PC_1_HI                           0x00000099
+
+#define REG_A3XX_RBBM_PERFCTR_PC_2_LO                           0x0000009a
+
+#define REG_A3XX_RBBM_PERFCTR_PC_2_HI                           0x0000009b
+
+#define REG_A3XX_RBBM_PERFCTR_PC_3_LO                           0x0000009c
+
+#define REG_A3XX_RBBM_PERFCTR_PC_3_HI                           0x0000009d
+
+#define REG_A3XX_RBBM_PERFCTR_VFD_0_LO                          0x0000009e
+
+#define REG_A3XX_RBBM_PERFCTR_VFD_0_HI                          0x0000009f
+
+#define REG_A3XX_RBBM_PERFCTR_VFD_1_LO                          0x000000a0
+
+#define REG_A3XX_RBBM_PERFCTR_VFD_1_HI                          0x000000a1
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO                         0x000000a2
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI                         0x000000a3
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO                         0x000000a4
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI                         0x000000a5
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO                         0x000000a6
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI                         0x000000a7
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO                         0x000000a8
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI                         0x000000a9
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO                         0x000000aa
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI                         0x000000ab
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO                         0x000000ac
+
+#define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI                         0x000000ad
+
+#define REG_A3XX_RBBM_PERFCTR_VPC_0_LO                          0x000000ae
+
+#define REG_A3XX_RBBM_PERFCTR_VPC_0_HI                          0x000000af
+
+#define REG_A3XX_RBBM_PERFCTR_VPC_1_LO                          0x000000b0
+
+#define REG_A3XX_RBBM_PERFCTR_VPC_1_HI                          0x000000b1
+
+#define REG_A3XX_RBBM_PERFCTR_TSE_0_LO                          0x000000b2
+
+#define REG_A3XX_RBBM_PERFCTR_TSE_0_HI                          0x000000b3
+
+#define REG_A3XX_RBBM_PERFCTR_TSE_1_LO                          0x000000b4
+
+#define REG_A3XX_RBBM_PERFCTR_TSE_1_HI                          0x000000b5
+
+#define REG_A3XX_RBBM_PERFCTR_RAS_0_LO                          0x000000b6
+
+#define REG_A3XX_RBBM_PERFCTR_RAS_0_HI                          0x000000b7
+
+#define REG_A3XX_RBBM_PERFCTR_RAS_1_LO                          0x000000b8
+
+#define REG_A3XX_RBBM_PERFCTR_RAS_1_HI                          0x000000b9
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO                         0x000000ba
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI                         0x000000bb
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO                         0x000000bc
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI                         0x000000bd
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO                         0x000000be
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI                         0x000000bf
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO                         0x000000c0
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI                         0x000000c1
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO                         0x000000c2
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI                         0x000000c3
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO                         0x000000c4
+
+#define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI                         0x000000c5
+
+#define REG_A3XX_RBBM_PERFCTR_TP_0_LO                           0x000000c6
+
+#define REG_A3XX_RBBM_PERFCTR_TP_0_HI                           0x000000c7
+
+#define REG_A3XX_RBBM_PERFCTR_TP_1_LO                           0x000000c8
+
+#define REG_A3XX_RBBM_PERFCTR_TP_1_HI                           0x000000c9
+
+#define REG_A3XX_RBBM_PERFCTR_TP_2_LO                           0x000000ca
+
+#define REG_A3XX_RBBM_PERFCTR_TP_2_HI                           0x000000cb
+
+#define REG_A3XX_RBBM_PERFCTR_TP_3_LO                           0x000000cc
+
+#define REG_A3XX_RBBM_PERFCTR_TP_3_HI                           0x000000cd
+
+#define REG_A3XX_RBBM_PERFCTR_TP_4_LO                           0x000000ce
+
+#define REG_A3XX_RBBM_PERFCTR_TP_4_HI                           0x000000cf
+
+#define REG_A3XX_RBBM_PERFCTR_TP_5_LO                           0x000000d0
+
+#define REG_A3XX_RBBM_PERFCTR_TP_5_HI                           0x000000d1
+
+#define REG_A3XX_RBBM_PERFCTR_SP_0_LO                           0x000000d2
+
+#define REG_A3XX_RBBM_PERFCTR_SP_0_HI                           0x000000d3
+
+#define REG_A3XX_RBBM_PERFCTR_SP_1_LO                           0x000000d4
+
+#define REG_A3XX_RBBM_PERFCTR_SP_1_HI                           0x000000d5
+
+#define REG_A3XX_RBBM_PERFCTR_SP_2_LO                           0x000000d6
+
+#define REG_A3XX_RBBM_PERFCTR_SP_2_HI                           0x000000d7
+
+#define REG_A3XX_RBBM_PERFCTR_SP_3_LO                           0x000000d8
+
+#define REG_A3XX_RBBM_PERFCTR_SP_3_HI                           0x000000d9
+
+#define REG_A3XX_RBBM_PERFCTR_SP_4_LO                           0x000000da
+
+#define REG_A3XX_RBBM_PERFCTR_SP_4_HI                           0x000000db
+
+#define REG_A3XX_RBBM_PERFCTR_SP_5_LO                           0x000000dc
+
+#define REG_A3XX_RBBM_PERFCTR_SP_5_HI                           0x000000dd
+
+#define REG_A3XX_RBBM_PERFCTR_SP_6_LO                           0x000000de
+
+#define REG_A3XX_RBBM_PERFCTR_SP_6_HI                           0x000000df
+
+#define REG_A3XX_RBBM_PERFCTR_SP_7_LO                           0x000000e0
+
+#define REG_A3XX_RBBM_PERFCTR_SP_7_HI                           0x000000e1
+
+#define REG_A3XX_RBBM_PERFCTR_RB_0_LO                           0x000000e2
+
+#define REG_A3XX_RBBM_PERFCTR_RB_0_HI                           0x000000e3
+
+#define REG_A3XX_RBBM_PERFCTR_RB_1_LO                           0x000000e4
+
+#define REG_A3XX_RBBM_PERFCTR_RB_1_HI                           0x000000e5
+
+#define REG_A3XX_RBBM_PERFCTR_PWR_0_LO                          0x000000ea
+
+#define REG_A3XX_RBBM_PERFCTR_PWR_0_HI                          0x000000eb
+
+#define REG_A3XX_RBBM_PERFCTR_PWR_1_LO                          0x000000ec
+
+#define REG_A3XX_RBBM_PERFCTR_PWR_1_HI                          0x000000ed
+
+#define REG_A3XX_RBBM_RBBM_CTL                                  0x00000100
+
+#define REG_A3XX_RBBM_DEBUG_BUS_CTL                             0x00000111
+
+#define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS                     0x00000112
+
+#define REG_A3XX_CP_PFP_UCODE_ADDR                              0x000001c9
+
+#define REG_A3XX_CP_PFP_UCODE_DATA                              0x000001ca
+
+#define REG_A3XX_CP_ROQ_ADDR                                    0x000001cc
+
+#define REG_A3XX_CP_ROQ_DATA                                    0x000001cd
+
+#define REG_A3XX_CP_MERCIU_ADDR                                 0x000001d1
+
+#define REG_A3XX_CP_MERCIU_DATA                                 0x000001d2
+
+#define REG_A3XX_CP_MERCIU_DATA2                                0x000001d3
+
+#define REG_A3XX_CP_MEQ_ADDR                                    0x000001da
+
+#define REG_A3XX_CP_MEQ_DATA                                    0x000001db
+
+#define REG_A3XX_CP_PERFCOUNTER_SELECT                          0x00000445
+
+#define REG_A3XX_CP_HW_FAULT                                    0x0000045c
+
+#define REG_A3XX_CP_PROTECT_CTRL                                0x0000045e
+
+#define REG_A3XX_CP_PROTECT_STATUS                              0x0000045f
+
+static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; }
+
+static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; }
+
+#define REG_A3XX_CP_AHB_FAULT                                   0x0000054d
+
+#define REG_A3XX_GRAS_CL_CLIP_CNTL                              0x00002040
+#define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER                  0x00001000
+#define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE                     0x00010000
+#define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE                0x00020000
+#define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE              0x00080000
+#define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE                 0x00100000
+#define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE           0x00200000
+
+#define REG_A3XX_GRAS_CL_GB_CLIP_ADJ                            0x00002044
+#define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK                     0x000003ff
+#define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT                    0
+static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
+{
+        return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK;
+}
+#define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK                     0x000ffc00
+#define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT                    10
+static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
+{
+        return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK;
+}
+
+#define REG_A3XX_GRAS_CL_VPORT_XOFFSET                          0x00002048
+#define A3XX_GRAS_CL_VPORT_XOFFSET__MASK                        0xffffffff
+#define A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT                       0
+static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val)
+{
+        return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK;
+}
+
+#define REG_A3XX_GRAS_CL_VPORT_XSCALE                           0x00002049
+#define A3XX_GRAS_CL_VPORT_XSCALE__MASK                         0xffffffff
+#define A3XX_GRAS_CL_VPORT_XSCALE__SHIFT                        0
+static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val)
+{
+        return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK;
+}
+
+#define REG_A3XX_GRAS_CL_VPORT_YOFFSET                          0x0000204a
+#define A3XX_GRAS_CL_VPORT_YOFFSET__MASK                        0xffffffff
+#define A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT                       0
+static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val)
+{
+        return ((fui(val)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK;
+}
+
+#define REG_A3XX_GRAS_CL_VPORT_YSCALE                           0x0000204b
+#define A3XX_GRAS_CL_VPORT_YSCALE__MASK                         0xffffffff
+#define A3XX_GRAS_CL_VPORT_YSCALE__SHIFT                        0
+static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val)
+{
+        return ((fui(val)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_YSCALE__MASK;
+}
+
+#define REG_A3XX_GRAS_CL_VPORT_ZOFFSET                          0x0000204c
+#define A3XX_GRAS_CL_VPORT_ZOFFSET__MASK                        0xffffffff
+#define A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT                       0
+static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val)
+{
+        return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK;
+}
+
+#define REG_A3XX_GRAS_CL_VPORT_ZSCALE                           0x0000204d
+#define A3XX_GRAS_CL_VPORT_ZSCALE__MASK                         0xffffffff
+#define A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT                        0
+static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val)
+{
+        return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK;
+}
+
+#define REG_A3XX_GRAS_SU_POINT_MINMAX                           0x00002068
+
+#define REG_A3XX_GRAS_SU_POINT_SIZE                             0x00002069
+
+#define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE                      0x0000206c
+#define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK                0x00ffffff
+#define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT               0
+static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val)
+{
+        return ((((uint32_t)(val * 40.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK;
+}
+
+#define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET                     0x0000206d
+#define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK                   0xffffffff
+#define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT                  0
+static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
+{
+        return ((((uint32_t)(val * 44.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
+}
+
+#define REG_A3XX_GRAS_SU_MODE_CONTROL                           0x00002070
+#define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT                    0x00000001
+#define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK                     0x00000002
+#define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK           0x000007fc
+#define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT          2
+static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(uint32_t val)
+{
+        return ((val) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
+}
+#define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET                   0x00000800
+
+#define REG_A3XX_GRAS_SC_CONTROL                                0x00002072
+#define A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK                  0x000000f0
+#define A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT                 4
+static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
+{
+        return ((val) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
+}
+#define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK                 0x00000f00
+#define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT                8
+static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val)
+{
+        return ((val) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
+}
+#define A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK                  0x0000f000
+#define A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT                 12
+static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
+{
+        return ((val) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
+}
+
+#define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL                      0x00002074
+#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE    0x80000000
+#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK                  0x00007fff
+#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT                 0
+static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
+{
+        return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
+}
+#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK                  0x7fff0000
+#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT                 16
+static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
+{
+        return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
+}
+
+#define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR                      0x00002075
+#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE    0x80000000
+#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK                  0x00007fff
+#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT                 0
+static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
+{
+        return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
+}
+#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK                  0x7fff0000
+#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT                 16
+static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
+{
+        return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
+}
+
+#define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL                      0x00002079
+#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE    0x80000000
+#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK                  0x00007fff
+#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT                 0
+static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
+{
+        return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
+}
+#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK                  0x7fff0000
+#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT                 16
+static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
+{
+        return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
+}
+
+#define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR                      0x0000207a
+#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE    0x80000000
+#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK                  0x00007fff
+#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT                 0
+static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
+{
+        return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
+}
+#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK                  0x7fff0000
+#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT                 16
+static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
+{
+        return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
+}
+
+#define REG_A3XX_RB_MODE_CONTROL                                0x000020c0
+#define A3XX_RB_MODE_CONTROL_GMEM_BYPASS                        0x00000080
+#define A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK                  0x00000700
+#define A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT                 8
+static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
+{
+        return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK;
+}
+#define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE              0x00008000
+#define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE                0x00010000
+
+#define REG_A3XX_RB_RENDER_CONTROL                              0x000020c1
+#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK                  0x00000ff0
+#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT                 4
+static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val)
+{
+        return ((val >> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK;
+}
+#define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE               0x00001000
+#define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM                      0x00002000
+#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK            0x07000000
+#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT           24
+static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
+{
+        return ((val) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK;
+}
+
+#define REG_A3XX_RB_MSAA_CONTROL                                0x000020c2
+#define A3XX_RB_MSAA_CONTROL_DISABLE                            0x00000400
+#define A3XX_RB_MSAA_CONTROL_SAMPLES__MASK                      0x0000f000
+#define A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT                     12
+static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val)
+{
+        return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK;
+}
+#define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK                  0xffff0000
+#define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT                 16
+static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val)
+{
+        return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK;
+}
+
+#define REG_A3XX_UNKNOWN_20C3                                   0x000020c3
+
+static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
+
+static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
+#define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE                    0x00000008
+#define A3XX_RB_MRT_CONTROL_BLEND                               0x00000010
+#define A3XX_RB_MRT_CONTROL_BLEND2                              0x00000020
+#define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK                      0x00000f00
+#define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT                     8
+static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(uint32_t val)
+{
+        return ((val) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK;
+}
+#define A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK                   0x00003000
+#define A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT                  12
+static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val)
+{
+        return ((val) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK;
+}
+#define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK              0x0f000000
+#define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT             24
+static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
+{
+        return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
+}
+
+static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; }
+#define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK                 0x0000003f
+#define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT                0
+static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val)
+{
+        return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
+}
+#define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK              0x000000c0
+#define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT             6
+static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val)
+{
+        return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
+}
+#define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK                   0x00000c00
+#define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT                  10
+static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
+{
+        return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
+}
+#define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK              0xfffe0000
+#define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT             17
+static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
+{
+        return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
+}
+
+static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; }
+#define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK               0xfffffff0
+#define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT              4
+static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val)
+{
+        return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK;
+}
+
+static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; }
+#define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK          0x0000001f
+#define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT         0
+static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
+{
+        return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
+}
+#define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK        0x000000e0
+#define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT       5
+static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum adreno_rb_blend_opcode val)
+{
+        return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
+}
+#define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK         0x00001f00
+#define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT        8
+static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
+{
+        return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
+}
+#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK        0x001f0000
+#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT       16
+static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
+{
+        return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
+}
+#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK      0x00e00000
+#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT     21
+static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum adreno_rb_blend_opcode val)
+{
+        return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
+}
+#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK       0x1f000000
+#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT      24
+static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
+{
+        return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
+}
+#define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE                  0x20000000
+
+#define REG_A3XX_RB_BLEND_RED                                   0x000020e4
+#define A3XX_RB_BLEND_RED_UINT__MASK                            0x000000ff
+#define A3XX_RB_BLEND_RED_UINT__SHIFT                           0
+static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val)
+{
+        return ((val) << A3XX_RB_BLEND_RED_UINT__SHIFT) & A3XX_RB_BLEND_RED_UINT__MASK;
+}
+#define A3XX_RB_BLEND_RED_FLOAT__MASK                           0xffff0000
+#define A3XX_RB_BLEND_RED_FLOAT__SHIFT                          16
+static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val)
+{
+        return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK;
+}
+
+#define REG_A3XX_RB_BLEND_GREEN                                 0x000020e5
+#define A3XX_RB_BLEND_GREEN_UINT__MASK                          0x000000ff
+#define A3XX_RB_BLEND_GREEN_UINT__SHIFT                         0
+static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val)
+{
+        return ((val) << A3XX_RB_BLEND_GREEN_UINT__SHIFT) & A3XX_RB_BLEND_GREEN_UINT__MASK;
+}
+#define A3XX_RB_BLEND_GREEN_FLOAT__MASK                         0xffff0000
+#define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT                        16
+static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val)
+{
+        return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK;
+}
+
+#define REG_A3XX_RB_BLEND_BLUE                                  0x000020e6
+#define A3XX_RB_BLEND_BLUE_UINT__MASK                           0x000000ff
+#define A3XX_RB_BLEND_BLUE_UINT__SHIFT                          0
+static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val)
+{
+        return ((val) << A3XX_RB_BLEND_BLUE_UINT__SHIFT) & A3XX_RB_BLEND_BLUE_UINT__MASK;
+}
+#define A3XX_RB_BLEND_BLUE_FLOAT__MASK                          0xffff0000
+#define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT                         16
+static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val)
+{
+        return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK;
+}
+
+#define REG_A3XX_RB_BLEND_ALPHA                                 0x000020e7
+#define A3XX_RB_BLEND_ALPHA_UINT__MASK                          0x000000ff
+#define A3XX_RB_BLEND_ALPHA_UINT__SHIFT                         0
+static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val)
+{
+        return ((val) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT) & A3XX_RB_BLEND_ALPHA_UINT__MASK;
+}
+#define A3XX_RB_BLEND_ALPHA_FLOAT__MASK                         0xffff0000
+#define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT                        16
+static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val)
+{
+        return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;
+}
+
+#define REG_A3XX_UNKNOWN_20E8                                   0x000020e8
+
+#define REG_A3XX_UNKNOWN_20E9                                   0x000020e9
+
+#define REG_A3XX_UNKNOWN_20EA                                   0x000020ea
+
+#define REG_A3XX_UNKNOWN_20EB                                   0x000020eb
+
+#define REG_A3XX_RB_COPY_CONTROL                                0x000020ec
+#define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK                 0x00000003
+#define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT                0
+static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
+{
+        return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
+}
+#define A3XX_RB_COPY_CONTROL_MODE__MASK                         0x00000070
+#define A3XX_RB_COPY_CONTROL_MODE__SHIFT                        4
+static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
+{
+        return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK;
+}
+#define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK                    0xfffffc00
+#define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT                   10
+static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
+{
+        return ((val >> 10) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
+}
+
+#define REG_A3XX_RB_COPY_DEST_BASE                              0x000020ed
+#define A3XX_RB_COPY_DEST_BASE_BASE__MASK                       0xfffffff0
+#define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT                      4
+static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
+{
+        return ((val >> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK;
+}
+
+#define REG_A3XX_RB_COPY_DEST_PITCH                             0x000020ee
+#define A3XX_RB_COPY_DEST_PITCH_PITCH__MASK                     0xffffffff
+#define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT                    0
+static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
+{
+        return ((val >> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK;
+}
+
+#define REG_A3XX_RB_COPY_DEST_INFO                              0x000020ef
+#define A3XX_RB_COPY_DEST_INFO_TILE__MASK                       0x00000003
+#define A3XX_RB_COPY_DEST_INFO_TILE__SHIFT                      0
+static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val)
+{
+        return ((val) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A3XX_RB_COPY_DEST_INFO_TILE__MASK;
+}
+#define A3XX_RB_COPY_DEST_INFO_FORMAT__MASK                     0x000000fc
+#define A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT                    2
+static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val)
+{
+        return ((val) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK;
+}
+#define A3XX_RB_COPY_DEST_INFO_SWAP__MASK                       0x00000300
+#define A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT                      8
+static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
+{
+        return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK;
+}
+#define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK           0x0003c000
+#define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT          14
+static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
+{
+        return ((val) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK;
+}
+#define A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK                     0x001c0000
+#define A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT                    18
+static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
+{
+        return ((val) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK;
+}
+
+#define REG_A3XX_RB_DEPTH_CONTROL                               0x00002100
+#define A3XX_RB_DEPTH_CONTROL_Z_ENABLE                          0x00000002
+#define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE                    0x00000004
+#define A3XX_RB_DEPTH_CONTROL_EARLY_Z_ENABLE                    0x00000008
+#define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK                       0x00000070
+#define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT                      4
+static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
+{
+        return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
+}
+#define A3XX_RB_DEPTH_CONTROL_BF_ENABLE                         0x00000080
+#define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE                     0x80000000
+
+#define REG_A3XX_UNKNOWN_2101                                   0x00002101
+
+#define REG_A3XX_RB_DEPTH_INFO                                  0x00002102
+#define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK                   0x00000001
+#define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT                  0
+static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val)
+{
+        return ((val) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
+}
+#define A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK                     0xfffff800
+#define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT                    11
+static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
+{
+        return ((val >> 10) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
+}
+
+#define REG_A3XX_RB_DEPTH_PITCH                                 0x00002103
+#define A3XX_RB_DEPTH_PITCH__MASK                               0xffffffff
+#define A3XX_RB_DEPTH_PITCH__SHIFT                              0
+static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val)
+{
+        return ((val >> 3) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK;
+}
+
+#define REG_A3XX_RB_STENCIL_CONTROL                             0x00002104
+#define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE                  0x00000001
+#define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF               0x00000004
+#define A3XX_RB_STENCIL_CONTROL_FUNC__MASK                      0x00000700
+#define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT                     8
+static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
+{
+        return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK;
+}
+#define A3XX_RB_STENCIL_CONTROL_FAIL__MASK                      0x00003800
+#define A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT                     11
+static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
+{
+        return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK;
+}
+#define A3XX_RB_STENCIL_CONTROL_ZPASS__MASK                     0x0001c000
+#define A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT                    14
+static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
+{
+        return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK;
+}
+#define A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK                     0x000e0000
+#define A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT                    17
+static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
+{
+        return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
+}
+#define A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK                   0x00700000
+#define A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT                  20
+static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
+{
+        return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
+}
+#define A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK                   0x03800000
+#define A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT                  23
+static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
+{
+        return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
+}
+#define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK                  0x1c000000
+#define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT                 26
+static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
+{
+        return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
+}
+#define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK                  0xe0000000
+#define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT                 29
+static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
+{
+        return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
+}
+
+#define REG_A3XX_UNKNOWN_2105                                   0x00002105
+
+#define REG_A3XX_UNKNOWN_2106                                   0x00002106
+
+#define REG_A3XX_UNKNOWN_2107                                   0x00002107
+
+#define REG_A3XX_RB_STENCILREFMASK                              0x00002108
+#define A3XX_RB_STENCILREFMASK_STENCILREF__MASK                 0x000000ff
+#define A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT                0
+static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
+{
+        return ((val) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK;
+}
+#define A3XX_RB_STENCILREFMASK_STENCILMASK__MASK                0x0000ff00
+#define A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT               8
+static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
+{
+        return ((val) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK;
+}
+#define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK           0x00ff0000
+#define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT          16
+static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
+{
+        return ((val) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
+}
+
+#define REG_A3XX_RB_STENCILREFMASK_BF                           0x00002109
+#define A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK              0x000000ff
+#define A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT             0
+static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
+{
+        return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
+}
+#define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK             0x0000ff00
+#define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT            8
+static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
+{
+        return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
+}
+#define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK        0x00ff0000
+#define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT       16
+static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
+{
+        return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
+}
+
+#define REG_A3XX_PA_SC_WINDOW_OFFSET                            0x0000210e
+#define A3XX_PA_SC_WINDOW_OFFSET_X__MASK                        0x0000ffff
+#define A3XX_PA_SC_WINDOW_OFFSET_X__SHIFT                       0
+static inline uint32_t A3XX_PA_SC_WINDOW_OFFSET_X(uint32_t val)
+{
+        return ((val) << A3XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A3XX_PA_SC_WINDOW_OFFSET_X__MASK;
+}
+#define A3XX_PA_SC_WINDOW_OFFSET_Y__MASK                        0xffff0000
+#define A3XX_PA_SC_WINDOW_OFFSET_Y__SHIFT                       16
+static inline uint32_t A3XX_PA_SC_WINDOW_OFFSET_Y(uint32_t val)
+{
+        return ((val) << A3XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A3XX_PA_SC_WINDOW_OFFSET_Y__MASK;
+}
+
+#define REG_A3XX_PC_VSTREAM_CONTROL                             0x000021e4
+
+#define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL                     0x000021ea
+
+#define REG_A3XX_PC_PRIM_VTX_CNTL                               0x000021ec
+#define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK               0x0000001f
+#define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT              0
+static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val)
+{
+        return ((val) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK;
+}
+#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK        0x000000e0
+#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT       5
+static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
+{
+        return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK;
+}
+#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK         0x00000700
+#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT        8
+static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
+{
+        return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK;
+}
+#define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST                0x02000000
+
+#define REG_A3XX_PC_RESTART_INDEX                               0x000021ed
+
+#define REG_A3XX_HLSQ_CONTROL_0_REG                             0x00002200
+#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK              0x00000010
+#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT             4
+static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
+{
+        return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
+}
+#define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE             0x00000040
+#define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART                 0x00000200
+#define A3XX_HLSQ_CONTROL_0_REG_RESERVED2                       0x00000400
+#define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE                    0x04000000
+#define A3XX_HLSQ_CONTROL_0_REG_CONSTSWITCHMODE                 0x08000000
+#define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE               0x10000000
+#define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE               0x20000000
+#define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE                    0x40000000
+#define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT                   0x80000000
+
+#define REG_A3XX_HLSQ_CONTROL_1_REG                             0x00002201
+#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK              0x00000040
+#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT             6
+static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
+{
+        return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
+}
+#define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE             0x00000100
+#define A3XX_HLSQ_CONTROL_1_REG_RESERVED1                       0x00000200
+
+#define REG_A3XX_HLSQ_CONTROL_2_REG                             0x00002202
+#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK        0xfc000000
+#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT       26
+static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
+}
+
+#define REG_A3XX_HLSQ_CONTROL_3_REG                             0x00002203
+
+#define REG_A3XX_HLSQ_VS_CONTROL_REG                            0x00002204
+#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK              0x00000fff
+#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT             0
+static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
+}
+#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK         0x00fff000
+#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT        12
+static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK;
+}
+#define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK              0xff000000
+#define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT             24
+static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
+}
+
+#define REG_A3XX_HLSQ_FS_CONTROL_REG                            0x00002205
+#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK              0x00000fff
+#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT             0
+static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
+}
+#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK         0x00fff000
+#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT        12
+static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK;
+}
+#define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK              0xff000000
+#define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT             24
+static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
+}
+
+#define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG                   0x00002206
+#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK      0x0000ffff
+#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT     0
+static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK;
+}
+#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK        0xffff0000
+#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT       16
+static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK;
+}
+
+#define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG                   0x00002207
+#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK      0x0000ffff
+#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT     0
+static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK;
+}
+#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK        0xffff0000
+#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT       16
+static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
+{
+        return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK;
+}
+
+#define REG_A3XX_HLSQ_CL_NDRANGE_0_REG                          0x0000220a
+
+#define REG_A3XX_HLSQ_CL_NDRANGE_1_REG                          0x0000220b
+
+#define REG_A3XX_HLSQ_CL_NDRANGE_2_REG                          0x0000220c
+
+#define REG_A3XX_HLSQ_CL_CONTROL_0_REG                          0x00002211
+
+#define REG_A3XX_HLSQ_CL_CONTROL_1_REG                          0x00002212
+
+#define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG                       0x00002214
+
+#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG                     0x00002215
+
+#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG                     0x00002217
+
+#define REG_A3XX_HLSQ_CL_WG_OFFSET_REG                          0x0000221a
+
+#define REG_A3XX_VFD_CONTROL_0                                  0x00002240
+#define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK                  0x0003ffff
+#define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT                 0
+static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
+{
+        return ((val) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK;
+}
+#define A3XX_VFD_CONTROL_0_PACKETSIZE__MASK                     0x003c0000
+#define A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT                    18
+static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val)
+{
+        return ((val) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK;
+}
+#define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK                0x07c00000
+#define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT               22
+static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
+{
+        return ((val) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK;
+}
+#define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK              0xf8000000
+#define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT             27
+static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
+{
+        return ((val) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
+}
+
+#define REG_A3XX_VFD_CONTROL_1                                  0x00002241
+#define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK                     0x0000ffff
+#define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT                    0
+static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
+{
+        return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
+}
+#define A3XX_VFD_CONTROL_1_REGID4VTX__MASK                      0x00ff0000
+#define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT                     16
+static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
+{
+        return ((val) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK;
+}
+#define A3XX_VFD_CONTROL_1_REGID4INST__MASK                     0xff000000
+#define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT                    24
+static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
+{
+        return ((val) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A3XX_VFD_CONTROL_1_REGID4INST__MASK;
+}
+
+#define REG_A3XX_VFD_INDEX_MIN                                  0x00002242
+
+#define REG_A3XX_VFD_INDEX_MAX                                  0x00002243
+
+#define REG_A3XX_VFD_INSTANCEID_OFFSET                          0x00002244
+
+#define REG_A3XX_VFD_INDEX_OFFSET                               0x00002245
+
+static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; }
+
+static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; }
+#define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK                  0x0000007f
+#define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT                 0
+static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
+{
+        return ((val) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK;
+}
+#define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK                  0x0001ff80
+#define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT                 7
+static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
+{
+        return ((val) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
+}
+#define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT                       0x00020000
+#define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK                  0x00fc0000
+#define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT                 18
+static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val)
+{
+        return ((val) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK;
+}
+#define A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK                   0xff000000
+#define A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT                  24
+static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val)
+{
+        return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK;
+}
+
+static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; }
+
+static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; }
+
+static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; }
+#define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK                   0x0000000f
+#define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT                  0
+static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
+{
+        return ((val) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK;
+}
+#define A3XX_VFD_DECODE_INSTR_CONSTFILL                         0x00000010
+#define A3XX_VFD_DECODE_INSTR_FORMAT__MASK                      0x00000fc0
+#define A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT                     6
+static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val)
+{
+        return ((val) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK;
+}
+#define A3XX_VFD_DECODE_INSTR_REGID__MASK                       0x000ff000
+#define A3XX_VFD_DECODE_INSTR_REGID__SHIFT                      12
+static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val)
+{
+        return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK;
+}
+#define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK                    0x1f000000
+#define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT                   24
+static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
+{
+        return ((val) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK;
+}
+#define A3XX_VFD_DECODE_INSTR_LASTCOMPVALID                     0x20000000
+#define A3XX_VFD_DECODE_INSTR_SWITCHNEXT                        0x40000000
+
+#define REG_A3XX_VFD_VS_THREADING_THRESHOLD                     0x0000227e
+#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK   0x0000000f
+#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT  0
+static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val)
+{
+        return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK;
+}
+#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK      0x0000ff00
+#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT     8
+static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val)
+{
+        return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK;
+}
+
+#define REG_A3XX_VPC_ATTR                                       0x00002280
+#define A3XX_VPC_ATTR_TOTALATTR__MASK                           0x00000fff
+#define A3XX_VPC_ATTR_TOTALATTR__SHIFT                          0
+static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val)
+{
+        return ((val) << A3XX_VPC_ATTR_TOTALATTR__SHIFT) & A3XX_VPC_ATTR_TOTALATTR__MASK;
+}
+#define A3XX_VPC_ATTR_THRDASSIGN__MASK                          0x0ffff000
+#define A3XX_VPC_ATTR_THRDASSIGN__SHIFT                         12
+static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val)
+{
+        return ((val) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT) & A3XX_VPC_ATTR_THRDASSIGN__MASK;
+}
+#define A3XX_VPC_ATTR_LMSIZE__MASK                              0xf0000000
+#define A3XX_VPC_ATTR_LMSIZE__SHIFT                             28
+static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val)
+{
+        return ((val) << A3XX_VPC_ATTR_LMSIZE__SHIFT) & A3XX_VPC_ATTR_LMSIZE__MASK;
+}
+
+#define REG_A3XX_VPC_PACK                                       0x00002281
+#define A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK                      0x0000ff00
+#define A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT                     8
+static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
+{
+        return ((val) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK;
+}
+#define A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK                      0x00ff0000
+#define A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT                     16
+static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
+{
+        return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
+}
+
+static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; }
+
+static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; }
+
+static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; }
+
+static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; }
+
+#define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0                      0x0000228a
+
+#define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1                      0x0000228b
+
+#define REG_A3XX_SP_SP_CTRL_REG                                 0x000022c0
+#define A3XX_SP_SP_CTRL_REG_RESOLVE                             0x00010000
+#define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK                     0x000c0000
+#define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT                    18
+static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val)
+{
+        return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK;
+}
+#define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK                     0x00300000
+#define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT                    20
+static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val)
+{
+        return ((val) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK;
+}
+#define A3XX_SP_SP_CTRL_REG_LOMODE__MASK                        0x00c00000
+#define A3XX_SP_SP_CTRL_REG_LOMODE__SHIFT                       22
+static inline uint32_t A3XX_SP_SP_CTRL_REG_LOMODE(uint32_t val)
+{
+        return ((val) << A3XX_SP_SP_CTRL_REG_LOMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_LOMODE__MASK;
+}
+
+#define REG_A3XX_SP_VS_CTRL_REG0                                0x000022c4
+#define A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK                   0x00000001
+#define A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT                  0
+static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
+{
+        return ((val) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
+}
+#define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK              0x00000002
+#define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT             1
+static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val)
+{
+        return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK;
+}
+#define A3XX_SP_VS_CTRL_REG0_CACHEINVALID                       0x00000004
+#define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x000003f0
+#define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            4
+static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
+}
+#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x0003fc00
+#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            10
+static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
+}
+#define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK              0x000c0000
+#define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT             18
+static inline uint32_t A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK;
+}
+#define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK                   0x00100000
+#define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT                  20
+static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
+{
+        return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
+}
+#define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE                    0x00200000
+#define A3XX_SP_VS_CTRL_REG0_PIXLODENABLE                       0x00400000
+#define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK                       0xff000000
+#define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT                      24
+static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK;
+}
+
+#define REG_A3XX_SP_VS_CTRL_REG1                                0x000022c5
+#define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK                  0x000003ff
+#define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT                 0
+static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK;
+}
+#define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK               0x000ffc00
+#define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT              10
+static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK;
+}
+#define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK           0x3f000000
+#define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT          24
+static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK;
+}
+
+#define REG_A3XX_SP_VS_PARAM_REG                                0x000022c6
+#define A3XX_SP_VS_PARAM_REG_POSREGID__MASK                     0x000000ff
+#define A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT                    0
+static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK;
+}
+#define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK                   0x0000ff00
+#define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT                  8
+static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
+}
+#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK                0xfff00000
+#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT               20
+static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
+}
+
+static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
+
+static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
+#define A3XX_SP_VS_OUT_REG_A_REGID__MASK                        0x000001ff
+#define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT                       0
+static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK;
+}
+#define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK                     0x00001e00
+#define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT                    9
+static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
+}
+#define A3XX_SP_VS_OUT_REG_B_REGID__MASK                        0x01ff0000
+#define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT                       16
+static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK;
+}
+#define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK                     0x1e000000
+#define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT                    25
+static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
+}
+
+static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
+
+static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
+#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK                    0x000000ff
+#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT                   0
+static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
+}
+#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK                    0x0000ff00
+#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT                   8
+static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
+}
+#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK                    0x00ff0000
+#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT                   16
+static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
+}
+#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK                    0xff000000
+#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT                   24
+static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
+}
+
+#define REG_A3XX_SP_VS_OBJ_OFFSET_REG                           0x000022d4
+#define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK       0x01ff0000
+#define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT      16
+static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
+}
+#define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK         0xfe000000
+#define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT        25
+static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
+}
+
+#define REG_A3XX_SP_VS_OBJ_START_REG                            0x000022d5
+
+#define REG_A3XX_SP_VS_PVT_MEM_CTRL_REG                         0x000022d6
+
+#define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG                         0x000022d7
+
+#define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG                         0x000022d8
+
+#define REG_A3XX_SP_VS_LENGTH_REG                               0x000022df
+#define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK                0xffffffff
+#define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT               0
+static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val)
+{
+        return ((val) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK;
+}
+
+#define REG_A3XX_SP_FS_CTRL_REG0                                0x000022e0
+#define A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK                   0x00000001
+#define A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT                  0
+static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
+{
+        return ((val) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
+}
+#define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK              0x00000002
+#define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT             1
+static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val)
+{
+        return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK;
+}
+#define A3XX_SP_FS_CTRL_REG0_CACHEINVALID                       0x00000004
+#define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK             0x000003f0
+#define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT            4
+static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
+}
+#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK             0x0003fc00
+#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT            10
+static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
+}
+#define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK              0x000c0000
+#define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT             18
+static inline uint32_t A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK;
+}
+#define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK                   0x00100000
+#define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT                  20
+static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
+{
+        return ((val) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
+}
+#define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE                    0x00200000
+#define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE                       0x00400000
+#define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK                       0xff000000
+#define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT                      24
+static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK;
+}
+
+#define REG_A3XX_SP_FS_CTRL_REG1                                0x000022e1
+#define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK                  0x000003ff
+#define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT                 0
+static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
+}
+#define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK               0x000ffc00
+#define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT              10
+static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK;
+}
+#define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK           0x00f00000
+#define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT          20
+static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK;
+}
+#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK            0x3f000000
+#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT           24
+static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK;
+}
+
+#define REG_A3XX_SP_FS_OBJ_OFFSET_REG                           0x000022e2
+#define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK       0x01ff0000
+#define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT      16
+static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
+}
+#define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK         0xfe000000
+#define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT        25
+static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
+}
+
+#define REG_A3XX_SP_FS_OBJ_START_REG                            0x000022e3
+
+#define REG_A3XX_SP_FS_PVT_MEM_CTRL_REG                         0x000022e4
+
+#define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG                         0x000022e5
+
+#define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG                         0x000022e6
+
+#define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0                     0x000022e8
+
+#define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1                     0x000022e9
+
+#define REG_A3XX_SP_FS_OUTPUT_REG                               0x000022ec
+
+static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; }
+
+static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; }
+#define A3XX_SP_FS_MRT_REG_REGID__MASK                          0x000000ff
+#define A3XX_SP_FS_MRT_REG_REGID__SHIFT                         0
+static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_MRT_REG_REGID__SHIFT) & A3XX_SP_FS_MRT_REG_REGID__MASK;
+}
+#define A3XX_SP_FS_MRT_REG_HALF_PRECISION                       0x00000100
+
+static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; }
+
+static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; }
+#define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK             0x0000003f
+#define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT            0
+static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val)
+{
+        return ((val) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK;
+}
+
+#define REG_A3XX_SP_FS_LENGTH_REG                               0x000022ff
+#define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK                0xffffffff
+#define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT               0
+static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val)
+{
+        return ((val) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK;
+}
+
+#define REG_A3XX_TPL1_TP_VS_TEX_OFFSET                          0x00002340
+#define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK          0x000000ff
+#define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT         0
+static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val)
+{
+        return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK;
+}
+#define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK           0x0000ff00
+#define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT          8
+static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val)
+{
+        return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK;
+}
+#define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK           0xffff0000
+#define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT          16
+static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val)
+{
+        return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK;
+}
+
+#define REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR              0x00002341
+
+#define REG_A3XX_TPL1_TP_FS_TEX_OFFSET                          0x00002342
+#define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK          0x000000ff
+#define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT         0
+static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val)
+{
+        return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK;
+}
+#define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK           0x0000ff00
+#define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT          8
+static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val)
+{
+        return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK;
+}
+#define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK           0xffff0000
+#define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT          16
+static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val)
+{
+        return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK;
+}
+
+#define REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR              0x00002343
+
+#define REG_A3XX_VBIF_CLKON                                     0x00003001
+
+#define REG_A3XX_VBIF_FIXED_SORT_EN                             0x0000300c
+
+#define REG_A3XX_VBIF_FIXED_SORT_SEL0                           0x0000300d
+
+#define REG_A3XX_VBIF_FIXED_SORT_SEL1                           0x0000300e
+
+#define REG_A3XX_VBIF_ABIT_SORT                                 0x0000301c
+
+#define REG_A3XX_VBIF_ABIT_SORT_CONF                            0x0000301d
+
+#define REG_A3XX_VBIF_GATE_OFF_WRREQ_EN                         0x0000302a
+
+#define REG_A3XX_VBIF_IN_RD_LIM_CONF0                           0x0000302c
+
+#define REG_A3XX_VBIF_IN_RD_LIM_CONF1                           0x0000302d
+
+#define REG_A3XX_VBIF_IN_WR_LIM_CONF0                           0x00003030
+
+#define REG_A3XX_VBIF_IN_WR_LIM_CONF1                           0x00003031
+
+#define REG_A3XX_VBIF_OUT_RD_LIM_CONF0                          0x00003034
+
+#define REG_A3XX_VBIF_OUT_WR_LIM_CONF0                          0x00003035
+
+#define REG_A3XX_VBIF_DDR_OUT_MAX_BURST                         0x00003036
+
+#define REG_A3XX_VBIF_ARB_CTL                                   0x0000303c
+
+#define REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB                       0x00003049
+
+#define REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0                    0x00003058
+
+#define REG_A3XX_VBIF_OUT_AXI_AOOO_EN                           0x0000305e
+
+#define REG_A3XX_VBIF_OUT_AXI_AOOO                              0x0000305f
+
+#define REG_A3XX_VSC_BIN_SIZE                                   0x00000c01
+#define A3XX_VSC_BIN_SIZE_WIDTH__MASK                           0x0000001f
+#define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT                          0
+static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
+{
+        return ((val >> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK;
+}
+#define A3XX_VSC_BIN_SIZE_HEIGHT__MASK                          0x000003e0
+#define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT                         5
+static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
+{
+        return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK;
+}
+
+#define REG_A3XX_VSC_SIZE_ADDRESS                               0x00000c02
+
+static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
+
+static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
+#define A3XX_VSC_PIPE_CONFIG_X__MASK                            0x000003ff
+#define A3XX_VSC_PIPE_CONFIG_X__SHIFT                           0
+static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val)
+{
+        return ((val) << A3XX_VSC_PIPE_CONFIG_X__SHIFT) & A3XX_VSC_PIPE_CONFIG_X__MASK;
+}
+#define A3XX_VSC_PIPE_CONFIG_Y__MASK                            0x000ffc00
+#define A3XX_VSC_PIPE_CONFIG_Y__SHIFT                           10
+static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val)
+{
+        return ((val) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT) & A3XX_VSC_PIPE_CONFIG_Y__MASK;
+}
+#define A3XX_VSC_PIPE_CONFIG_W__MASK                            0x00f00000
+#define A3XX_VSC_PIPE_CONFIG_W__SHIFT                           20
+static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val)
+{
+        return ((val) << A3XX_VSC_PIPE_CONFIG_W__SHIFT) & A3XX_VSC_PIPE_CONFIG_W__MASK;
+}
+#define A3XX_VSC_PIPE_CONFIG_H__MASK                            0x0f000000
+#define A3XX_VSC_PIPE_CONFIG_H__SHIFT                           24
+static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val)
+{
+        return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK;
+}
+
+static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; }
+
+static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }
+
+#define REG_A3XX_UNKNOWN_0C3D                                   0x00000c3d
+
+#define REG_A3XX_PC_PERFCOUNTER0_SELECT                         0x00000c48
+
+#define REG_A3XX_PC_PERFCOUNTER1_SELECT                         0x00000c49
+
+#define REG_A3XX_PC_PERFCOUNTER2_SELECT                         0x00000c4a
+
+#define REG_A3XX_PC_PERFCOUNTER3_SELECT                         0x00000c4b
+
+#define REG_A3XX_UNKNOWN_0C81                                   0x00000c81
+
+#define REG_A3XX_GRAS_PERFCOUNTER0_SELECT                       0x00000c88
+
+#define REG_A3XX_GRAS_PERFCOUNTER1_SELECT                       0x00000c89
+
+#define REG_A3XX_GRAS_PERFCOUNTER2_SELECT                       0x00000c8a
+
+#define REG_A3XX_GRAS_PERFCOUNTER3_SELECT                       0x00000c8b
+
+static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; }
+
+static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; }
+
+static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; }
+
+static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; }
+
+static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; }
+
+#define REG_A3XX_RB_GMEM_BASE_ADDR                              0x00000cc0
+
+#define REG_A3XX_RB_PERFCOUNTER0_SELECT                         0x00000cc6
+
+#define REG_A3XX_RB_PERFCOUNTER1_SELECT                         0x00000cc7
+
+#define REG_A3XX_RB_WINDOW_SIZE                                 0x00000ce0
+#define A3XX_RB_WINDOW_SIZE_WIDTH__MASK                         0x00003fff
+#define A3XX_RB_WINDOW_SIZE_WIDTH__SHIFT                        0
+static inline uint32_t A3XX_RB_WINDOW_SIZE_WIDTH(uint32_t val)
+{
+        return ((val) << A3XX_RB_WINDOW_SIZE_WIDTH__SHIFT) & A3XX_RB_WINDOW_SIZE_WIDTH__MASK;
+}
+#define A3XX_RB_WINDOW_SIZE_HEIGHT__MASK                        0x0fffc000
+#define A3XX_RB_WINDOW_SIZE_HEIGHT__SHIFT                       14
+static inline uint32_t A3XX_RB_WINDOW_SIZE_HEIGHT(uint32_t val)
+{
+        return ((val) << A3XX_RB_WINDOW_SIZE_HEIGHT__SHIFT) & A3XX_RB_WINDOW_SIZE_HEIGHT__MASK;
+}
+
+#define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT                       0x00000e00
+
+#define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT                       0x00000e01
+
+#define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT                       0x00000e02
+
+#define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT                       0x00000e03
+
+#define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT                       0x00000e04
+
+#define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT                       0x00000e05
+
+#define REG_A3XX_UNKNOWN_0E43                                   0x00000e43
+
+#define REG_A3XX_VFD_PERFCOUNTER0_SELECT                        0x00000e44
+
+#define REG_A3XX_VFD_PERFCOUNTER1_SELECT                        0x00000e45
+
+#define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL                          0x00000e61
+
+#define REG_A3XX_VPC_VPC_DEBUG_RAM_READ                         0x00000e62
+
+#define REG_A3XX_VPC_PERFCOUNTER0_SELECT                        0x00000e64
+
+#define REG_A3XX_VPC_PERFCOUNTER1_SELECT                        0x00000e65
+
+#define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG                    0x00000e82
+
+#define REG_A3XX_UCHE_PERFCOUNTER0_SELECT                       0x00000e84
+
+#define REG_A3XX_UCHE_PERFCOUNTER1_SELECT                       0x00000e85
+
+#define REG_A3XX_UCHE_PERFCOUNTER2_SELECT                       0x00000e86
+
+#define REG_A3XX_UCHE_PERFCOUNTER3_SELECT                       0x00000e87
+
+#define REG_A3XX_UCHE_PERFCOUNTER4_SELECT                       0x00000e88
+
+#define REG_A3XX_UCHE_PERFCOUNTER5_SELECT                       0x00000e89
+
+#define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG                     0x00000ea0
+#define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK              0x0fffffff
+#define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT             0
+static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val)
+{
+        return ((val) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK;
+}
+
+#define REG_A3XX_UCHE_CACHE_INVALIDATE1_REG                     0x00000ea1
+#define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK              0x0fffffff
+#define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT             0
+static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val)
+{
+        return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK;
+}
+#define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK            0x30000000
+#define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT           28
+static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val)
+{
+        return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK;
+}
+#define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE            0x80000000
+
+#define REG_A3XX_SP_PERFCOUNTER0_SELECT                         0x00000ec4
+
+#define REG_A3XX_SP_PERFCOUNTER1_SELECT                         0x00000ec5
+
+#define REG_A3XX_SP_PERFCOUNTER2_SELECT                         0x00000ec6
+
+#define REG_A3XX_SP_PERFCOUNTER3_SELECT                         0x00000ec7
+
+#define REG_A3XX_SP_PERFCOUNTER4_SELECT                         0x00000ec8
+
+#define REG_A3XX_SP_PERFCOUNTER5_SELECT                         0x00000ec9
+
+#define REG_A3XX_SP_PERFCOUNTER6_SELECT                         0x00000eca
+
+#define REG_A3XX_SP_PERFCOUNTER7_SELECT                         0x00000ecb
+
+#define REG_A3XX_UNKNOWN_0EE0                                   0x00000ee0
+
+#define REG_A3XX_UNKNOWN_0F03                                   0x00000f03
+
+#define REG_A3XX_TP_PERFCOUNTER0_SELECT                         0x00000f04
+
+#define REG_A3XX_TP_PERFCOUNTER1_SELECT                         0x00000f05
+
+#define REG_A3XX_TP_PERFCOUNTER2_SELECT                         0x00000f06
+
+#define REG_A3XX_TP_PERFCOUNTER3_SELECT                         0x00000f07
+
+#define REG_A3XX_TP_PERFCOUNTER4_SELECT                         0x00000f08
+
+#define REG_A3XX_TP_PERFCOUNTER5_SELECT                         0x00000f09
+
+#define REG_A3XX_TEX_SAMP_0                                     0x00000000
+#define A3XX_TEX_SAMP_0_XY_MAG__MASK                            0x0000000c
+#define A3XX_TEX_SAMP_0_XY_MAG__SHIFT                           2
+static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val)
+{
+        return ((val) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT) & A3XX_TEX_SAMP_0_XY_MAG__MASK;
+}
+#define A3XX_TEX_SAMP_0_XY_MIN__MASK                            0x00000030
+#define A3XX_TEX_SAMP_0_XY_MIN__SHIFT                           4
+static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val)
+{
+        return ((val) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT) & A3XX_TEX_SAMP_0_XY_MIN__MASK;
+}
+#define A3XX_TEX_SAMP_0_WRAP_S__MASK                            0x000001c0
+#define A3XX_TEX_SAMP_0_WRAP_S__SHIFT                           6
+static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val)
+{
+        return ((val) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT) & A3XX_TEX_SAMP_0_WRAP_S__MASK;
+}
+#define A3XX_TEX_SAMP_0_WRAP_T__MASK                            0x00000e00
+#define A3XX_TEX_SAMP_0_WRAP_T__SHIFT                           9
+static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val)
+{
+        return ((val) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT) & A3XX_TEX_SAMP_0_WRAP_T__MASK;
+}
+#define A3XX_TEX_SAMP_0_WRAP_R__MASK                            0x00007000
+#define A3XX_TEX_SAMP_0_WRAP_R__SHIFT                           12
+static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val)
+{
+        return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK;
+}
+#define A3XX_TEX_SAMP_0_UNNORM_COORDS                           0x80000000
+
+#define REG_A3XX_TEX_SAMP_1                                     0x00000001
+
+#define REG_A3XX_TEX_CONST_0                                    0x00000000
+#define A3XX_TEX_CONST_0_TILED                                  0x00000001
+#define A3XX_TEX_CONST_0_SWIZ_X__MASK                           0x00000070
+#define A3XX_TEX_CONST_0_SWIZ_X__SHIFT                          4
+static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val)
+{
+        return ((val) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT) & A3XX_TEX_CONST_0_SWIZ_X__MASK;
+}
+#define A3XX_TEX_CONST_0_SWIZ_Y__MASK                           0x00000380
+#define A3XX_TEX_CONST_0_SWIZ_Y__SHIFT                          7
+static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val)
+{
+        return ((val) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Y__MASK;
+}
+#define A3XX_TEX_CONST_0_SWIZ_Z__MASK                           0x00001c00
+#define A3XX_TEX_CONST_0_SWIZ_Z__SHIFT                          10
+static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val)
+{
+        return ((val) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Z__MASK;
+}
+#define A3XX_TEX_CONST_0_SWIZ_W__MASK                           0x0000e000
+#define A3XX_TEX_CONST_0_SWIZ_W__SHIFT                          13
+static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val)
+{
+        return ((val) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT) & A3XX_TEX_CONST_0_SWIZ_W__MASK;
+}
+#define A3XX_TEX_CONST_0_FMT__MASK                              0x1fc00000
+#define A3XX_TEX_CONST_0_FMT__SHIFT                             22
+static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val)
+{
+        return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK;
+}
+#define A3XX_TEX_CONST_0_TYPE__MASK                             0xc0000000
+#define A3XX_TEX_CONST_0_TYPE__SHIFT                            30
+static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val)
+{
+        return ((val) << A3XX_TEX_CONST_0_TYPE__SHIFT) & A3XX_TEX_CONST_0_TYPE__MASK;
+}
+
+#define REG_A3XX_TEX_CONST_1                                    0x00000001
+#define A3XX_TEX_CONST_1_HEIGHT__MASK                           0x00003fff
+#define A3XX_TEX_CONST_1_HEIGHT__SHIFT                          0
+static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val)
+{
+        return ((val) << A3XX_TEX_CONST_1_HEIGHT__SHIFT) & A3XX_TEX_CONST_1_HEIGHT__MASK;
+}
+#define A3XX_TEX_CONST_1_WIDTH__MASK                            0x0fffc000
+#define A3XX_TEX_CONST_1_WIDTH__SHIFT                           14
+static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val)
+{
+        return ((val) << A3XX_TEX_CONST_1_WIDTH__SHIFT) & A3XX_TEX_CONST_1_WIDTH__MASK;
+}
+#define A3XX_TEX_CONST_1_FETCHSIZE__MASK                        0xf0000000
+#define A3XX_TEX_CONST_1_FETCHSIZE__SHIFT                       28
+static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val)
+{
+        return ((val) << A3XX_TEX_CONST_1_FETCHSIZE__SHIFT) & A3XX_TEX_CONST_1_FETCHSIZE__MASK;
+}
+
+#define REG_A3XX_TEX_CONST_2                                    0x00000002
+#define A3XX_TEX_CONST_2_INDX__MASK                             0x000000ff
+#define A3XX_TEX_CONST_2_INDX__SHIFT                            0
+static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val)
+{
+        return ((val) << A3XX_TEX_CONST_2_INDX__SHIFT) & A3XX_TEX_CONST_2_INDX__MASK;
+}
+#define A3XX_TEX_CONST_2_PITCH__MASK                            0x3ffff000
+#define A3XX_TEX_CONST_2_PITCH__SHIFT                           12
+static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val)
+{
+        return ((val) << A3XX_TEX_CONST_2_PITCH__SHIFT) & A3XX_TEX_CONST_2_PITCH__MASK;
+}
+#define A3XX_TEX_CONST_2_SWAP__MASK                             0xc0000000
+#define A3XX_TEX_CONST_2_SWAP__SHIFT                            30
+static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
+{
+        return ((val) << A3XX_TEX_CONST_2_SWAP__SHIFT) & A3XX_TEX_CONST_2_SWAP__MASK;
+}
+
+#define REG_A3XX_TEX_CONST_3                                    0x00000003
+
+
+#endif /* A3XX_XML */
diff --git a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
new file mode 100644
index 000000000000..61979d458ac0
--- /dev/null
+++ b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
@@ -0,0 +1,432 @@
+#ifndef ADRENO_COMMON_XML
+#define ADRENO_COMMON_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml              (    327 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
+- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml           (  30005 bytes, from 2013-07-19 21:30:48)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml       (   8983 bytes, from 2013-07-24 01:38:36)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml          (   9712 bytes, from 2013-05-26 15:22:37)
+- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml           (  51415 bytes, from 2013-08-03 14:26:05)
+
+Copyright (C) 2013 by the following authors:
+- Rob Clark <robdclark@gmail.com> (robclark)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+enum adreno_pa_su_sc_draw {
+        PC_DRAW_POINTS = 0,
+        PC_DRAW_LINES = 1,
+        PC_DRAW_TRIANGLES = 2,
+};
+
+enum adreno_compare_func {
+        FUNC_NEVER = 0,
+        FUNC_LESS = 1,
+        FUNC_EQUAL = 2,
+        FUNC_LEQUAL = 3,
+        FUNC_GREATER = 4,
+        FUNC_NOTEQUAL = 5,
+        FUNC_GEQUAL = 6,
+        FUNC_ALWAYS = 7,
+};
+
+enum adreno_stencil_op {
+        STENCIL_KEEP = 0,
+        STENCIL_ZERO = 1,
+        STENCIL_REPLACE = 2,
+        STENCIL_INCR_CLAMP = 3,
+        STENCIL_DECR_CLAMP = 4,
+        STENCIL_INVERT = 5,
+        STENCIL_INCR_WRAP = 6,
+        STENCIL_DECR_WRAP = 7,
+};
+
+enum adreno_rb_blend_factor {
+        FACTOR_ZERO = 0,
+        FACTOR_ONE = 1,
+        FACTOR_SRC_COLOR = 4,
+        FACTOR_ONE_MINUS_SRC_COLOR = 5,
+        FACTOR_SRC_ALPHA = 6,
+        FACTOR_ONE_MINUS_SRC_ALPHA = 7,
+        FACTOR_DST_COLOR = 8,
+        FACTOR_ONE_MINUS_DST_COLOR = 9,
+        FACTOR_DST_ALPHA = 10,
+        FACTOR_ONE_MINUS_DST_ALPHA = 11,
+        FACTOR_CONSTANT_COLOR = 12,
+        FACTOR_ONE_MINUS_CONSTANT_COLOR = 13,
+        FACTOR_CONSTANT_ALPHA = 14,
+        FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15,
+        FACTOR_SRC_ALPHA_SATURATE = 16,
+};
+
+enum adreno_rb_blend_opcode {
+        BLEND_DST_PLUS_SRC = 0,
+        BLEND_SRC_MINUS_DST = 1,
+        BLEND_MIN_DST_SRC = 2,
+        BLEND_MAX_DST_SRC = 3,
+        BLEND_DST_MINUS_SRC = 4,
+        BLEND_DST_PLUS_SRC_BIAS = 5,
+};
+
+enum adreno_rb_surface_endian {
+        ENDIAN_NONE = 0,
+        ENDIAN_8IN16 = 1,
+        ENDIAN_8IN32 = 2,
+        ENDIAN_16IN32 = 3,
+        ENDIAN_8IN64 = 4,
+        ENDIAN_8IN128 = 5,
+};
+
+enum adreno_rb_dither_mode {
+        DITHER_DISABLE = 0,
+        DITHER_ALWAYS = 1,
+        DITHER_IF_ALPHA_OFF = 2,
+};
+
+enum adreno_rb_depth_format {
+        DEPTHX_16 = 0,
+        DEPTHX_24_8 = 1,
+};
+
+enum adreno_mmu_clnt_beh {
+        BEH_NEVR = 0,
+        BEH_TRAN_RNG = 1,
+        BEH_TRAN_FLT = 2,
+};
+
+#define REG_AXXX_MH_MMU_CONFIG                                  0x00000040
+#define AXXX_MH_MMU_CONFIG_MMU_ENABLE                           0x00000001
+#define AXXX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE                    0x00000002
+#define AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK             0x00000030
+#define AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT            4
+static inline uint32_t AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+        return ((val) << AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK;
+}
+#define AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK             0x000000c0
+#define AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT            6
+static inline uint32_t AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+        return ((val) << AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK;
+}
+#define AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK            0x00000300
+#define AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT           8
+static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+        return ((val) << AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK;
+}
+#define AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK            0x00000c00
+#define AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT           10
+static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+        return ((val) << AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK;
+}
+#define AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK            0x00003000
+#define AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT           12
+static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+        return ((val) << AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK;
+}
+#define AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK            0x0000c000
+#define AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT           14
+static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+        return ((val) << AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK;
+}
+#define AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK            0x00030000
+#define AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT           16
+static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+        return ((val) << AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK;
+}
+#define AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK           0x000c0000
+#define AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT          18
+static inline uint32_t AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+        return ((val) << AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK;
+}
+#define AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK           0x00300000
+#define AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT          20
+static inline uint32_t AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+        return ((val) << AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK;
+}
+#define AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK             0x00c00000
+#define AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT            22
+static inline uint32_t AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+        return ((val) << AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK;
+}
+#define AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK             0x03000000
+#define AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT            24
+static inline uint32_t AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
+{
+        return ((val) << AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK;
+}
+
+#define REG_AXXX_MH_MMU_VA_RANGE                                0x00000041
+
+#define REG_AXXX_MH_MMU_PT_BASE                                 0x00000042
+
+#define REG_AXXX_MH_MMU_PAGE_FAULT                              0x00000043
+
+#define REG_AXXX_MH_MMU_TRAN_ERROR                              0x00000044
+
+#define REG_AXXX_MH_MMU_INVALIDATE                              0x00000045
+
+#define REG_AXXX_MH_MMU_MPU_BASE                                0x00000046
+
+#define REG_AXXX_MH_MMU_MPU_END                                 0x00000047
+
+#define REG_AXXX_CP_RB_BASE                                     0x000001c0
+
+#define REG_AXXX_CP_RB_CNTL                                     0x000001c1
+#define AXXX_CP_RB_CNTL_BUFSZ__MASK                             0x0000003f
+#define AXXX_CP_RB_CNTL_BUFSZ__SHIFT                            0
+static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val)
+{
+        return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK;
+}
+#define AXXX_CP_RB_CNTL_BLKSZ__MASK                             0x00003f00
+#define AXXX_CP_RB_CNTL_BLKSZ__SHIFT                            8
+static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val)
+{
+        return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK;
+}
+#define AXXX_CP_RB_CNTL_BUF_SWAP__MASK                          0x00030000
+#define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT                         16
+static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val)
+{
+        return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK;
+}
+#define AXXX_CP_RB_CNTL_POLL_EN                                 0x00100000
+#define AXXX_CP_RB_CNTL_NO_UPDATE                               0x08000000
+#define AXXX_CP_RB_CNTL_RPTR_WR_EN                              0x80000000
+
+#define REG_AXXX_CP_RB_RPTR_ADDR                                0x000001c3
+#define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK                         0x00000003
+#define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT                        0
+static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val)
+{
+        return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK;
+}
+#define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK                         0xfffffffc
+#define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT                        2
+static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val)
+{
+        return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK;
+}
+
+#define REG_AXXX_CP_RB_RPTR                                     0x000001c4
+
+#define REG_AXXX_CP_RB_WPTR                                     0x000001c5
+
+#define REG_AXXX_CP_RB_WPTR_DELAY                               0x000001c6
+
+#define REG_AXXX_CP_RB_RPTR_WR                                  0x000001c7
+
+#define REG_AXXX_CP_RB_WPTR_BASE                                0x000001c8
+
+#define REG_AXXX_CP_QUEUE_THRESHOLDS                            0x000001d5
+#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK            0x0000000f
+#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT           0
+static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val)
+{
+        return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK;
+}
+#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK            0x00000f00
+#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT           8
+static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val)
+{
+        return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK;
+}
+#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK             0x000f0000
+#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT            16
+static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val)
+{
+        return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK;
+}
+
+#define REG_AXXX_CP_MEQ_THRESHOLDS                              0x000001d6
+
+#define REG_AXXX_CP_CSQ_AVAIL                                   0x000001d7
+#define AXXX_CP_CSQ_AVAIL_RING__MASK                            0x0000007f
+#define AXXX_CP_CSQ_AVAIL_RING__SHIFT                           0
+static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val)
+{
+        return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK;
+}
+#define AXXX_CP_CSQ_AVAIL_IB1__MASK                             0x00007f00
+#define AXXX_CP_CSQ_AVAIL_IB1__SHIFT                            8
+static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val)
+{
+        return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK;
+}
+#define AXXX_CP_CSQ_AVAIL_IB2__MASK                             0x007f0000
+#define AXXX_CP_CSQ_AVAIL_IB2__SHIFT                            16
+static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val)
+{
+        return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK;
+}
+
+#define REG_AXXX_CP_STQ_AVAIL                                   0x000001d8
+#define AXXX_CP_STQ_AVAIL_ST__MASK                              0x0000007f
+#define AXXX_CP_STQ_AVAIL_ST__SHIFT                             0
+static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val)
+{
+        return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK;
+}
+
+#define REG_AXXX_CP_MEQ_AVAIL                                   0x000001d9
+#define AXXX_CP_MEQ_AVAIL_MEQ__MASK                             0x0000001f
+#define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT                            0
+static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val)
+{
+        return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK;
+}
+
+#define REG_AXXX_SCRATCH_UMSK                                   0x000001dc
+#define AXXX_SCRATCH_UMSK_UMSK__MASK                            0x000000ff
+#define AXXX_SCRATCH_UMSK_UMSK__SHIFT                           0
+static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val)
+{
+        return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK;
+}
+#define AXXX_SCRATCH_UMSK_SWAP__MASK                            0x00030000
+#define AXXX_SCRATCH_UMSK_SWAP__SHIFT                           16
+static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val)
+{
+        return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK;
+}
+
+#define REG_AXXX_SCRATCH_ADDR                                   0x000001dd
+
+#define REG_AXXX_CP_ME_RDADDR                                   0x000001ea
+
+#define REG_AXXX_CP_STATE_DEBUG_INDEX                           0x000001ec
+
+#define REG_AXXX_CP_STATE_DEBUG_DATA                            0x000001ed
+
+#define REG_AXXX_CP_INT_CNTL                                    0x000001f2
+
+#define REG_AXXX_CP_INT_STATUS                                  0x000001f3
+
+#define REG_AXXX_CP_INT_ACK                                     0x000001f4
+
+#define REG_AXXX_CP_ME_CNTL                                     0x000001f6
+
+#define REG_AXXX_CP_ME_STATUS                                   0x000001f7
+
+#define REG_AXXX_CP_ME_RAM_WADDR                                0x000001f8
+
+#define REG_AXXX_CP_ME_RAM_RADDR                                0x000001f9
+
+#define REG_AXXX_CP_ME_RAM_DATA                                 0x000001fa
+
+#define REG_AXXX_CP_DEBUG                                       0x000001fc
+#define AXXX_CP_DEBUG_PREDICATE_DISABLE                         0x00800000
+#define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE                       0x01000000
+#define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE                   0x02000000
+#define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS                        0x04000000
+#define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE                       0x08000000
+#define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE                    0x10000000
+#define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL                    0x40000000
+#define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE                    0x80000000
+
+#define REG_AXXX_CP_CSQ_RB_STAT                                 0x000001fd
+#define AXXX_CP_CSQ_RB_STAT_RPTR__MASK                          0x0000007f
+#define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT                         0
+static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val)
+{
+        return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK;
+}
+#define AXXX_CP_CSQ_RB_STAT_WPTR__MASK                          0x007f0000
+#define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT                         16
+static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val)
+{
+        return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK;
+}
+
+#define REG_AXXX_CP_CSQ_IB1_STAT                                0x000001fe
+#define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK                         0x0000007f
+#define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT                        0
+static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val)
+{
+        return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK;
+}
+#define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK                         0x007f0000
+#define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT                        16
+static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val)
+{
+        return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK;
+}
+
+#define REG_AXXX_CP_CSQ_IB2_STAT                                0x000001ff
+#define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK                         0x0000007f
+#define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT                        0
+static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val)
+{
+        return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK;
+}
+#define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK                         0x007f0000
+#define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT                        16
+static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
+{
+        return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK;
+}
+
+#define REG_AXXX_CP_SCRATCH_REG0                                0x00000578
+
+#define REG_AXXX_CP_SCRATCH_REG1                                0x00000579
+
+#define REG_AXXX_CP_SCRATCH_REG2                                0x0000057a
+
+#define REG_AXXX_CP_SCRATCH_REG3                                0x0000057b
+
+#define REG_AXXX_CP_SCRATCH_REG4                                0x0000057c
+
+#define REG_AXXX_CP_SCRATCH_REG5                                0x0000057d
+
+#define REG_AXXX_CP_SCRATCH_REG6                                0x0000057e
+
+#define REG_AXXX_CP_SCRATCH_REG7                                0x0000057f
+
+#define REG_AXXX_CP_ME_CF_EVENT_SRC                             0x0000060a
+
+#define REG_AXXX_CP_ME_CF_EVENT_ADDR                            0x0000060b
+
+#define REG_AXXX_CP_ME_CF_EVENT_DATA                            0x0000060c
+
+#define REG_AXXX_CP_ME_NRT_ADDR                                 0x0000060d
+
+#define REG_AXXX_CP_ME_NRT_DATA                                 0x0000060e
+
+
+#endif /* ADRENO_COMMON_XML */
diff --git a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
new file mode 100644
index 000000000000..94c13f418e75
--- /dev/null
+++ b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
@@ -0,0 +1,254 @@
+#ifndef ADRENO_PM4_XML
+#define ADRENO_PM4_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml              (    327 bytes, from 2013-07-05 19:21:12)
+- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
+- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml           (  30005 bytes, from 2013-07-19 21:30:48)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml       (   8983 bytes, from 2013-07-24 01:38:36)
+- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml          (   9712 bytes, from 2013-05-26 15:22:37)
+- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml           (  51415 bytes, from 2013-08-03 14:26:05)
+
+Copyright (C) 2013 by the following authors:
+- Rob Clark <robdclark@gmail.com> (robclark)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+enum vgt_event_type {
+        VS_DEALLOC = 0,
+        PS_DEALLOC = 1,
+        VS_DONE_TS = 2,
+        PS_DONE_TS = 3,
+        CACHE_FLUSH_TS = 4,
+        CONTEXT_DONE = 5,
+        CACHE_FLUSH = 6,
+        HLSQ_FLUSH = 7,
+        VIZQUERY_START = 7,
+        VIZQUERY_END = 8,
+        SC_WAIT_WC = 9,
+        RST_PIX_CNT = 13,
+        RST_VTX_CNT = 14,
+        TILE_FLUSH = 15,
+        CACHE_FLUSH_AND_INV_TS_EVENT = 20,
+        ZPASS_DONE = 21,
+        CACHE_FLUSH_AND_INV_EVENT = 22,
+        PERFCOUNTER_START = 23,
+        PERFCOUNTER_STOP = 24,
+        VS_FETCH_DONE = 27,
+        FACENESS_FLUSH = 28,
+};
+
+enum pc_di_primtype {
+        DI_PT_NONE = 0,
+        DI_PT_POINTLIST = 1,
+        DI_PT_LINELIST = 2,
+        DI_PT_LINESTRIP = 3,
+        DI_PT_TRILIST = 4,
+        DI_PT_TRIFAN = 5,
+        DI_PT_TRISTRIP = 6,
+        DI_PT_RECTLIST = 8,
+        DI_PT_QUADLIST = 13,
+        DI_PT_QUADSTRIP = 14,
+        DI_PT_POLYGON = 15,
+        DI_PT_2D_COPY_RECT_LIST_V0 = 16,
+        DI_PT_2D_COPY_RECT_LIST_V1 = 17,
+        DI_PT_2D_COPY_RECT_LIST_V2 = 18,
+        DI_PT_2D_COPY_RECT_LIST_V3 = 19,
+        DI_PT_2D_FILL_RECT_LIST = 20,
+        DI_PT_2D_LINE_STRIP = 21,
+        DI_PT_2D_TRI_STRIP = 22,
+};
+
+enum pc_di_src_sel {
+        DI_SRC_SEL_DMA = 0,
+        DI_SRC_SEL_IMMEDIATE = 1,
+        DI_SRC_SEL_AUTO_INDEX = 2,
+        DI_SRC_SEL_RESERVED = 3,
+};
+
+enum pc_di_index_size {
+        INDEX_SIZE_IGN = 0,
+        INDEX_SIZE_16_BIT = 0,
+        INDEX_SIZE_32_BIT = 1,
+        INDEX_SIZE_8_BIT = 2,
+        INDEX_SIZE_INVALID = 0,
+};
+
+enum pc_di_vis_cull_mode {
+        IGNORE_VISIBILITY = 0,
+};
+
+enum adreno_pm4_packet_type {
+        CP_TYPE0_PKT = 0,
+        CP_TYPE1_PKT = 0x40000000,
+        CP_TYPE2_PKT = 0x80000000,
+        CP_TYPE3_PKT = 0xc0000000,
+};
+
+enum adreno_pm4_type3_packets {
+        CP_ME_INIT = 72,
+        CP_NOP = 16,
+        CP_INDIRECT_BUFFER = 63,
+        CP_INDIRECT_BUFFER_PFD = 55,
+        CP_WAIT_FOR_IDLE = 38,
+        CP_WAIT_REG_MEM = 60,
+        CP_WAIT_REG_EQ = 82,
+        CP_WAT_REG_GTE = 83,
+        CP_WAIT_UNTIL_READ = 92,
+        CP_WAIT_IB_PFD_COMPLETE = 93,
+        CP_REG_RMW = 33,
+        CP_SET_BIN_DATA = 47,
+        CP_REG_TO_MEM = 62,
+        CP_MEM_WRITE = 61,
+        CP_MEM_WRITE_CNTR = 79,
+        CP_COND_EXEC = 68,
+        CP_COND_WRITE = 69,
+        CP_EVENT_WRITE = 70,
+        CP_EVENT_WRITE_SHD = 88,
+        CP_EVENT_WRITE_CFL = 89,
+        CP_EVENT_WRITE_ZPD = 91,
+        CP_RUN_OPENCL = 49,
+        CP_DRAW_INDX = 34,
+        CP_DRAW_INDX_2 = 54,
+        CP_DRAW_INDX_BIN = 52,
+        CP_DRAW_INDX_2_BIN = 53,
+        CP_VIZ_QUERY = 35,
+        CP_SET_STATE = 37,
+        CP_SET_CONSTANT = 45,
+        CP_IM_LOAD = 39,
+        CP_IM_LOAD_IMMEDIATE = 43,
+        CP_LOAD_CONSTANT_CONTEXT = 46,
+        CP_INVALIDATE_STATE = 59,
+        CP_SET_SHADER_BASES = 74,
+        CP_SET_BIN_MASK = 80,
+        CP_SET_BIN_SELECT = 81,
+        CP_CONTEXT_UPDATE = 94,
+        CP_INTERRUPT = 64,
+        CP_IM_STORE = 44,
+        CP_SET_BIN_BASE_OFFSET = 75,
+        CP_SET_DRAW_INIT_FLAGS = 75,
+        CP_SET_PROTECTED_MODE = 95,
+        CP_LOAD_STATE = 48,
+        CP_COND_INDIRECT_BUFFER_PFE = 58,
+        CP_COND_INDIRECT_BUFFER_PFD = 50,
+        CP_INDIRECT_BUFFER_PFE = 63,
+        CP_SET_BIN = 76,
+};
+
+enum adreno_state_block {
+        SB_VERT_TEX = 0,
+        SB_VERT_MIPADDR = 1,
+        SB_FRAG_TEX = 2,
+        SB_FRAG_MIPADDR = 3,
+        SB_VERT_SHADER = 4,
+        SB_FRAG_SHADER = 6,
+};
+
+enum adreno_state_type {
+        ST_SHADER = 0,
+        ST_CONSTANTS = 1,
+};
+
+enum adreno_state_src {
+        SS_DIRECT = 0,
+        SS_INDIRECT = 4,
+};
+
+#define REG_CP_LOAD_STATE_0                                     0x00000000
+#define CP_LOAD_STATE_0_DST_OFF__MASK                           0x0000ffff
+#define CP_LOAD_STATE_0_DST_OFF__SHIFT                          0
+static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
+{
+        return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
+}
+#define CP_LOAD_STATE_0_STATE_SRC__MASK                         0x00070000
+#define CP_LOAD_STATE_0_STATE_SRC__SHIFT                        16
+static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
+{
+        return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
+}
+#define CP_LOAD_STATE_0_STATE_BLOCK__MASK                       0x00380000
+#define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT                      19
+static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
+{
+        return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
+}
+#define CP_LOAD_STATE_0_NUM_UNIT__MASK                          0x7fc00000
+#define CP_LOAD_STATE_0_NUM_UNIT__SHIFT                         22
+static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
+{
+        return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
+}
+
+#define REG_CP_LOAD_STATE_1                                     0x00000001
+#define CP_LOAD_STATE_1_STATE_TYPE__MASK                        0x00000003
+#define CP_LOAD_STATE_1_STATE_TYPE__SHIFT                       0
+static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
+{
+        return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
+}
+#define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK                      0xfffffffc
+#define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT                     2
+static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
+{
+        return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
+}
+
+#define REG_CP_SET_BIN_0                                        0x00000000
+
+#define REG_CP_SET_BIN_1                                        0x00000001
+#define CP_SET_BIN_1_X1__MASK                                   0x0000ffff
+#define CP_SET_BIN_1_X1__SHIFT                                  0
+static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
+{
+        return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
+}
+#define CP_SET_BIN_1_Y1__MASK                                   0xffff0000
+#define CP_SET_BIN_1_Y1__SHIFT                                  16
+static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
+{
+        return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
+}
+
+#define REG_CP_SET_BIN_2                                        0x00000002
+#define CP_SET_BIN_2_X2__MASK                                   0x0000ffff
+#define CP_SET_BIN_2_X2__SHIFT                                  0
+static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
+{
+        return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
+}
+#define CP_SET_BIN_2_Y2__MASK                                   0xffff0000
+#define CP_SET_BIN_2_Y2__SHIFT                                  16
+static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
+{
+        return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
+}
+
+
+#endif /* ADRENO_PM4_XML */