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authorAndy Yan <andy.yan@rock-chips.com>2014-12-05 01:26:31 -0500
committerPhilipp Zabel <p.zabel@pengutronix.de>2015-01-07 12:31:56 -0500
commitb21f4b658df885068c65852ef3d9d2f4f2821b03 (patch)
treeeaad214ec186ccbd6a7c4cd2d67b23d91e02e2be /drivers/gpu/drm/imx
parentaaa757a092c281461d4358e439143748142d5d72 (diff)
drm: imx: imx-hdmi: move imx-hdmi to bridge/dw_hdmi
the original imx hdmi driver is under drm/imx/, which depends on imx-drm, so move the imx hdmi driver out to drm/bridge and rename it to dw_hdmi Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Tested-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Diffstat (limited to 'drivers/gpu/drm/imx')
-rw-r--r--drivers/gpu/drm/imx/Kconfig1
-rw-r--r--drivers/gpu/drm/imx/Makefile2
-rw-r--r--drivers/gpu/drm/imx/dw_hdmi-imx.c (renamed from drivers/gpu/drm/imx/imx-hdmi_pltfm.c)110
-rw-r--r--drivers/gpu/drm/imx/imx-hdmi.c1643
-rw-r--r--drivers/gpu/drm/imx/imx-hdmi.h1076
5 files changed, 56 insertions, 2776 deletions
diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index ab31848e92cf..5d5e4092d40a 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -49,6 +49,7 @@ config DRM_IMX_IPUV3
49 49
50config DRM_IMX_HDMI 50config DRM_IMX_HDMI
51 tristate "Freescale i.MX DRM HDMI" 51 tristate "Freescale i.MX DRM HDMI"
52 select DRM_DW_HDMI
52 depends on DRM_IMX 53 depends on DRM_IMX
53 help 54 help
54 Choose this if you want to use HDMI on i.MX6. 55 Choose this if you want to use HDMI on i.MX6.
diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
index 63cf56ad5c61..f3ecd8903d97 100644
--- a/drivers/gpu/drm/imx/Makefile
+++ b/drivers/gpu/drm/imx/Makefile
@@ -9,4 +9,4 @@ obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
9 9
10imx-ipuv3-crtc-objs := ipuv3-crtc.o ipuv3-plane.o 10imx-ipuv3-crtc-objs := ipuv3-crtc.o ipuv3-plane.o
11obj-$(CONFIG_DRM_IMX_IPUV3) += imx-ipuv3-crtc.o 11obj-$(CONFIG_DRM_IMX_IPUV3) += imx-ipuv3-crtc.o
12obj-$(CONFIG_DRM_IMX_HDMI) += imx-hdmi.o imx-hdmi_pltfm.o 12obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
diff --git a/drivers/gpu/drm/imx/imx-hdmi_pltfm.c b/drivers/gpu/drm/imx/dw_hdmi-imx.c
index 830531fd57f6..121d30ca2d44 100644
--- a/drivers/gpu/drm/imx/imx-hdmi_pltfm.c
+++ b/drivers/gpu/drm/imx/dw_hdmi-imx.c
@@ -1,6 +1,6 @@
1/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 1/* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
2 * 2 *
3 * derived from imx-hdmi.c 3 * derived from imx-hdmi.c(renamed to bridge/dw_hdmi.c now)
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as 6 * it under the terms of the GNU General Public License version 2 as
@@ -11,6 +11,7 @@
11#include <linux/component.h> 11#include <linux/component.h>
12#include <linux/mfd/syscon.h> 12#include <linux/mfd/syscon.h>
13#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 13#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
14#include <drm/bridge/dw_hdmi.h>
14#include <video/imx-ipu-v3.h> 15#include <video/imx-ipu-v3.h>
15#include <linux/regmap.h> 16#include <linux/regmap.h>
16#include <drm/drm_of.h> 17#include <drm/drm_of.h>
@@ -20,15 +21,14 @@
20#include <drm/drm_encoder_slave.h> 21#include <drm/drm_encoder_slave.h>
21 22
22#include "imx-drm.h" 23#include "imx-drm.h"
23#include "imx-hdmi.h"
24 24
25struct imx_hdmi_priv { 25struct imx_hdmi {
26 struct device *dev; 26 struct device *dev;
27 struct drm_encoder encoder; 27 struct drm_encoder encoder;
28 struct regmap *regmap; 28 struct regmap *regmap;
29}; 29};
30 30
31static const struct mpll_config imx_mpll_cfg[] = { 31static const struct dw_hdmi_mpll_config imx_mpll_cfg[] = {
32 { 32 {
33 45250000, { 33 45250000, {
34 { 0x01e0, 0x0000 }, 34 { 0x01e0, 0x0000 },
@@ -56,7 +56,7 @@ static const struct mpll_config imx_mpll_cfg[] = {
56 } 56 }
57}; 57};
58 58
59static const struct curr_ctrl imx_cur_ctr[] = { 59static const struct dw_hdmi_curr_ctrl imx_cur_ctr[] = {
60 /* pixelclk bpp8 bpp10 bpp12 */ 60 /* pixelclk bpp8 bpp10 bpp12 */
61 { 61 {
62 54000000, { 0x091c, 0x091c, 0x06dc }, 62 54000000, { 0x091c, 0x091c, 0x06dc },
@@ -73,13 +73,13 @@ static const struct curr_ctrl imx_cur_ctr[] = {
73 } 73 }
74}; 74};
75 75
76static const struct sym_term imx_sym_term[] = { 76static const struct dw_hdmi_sym_term imx_sym_term[] = {
77 /*pixelclk symbol term*/ 77 /*pixelclk symbol term*/
78 { 148500000, 0x800d, 0x0005 }, 78 { 148500000, 0x800d, 0x0005 },
79 { ~0UL, 0x0000, 0x0000 } 79 { ~0UL, 0x0000, 0x0000 }
80}; 80};
81 81
82static int imx_hdmi_parse_dt(struct imx_hdmi_priv *hdmi) 82static int dw_hdmi_imx_parse_dt(struct imx_hdmi *hdmi)
83{ 83{
84 struct device_node *np = hdmi->dev->of_node; 84 struct device_node *np = hdmi->dev->of_node;
85 85
@@ -92,28 +92,26 @@ static int imx_hdmi_parse_dt(struct imx_hdmi_priv *hdmi)
92 return 0; 92 return 0;
93} 93}
94 94
95static void imx_hdmi_encoder_disable(struct drm_encoder *encoder) 95static void dw_hdmi_imx_encoder_disable(struct drm_encoder *encoder)
96{ 96{
97} 97}
98 98
99static bool imx_hdmi_encoder_mode_fixup(struct drm_encoder *encoder, 99static bool dw_hdmi_imx_encoder_mode_fixup(struct drm_encoder *encoder,
100 const struct drm_display_mode *mode, 100 const struct drm_display_mode *mode,
101 struct drm_display_mode *adj_mode) 101 struct drm_display_mode *adj_mode)
102{ 102{
103 return true; 103 return true;
104} 104}
105 105
106static void imx_hdmi_encoder_mode_set(struct drm_encoder *encoder, 106static void dw_hdmi_imx_encoder_mode_set(struct drm_encoder *encoder,
107 struct drm_display_mode *mode, 107 struct drm_display_mode *mode,
108 struct drm_display_mode *adj_mode) 108 struct drm_display_mode *adj_mode)
109{ 109{
110} 110}
111 111
112static void imx_hdmi_encoder_commit(struct drm_encoder *encoder) 112static void dw_hdmi_imx_encoder_commit(struct drm_encoder *encoder)
113{ 113{
114 struct imx_hdmi_priv *hdmi = container_of(encoder, 114 struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
115 struct imx_hdmi_priv,
116 encoder);
117 int mux = imx_drm_encoder_get_mux_id(hdmi->dev->of_node, encoder); 115 int mux = imx_drm_encoder_get_mux_id(hdmi->dev->of_node, encoder);
118 116
119 regmap_update_bits(hdmi->regmap, IOMUXC_GPR3, 117 regmap_update_bits(hdmi->regmap, IOMUXC_GPR3,
@@ -121,38 +119,38 @@ static void imx_hdmi_encoder_commit(struct drm_encoder *encoder)
121 mux << IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT); 119 mux << IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT);
122} 120}
123 121
124static void imx_hdmi_encoder_prepare(struct drm_encoder *encoder) 122static void dw_hdmi_imx_encoder_prepare(struct drm_encoder *encoder)
125{ 123{
126 imx_drm_panel_format(encoder, V4L2_PIX_FMT_RGB24); 124 imx_drm_panel_format(encoder, V4L2_PIX_FMT_RGB24);
127} 125}
128 126
129static struct drm_encoder_helper_funcs imx_hdmi_encoder_helper_funcs = { 127static struct drm_encoder_helper_funcs dw_hdmi_imx_encoder_helper_funcs = {
130 .mode_fixup = imx_hdmi_encoder_mode_fixup, 128 .mode_fixup = dw_hdmi_imx_encoder_mode_fixup,
131 .mode_set = imx_hdmi_encoder_mode_set, 129 .mode_set = dw_hdmi_imx_encoder_mode_set,
132 .prepare = imx_hdmi_encoder_prepare, 130 .prepare = dw_hdmi_imx_encoder_prepare,
133 .commit = imx_hdmi_encoder_commit, 131 .commit = dw_hdmi_imx_encoder_commit,
134 .disable = imx_hdmi_encoder_disable, 132 .disable = dw_hdmi_imx_encoder_disable,
135}; 133};
136 134
137static struct drm_encoder_funcs imx_hdmi_encoder_funcs = { 135static struct drm_encoder_funcs dw_hdmi_imx_encoder_funcs = {
138 .destroy = drm_encoder_cleanup, 136 .destroy = drm_encoder_cleanup,
139}; 137};
140 138
141static struct imx_hdmi_plat_data imx6q_hdmi_drv_data = { 139static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = {
142 .mpll_cfg = imx_mpll_cfg, 140 .mpll_cfg = imx_mpll_cfg,
143 .cur_ctr = imx_cur_ctr, 141 .cur_ctr = imx_cur_ctr,
144 .sym_term = imx_sym_term, 142 .sym_term = imx_sym_term,
145 .dev_type = IMX6Q_HDMI, 143 .dev_type = IMX6Q_HDMI,
146}; 144};
147 145
148static struct imx_hdmi_plat_data imx6dl_hdmi_drv_data = { 146static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = {
149 .mpll_cfg = imx_mpll_cfg, 147 .mpll_cfg = imx_mpll_cfg,
150 .cur_ctr = imx_cur_ctr, 148 .cur_ctr = imx_cur_ctr,
151 .sym_term = imx_sym_term, 149 .sym_term = imx_sym_term,
152 .dev_type = IMX6DL_HDMI, 150 .dev_type = IMX6DL_HDMI,
153}; 151};
154 152
155static const struct of_device_id imx_hdmi_dt_ids[] = { 153static const struct of_device_id dw_hdmi_imx_dt_ids[] = {
156 { .compatible = "fsl,imx6q-hdmi", 154 { .compatible = "fsl,imx6q-hdmi",
157 .data = &imx6q_hdmi_drv_data 155 .data = &imx6q_hdmi_drv_data
158 }, { 156 }, {
@@ -161,17 +159,17 @@ static const struct of_device_id imx_hdmi_dt_ids[] = {
161 }, 159 },
162 {}, 160 {},
163}; 161};
164MODULE_DEVICE_TABLE(of, imx_hdmi_dt_ids); 162MODULE_DEVICE_TABLE(of, dw_hdmi_imx_dt_ids);
165 163
166static int imx_hdmi_pltfm_bind(struct device *dev, struct device *master, 164static int dw_hdmi_imx_bind(struct device *dev, struct device *master,
167 void *data) 165 void *data)
168{ 166{
169 struct platform_device *pdev = to_platform_device(dev); 167 struct platform_device *pdev = to_platform_device(dev);
170 const struct imx_hdmi_plat_data *plat_data; 168 const struct dw_hdmi_plat_data *plat_data;
171 const struct of_device_id *match; 169 const struct of_device_id *match;
172 struct drm_device *drm = data; 170 struct drm_device *drm = data;
173 struct drm_encoder *encoder; 171 struct drm_encoder *encoder;
174 struct imx_hdmi_priv *hdmi; 172 struct imx_hdmi *hdmi;
175 struct resource *iores; 173 struct resource *iores;
176 int irq; 174 int irq;
177 int ret; 175 int ret;
@@ -183,7 +181,7 @@ static int imx_hdmi_pltfm_bind(struct device *dev, struct device *master,
183 if (!hdmi) 181 if (!hdmi)
184 return -ENOMEM; 182 return -ENOMEM;
185 183
186 match = of_match_node(imx_hdmi_dt_ids, pdev->dev.of_node); 184 match = of_match_node(dw_hdmi_imx_dt_ids, pdev->dev.of_node);
187 plat_data = match->data; 185 plat_data = match->data;
188 hdmi->dev = &pdev->dev; 186 hdmi->dev = &pdev->dev;
189 encoder = &hdmi->encoder; 187 encoder = &hdmi->encoder;
@@ -208,53 +206,53 @@ static int imx_hdmi_pltfm_bind(struct device *dev, struct device *master,
208 if (encoder->possible_crtcs == 0) 206 if (encoder->possible_crtcs == 0)
209 return -EPROBE_DEFER; 207 return -EPROBE_DEFER;
210 208
211 ret = imx_hdmi_parse_dt(hdmi); 209 ret = dw_hdmi_imx_parse_dt(hdmi);
212 if (ret < 0) 210 if (ret < 0)
213 return ret; 211 return ret;
214 212
215 drm_encoder_helper_add(encoder, &imx_hdmi_encoder_helper_funcs); 213 drm_encoder_helper_add(encoder, &dw_hdmi_imx_encoder_helper_funcs);
216 drm_encoder_init(drm, encoder, &imx_hdmi_encoder_funcs, 214 drm_encoder_init(drm, encoder, &dw_hdmi_imx_encoder_funcs,
217 DRM_MODE_ENCODER_TMDS); 215 DRM_MODE_ENCODER_TMDS);
218 216
219 return imx_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data); 217 return dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data);
220} 218}
221 219
222static void imx_hdmi_pltfm_unbind(struct device *dev, struct device *master, 220static void dw_hdmi_imx_unbind(struct device *dev, struct device *master,
223 void *data) 221 void *data)
224{ 222{
225 return imx_hdmi_unbind(dev, master, data); 223 return dw_hdmi_unbind(dev, master, data);
226} 224}
227 225
228static const struct component_ops imx_hdmi_ops = { 226static const struct component_ops dw_hdmi_imx_ops = {
229 .bind = imx_hdmi_pltfm_bind, 227 .bind = dw_hdmi_imx_bind,
230 .unbind = imx_hdmi_pltfm_unbind, 228 .unbind = dw_hdmi_imx_unbind,
231}; 229};
232 230
233static int imx_hdmi_probe(struct platform_device *pdev) 231static int dw_hdmi_imx_probe(struct platform_device *pdev)
234{ 232{
235 return component_add(&pdev->dev, &imx_hdmi_ops); 233 return component_add(&pdev->dev, &dw_hdmi_imx_ops);
236} 234}
237 235
238static int imx_hdmi_remove(struct platform_device *pdev) 236static int dw_hdmi_imx_remove(struct platform_device *pdev)
239{ 237{
240 component_del(&pdev->dev, &imx_hdmi_ops); 238 component_del(&pdev->dev, &dw_hdmi_imx_ops);
241 239
242 return 0; 240 return 0;
243} 241}
244 242
245static struct platform_driver imx_hdmi_pltfm_driver = { 243static struct platform_driver dw_hdmi_imx_platform_driver = {
246 .probe = imx_hdmi_probe, 244 .probe = dw_hdmi_imx_probe,
247 .remove = imx_hdmi_remove, 245 .remove = dw_hdmi_imx_remove,
248 .driver = { 246 .driver = {
249 .name = "hdmi-imx", 247 .name = "dwhdmi-imx",
250 .of_match_table = imx_hdmi_dt_ids, 248 .of_match_table = dw_hdmi_imx_dt_ids,
251 }, 249 },
252}; 250};
253 251
254module_platform_driver(imx_hdmi_pltfm_driver); 252module_platform_driver(dw_hdmi_imx_platform_driver);
255 253
256MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); 254MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
257MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); 255MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
258MODULE_DESCRIPTION("IMX6 Specific DW-HDMI Driver Extension"); 256MODULE_DESCRIPTION("IMX6 Specific DW-HDMI Driver Extension");
259MODULE_LICENSE("GPL"); 257MODULE_LICENSE("GPL");
260MODULE_ALIAS("platform:hdmi-imx"); 258MODULE_ALIAS("platform:dwhdmi-imx");
diff --git a/drivers/gpu/drm/imx/imx-hdmi.c b/drivers/gpu/drm/imx/imx-hdmi.c
deleted file mode 100644
index 998f3fd354ee..000000000000
--- a/drivers/gpu/drm/imx/imx-hdmi.c
+++ /dev/null
@@ -1,1643 +0,0 @@
1/*
2 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
10 * for SLISHDMI13T and SLIPHDMIT IP cores
11 *
12 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
13 */
14
15#include <linux/irq.h>
16#include <linux/delay.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19#include <linux/hdmi.h>
20#include <linux/of_device.h>
21
22#include <drm/drm_of.h>
23#include <drm/drmP.h>
24#include <drm/drm_crtc_helper.h>
25#include <drm/drm_edid.h>
26#include <drm/drm_encoder_slave.h>
27
28#include "imx-hdmi.h"
29
30#define HDMI_EDID_LEN 512
31
32#define RGB 0
33#define YCBCR444 1
34#define YCBCR422_16BITS 2
35#define YCBCR422_8BITS 3
36#define XVYCC444 4
37
38enum hdmi_datamap {
39 RGB444_8B = 0x01,
40 RGB444_10B = 0x03,
41 RGB444_12B = 0x05,
42 RGB444_16B = 0x07,
43 YCbCr444_8B = 0x09,
44 YCbCr444_10B = 0x0B,
45 YCbCr444_12B = 0x0D,
46 YCbCr444_16B = 0x0F,
47 YCbCr422_8B = 0x16,
48 YCbCr422_10B = 0x14,
49 YCbCr422_12B = 0x12,
50};
51
52static const u16 csc_coeff_default[3][4] = {
53 { 0x2000, 0x0000, 0x0000, 0x0000 },
54 { 0x0000, 0x2000, 0x0000, 0x0000 },
55 { 0x0000, 0x0000, 0x2000, 0x0000 }
56};
57
58static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
59 { 0x2000, 0x6926, 0x74fd, 0x010e },
60 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
61 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
62};
63
64static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
65 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
66 { 0x2000, 0x3264, 0x0000, 0x7e6d },
67 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
68};
69
70static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
71 { 0x2591, 0x1322, 0x074b, 0x0000 },
72 { 0x6535, 0x2000, 0x7acc, 0x0200 },
73 { 0x6acd, 0x7534, 0x2000, 0x0200 }
74};
75
76static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
77 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
78 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
79 { 0x6756, 0x78ab, 0x2000, 0x0200 }
80};
81
82struct hdmi_vmode {
83 bool mdvi;
84 bool mhsyncpolarity;
85 bool mvsyncpolarity;
86 bool minterlaced;
87 bool mdataenablepolarity;
88
89 unsigned int mpixelclock;
90 unsigned int mpixelrepetitioninput;
91 unsigned int mpixelrepetitionoutput;
92};
93
94struct hdmi_data_info {
95 unsigned int enc_in_format;
96 unsigned int enc_out_format;
97 unsigned int enc_color_depth;
98 unsigned int colorimetry;
99 unsigned int pix_repet_factor;
100 unsigned int hdcp_enable;
101 struct hdmi_vmode video_mode;
102};
103
104struct imx_hdmi {
105 struct drm_connector connector;
106 struct drm_encoder *encoder;
107 struct drm_bridge *bridge;
108
109 enum imx_hdmi_devtype dev_type;
110 struct device *dev;
111 struct clk *isfr_clk;
112 struct clk *iahb_clk;
113
114 struct hdmi_data_info hdmi_data;
115 const struct imx_hdmi_plat_data *plat_data;
116 int vic;
117
118 u8 edid[HDMI_EDID_LEN];
119 bool cable_plugin;
120
121 bool phy_enabled;
122 struct drm_display_mode previous_mode;
123
124 struct regmap *regmap;
125 struct i2c_adapter *ddc;
126 void __iomem *regs;
127
128 unsigned int sample_rate;
129 int ratio;
130};
131
132static inline void hdmi_writeb(struct imx_hdmi *hdmi, u8 val, int offset)
133{
134 writeb(val, hdmi->regs + offset);
135}
136
137static inline u8 hdmi_readb(struct imx_hdmi *hdmi, int offset)
138{
139 return readb(hdmi->regs + offset);
140}
141
142static void hdmi_modb(struct imx_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
143{
144 u8 val = hdmi_readb(hdmi, reg) & ~mask;
145
146 val |= data & mask;
147 hdmi_writeb(hdmi, val, reg);
148}
149
150static void hdmi_mask_writeb(struct imx_hdmi *hdmi, u8 data, unsigned int reg,
151 u8 shift, u8 mask)
152{
153 hdmi_modb(hdmi, data << shift, mask, reg);
154}
155
156static void hdmi_set_clock_regenerator_n(struct imx_hdmi *hdmi,
157 unsigned int value)
158{
159 hdmi_writeb(hdmi, value & 0xff, HDMI_AUD_N1);
160 hdmi_writeb(hdmi, (value >> 8) & 0xff, HDMI_AUD_N2);
161 hdmi_writeb(hdmi, (value >> 16) & 0x0f, HDMI_AUD_N3);
162
163 /* nshift factor = 0 */
164 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
165}
166
167static void hdmi_regenerate_cts(struct imx_hdmi *hdmi, unsigned int cts)
168{
169 /* Must be set/cleared first */
170 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
171
172 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
173 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
174 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
175 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
176}
177
178static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
179 unsigned int ratio)
180{
181 unsigned int n = (128 * freq) / 1000;
182
183 switch (freq) {
184 case 32000:
185 if (pixel_clk == 25170000)
186 n = (ratio == 150) ? 9152 : 4576;
187 else if (pixel_clk == 27020000)
188 n = (ratio == 150) ? 8192 : 4096;
189 else if (pixel_clk == 74170000 || pixel_clk == 148350000)
190 n = 11648;
191 else
192 n = 4096;
193 break;
194
195 case 44100:
196 if (pixel_clk == 25170000)
197 n = 7007;
198 else if (pixel_clk == 74170000)
199 n = 17836;
200 else if (pixel_clk == 148350000)
201 n = (ratio == 150) ? 17836 : 8918;
202 else
203 n = 6272;
204 break;
205
206 case 48000:
207 if (pixel_clk == 25170000)
208 n = (ratio == 150) ? 9152 : 6864;
209 else if (pixel_clk == 27020000)
210 n = (ratio == 150) ? 8192 : 6144;
211 else if (pixel_clk == 74170000)
212 n = 11648;
213 else if (pixel_clk == 148350000)
214 n = (ratio == 150) ? 11648 : 5824;
215 else
216 n = 6144;
217 break;
218
219 case 88200:
220 n = hdmi_compute_n(44100, pixel_clk, ratio) * 2;
221 break;
222
223 case 96000:
224 n = hdmi_compute_n(48000, pixel_clk, ratio) * 2;
225 break;
226
227 case 176400:
228 n = hdmi_compute_n(44100, pixel_clk, ratio) * 4;
229 break;
230
231 case 192000:
232 n = hdmi_compute_n(48000, pixel_clk, ratio) * 4;
233 break;
234
235 default:
236 break;
237 }
238
239 return n;
240}
241
242static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk,
243 unsigned int ratio)
244{
245 unsigned int cts = 0;
246
247 pr_debug("%s: freq: %d pixel_clk: %ld ratio: %d\n", __func__, freq,
248 pixel_clk, ratio);
249
250 switch (freq) {
251 case 32000:
252 if (pixel_clk == 297000000) {
253 cts = 222750;
254 break;
255 }
256 case 48000:
257 case 96000:
258 case 192000:
259 switch (pixel_clk) {
260 case 25200000:
261 case 27000000:
262 case 54000000:
263 case 74250000:
264 case 148500000:
265 cts = pixel_clk / 1000;
266 break;
267 case 297000000:
268 cts = 247500;
269 break;
270 /*
271 * All other TMDS clocks are not supported by
272 * DWC_hdmi_tx. The TMDS clocks divided or
273 * multiplied by 1,001 coefficients are not
274 * supported.
275 */
276 default:
277 break;
278 }
279 break;
280 case 44100:
281 case 88200:
282 case 176400:
283 switch (pixel_clk) {
284 case 25200000:
285 cts = 28000;
286 break;
287 case 27000000:
288 cts = 30000;
289 break;
290 case 54000000:
291 cts = 60000;
292 break;
293 case 74250000:
294 cts = 82500;
295 break;
296 case 148500000:
297 cts = 165000;
298 break;
299 case 297000000:
300 cts = 247500;
301 break;
302 default:
303 break;
304 }
305 break;
306 default:
307 break;
308 }
309 if (ratio == 100)
310 return cts;
311 return (cts * ratio) / 100;
312}
313
314static void hdmi_set_clk_regenerator(struct imx_hdmi *hdmi,
315 unsigned long pixel_clk)
316{
317 unsigned int clk_n, clk_cts;
318
319 clk_n = hdmi_compute_n(hdmi->sample_rate, pixel_clk,
320 hdmi->ratio);
321 clk_cts = hdmi_compute_cts(hdmi->sample_rate, pixel_clk,
322 hdmi->ratio);
323
324 if (!clk_cts) {
325 dev_dbg(hdmi->dev, "%s: pixel clock not supported: %lu\n",
326 __func__, pixel_clk);
327 return;
328 }
329
330 dev_dbg(hdmi->dev, "%s: samplerate=%d ratio=%d pixelclk=%lu N=%d cts=%d\n",
331 __func__, hdmi->sample_rate, hdmi->ratio,
332 pixel_clk, clk_n, clk_cts);
333
334 hdmi_set_clock_regenerator_n(hdmi, clk_n);
335 hdmi_regenerate_cts(hdmi, clk_cts);
336}
337
338static void hdmi_init_clk_regenerator(struct imx_hdmi *hdmi)
339{
340 hdmi_set_clk_regenerator(hdmi, 74250000);
341}
342
343static void hdmi_clk_regenerator_update_pixel_clock(struct imx_hdmi *hdmi)
344{
345 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock);
346}
347
348/*
349 * this submodule is responsible for the video data synchronization.
350 * for example, for RGB 4:4:4 input, the data map is defined as
351 * pin{47~40} <==> R[7:0]
352 * pin{31~24} <==> G[7:0]
353 * pin{15~8} <==> B[7:0]
354 */
355static void hdmi_video_sample(struct imx_hdmi *hdmi)
356{
357 int color_format = 0;
358 u8 val;
359
360 if (hdmi->hdmi_data.enc_in_format == RGB) {
361 if (hdmi->hdmi_data.enc_color_depth == 8)
362 color_format = 0x01;
363 else if (hdmi->hdmi_data.enc_color_depth == 10)
364 color_format = 0x03;
365 else if (hdmi->hdmi_data.enc_color_depth == 12)
366 color_format = 0x05;
367 else if (hdmi->hdmi_data.enc_color_depth == 16)
368 color_format = 0x07;
369 else
370 return;
371 } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
372 if (hdmi->hdmi_data.enc_color_depth == 8)
373 color_format = 0x09;
374 else if (hdmi->hdmi_data.enc_color_depth == 10)
375 color_format = 0x0B;
376 else if (hdmi->hdmi_data.enc_color_depth == 12)
377 color_format = 0x0D;
378 else if (hdmi->hdmi_data.enc_color_depth == 16)
379 color_format = 0x0F;
380 else
381 return;
382 } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
383 if (hdmi->hdmi_data.enc_color_depth == 8)
384 color_format = 0x16;
385 else if (hdmi->hdmi_data.enc_color_depth == 10)
386 color_format = 0x14;
387 else if (hdmi->hdmi_data.enc_color_depth == 12)
388 color_format = 0x12;
389 else
390 return;
391 }
392
393 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
394 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
395 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
396 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
397
398 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
399 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
400 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
401 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
402 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
403 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
404 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
405 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
406 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
407 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
408 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
409}
410
411static int is_color_space_conversion(struct imx_hdmi *hdmi)
412{
413 return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
414}
415
416static int is_color_space_decimation(struct imx_hdmi *hdmi)
417{
418 if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
419 return 0;
420 if (hdmi->hdmi_data.enc_in_format == RGB ||
421 hdmi->hdmi_data.enc_in_format == YCBCR444)
422 return 1;
423 return 0;
424}
425
426static int is_color_space_interpolation(struct imx_hdmi *hdmi)
427{
428 if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
429 return 0;
430 if (hdmi->hdmi_data.enc_out_format == RGB ||
431 hdmi->hdmi_data.enc_out_format == YCBCR444)
432 return 1;
433 return 0;
434}
435
436static void imx_hdmi_update_csc_coeffs(struct imx_hdmi *hdmi)
437{
438 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
439 unsigned i;
440 u32 csc_scale = 1;
441
442 if (is_color_space_conversion(hdmi)) {
443 if (hdmi->hdmi_data.enc_out_format == RGB) {
444 if (hdmi->hdmi_data.colorimetry ==
445 HDMI_COLORIMETRY_ITU_601)
446 csc_coeff = &csc_coeff_rgb_out_eitu601;
447 else
448 csc_coeff = &csc_coeff_rgb_out_eitu709;
449 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
450 if (hdmi->hdmi_data.colorimetry ==
451 HDMI_COLORIMETRY_ITU_601)
452 csc_coeff = &csc_coeff_rgb_in_eitu601;
453 else
454 csc_coeff = &csc_coeff_rgb_in_eitu709;
455 csc_scale = 0;
456 }
457 }
458
459 /* The CSC registers are sequential, alternating MSB then LSB */
460 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
461 u16 coeff_a = (*csc_coeff)[0][i];
462 u16 coeff_b = (*csc_coeff)[1][i];
463 u16 coeff_c = (*csc_coeff)[2][i];
464
465 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
466 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
467 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
468 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
469 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
470 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
471 }
472
473 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
474 HDMI_CSC_SCALE);
475}
476
477static void hdmi_video_csc(struct imx_hdmi *hdmi)
478{
479 int color_depth = 0;
480 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
481 int decimation = 0;
482
483 /* YCC422 interpolation to 444 mode */
484 if (is_color_space_interpolation(hdmi))
485 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
486 else if (is_color_space_decimation(hdmi))
487 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
488
489 if (hdmi->hdmi_data.enc_color_depth == 8)
490 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
491 else if (hdmi->hdmi_data.enc_color_depth == 10)
492 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
493 else if (hdmi->hdmi_data.enc_color_depth == 12)
494 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
495 else if (hdmi->hdmi_data.enc_color_depth == 16)
496 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
497 else
498 return;
499
500 /* Configure the CSC registers */
501 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
502 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
503 HDMI_CSC_SCALE);
504
505 imx_hdmi_update_csc_coeffs(hdmi);
506}
507
508/*
509 * HDMI video packetizer is used to packetize the data.
510 * for example, if input is YCC422 mode or repeater is used,
511 * data should be repacked this module can be bypassed.
512 */
513static void hdmi_video_packetize(struct imx_hdmi *hdmi)
514{
515 unsigned int color_depth = 0;
516 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
517 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
518 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
519 u8 val, vp_conf;
520
521 if (hdmi_data->enc_out_format == RGB ||
522 hdmi_data->enc_out_format == YCBCR444) {
523 if (!hdmi_data->enc_color_depth) {
524 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
525 } else if (hdmi_data->enc_color_depth == 8) {
526 color_depth = 4;
527 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
528 } else if (hdmi_data->enc_color_depth == 10) {
529 color_depth = 5;
530 } else if (hdmi_data->enc_color_depth == 12) {
531 color_depth = 6;
532 } else if (hdmi_data->enc_color_depth == 16) {
533 color_depth = 7;
534 } else {
535 return;
536 }
537 } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
538 if (!hdmi_data->enc_color_depth ||
539 hdmi_data->enc_color_depth == 8)
540 remap_size = HDMI_VP_REMAP_YCC422_16bit;
541 else if (hdmi_data->enc_color_depth == 10)
542 remap_size = HDMI_VP_REMAP_YCC422_20bit;
543 else if (hdmi_data->enc_color_depth == 12)
544 remap_size = HDMI_VP_REMAP_YCC422_24bit;
545 else
546 return;
547 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
548 } else {
549 return;
550 }
551
552 /* set the packetizer registers */
553 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
554 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
555 ((hdmi_data->pix_repet_factor <<
556 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
557 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
558 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
559
560 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
561 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
562
563 /* Data from pixel repeater block */
564 if (hdmi_data->pix_repet_factor > 1) {
565 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
566 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
567 } else { /* data from packetizer block */
568 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
569 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
570 }
571
572 hdmi_modb(hdmi, vp_conf,
573 HDMI_VP_CONF_PR_EN_MASK |
574 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
575
576 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
577 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
578
579 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
580
581 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
582 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
583 HDMI_VP_CONF_PP_EN_ENABLE |
584 HDMI_VP_CONF_YCC422_EN_DISABLE;
585 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
586 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
587 HDMI_VP_CONF_PP_EN_DISABLE |
588 HDMI_VP_CONF_YCC422_EN_ENABLE;
589 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
590 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
591 HDMI_VP_CONF_PP_EN_DISABLE |
592 HDMI_VP_CONF_YCC422_EN_DISABLE;
593 } else {
594 return;
595 }
596
597 hdmi_modb(hdmi, vp_conf,
598 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
599 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
600
601 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
602 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
603 HDMI_VP_STUFF_PP_STUFFING_MASK |
604 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
605
606 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
607 HDMI_VP_CONF);
608}
609
610static inline void hdmi_phy_test_clear(struct imx_hdmi *hdmi,
611 unsigned char bit)
612{
613 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
614 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
615}
616
617static inline void hdmi_phy_test_enable(struct imx_hdmi *hdmi,
618 unsigned char bit)
619{
620 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
621 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
622}
623
624static inline void hdmi_phy_test_clock(struct imx_hdmi *hdmi,
625 unsigned char bit)
626{
627 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
628 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
629}
630
631static inline void hdmi_phy_test_din(struct imx_hdmi *hdmi,
632 unsigned char bit)
633{
634 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
635}
636
637static inline void hdmi_phy_test_dout(struct imx_hdmi *hdmi,
638 unsigned char bit)
639{
640 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
641}
642
643static bool hdmi_phy_wait_i2c_done(struct imx_hdmi *hdmi, int msec)
644{
645 while ((hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
646 if (msec-- == 0)
647 return false;
648 udelay(1000);
649 }
650 return true;
651}
652
653static void __hdmi_phy_i2c_write(struct imx_hdmi *hdmi, unsigned short data,
654 unsigned char addr)
655{
656 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
657 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
658 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
659 HDMI_PHY_I2CM_DATAO_1_ADDR);
660 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
661 HDMI_PHY_I2CM_DATAO_0_ADDR);
662 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
663 HDMI_PHY_I2CM_OPERATION_ADDR);
664 hdmi_phy_wait_i2c_done(hdmi, 1000);
665}
666
667static int hdmi_phy_i2c_write(struct imx_hdmi *hdmi, unsigned short data,
668 unsigned char addr)
669{
670 __hdmi_phy_i2c_write(hdmi, data, addr);
671 return 0;
672}
673
674static void imx_hdmi_phy_enable_power(struct imx_hdmi *hdmi, u8 enable)
675{
676 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
677 HDMI_PHY_CONF0_PDZ_OFFSET,
678 HDMI_PHY_CONF0_PDZ_MASK);
679}
680
681static void imx_hdmi_phy_enable_tmds(struct imx_hdmi *hdmi, u8 enable)
682{
683 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
684 HDMI_PHY_CONF0_ENTMDS_OFFSET,
685 HDMI_PHY_CONF0_ENTMDS_MASK);
686}
687
688static void imx_hdmi_phy_gen2_pddq(struct imx_hdmi *hdmi, u8 enable)
689{
690 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
691 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
692 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
693}
694
695static void imx_hdmi_phy_gen2_txpwron(struct imx_hdmi *hdmi, u8 enable)
696{
697 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
698 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
699 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
700}
701
702static void imx_hdmi_phy_sel_data_en_pol(struct imx_hdmi *hdmi, u8 enable)
703{
704 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
705 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
706 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
707}
708
709static void imx_hdmi_phy_sel_interface_control(struct imx_hdmi *hdmi, u8 enable)
710{
711 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
712 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
713 HDMI_PHY_CONF0_SELDIPIF_MASK);
714}
715
716static int hdmi_phy_configure(struct imx_hdmi *hdmi, unsigned char prep,
717 unsigned char res, int cscon)
718{
719 unsigned res_idx, i;
720 u8 val, msec;
721 const struct mpll_config *mpll_config = hdmi->plat_data->mpll_cfg;
722 const struct curr_ctrl *curr_ctrl = hdmi->plat_data->cur_ctr;
723 const struct sym_term *sym_term = hdmi->plat_data->sym_term;
724
725 if (prep)
726 return -EINVAL;
727
728 switch (res) {
729 case 0: /* color resolution 0 is 8 bit colour depth */
730 case 8:
731 res_idx = RES_8;
732 break;
733 case 10:
734 res_idx = RES_10;
735 break;
736 case 12:
737 res_idx = RES_12;
738 break;
739 default:
740 return -EINVAL;
741 }
742
743 /* Enable csc path */
744 if (cscon)
745 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
746 else
747 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
748
749 hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
750
751 /* gen2 tx power off */
752 imx_hdmi_phy_gen2_txpwron(hdmi, 0);
753
754 /* gen2 pddq */
755 imx_hdmi_phy_gen2_pddq(hdmi, 1);
756
757 /* PHY reset */
758 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
759 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
760
761 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
762
763 hdmi_phy_test_clear(hdmi, 1);
764 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
765 HDMI_PHY_I2CM_SLAVE_ADDR);
766 hdmi_phy_test_clear(hdmi, 0);
767
768 /* PLL/MPLL Cfg - always match on final entry */
769 for (i = 0; mpll_config[i].mpixelclock != (~0UL); i++)
770 if (hdmi->hdmi_data.video_mode.mpixelclock <=
771 mpll_config[i].mpixelclock)
772 break;
773
774 hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].cpce, 0x06);
775 hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].gmp, 0x15);
776
777 for (i = 0; curr_ctrl[i].mpixelclock != (~0UL); i++)
778 if (hdmi->hdmi_data.video_mode.mpixelclock <=
779 curr_ctrl[i].mpixelclock)
780 break;
781
782 if (curr_ctrl[i].mpixelclock == (~0UL)) {
783 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
784 hdmi->hdmi_data.video_mode.mpixelclock);
785 return -EINVAL;
786 }
787
788 /* CURRCTRL */
789 hdmi_phy_i2c_write(hdmi, curr_ctrl[i].curr[res_idx], 0x10);
790
791 hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
792 hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
793
794 for (i = 0; sym_term[i].mpixelclock != (~0UL); i++)
795 if (hdmi->hdmi_data.video_mode.mpixelclock <=
796 sym_term[i].mpixelclock)
797 break;
798
799 /* RESISTANCE TERM 133Ohm Cfg */
800 hdmi_phy_i2c_write(hdmi, sym_term[i].term, 0x19); /* TXTERM */
801 /* PREEMP Cgf 0.00 */
802 hdmi_phy_i2c_write(hdmi, sym_term[i].sym_ctr, 0x09); /* CKSYMTXCTRL */
803
804 /* TX/CK LVL 10 */
805 hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E); /* VLEVCTRL */
806 /* REMOVE CLK TERM */
807 hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */
808
809 imx_hdmi_phy_enable_power(hdmi, 1);
810
811 /* toggle TMDS enable */
812 imx_hdmi_phy_enable_tmds(hdmi, 0);
813 imx_hdmi_phy_enable_tmds(hdmi, 1);
814
815 /* gen2 tx power on */
816 imx_hdmi_phy_gen2_txpwron(hdmi, 1);
817 imx_hdmi_phy_gen2_pddq(hdmi, 0);
818
819 /*Wait for PHY PLL lock */
820 msec = 5;
821 do {
822 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
823 if (!val)
824 break;
825
826 if (msec == 0) {
827 dev_err(hdmi->dev, "PHY PLL not locked\n");
828 return -ETIMEDOUT;
829 }
830
831 udelay(1000);
832 msec--;
833 } while (1);
834
835 return 0;
836}
837
838static int imx_hdmi_phy_init(struct imx_hdmi *hdmi)
839{
840 int i, ret;
841 bool cscon = false;
842
843 /*check csc whether needed activated in HDMI mode */
844 cscon = (is_color_space_conversion(hdmi) &&
845 !hdmi->hdmi_data.video_mode.mdvi);
846
847 /* HDMI Phy spec says to do the phy initialization sequence twice */
848 for (i = 0; i < 2; i++) {
849 imx_hdmi_phy_sel_data_en_pol(hdmi, 1);
850 imx_hdmi_phy_sel_interface_control(hdmi, 0);
851 imx_hdmi_phy_enable_tmds(hdmi, 0);
852 imx_hdmi_phy_enable_power(hdmi, 0);
853
854 /* Enable CSC */
855 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
856 if (ret)
857 return ret;
858 }
859
860 hdmi->phy_enabled = true;
861 return 0;
862}
863
864static void hdmi_tx_hdcp_config(struct imx_hdmi *hdmi)
865{
866 u8 de;
867
868 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
869 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
870 else
871 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
872
873 /* disable rx detect */
874 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
875 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
876
877 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
878
879 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
880 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
881}
882
883static void hdmi_config_AVI(struct imx_hdmi *hdmi)
884{
885 u8 val, pix_fmt, under_scan;
886 u8 act_ratio, coded_ratio, colorimetry, ext_colorimetry;
887 bool aspect_16_9;
888
889 aspect_16_9 = false; /* FIXME */
890
891 /* AVI Data Byte 1 */
892 if (hdmi->hdmi_data.enc_out_format == YCBCR444)
893 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR444;
894 else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
895 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR422;
896 else
897 pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_RGB;
898
899 under_scan = HDMI_FC_AVICONF0_SCAN_INFO_NODATA;
900
901 /*
902 * Active format identification data is present in the AVI InfoFrame.
903 * Under scan info, no bar data
904 */
905 val = pix_fmt | under_scan |
906 HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT |
907 HDMI_FC_AVICONF0_BAR_DATA_NO_DATA;
908
909 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
910
911 /* AVI Data Byte 2 -Set the Aspect Ratio */
912 if (aspect_16_9) {
913 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9;
914 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9;
915 } else {
916 act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3;
917 coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3;
918 }
919
920 /* Set up colorimetry */
921 if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
922 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO;
923 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
924 ext_colorimetry =
925 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
926 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
927 ext_colorimetry =
928 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709;
929 } else if (hdmi->hdmi_data.enc_out_format != RGB) {
930 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
931 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_SMPTE;
932 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
933 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_ITUR;
934 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
935 } else { /* Carries no data */
936 colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA;
937 ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
938 }
939
940 val = colorimetry | coded_ratio | act_ratio;
941 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
942
943 /* AVI Data Byte 3 */
944 val = HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA | ext_colorimetry |
945 HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT |
946 HDMI_FC_AVICONF2_SCALING_NONE;
947 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
948
949 /* AVI Data Byte 4 */
950 hdmi_writeb(hdmi, hdmi->vic, HDMI_FC_AVIVID);
951
952 /* AVI Data Byte 5- set up input and output pixel repetition */
953 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
954 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
955 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
956 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
957 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
958 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
959 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
960
961 /* IT Content and quantization range = don't care */
962 val = HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS |
963 HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED;
964 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
965
966 /* AVI Data Bytes 6-13 */
967 hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB0);
968 hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB1);
969 hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB0);
970 hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB1);
971 hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB0);
972 hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB1);
973 hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB0);
974 hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB1);
975}
976
977static void hdmi_av_composer(struct imx_hdmi *hdmi,
978 const struct drm_display_mode *mode)
979{
980 u8 inv_val;
981 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
982 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
983
984 vmode->mhsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PHSYNC);
985 vmode->mvsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PVSYNC);
986 vmode->minterlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
987 vmode->mpixelclock = mode->clock * 1000;
988
989 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
990
991 /* Set up HDMI_FC_INVIDCONF */
992 inv_val = (hdmi->hdmi_data.hdcp_enable ?
993 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
994 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
995
996 inv_val |= (vmode->mvsyncpolarity ?
997 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
998 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
999
1000 inv_val |= (vmode->mhsyncpolarity ?
1001 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1002 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
1003
1004 inv_val |= (vmode->mdataenablepolarity ?
1005 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1006 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1007
1008 if (hdmi->vic == 39)
1009 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1010 else
1011 inv_val |= (vmode->minterlaced ?
1012 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1013 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW);
1014
1015 inv_val |= (vmode->minterlaced ?
1016 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1017 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE);
1018
1019 inv_val |= (vmode->mdvi ?
1020 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE :
1021 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE);
1022
1023 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1024
1025 /* Set up horizontal active pixel width */
1026 hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1027 hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1028
1029 /* Set up vertical active lines */
1030 hdmi_writeb(hdmi, mode->vdisplay >> 8, HDMI_FC_INVACTV1);
1031 hdmi_writeb(hdmi, mode->vdisplay, HDMI_FC_INVACTV0);
1032
1033 /* Set up horizontal blanking pixel region width */
1034 hblank = mode->htotal - mode->hdisplay;
1035 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1036 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1037
1038 /* Set up vertical blanking pixel region width */
1039 vblank = mode->vtotal - mode->vdisplay;
1040 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1041
1042 /* Set up HSYNC active edge delay width (in pixel clks) */
1043 h_de_hs = mode->hsync_start - mode->hdisplay;
1044 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1045 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1046
1047 /* Set up VSYNC active edge delay (in lines) */
1048 v_de_vs = mode->vsync_start - mode->vdisplay;
1049 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1050
1051 /* Set up HSYNC active pulse width (in pixel clks) */
1052 hsync_len = mode->hsync_end - mode->hsync_start;
1053 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1054 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1055
1056 /* Set up VSYNC active edge delay (in lines) */
1057 vsync_len = mode->vsync_end - mode->vsync_start;
1058 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1059}
1060
1061static void imx_hdmi_phy_disable(struct imx_hdmi *hdmi)
1062{
1063 if (!hdmi->phy_enabled)
1064 return;
1065
1066 imx_hdmi_phy_enable_tmds(hdmi, 0);
1067 imx_hdmi_phy_enable_power(hdmi, 0);
1068
1069 hdmi->phy_enabled = false;
1070}
1071
1072/* HDMI Initialization Step B.4 */
1073static void imx_hdmi_enable_video_path(struct imx_hdmi *hdmi)
1074{
1075 u8 clkdis;
1076
1077 /* control period minimum duration */
1078 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1079 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1080 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1081
1082 /* Set to fill TMDS data channels */
1083 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1084 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1085 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1086
1087 /* Enable pixel clock and tmds data path */
1088 clkdis = 0x7F;
1089 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1090 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1091
1092 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1093 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1094
1095 /* Enable csc path */
1096 if (is_color_space_conversion(hdmi)) {
1097 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1098 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1099 }
1100}
1101
1102static void hdmi_enable_audio_clk(struct imx_hdmi *hdmi)
1103{
1104 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1105}
1106
1107/* Workaround to clear the overflow condition */
1108static void imx_hdmi_clear_overflow(struct imx_hdmi *hdmi)
1109{
1110 int count;
1111 u8 val;
1112
1113 /* TMDS software reset */
1114 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1115
1116 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1117 if (hdmi->dev_type == IMX6DL_HDMI) {
1118 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1119 return;
1120 }
1121
1122 for (count = 0; count < 4; count++)
1123 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1124}
1125
1126static void hdmi_enable_overflow_interrupts(struct imx_hdmi *hdmi)
1127{
1128 hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1129 hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1130}
1131
1132static void hdmi_disable_overflow_interrupts(struct imx_hdmi *hdmi)
1133{
1134 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1135 HDMI_IH_MUTE_FC_STAT2);
1136}
1137
1138static int imx_hdmi_setup(struct imx_hdmi *hdmi, struct drm_display_mode *mode)
1139{
1140 int ret;
1141
1142 hdmi_disable_overflow_interrupts(hdmi);
1143
1144 hdmi->vic = drm_match_cea_mode(mode);
1145
1146 if (!hdmi->vic) {
1147 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1148 hdmi->hdmi_data.video_mode.mdvi = true;
1149 } else {
1150 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1151 hdmi->hdmi_data.video_mode.mdvi = false;
1152 }
1153
1154 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1155 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1156 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1157 (hdmi->vic == 17) || (hdmi->vic == 18))
1158 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1159 else
1160 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1161
1162 if ((hdmi->vic == 10) || (hdmi->vic == 11) ||
1163 (hdmi->vic == 12) || (hdmi->vic == 13) ||
1164 (hdmi->vic == 14) || (hdmi->vic == 15) ||
1165 (hdmi->vic == 25) || (hdmi->vic == 26) ||
1166 (hdmi->vic == 27) || (hdmi->vic == 28) ||
1167 (hdmi->vic == 29) || (hdmi->vic == 30) ||
1168 (hdmi->vic == 35) || (hdmi->vic == 36) ||
1169 (hdmi->vic == 37) || (hdmi->vic == 38))
1170 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1171 else
1172 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1173
1174 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1175
1176 /* TODO: Get input format from IPU (via FB driver interface) */
1177 hdmi->hdmi_data.enc_in_format = RGB;
1178
1179 hdmi->hdmi_data.enc_out_format = RGB;
1180
1181 hdmi->hdmi_data.enc_color_depth = 8;
1182 hdmi->hdmi_data.pix_repet_factor = 0;
1183 hdmi->hdmi_data.hdcp_enable = 0;
1184 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1185
1186 /* HDMI Initialization Step B.1 */
1187 hdmi_av_composer(hdmi, mode);
1188
1189 /* HDMI Initializateion Step B.2 */
1190 ret = imx_hdmi_phy_init(hdmi);
1191 if (ret)
1192 return ret;
1193
1194 /* HDMI Initialization Step B.3 */
1195 imx_hdmi_enable_video_path(hdmi);
1196
1197 /* not for DVI mode */
1198 if (hdmi->hdmi_data.video_mode.mdvi) {
1199 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1200 } else {
1201 dev_dbg(hdmi->dev, "%s CEA mode\n", __func__);
1202
1203 /* HDMI Initialization Step E - Configure audio */
1204 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1205 hdmi_enable_audio_clk(hdmi);
1206
1207 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1208 hdmi_config_AVI(hdmi);
1209 }
1210
1211 hdmi_video_packetize(hdmi);
1212 hdmi_video_csc(hdmi);
1213 hdmi_video_sample(hdmi);
1214 hdmi_tx_hdcp_config(hdmi);
1215
1216 imx_hdmi_clear_overflow(hdmi);
1217 if (hdmi->cable_plugin && !hdmi->hdmi_data.video_mode.mdvi)
1218 hdmi_enable_overflow_interrupts(hdmi);
1219
1220 return 0;
1221}
1222
1223/* Wait until we are registered to enable interrupts */
1224static int imx_hdmi_fb_registered(struct imx_hdmi *hdmi)
1225{
1226 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1227 HDMI_PHY_I2CM_INT_ADDR);
1228
1229 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1230 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1231 HDMI_PHY_I2CM_CTLINT_ADDR);
1232
1233 /* enable cable hot plug irq */
1234 hdmi_writeb(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
1235
1236 /* Clear Hotplug interrupts */
1237 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1238
1239 return 0;
1240}
1241
1242static void initialize_hdmi_ih_mutes(struct imx_hdmi *hdmi)
1243{
1244 u8 ih_mute;
1245
1246 /*
1247 * Boot up defaults are:
1248 * HDMI_IH_MUTE = 0x03 (disabled)
1249 * HDMI_IH_MUTE_* = 0x00 (enabled)
1250 *
1251 * Disable top level interrupt bits in HDMI block
1252 */
1253 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1254 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1255 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1256
1257 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1258
1259 /* by default mask all interrupts */
1260 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1261 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1262 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1263 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1264 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1265 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1266 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1267 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1268 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1269 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1270 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1271 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1272 hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1273 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1274 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1275
1276 /* Disable interrupts in the IH_MUTE_* registers */
1277 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1278 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1279 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1280 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1281 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1282 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1283 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1284 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1285 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1286 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1287
1288 /* Enable top level interrupt bits in HDMI block */
1289 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1290 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1291 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1292}
1293
1294static void imx_hdmi_poweron(struct imx_hdmi *hdmi)
1295{
1296 imx_hdmi_setup(hdmi, &hdmi->previous_mode);
1297}
1298
1299static void imx_hdmi_poweroff(struct imx_hdmi *hdmi)
1300{
1301 imx_hdmi_phy_disable(hdmi);
1302}
1303
1304static void imx_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1305 struct drm_display_mode *mode,
1306 struct drm_display_mode *adjusted_mode)
1307{
1308 struct imx_hdmi *hdmi = bridge->driver_private;
1309
1310 imx_hdmi_setup(hdmi, mode);
1311
1312 /* Store the display mode for plugin/DKMS poweron events */
1313 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1314}
1315
1316static bool imx_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1317 const struct drm_display_mode *mode,
1318 struct drm_display_mode *adjusted_mode)
1319{
1320 return true;
1321}
1322
1323static void imx_hdmi_bridge_disable(struct drm_bridge *bridge)
1324{
1325 struct imx_hdmi *hdmi = bridge->driver_private;
1326
1327 imx_hdmi_poweroff(hdmi);
1328}
1329
1330static void imx_hdmi_bridge_enable(struct drm_bridge *bridge)
1331{
1332 struct imx_hdmi *hdmi = bridge->driver_private;
1333
1334 imx_hdmi_poweron(hdmi);
1335}
1336
1337static void imx_hdmi_bridge_destroy(struct drm_bridge *bridge)
1338{
1339 drm_bridge_cleanup(bridge);
1340 kfree(bridge);
1341}
1342
1343static void imx_hdmi_bridge_nop(struct drm_bridge *bridge)
1344{
1345 /* do nothing */
1346}
1347
1348static enum drm_connector_status imx_hdmi_connector_detect(struct drm_connector
1349 *connector, bool force)
1350{
1351 struct imx_hdmi *hdmi = container_of(connector, struct imx_hdmi,
1352 connector);
1353
1354 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1355 connector_status_connected : connector_status_disconnected;
1356}
1357
1358static int imx_hdmi_connector_get_modes(struct drm_connector *connector)
1359{
1360 struct imx_hdmi *hdmi = container_of(connector, struct imx_hdmi,
1361 connector);
1362 struct edid *edid;
1363 int ret;
1364
1365 if (!hdmi->ddc)
1366 return 0;
1367
1368 edid = drm_get_edid(connector, hdmi->ddc);
1369 if (edid) {
1370 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1371 edid->width_cm, edid->height_cm);
1372
1373 drm_mode_connector_update_edid_property(connector, edid);
1374 ret = drm_add_edid_modes(connector, edid);
1375 kfree(edid);
1376 } else {
1377 dev_dbg(hdmi->dev, "failed to get edid\n");
1378 }
1379
1380 return 0;
1381}
1382
1383static struct drm_encoder *imx_hdmi_connector_best_encoder(struct drm_connector
1384 *connector)
1385{
1386 struct imx_hdmi *hdmi = container_of(connector, struct imx_hdmi,
1387 connector);
1388
1389 return hdmi->encoder;
1390}
1391
1392static void imx_hdmi_connector_destroy(struct drm_connector *connector)
1393{
1394 drm_connector_unregister(connector);
1395 drm_connector_cleanup(connector);
1396}
1397
1398static struct drm_connector_funcs imx_hdmi_connector_funcs = {
1399 .dpms = drm_helper_connector_dpms,
1400 .fill_modes = drm_helper_probe_single_connector_modes,
1401 .detect = imx_hdmi_connector_detect,
1402 .destroy = imx_hdmi_connector_destroy,
1403};
1404
1405static struct drm_connector_helper_funcs imx_hdmi_connector_helper_funcs = {
1406 .get_modes = imx_hdmi_connector_get_modes,
1407 .best_encoder = imx_hdmi_connector_best_encoder,
1408};
1409
1410struct drm_bridge_funcs imx_hdmi_bridge_funcs = {
1411 .enable = imx_hdmi_bridge_enable,
1412 .disable = imx_hdmi_bridge_disable,
1413 .pre_enable = imx_hdmi_bridge_nop,
1414 .post_disable = imx_hdmi_bridge_nop,
1415 .mode_set = imx_hdmi_bridge_mode_set,
1416 .mode_fixup = imx_hdmi_bridge_mode_fixup,
1417 .destroy = imx_hdmi_bridge_destroy,
1418};
1419
1420static irqreturn_t imx_hdmi_hardirq(int irq, void *dev_id)
1421{
1422 struct imx_hdmi *hdmi = dev_id;
1423 u8 intr_stat;
1424
1425 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1426 if (intr_stat)
1427 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1428
1429 return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
1430}
1431
1432static irqreturn_t imx_hdmi_irq(int irq, void *dev_id)
1433{
1434 struct imx_hdmi *hdmi = dev_id;
1435 u8 intr_stat;
1436 u8 phy_int_pol;
1437
1438 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1439
1440 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1441
1442 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1443 if (phy_int_pol & HDMI_PHY_HPD) {
1444 dev_dbg(hdmi->dev, "EVENT=plugin\n");
1445
1446 hdmi_modb(hdmi, 0, HDMI_PHY_HPD, HDMI_PHY_POL0);
1447
1448 imx_hdmi_poweron(hdmi);
1449 } else {
1450 dev_dbg(hdmi->dev, "EVENT=plugout\n");
1451
1452 hdmi_modb(hdmi, HDMI_PHY_HPD, HDMI_PHY_HPD,
1453 HDMI_PHY_POL0);
1454
1455 imx_hdmi_poweroff(hdmi);
1456 }
1457 drm_helper_hpd_irq_event(hdmi->connector.dev);
1458 }
1459
1460 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1461 hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1462
1463 return IRQ_HANDLED;
1464}
1465
1466static int imx_hdmi_register(struct drm_device *drm, struct imx_hdmi *hdmi)
1467{
1468 struct drm_encoder *encoder = hdmi->encoder;
1469 struct drm_bridge *bridge;
1470 int ret;
1471
1472 bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1473 if (!bridge) {
1474 DRM_ERROR("Failed to allocate drm bridge\n");
1475 return -ENOMEM;
1476 }
1477
1478 hdmi->bridge = bridge;
1479 bridge->driver_private = hdmi;
1480
1481 ret = drm_bridge_init(drm, bridge, &imx_hdmi_bridge_funcs);
1482 if (ret) {
1483 DRM_ERROR("Failed to initialize bridge with drm\n");
1484 return -EINVAL;
1485 }
1486
1487 encoder->bridge = bridge;
1488 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1489
1490 drm_connector_helper_add(&hdmi->connector,
1491 &imx_hdmi_connector_helper_funcs);
1492 drm_connector_init(drm, &hdmi->connector, &imx_hdmi_connector_funcs,
1493 DRM_MODE_CONNECTOR_HDMIA);
1494
1495 hdmi->connector.encoder = encoder;
1496
1497 drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
1498
1499 return 0;
1500}
1501
1502int imx_hdmi_bind(struct device *dev, struct device *master,
1503 void *data, struct drm_encoder *encoder,
1504 struct resource *iores, int irq,
1505 const struct dw_hdmi_plat_data *plat_data)
1506{
1507 struct drm_device *drm = data;
1508 struct device_node *np = dev->of_node;
1509 struct device_node *ddc_node;
1510 struct imx_hdmi *hdmi;
1511 int ret;
1512
1513 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1514 if (!hdmi)
1515 return -ENOMEM;
1516
1517 hdmi->plat_data = plat_data;
1518 hdmi->dev = dev;
1519 hdmi->dev_type = plat_data->dev_type;
1520 hdmi->sample_rate = 48000;
1521 hdmi->ratio = 100;
1522 hdmi->encoder = encoder;
1523
1524 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
1525 if (ddc_node) {
1526 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1527 of_node_put(ddc_node);
1528 if (!hdmi->ddc) {
1529 dev_dbg(hdmi->dev, "failed to read ddc node\n");
1530 return -EPROBE_DEFER;
1531 }
1532
1533 } else {
1534 dev_dbg(hdmi->dev, "no ddc property found\n");
1535 }
1536
1537 ret = devm_request_threaded_irq(dev, irq, imx_hdmi_hardirq,
1538 imx_hdmi_irq, IRQF_SHARED,
1539 dev_name(dev), hdmi);
1540 if (ret)
1541 return ret;
1542
1543 hdmi->regs = devm_ioremap_resource(dev, iores);
1544 if (IS_ERR(hdmi->regs))
1545 return PTR_ERR(hdmi->regs);
1546
1547 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1548 if (IS_ERR(hdmi->isfr_clk)) {
1549 ret = PTR_ERR(hdmi->isfr_clk);
1550 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
1551 return ret;
1552 }
1553
1554 ret = clk_prepare_enable(hdmi->isfr_clk);
1555 if (ret) {
1556 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
1557 return ret;
1558 }
1559
1560 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1561 if (IS_ERR(hdmi->iahb_clk)) {
1562 ret = PTR_ERR(hdmi->iahb_clk);
1563 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
1564 goto err_isfr;
1565 }
1566
1567 ret = clk_prepare_enable(hdmi->iahb_clk);
1568 if (ret) {
1569 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
1570 goto err_isfr;
1571 }
1572
1573 /* Product and revision IDs */
1574 dev_info(dev,
1575 "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1576 hdmi_readb(hdmi, HDMI_DESIGN_ID),
1577 hdmi_readb(hdmi, HDMI_REVISION_ID),
1578 hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1579 hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
1580
1581 initialize_hdmi_ih_mutes(hdmi);
1582
1583 /*
1584 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1585 * N and cts values before enabling phy
1586 */
1587 hdmi_init_clk_regenerator(hdmi);
1588
1589 /*
1590 * Configure registers related to HDMI interrupt
1591 * generation before registering IRQ.
1592 */
1593 hdmi_writeb(hdmi, HDMI_PHY_HPD, HDMI_PHY_POL0);
1594
1595 /* Clear Hotplug interrupts */
1596 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1597
1598 ret = imx_hdmi_fb_registered(hdmi);
1599 if (ret)
1600 goto err_iahb;
1601
1602 ret = imx_hdmi_register(drm, hdmi);
1603 if (ret)
1604 goto err_iahb;
1605
1606 /* Unmute interrupts */
1607 hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1608
1609 dev_set_drvdata(dev, hdmi);
1610
1611 return 0;
1612
1613err_iahb:
1614 clk_disable_unprepare(hdmi->iahb_clk);
1615err_isfr:
1616 clk_disable_unprepare(hdmi->isfr_clk);
1617
1618 return ret;
1619}
1620EXPORT_SYMBOL_GPL(imx_hdmi_bind);
1621
1622void imx_hdmi_unbind(struct device *dev, struct device *master, void *data)
1623{
1624 struct imx_hdmi *hdmi = dev_get_drvdata(dev);
1625
1626 /* Disable all interrupts */
1627 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1628
1629 hdmi->connector.funcs->destroy(&hdmi->connector);
1630 hdmi->encoder->funcs->destroy(hdmi->encoder);
1631
1632 clk_disable_unprepare(hdmi->iahb_clk);
1633 clk_disable_unprepare(hdmi->isfr_clk);
1634 i2c_put_adapter(hdmi->ddc);
1635}
1636EXPORT_SYMBOL_GPL(imx_hdmi_unbind);
1637
1638MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1639MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
1640MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
1641MODULE_DESCRIPTION("i.MX6 HDMI transmitter driver");
1642MODULE_LICENSE("GPL");
1643MODULE_ALIAS("platform:imx-hdmi");
diff --git a/drivers/gpu/drm/imx/imx-hdmi.h b/drivers/gpu/drm/imx/imx-hdmi.h
deleted file mode 100644
index db407f0a84f2..000000000000
--- a/drivers/gpu/drm/imx/imx-hdmi.h
+++ /dev/null
@@ -1,1076 +0,0 @@
1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef __IMX_HDMI_H__
11#define __IMX_HDMI_H__
12
13/* Identification Registers */
14#define HDMI_DESIGN_ID 0x0000
15#define HDMI_REVISION_ID 0x0001
16#define HDMI_PRODUCT_ID0 0x0002
17#define HDMI_PRODUCT_ID1 0x0003
18#define HDMI_CONFIG0_ID 0x0004
19#define HDMI_CONFIG1_ID 0x0005
20#define HDMI_CONFIG2_ID 0x0006
21#define HDMI_CONFIG3_ID 0x0007
22
23/* Interrupt Registers */
24#define HDMI_IH_FC_STAT0 0x0100
25#define HDMI_IH_FC_STAT1 0x0101
26#define HDMI_IH_FC_STAT2 0x0102
27#define HDMI_IH_AS_STAT0 0x0103
28#define HDMI_IH_PHY_STAT0 0x0104
29#define HDMI_IH_I2CM_STAT0 0x0105
30#define HDMI_IH_CEC_STAT0 0x0106
31#define HDMI_IH_VP_STAT0 0x0107
32#define HDMI_IH_I2CMPHY_STAT0 0x0108
33#define HDMI_IH_AHBDMAAUD_STAT0 0x0109
34
35#define HDMI_IH_MUTE_FC_STAT0 0x0180
36#define HDMI_IH_MUTE_FC_STAT1 0x0181
37#define HDMI_IH_MUTE_FC_STAT2 0x0182
38#define HDMI_IH_MUTE_AS_STAT0 0x0183
39#define HDMI_IH_MUTE_PHY_STAT0 0x0184
40#define HDMI_IH_MUTE_I2CM_STAT0 0x0185
41#define HDMI_IH_MUTE_CEC_STAT0 0x0186
42#define HDMI_IH_MUTE_VP_STAT0 0x0187
43#define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188
44#define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189
45#define HDMI_IH_MUTE 0x01FF
46
47/* Video Sample Registers */
48#define HDMI_TX_INVID0 0x0200
49#define HDMI_TX_INSTUFFING 0x0201
50#define HDMI_TX_GYDATA0 0x0202
51#define HDMI_TX_GYDATA1 0x0203
52#define HDMI_TX_RCRDATA0 0x0204
53#define HDMI_TX_RCRDATA1 0x0205
54#define HDMI_TX_BCBDATA0 0x0206
55#define HDMI_TX_BCBDATA1 0x0207
56
57/* Video Packetizer Registers */
58#define HDMI_VP_STATUS 0x0800
59#define HDMI_VP_PR_CD 0x0801
60#define HDMI_VP_STUFF 0x0802
61#define HDMI_VP_REMAP 0x0803
62#define HDMI_VP_CONF 0x0804
63#define HDMI_VP_STAT 0x0805
64#define HDMI_VP_INT 0x0806
65#define HDMI_VP_MASK 0x0807
66#define HDMI_VP_POL 0x0808
67
68/* Frame Composer Registers */
69#define HDMI_FC_INVIDCONF 0x1000
70#define HDMI_FC_INHACTV0 0x1001
71#define HDMI_FC_INHACTV1 0x1002
72#define HDMI_FC_INHBLANK0 0x1003
73#define HDMI_FC_INHBLANK1 0x1004
74#define HDMI_FC_INVACTV0 0x1005
75#define HDMI_FC_INVACTV1 0x1006
76#define HDMI_FC_INVBLANK 0x1007
77#define HDMI_FC_HSYNCINDELAY0 0x1008
78#define HDMI_FC_HSYNCINDELAY1 0x1009
79#define HDMI_FC_HSYNCINWIDTH0 0x100A
80#define HDMI_FC_HSYNCINWIDTH1 0x100B
81#define HDMI_FC_VSYNCINDELAY 0x100C
82#define HDMI_FC_VSYNCINWIDTH 0x100D
83#define HDMI_FC_INFREQ0 0x100E
84#define HDMI_FC_INFREQ1 0x100F
85#define HDMI_FC_INFREQ2 0x1010
86#define HDMI_FC_CTRLDUR 0x1011
87#define HDMI_FC_EXCTRLDUR 0x1012
88#define HDMI_FC_EXCTRLSPAC 0x1013
89#define HDMI_FC_CH0PREAM 0x1014
90#define HDMI_FC_CH1PREAM 0x1015
91#define HDMI_FC_CH2PREAM 0x1016
92#define HDMI_FC_AVICONF3 0x1017
93#define HDMI_FC_GCP 0x1018
94#define HDMI_FC_AVICONF0 0x1019
95#define HDMI_FC_AVICONF1 0x101A
96#define HDMI_FC_AVICONF2 0x101B
97#define HDMI_FC_AVIVID 0x101C
98#define HDMI_FC_AVIETB0 0x101D
99#define HDMI_FC_AVIETB1 0x101E
100#define HDMI_FC_AVISBB0 0x101F
101#define HDMI_FC_AVISBB1 0x1020
102#define HDMI_FC_AVIELB0 0x1021
103#define HDMI_FC_AVIELB1 0x1022
104#define HDMI_FC_AVISRB0 0x1023
105#define HDMI_FC_AVISRB1 0x1024
106#define HDMI_FC_AUDICONF0 0x1025
107#define HDMI_FC_AUDICONF1 0x1026
108#define HDMI_FC_AUDICONF2 0x1027
109#define HDMI_FC_AUDICONF3 0x1028
110#define HDMI_FC_VSDIEEEID0 0x1029
111#define HDMI_FC_VSDSIZE 0x102A
112#define HDMI_FC_VSDIEEEID1 0x1030
113#define HDMI_FC_VSDIEEEID2 0x1031
114#define HDMI_FC_VSDPAYLOAD0 0x1032
115#define HDMI_FC_VSDPAYLOAD1 0x1033
116#define HDMI_FC_VSDPAYLOAD2 0x1034
117#define HDMI_FC_VSDPAYLOAD3 0x1035
118#define HDMI_FC_VSDPAYLOAD4 0x1036
119#define HDMI_FC_VSDPAYLOAD5 0x1037
120#define HDMI_FC_VSDPAYLOAD6 0x1038
121#define HDMI_FC_VSDPAYLOAD7 0x1039
122#define HDMI_FC_VSDPAYLOAD8 0x103A
123#define HDMI_FC_VSDPAYLOAD9 0x103B
124#define HDMI_FC_VSDPAYLOAD10 0x103C
125#define HDMI_FC_VSDPAYLOAD11 0x103D
126#define HDMI_FC_VSDPAYLOAD12 0x103E
127#define HDMI_FC_VSDPAYLOAD13 0x103F
128#define HDMI_FC_VSDPAYLOAD14 0x1040
129#define HDMI_FC_VSDPAYLOAD15 0x1041
130#define HDMI_FC_VSDPAYLOAD16 0x1042
131#define HDMI_FC_VSDPAYLOAD17 0x1043
132#define HDMI_FC_VSDPAYLOAD18 0x1044
133#define HDMI_FC_VSDPAYLOAD19 0x1045
134#define HDMI_FC_VSDPAYLOAD20 0x1046
135#define HDMI_FC_VSDPAYLOAD21 0x1047
136#define HDMI_FC_VSDPAYLOAD22 0x1048
137#define HDMI_FC_VSDPAYLOAD23 0x1049
138#define HDMI_FC_SPDVENDORNAME0 0x104A
139#define HDMI_FC_SPDVENDORNAME1 0x104B
140#define HDMI_FC_SPDVENDORNAME2 0x104C
141#define HDMI_FC_SPDVENDORNAME3 0x104D
142#define HDMI_FC_SPDVENDORNAME4 0x104E
143#define HDMI_FC_SPDVENDORNAME5 0x104F
144#define HDMI_FC_SPDVENDORNAME6 0x1050
145#define HDMI_FC_SPDVENDORNAME7 0x1051
146#define HDMI_FC_SDPPRODUCTNAME0 0x1052
147#define HDMI_FC_SDPPRODUCTNAME1 0x1053
148#define HDMI_FC_SDPPRODUCTNAME2 0x1054
149#define HDMI_FC_SDPPRODUCTNAME3 0x1055
150#define HDMI_FC_SDPPRODUCTNAME4 0x1056
151#define HDMI_FC_SDPPRODUCTNAME5 0x1057
152#define HDMI_FC_SDPPRODUCTNAME6 0x1058
153#define HDMI_FC_SDPPRODUCTNAME7 0x1059
154#define HDMI_FC_SDPPRODUCTNAME8 0x105A
155#define HDMI_FC_SDPPRODUCTNAME9 0x105B
156#define HDMI_FC_SDPPRODUCTNAME10 0x105C
157#define HDMI_FC_SDPPRODUCTNAME11 0x105D
158#define HDMI_FC_SDPPRODUCTNAME12 0x105E
159#define HDMI_FC_SDPPRODUCTNAME13 0x105F
160#define HDMI_FC_SDPPRODUCTNAME14 0x1060
161#define HDMI_FC_SPDPRODUCTNAME15 0x1061
162#define HDMI_FC_SPDDEVICEINF 0x1062
163#define HDMI_FC_AUDSCONF 0x1063
164#define HDMI_FC_AUDSSTAT 0x1064
165#define HDMI_FC_DATACH0FILL 0x1070
166#define HDMI_FC_DATACH1FILL 0x1071
167#define HDMI_FC_DATACH2FILL 0x1072
168#define HDMI_FC_CTRLQHIGH 0x1073
169#define HDMI_FC_CTRLQLOW 0x1074
170#define HDMI_FC_ACP0 0x1075
171#define HDMI_FC_ACP28 0x1076
172#define HDMI_FC_ACP27 0x1077
173#define HDMI_FC_ACP26 0x1078
174#define HDMI_FC_ACP25 0x1079
175#define HDMI_FC_ACP24 0x107A
176#define HDMI_FC_ACP23 0x107B
177#define HDMI_FC_ACP22 0x107C
178#define HDMI_FC_ACP21 0x107D
179#define HDMI_FC_ACP20 0x107E
180#define HDMI_FC_ACP19 0x107F
181#define HDMI_FC_ACP18 0x1080
182#define HDMI_FC_ACP17 0x1081
183#define HDMI_FC_ACP16 0x1082
184#define HDMI_FC_ACP15 0x1083
185#define HDMI_FC_ACP14 0x1084
186#define HDMI_FC_ACP13 0x1085
187#define HDMI_FC_ACP12 0x1086
188#define HDMI_FC_ACP11 0x1087
189#define HDMI_FC_ACP10 0x1088
190#define HDMI_FC_ACP9 0x1089
191#define HDMI_FC_ACP8 0x108A
192#define HDMI_FC_ACP7 0x108B
193#define HDMI_FC_ACP6 0x108C
194#define HDMI_FC_ACP5 0x108D
195#define HDMI_FC_ACP4 0x108E
196#define HDMI_FC_ACP3 0x108F
197#define HDMI_FC_ACP2 0x1090
198#define HDMI_FC_ACP1 0x1091
199#define HDMI_FC_ISCR1_0 0x1092
200#define HDMI_FC_ISCR1_16 0x1093
201#define HDMI_FC_ISCR1_15 0x1094
202#define HDMI_FC_ISCR1_14 0x1095
203#define HDMI_FC_ISCR1_13 0x1096
204#define HDMI_FC_ISCR1_12 0x1097
205#define HDMI_FC_ISCR1_11 0x1098
206#define HDMI_FC_ISCR1_10 0x1099
207#define HDMI_FC_ISCR1_9 0x109A
208#define HDMI_FC_ISCR1_8 0x109B
209#define HDMI_FC_ISCR1_7 0x109C
210#define HDMI_FC_ISCR1_6 0x109D
211#define HDMI_FC_ISCR1_5 0x109E
212#define HDMI_FC_ISCR1_4 0x109F
213#define HDMI_FC_ISCR1_3 0x10A0
214#define HDMI_FC_ISCR1_2 0x10A1
215#define HDMI_FC_ISCR1_1 0x10A2
216#define HDMI_FC_ISCR2_15 0x10A3
217#define HDMI_FC_ISCR2_14 0x10A4
218#define HDMI_FC_ISCR2_13 0x10A5
219#define HDMI_FC_ISCR2_12 0x10A6
220#define HDMI_FC_ISCR2_11 0x10A7
221#define HDMI_FC_ISCR2_10 0x10A8
222#define HDMI_FC_ISCR2_9 0x10A9
223#define HDMI_FC_ISCR2_8 0x10AA
224#define HDMI_FC_ISCR2_7 0x10AB
225#define HDMI_FC_ISCR2_6 0x10AC
226#define HDMI_FC_ISCR2_5 0x10AD
227#define HDMI_FC_ISCR2_4 0x10AE
228#define HDMI_FC_ISCR2_3 0x10AF
229#define HDMI_FC_ISCR2_2 0x10B0
230#define HDMI_FC_ISCR2_1 0x10B1
231#define HDMI_FC_ISCR2_0 0x10B2
232#define HDMI_FC_DATAUTO0 0x10B3
233#define HDMI_FC_DATAUTO1 0x10B4
234#define HDMI_FC_DATAUTO2 0x10B5
235#define HDMI_FC_DATMAN 0x10B6
236#define HDMI_FC_DATAUTO3 0x10B7
237#define HDMI_FC_RDRB0 0x10B8
238#define HDMI_FC_RDRB1 0x10B9
239#define HDMI_FC_RDRB2 0x10BA
240#define HDMI_FC_RDRB3 0x10BB
241#define HDMI_FC_RDRB4 0x10BC
242#define HDMI_FC_RDRB5 0x10BD
243#define HDMI_FC_RDRB6 0x10BE
244#define HDMI_FC_RDRB7 0x10BF
245#define HDMI_FC_STAT0 0x10D0
246#define HDMI_FC_INT0 0x10D1
247#define HDMI_FC_MASK0 0x10D2
248#define HDMI_FC_POL0 0x10D3
249#define HDMI_FC_STAT1 0x10D4
250#define HDMI_FC_INT1 0x10D5
251#define HDMI_FC_MASK1 0x10D6
252#define HDMI_FC_POL1 0x10D7
253#define HDMI_FC_STAT2 0x10D8
254#define HDMI_FC_INT2 0x10D9
255#define HDMI_FC_MASK2 0x10DA
256#define HDMI_FC_POL2 0x10DB
257#define HDMI_FC_PRCONF 0x10E0
258
259#define HDMI_FC_GMD_STAT 0x1100
260#define HDMI_FC_GMD_EN 0x1101
261#define HDMI_FC_GMD_UP 0x1102
262#define HDMI_FC_GMD_CONF 0x1103
263#define HDMI_FC_GMD_HB 0x1104
264#define HDMI_FC_GMD_PB0 0x1105
265#define HDMI_FC_GMD_PB1 0x1106
266#define HDMI_FC_GMD_PB2 0x1107
267#define HDMI_FC_GMD_PB3 0x1108
268#define HDMI_FC_GMD_PB4 0x1109
269#define HDMI_FC_GMD_PB5 0x110A
270#define HDMI_FC_GMD_PB6 0x110B
271#define HDMI_FC_GMD_PB7 0x110C
272#define HDMI_FC_GMD_PB8 0x110D
273#define HDMI_FC_GMD_PB9 0x110E
274#define HDMI_FC_GMD_PB10 0x110F
275#define HDMI_FC_GMD_PB11 0x1110
276#define HDMI_FC_GMD_PB12 0x1111
277#define HDMI_FC_GMD_PB13 0x1112
278#define HDMI_FC_GMD_PB14 0x1113
279#define HDMI_FC_GMD_PB15 0x1114
280#define HDMI_FC_GMD_PB16 0x1115
281#define HDMI_FC_GMD_PB17 0x1116
282#define HDMI_FC_GMD_PB18 0x1117
283#define HDMI_FC_GMD_PB19 0x1118
284#define HDMI_FC_GMD_PB20 0x1119
285#define HDMI_FC_GMD_PB21 0x111A
286#define HDMI_FC_GMD_PB22 0x111B
287#define HDMI_FC_GMD_PB23 0x111C
288#define HDMI_FC_GMD_PB24 0x111D
289#define HDMI_FC_GMD_PB25 0x111E
290#define HDMI_FC_GMD_PB26 0x111F
291#define HDMI_FC_GMD_PB27 0x1120
292
293#define HDMI_FC_DBGFORCE 0x1200
294#define HDMI_FC_DBGAUD0CH0 0x1201
295#define HDMI_FC_DBGAUD1CH0 0x1202
296#define HDMI_FC_DBGAUD2CH0 0x1203
297#define HDMI_FC_DBGAUD0CH1 0x1204
298#define HDMI_FC_DBGAUD1CH1 0x1205
299#define HDMI_FC_DBGAUD2CH1 0x1206
300#define HDMI_FC_DBGAUD0CH2 0x1207
301#define HDMI_FC_DBGAUD1CH2 0x1208
302#define HDMI_FC_DBGAUD2CH2 0x1209
303#define HDMI_FC_DBGAUD0CH3 0x120A
304#define HDMI_FC_DBGAUD1CH3 0x120B
305#define HDMI_FC_DBGAUD2CH3 0x120C
306#define HDMI_FC_DBGAUD0CH4 0x120D
307#define HDMI_FC_DBGAUD1CH4 0x120E
308#define HDMI_FC_DBGAUD2CH4 0x120F
309#define HDMI_FC_DBGAUD0CH5 0x1210
310#define HDMI_FC_DBGAUD1CH5 0x1211
311#define HDMI_FC_DBGAUD2CH5 0x1212
312#define HDMI_FC_DBGAUD0CH6 0x1213
313#define HDMI_FC_DBGAUD1CH6 0x1214
314#define HDMI_FC_DBGAUD2CH6 0x1215
315#define HDMI_FC_DBGAUD0CH7 0x1216
316#define HDMI_FC_DBGAUD1CH7 0x1217
317#define HDMI_FC_DBGAUD2CH7 0x1218
318#define HDMI_FC_DBGTMDS0 0x1219
319#define HDMI_FC_DBGTMDS1 0x121A
320#define HDMI_FC_DBGTMDS2 0x121B
321
322/* HDMI Source PHY Registers */
323#define HDMI_PHY_CONF0 0x3000
324#define HDMI_PHY_TST0 0x3001
325#define HDMI_PHY_TST1 0x3002
326#define HDMI_PHY_TST2 0x3003
327#define HDMI_PHY_STAT0 0x3004
328#define HDMI_PHY_INT0 0x3005
329#define HDMI_PHY_MASK0 0x3006
330#define HDMI_PHY_POL0 0x3007
331
332/* HDMI Master PHY Registers */
333#define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020
334#define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021
335#define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022
336#define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023
337#define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024
338#define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025
339#define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026
340#define HDMI_PHY_I2CM_INT_ADDR 0x3027
341#define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028
342#define HDMI_PHY_I2CM_DIV_ADDR 0x3029
343#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a
344#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b
345#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c
346#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d
347#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e
348#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f
349#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030
350#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031
351#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032
352
353/* Audio Sampler Registers */
354#define HDMI_AUD_CONF0 0x3100
355#define HDMI_AUD_CONF1 0x3101
356#define HDMI_AUD_INT 0x3102
357#define HDMI_AUD_CONF2 0x3103
358#define HDMI_AUD_N1 0x3200
359#define HDMI_AUD_N2 0x3201
360#define HDMI_AUD_N3 0x3202
361#define HDMI_AUD_CTS1 0x3203
362#define HDMI_AUD_CTS2 0x3204
363#define HDMI_AUD_CTS3 0x3205
364#define HDMI_AUD_INPUTCLKFS 0x3206
365#define HDMI_AUD_SPDIFINT 0x3302
366#define HDMI_AUD_CONF0_HBR 0x3400
367#define HDMI_AUD_HBR_STATUS 0x3401
368#define HDMI_AUD_HBR_INT 0x3402
369#define HDMI_AUD_HBR_POL 0x3403
370#define HDMI_AUD_HBR_MASK 0x3404
371
372/*
373 * Generic Parallel Audio Interface Registers
374 * Not used as GPAUD interface is not enabled in hw
375 */
376#define HDMI_GP_CONF0 0x3500
377#define HDMI_GP_CONF1 0x3501
378#define HDMI_GP_CONF2 0x3502
379#define HDMI_GP_STAT 0x3503
380#define HDMI_GP_INT 0x3504
381#define HDMI_GP_MASK 0x3505
382#define HDMI_GP_POL 0x3506
383
384/* Audio DMA Registers */
385#define HDMI_AHB_DMA_CONF0 0x3600
386#define HDMI_AHB_DMA_START 0x3601
387#define HDMI_AHB_DMA_STOP 0x3602
388#define HDMI_AHB_DMA_THRSLD 0x3603
389#define HDMI_AHB_DMA_STRADDR0 0x3604
390#define HDMI_AHB_DMA_STRADDR1 0x3605
391#define HDMI_AHB_DMA_STRADDR2 0x3606
392#define HDMI_AHB_DMA_STRADDR3 0x3607
393#define HDMI_AHB_DMA_STPADDR0 0x3608
394#define HDMI_AHB_DMA_STPADDR1 0x3609
395#define HDMI_AHB_DMA_STPADDR2 0x360a
396#define HDMI_AHB_DMA_STPADDR3 0x360b
397#define HDMI_AHB_DMA_BSTADDR0 0x360c
398#define HDMI_AHB_DMA_BSTADDR1 0x360d
399#define HDMI_AHB_DMA_BSTADDR2 0x360e
400#define HDMI_AHB_DMA_BSTADDR3 0x360f
401#define HDMI_AHB_DMA_MBLENGTH0 0x3610
402#define HDMI_AHB_DMA_MBLENGTH1 0x3611
403#define HDMI_AHB_DMA_STAT 0x3612
404#define HDMI_AHB_DMA_INT 0x3613
405#define HDMI_AHB_DMA_MASK 0x3614
406#define HDMI_AHB_DMA_POL 0x3615
407#define HDMI_AHB_DMA_CONF1 0x3616
408#define HDMI_AHB_DMA_BUFFSTAT 0x3617
409#define HDMI_AHB_DMA_BUFFINT 0x3618
410#define HDMI_AHB_DMA_BUFFMASK 0x3619
411#define HDMI_AHB_DMA_BUFFPOL 0x361a
412
413/* Main Controller Registers */
414#define HDMI_MC_SFRDIV 0x4000
415#define HDMI_MC_CLKDIS 0x4001
416#define HDMI_MC_SWRSTZ 0x4002
417#define HDMI_MC_OPCTRL 0x4003
418#define HDMI_MC_FLOWCTRL 0x4004
419#define HDMI_MC_PHYRSTZ 0x4005
420#define HDMI_MC_LOCKONCLOCK 0x4006
421#define HDMI_MC_HEACPHY_RST 0x4007
422
423/* Color Space Converter Registers */
424#define HDMI_CSC_CFG 0x4100
425#define HDMI_CSC_SCALE 0x4101
426#define HDMI_CSC_COEF_A1_MSB 0x4102
427#define HDMI_CSC_COEF_A1_LSB 0x4103
428#define HDMI_CSC_COEF_A2_MSB 0x4104
429#define HDMI_CSC_COEF_A2_LSB 0x4105
430#define HDMI_CSC_COEF_A3_MSB 0x4106
431#define HDMI_CSC_COEF_A3_LSB 0x4107
432#define HDMI_CSC_COEF_A4_MSB 0x4108
433#define HDMI_CSC_COEF_A4_LSB 0x4109
434#define HDMI_CSC_COEF_B1_MSB 0x410A
435#define HDMI_CSC_COEF_B1_LSB 0x410B
436#define HDMI_CSC_COEF_B2_MSB 0x410C
437#define HDMI_CSC_COEF_B2_LSB 0x410D
438#define HDMI_CSC_COEF_B3_MSB 0x410E
439#define HDMI_CSC_COEF_B3_LSB 0x410F
440#define HDMI_CSC_COEF_B4_MSB 0x4110
441#define HDMI_CSC_COEF_B4_LSB 0x4111
442#define HDMI_CSC_COEF_C1_MSB 0x4112
443#define HDMI_CSC_COEF_C1_LSB 0x4113
444#define HDMI_CSC_COEF_C2_MSB 0x4114
445#define HDMI_CSC_COEF_C2_LSB 0x4115
446#define HDMI_CSC_COEF_C3_MSB 0x4116
447#define HDMI_CSC_COEF_C3_LSB 0x4117
448#define HDMI_CSC_COEF_C4_MSB 0x4118
449#define HDMI_CSC_COEF_C4_LSB 0x4119
450
451/* HDCP Encryption Engine Registers */
452#define HDMI_A_HDCPCFG0 0x5000
453#define HDMI_A_HDCPCFG1 0x5001
454#define HDMI_A_HDCPOBS0 0x5002
455#define HDMI_A_HDCPOBS1 0x5003
456#define HDMI_A_HDCPOBS2 0x5004
457#define HDMI_A_HDCPOBS3 0x5005
458#define HDMI_A_APIINTCLR 0x5006
459#define HDMI_A_APIINTSTAT 0x5007
460#define HDMI_A_APIINTMSK 0x5008
461#define HDMI_A_VIDPOLCFG 0x5009
462#define HDMI_A_OESSWCFG 0x500A
463#define HDMI_A_TIMER1SETUP0 0x500B
464#define HDMI_A_TIMER1SETUP1 0x500C
465#define HDMI_A_TIMER2SETUP0 0x500D
466#define HDMI_A_TIMER2SETUP1 0x500E
467#define HDMI_A_100MSCFG 0x500F
468#define HDMI_A_2SCFG0 0x5010
469#define HDMI_A_2SCFG1 0x5011
470#define HDMI_A_5SCFG0 0x5012
471#define HDMI_A_5SCFG1 0x5013
472#define HDMI_A_SRMVERLSB 0x5014
473#define HDMI_A_SRMVERMSB 0x5015
474#define HDMI_A_SRMCTRL 0x5016
475#define HDMI_A_SFRSETUP 0x5017
476#define HDMI_A_I2CHSETUP 0x5018
477#define HDMI_A_INTSETUP 0x5019
478#define HDMI_A_PRESETUP 0x501A
479#define HDMI_A_SRM_BASE 0x5020
480
481/* CEC Engine Registers */
482#define HDMI_CEC_CTRL 0x7D00
483#define HDMI_CEC_STAT 0x7D01
484#define HDMI_CEC_MASK 0x7D02
485#define HDMI_CEC_POLARITY 0x7D03
486#define HDMI_CEC_INT 0x7D04
487#define HDMI_CEC_ADDR_L 0x7D05
488#define HDMI_CEC_ADDR_H 0x7D06
489#define HDMI_CEC_TX_CNT 0x7D07
490#define HDMI_CEC_RX_CNT 0x7D08
491#define HDMI_CEC_TX_DATA0 0x7D10
492#define HDMI_CEC_TX_DATA1 0x7D11
493#define HDMI_CEC_TX_DATA2 0x7D12
494#define HDMI_CEC_TX_DATA3 0x7D13
495#define HDMI_CEC_TX_DATA4 0x7D14
496#define HDMI_CEC_TX_DATA5 0x7D15
497#define HDMI_CEC_TX_DATA6 0x7D16
498#define HDMI_CEC_TX_DATA7 0x7D17
499#define HDMI_CEC_TX_DATA8 0x7D18
500#define HDMI_CEC_TX_DATA9 0x7D19
501#define HDMI_CEC_TX_DATA10 0x7D1a
502#define HDMI_CEC_TX_DATA11 0x7D1b
503#define HDMI_CEC_TX_DATA12 0x7D1c
504#define HDMI_CEC_TX_DATA13 0x7D1d
505#define HDMI_CEC_TX_DATA14 0x7D1e
506#define HDMI_CEC_TX_DATA15 0x7D1f
507#define HDMI_CEC_RX_DATA0 0x7D20
508#define HDMI_CEC_RX_DATA1 0x7D21
509#define HDMI_CEC_RX_DATA2 0x7D22
510#define HDMI_CEC_RX_DATA3 0x7D23
511#define HDMI_CEC_RX_DATA4 0x7D24
512#define HDMI_CEC_RX_DATA5 0x7D25
513#define HDMI_CEC_RX_DATA6 0x7D26
514#define HDMI_CEC_RX_DATA7 0x7D27
515#define HDMI_CEC_RX_DATA8 0x7D28
516#define HDMI_CEC_RX_DATA9 0x7D29
517#define HDMI_CEC_RX_DATA10 0x7D2a
518#define HDMI_CEC_RX_DATA11 0x7D2b
519#define HDMI_CEC_RX_DATA12 0x7D2c
520#define HDMI_CEC_RX_DATA13 0x7D2d
521#define HDMI_CEC_RX_DATA14 0x7D2e
522#define HDMI_CEC_RX_DATA15 0x7D2f
523#define HDMI_CEC_LOCK 0x7D30
524#define HDMI_CEC_WKUPCTRL 0x7D31
525
526/* I2C Master Registers (E-DDC) */
527#define HDMI_I2CM_SLAVE 0x7E00
528#define HDMI_I2CMESS 0x7E01
529#define HDMI_I2CM_DATAO 0x7E02
530#define HDMI_I2CM_DATAI 0x7E03
531#define HDMI_I2CM_OPERATION 0x7E04
532#define HDMI_I2CM_INT 0x7E05
533#define HDMI_I2CM_CTLINT 0x7E06
534#define HDMI_I2CM_DIV 0x7E07
535#define HDMI_I2CM_SEGADDR 0x7E08
536#define HDMI_I2CM_SOFTRSTZ 0x7E09
537#define HDMI_I2CM_SEGPTR 0x7E0A
538#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B
539#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C
540#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D
541#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E
542#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F
543#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10
544#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11
545#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12
546
547enum {
548/* IH_FC_INT2 field values */
549 HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03,
550 HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
551 HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
552
553/* IH_FC_STAT2 field values */
554 HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03,
555 HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
556 HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
557
558/* IH_PHY_STAT0 field values */
559 HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20,
560 HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10,
561 HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8,
562 HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4,
563 HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2,
564 HDMI_IH_PHY_STAT0_HPD = 0x1,
565
566/* IH_MUTE_I2CMPHY_STAT0 field values */
567 HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2,
568 HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1,
569
570/* IH_AHBDMAAUD_STAT0 field values */
571 HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20,
572 HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10,
573 HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08,
574 HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04,
575 HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
576 HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
577
578/* IH_MUTE_FC_STAT2 field values */
579 HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03,
580 HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
581 HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
582
583/* IH_MUTE_AHBDMAAUD_STAT0 field values */
584 HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20,
585 HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10,
586 HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08,
587 HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04,
588 HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
589 HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
590
591/* IH_MUTE field values */
592 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
593 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
594
595/* TX_INVID0 field values */
596 HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80,
597 HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80,
598 HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
599 HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F,
600 HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
601
602/* TX_INSTUFFING field values */
603 HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4,
604 HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
605 HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0,
606 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2,
607 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
608 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0,
609 HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1,
610 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
611 HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0,
612
613/* VP_PR_CD field values */
614 HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0,
615 HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
616 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F,
617 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
618
619/* VP_STUFF field values */
620 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
621 HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
622 HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10,
623 HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4,
624 HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8,
625 HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3,
626 HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
627 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
628 HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0,
629 HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
630 HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
631 HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0,
632 HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
633 HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
634 HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0,
635
636/* VP_CONF field values */
637 HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
638 HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
639 HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00,
640 HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
641 HDMI_VP_CONF_PP_EN_ENABLE = 0x20,
642 HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
643 HDMI_VP_CONF_PR_EN_MASK = 0x10,
644 HDMI_VP_CONF_PR_EN_ENABLE = 0x10,
645 HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
646 HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
647 HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8,
648 HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
649 HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
650 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
651 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0,
652 HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
653 HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
654 HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1,
655 HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0,
656
657/* VP_REMAP field values */
658 HDMI_VP_REMAP_MASK = 0x3,
659 HDMI_VP_REMAP_YCC422_24bit = 0x2,
660 HDMI_VP_REMAP_YCC422_20bit = 0x1,
661 HDMI_VP_REMAP_YCC422_16bit = 0x0,
662
663/* FC_INVIDCONF field values */
664 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
665 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
666 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
667 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
668 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
669 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
670 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
671 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
672 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
673 HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
674 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
675 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
676 HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
677 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
678 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
679 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
680 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
681 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
682 HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
683 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
684 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
685
686/* FC_AUDICONF0 field values */
687 HDMI_FC_AUDICONF0_CC_OFFSET = 4,
688 HDMI_FC_AUDICONF0_CC_MASK = 0x70,
689 HDMI_FC_AUDICONF0_CT_OFFSET = 0,
690 HDMI_FC_AUDICONF0_CT_MASK = 0xF,
691
692/* FC_AUDICONF1 field values */
693 HDMI_FC_AUDICONF1_SS_OFFSET = 3,
694 HDMI_FC_AUDICONF1_SS_MASK = 0x18,
695 HDMI_FC_AUDICONF1_SF_OFFSET = 0,
696 HDMI_FC_AUDICONF1_SF_MASK = 0x7,
697
698/* FC_AUDICONF3 field values */
699 HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5,
700 HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60,
701 HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4,
702 HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10,
703 HDMI_FC_AUDICONF3_LSV_OFFSET = 0,
704 HDMI_FC_AUDICONF3_LSV_MASK = 0xF,
705
706/* FC_AUDSCHNLS0 field values */
707 HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4,
708 HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30,
709 HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0,
710 HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01,
711
712/* FC_AUDSCHNLS3-6 field values */
713 HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0,
714 HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f,
715 HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4,
716 HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0,
717 HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0,
718 HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f,
719 HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4,
720 HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0,
721
722 HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0,
723 HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f,
724 HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4,
725 HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0,
726 HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0,
727 HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f,
728 HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4,
729 HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0,
730
731/* HDMI_FC_AUDSCHNLS7 field values */
732 HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4,
733 HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
734
735/* HDMI_FC_AUDSCHNLS8 field values */
736 HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0,
737 HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4,
738 HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f,
739 HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0,
740
741/* FC_AUDSCONF field values */
742 HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0,
743 HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4,
744 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1,
745 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0,
746 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1,
747 HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0,
748
749/* FC_STAT2 field values */
750 HDMI_FC_STAT2_OVERFLOW_MASK = 0x03,
751 HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
752 HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
753
754/* FC_INT2 field values */
755 HDMI_FC_INT2_OVERFLOW_MASK = 0x03,
756 HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
757 HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
758
759/* FC_MASK2 field values */
760 HDMI_FC_MASK2_OVERFLOW_MASK = 0x03,
761 HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02,
762 HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01,
763
764/* FC_PRCONF field values */
765 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0,
766 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4,
767 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F,
768 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0,
769
770/* FC_AVICONF0-FC_AVICONF3 field values */
771 HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
772 HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
773 HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
774 HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
775 HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
776 HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
777 HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
778 HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C,
779 HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
780 HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
781 HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
782 HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C,
783 HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
784 HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
785 HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
786 HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
787
788 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F,
789 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
790 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
791 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A,
792 HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B,
793 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
794 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
795 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
796 HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
797 HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0,
798 HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
799 HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
800 HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
801 HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0,
802
803 HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
804 HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
805 HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
806 HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
807 HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03,
808 HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C,
809 HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
810 HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
811 HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
812 HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
813 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
814 HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
815 HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
816 HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
817 HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
818 HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
819 HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
820 HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
821
822 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
823 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
824 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
825 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
826 HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
827 HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C,
828 HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
829 HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
830
831/* FC_DBGFORCE field values */
832 HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
833 HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
834
835/* PHY_CONF0 field values */
836 HDMI_PHY_CONF0_PDZ_MASK = 0x80,
837 HDMI_PHY_CONF0_PDZ_OFFSET = 7,
838 HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
839 HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
840 HDMI_PHY_CONF0_SPARECTRL = 0x20,
841 HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
842 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
843 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
844 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
845 HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4,
846 HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2,
847 HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
848 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
849 HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
850 HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
851
852/* PHY_TST0 field values */
853 HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
854 HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
855 HDMI_PHY_TST0_TSTEN_MASK = 0x10,
856 HDMI_PHY_TST0_TSTEN_OFFSET = 4,
857 HDMI_PHY_TST0_TSTCLK_MASK = 0x1,
858 HDMI_PHY_TST0_TSTCLK_OFFSET = 0,
859
860/* PHY_STAT0 field values */
861 HDMI_PHY_RX_SENSE3 = 0x80,
862 HDMI_PHY_RX_SENSE2 = 0x40,
863 HDMI_PHY_RX_SENSE1 = 0x20,
864 HDMI_PHY_RX_SENSE0 = 0x10,
865 HDMI_PHY_HPD = 0x02,
866 HDMI_PHY_TX_PHY_LOCK = 0x01,
867
868/* PHY_I2CM_SLAVE_ADDR field values */
869 HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
870 HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49,
871
872/* PHY_I2CM_OPERATION_ADDR field values */
873 HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
874 HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1,
875
876/* HDMI_PHY_I2CM_INT_ADDR */
877 HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
878 HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04,
879
880/* HDMI_PHY_I2CM_CTLINT_ADDR */
881 HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
882 HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40,
883 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
884 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04,
885
886/* AUD_CTS3 field values */
887 HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
888 HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
889 HDMI_AUD_CTS3_N_SHIFT_1 = 0,
890 HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
891 HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
892 HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
893 HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
894 HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
895 /* note that the CTS3 MANUAL bit has been removed
896 from our part. Can't set it, will read as 0. */
897 HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
898 HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
899
900/* AHB_DMA_CONF0 field values */
901 HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7,
902 HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80,
903 HDMI_AHB_DMA_CONF0_HBR = 0x10,
904 HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3,
905 HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08,
906 HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1,
907 HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06,
908 HDMI_AHB_DMA_CONF0_INCR4 = 0x0,
909 HDMI_AHB_DMA_CONF0_INCR8 = 0x2,
910 HDMI_AHB_DMA_CONF0_INCR16 = 0x4,
911 HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1,
912
913/* HDMI_AHB_DMA_START field values */
914 HDMI_AHB_DMA_START_START_OFFSET = 0,
915 HDMI_AHB_DMA_START_START_MASK = 0x01,
916
917/* HDMI_AHB_DMA_STOP field values */
918 HDMI_AHB_DMA_STOP_STOP_OFFSET = 0,
919 HDMI_AHB_DMA_STOP_STOP_MASK = 0x01,
920
921/* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */
922 HDMI_AHB_DMA_DONE = 0x80,
923 HDMI_AHB_DMA_RETRY_SPLIT = 0x40,
924 HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20,
925 HDMI_AHB_DMA_ERROR = 0x10,
926 HDMI_AHB_DMA_FIFO_THREMPTY = 0x04,
927 HDMI_AHB_DMA_FIFO_FULL = 0x02,
928 HDMI_AHB_DMA_FIFO_EMPTY = 0x01,
929
930/* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT,AHB_DMA_BUFFMASK,AHB_DMA_BUFFPOL values */
931 HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02,
932 HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01,
933
934/* MC_CLKDIS field values */
935 HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40,
936 HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20,
937 HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10,
938 HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
939 HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4,
940 HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
941 HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
942
943/* MC_SWRSTZ field values */
944 HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
945
946/* MC_FLOWCTRL field values */
947 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1,
948 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
949 HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
950
951/* MC_PHYRSTZ field values */
952 HDMI_MC_PHYRSTZ_ASSERT = 0x0,
953 HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
954
955/* MC_HEACPHY_RST field values */
956 HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
957 HDMI_MC_HEACPHY_RST_DEASSERT = 0x0,
958
959/* CSC_CFG field values */
960 HDMI_CSC_CFG_INTMODE_MASK = 0x30,
961 HDMI_CSC_CFG_INTMODE_OFFSET = 4,
962 HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
963 HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10,
964 HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20,
965 HDMI_CSC_CFG_DECMODE_MASK = 0x3,
966 HDMI_CSC_CFG_DECMODE_OFFSET = 0,
967 HDMI_CSC_CFG_DECMODE_DISABLE = 0x0,
968 HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1,
969 HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2,
970 HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3,
971
972/* CSC_SCALE field values */
973 HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0,
974 HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
975 HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
976 HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
977 HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
978 HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
979
980/* A_HDCPCFG0 field values */
981 HDMI_A_HDCPCFG0_ELVENA_MASK = 0x80,
982 HDMI_A_HDCPCFG0_ELVENA_ENABLE = 0x80,
983 HDMI_A_HDCPCFG0_ELVENA_DISABLE = 0x00,
984 HDMI_A_HDCPCFG0_I2CFASTMODE_MASK = 0x40,
985 HDMI_A_HDCPCFG0_I2CFASTMODE_ENABLE = 0x40,
986 HDMI_A_HDCPCFG0_I2CFASTMODE_DISABLE = 0x00,
987 HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK = 0x20,
988 HDMI_A_HDCPCFG0_BYPENCRYPTION_ENABLE = 0x20,
989 HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE = 0x00,
990 HDMI_A_HDCPCFG0_SYNCRICHECK_MASK = 0x10,
991 HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE = 0x10,
992 HDMI_A_HDCPCFG0_SYNCRICHECK_DISABLE = 0x00,
993 HDMI_A_HDCPCFG0_AVMUTE_MASK = 0x8,
994 HDMI_A_HDCPCFG0_AVMUTE_ENABLE = 0x8,
995 HDMI_A_HDCPCFG0_AVMUTE_DISABLE = 0x0,
996 HDMI_A_HDCPCFG0_RXDETECT_MASK = 0x4,
997 HDMI_A_HDCPCFG0_RXDETECT_ENABLE = 0x4,
998 HDMI_A_HDCPCFG0_RXDETECT_DISABLE = 0x0,
999 HDMI_A_HDCPCFG0_EN11FEATURE_MASK = 0x2,
1000 HDMI_A_HDCPCFG0_EN11FEATURE_ENABLE = 0x2,
1001 HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE = 0x0,
1002 HDMI_A_HDCPCFG0_HDMIDVI_MASK = 0x1,
1003 HDMI_A_HDCPCFG0_HDMIDVI_HDMI = 0x1,
1004 HDMI_A_HDCPCFG0_HDMIDVI_DVI = 0x0,
1005
1006/* A_HDCPCFG1 field values */
1007 HDMI_A_HDCPCFG1_DISSHA1CHECK_MASK = 0x8,
1008 HDMI_A_HDCPCFG1_DISSHA1CHECK_DISABLE = 0x8,
1009 HDMI_A_HDCPCFG1_DISSHA1CHECK_ENABLE = 0x0,
1010 HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK = 0x4,
1011 HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE = 0x4,
1012 HDMI_A_HDCPCFG1_PH2UPSHFTENC_DISABLE = 0x0,
1013 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK = 0x2,
1014 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE = 0x2,
1015 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE = 0x0,
1016 HDMI_A_HDCPCFG1_SWRESET_MASK = 0x1,
1017 HDMI_A_HDCPCFG1_SWRESET_ASSERT = 0x0,
1018
1019/* A_VIDPOLCFG field values */
1020 HDMI_A_VIDPOLCFG_UNENCRYPTCONF_MASK = 0x60,
1021 HDMI_A_VIDPOLCFG_UNENCRYPTCONF_OFFSET = 5,
1022 HDMI_A_VIDPOLCFG_DATAENPOL_MASK = 0x10,
1023 HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH = 0x10,
1024 HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW = 0x0,
1025 HDMI_A_VIDPOLCFG_VSYNCPOL_MASK = 0x8,
1026 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH = 0x8,
1027 HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW = 0x0,
1028 HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2,
1029 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2,
1030 HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0,
1031};
1032
1033enum imx_hdmi_devtype {
1034 IMX6Q_HDMI,
1035 IMX6DL_HDMI,
1036};
1037
1038struct imx_hdmi_plat_data {
1039 enum imx_hdmi_devtype dev_type;
1040 const struct mpll_config *mpll_cfg;
1041 const struct curr_ctrl *cur_ctr;
1042 const struct sym_term *sym_term;
1043};
1044
1045enum {
1046 RES_8,
1047 RES_10,
1048 RES_12,
1049 RES_MAX,
1050};
1051
1052struct mpll_config {
1053 unsigned long mpixelclock;
1054 struct {
1055 u16 cpce;
1056 u16 gmp;
1057 } res[RES_MAX];
1058};
1059
1060struct curr_ctrl {
1061 unsigned long mpixelclock;
1062 u16 curr[RES_MAX];
1063};
1064
1065struct sym_term {
1066 unsigned long mpixelclock;
1067 u16 sym_ctr; /*clock symbol and transmitter control*/
1068 u16 term; /*transmission termination value*/
1069};
1070
1071int imx_hdmi_bind(struct device *dev, struct device *master,
1072 void *data, struct drm_encoder *encoder,
1073 struct resource *iores, int irq,
1074 const struct imx_hdmi_plat_data *plat_data);
1075void imx_hdmi_unbind(struct device *dev, struct device *master, void *data);
1076#endif /* __IMX_HDMI_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-15 07:57:21 -0400