drm/i915: Add second slice l3 remapping

Certain HSW SKUs have a second bank of L3. This L3 remapping has a
separate register set, and interrupt from the first "slice". A slice is
simply a term to define some subset of the GPU's l3 cache. This patch
implements both the interrupt handler, and ability to communicate with
userspace about this second slice.

v2:  Remove redundant check about non-existent slice.
Change warning about interrupts of unknown slices to WARN_ON_ONCE
Handle the case where we get 2 slice interrupts concurrently, and switch
the tracking of interrupts to be non-destructive (all Ville)
Don't enable/mask the second slice parity interrupt for ivb/vlv (even
though all docs I can find claim it's rsvd) (Ville + Bryan)
Keep BYT excluded from L3 parity

v3: Fix the slice = ffs to be decremented by one (found by Ville). When
I initially did my testing on the series, I was using 1-based slice
counting, so this code was correct. Not sure why my simpler tests that
I've been running since then didn't pick it up sooner.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 7 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index af6f93ca7296..c4f9bef6d073 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -927,6 +927,7 @@
 #define GT_BLT_USER_INTERRUPT                   (1 << 22)
 #define GT_BSD_CS_ERROR_INTERRUPT               (1 << 15)
 #define GT_BSD_USER_INTERRUPT                   (1 << 12)
+#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1  (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT     (1 <<  5) /* !snb */
 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT      (1 <<  4)
 #define GT_RENDER_CS_MASTER_ERROR_INTERRUPT     (1 <<  3)
@@ -937,6 +938,10 @@
 #define PM_VEBOX_CS_ERROR_INTERRUPT             (1 << 12) /* hsw+ */
 #define PM_VEBOX_USER_INTERRUPT                 (1 << 10) /* hsw+ */
 
+#define GT_PARITY_ERROR(dev) \
+        (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
+         IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)
+
 /* These are all the "old" interrupts */
 #define ILK_BSD_USER_INTERRUPT                          (1<<5)
 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT              (1<<18)
@@ -4747,6 +4752,7 @@
 
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1                 0xB008 /* L3CD Error Status 1 */
+#define HSW_L3CDERRST11                 0xB208 /* L3CD Error Status register 1 slice 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK      (0x7ff<<14)
 #define   GEN7_PARITY_ERROR_VALID       (1<<13)
 #define   GEN7_L3CDERRST1_BANK_MASK     (3<<11)
@@ -4760,6 +4766,7 @@
 #define   GEN7_L3CDERRST1_ENABLE        (1<<7)
 
 #define GEN7_L3LOG_BASE                 0xB070
+#define HSW_L3LOG_BASE_SLICE1           0xB270
 #define GEN7_L3LOG_SIZE                 0x80
 
 #define GEN7_HALF_SLICE_CHICKEN1        0xe100 /* IVB GT1 + VLV */