drm/i915: Add second slice l3 remapping

Certain HSW SKUs have a second bank of L3. This L3 remapping has a
separate register set, and interrupt from the first "slice". A slice is
simply a term to define some subset of the GPU's l3 cache. This patch
implements both the interrupt handler, and ability to communicate with
userspace about this second slice.

v2:  Remove redundant check about non-existent slice.
Change warning about interrupts of unknown slices to WARN_ON_ONCE
Handle the case where we get 2 slice interrupts concurrently, and switch
the tracking of interrupts to be non-destructive (all Ville)
Don't enable/mask the second slice parity interrupt for ivb/vlv (even
though all docs I can find claim it's rsvd) (Ville + Bryan)
Keep BYT excluded from L3 parity

v3: Fix the slice = ffs to be decremented by one (found by Ville). When
I initially did my testing on the series, I was using 1-based slice
counting, so this code was correct. Not sure why my simpler tests that
I've been running since then didn't pick it up sooner.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

7 files changed, 117 insertions, 61 deletions

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8b16d47280f9..c6e8df737566 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -917,9 +917,11 @@ struct i915_ums_state {
         int mm_suspended;
 };
 
+#define MAX_L3_SLICES 2
 struct intel_l3_parity {
-        u32 *remap_info;
+        u32 *remap_info[MAX_L3_SLICES];
         struct work_struct error_work;
+        int which_slice;
 };
 
 struct i915_gem_mm {
@@ -1686,6 +1688,7 @@ struct drm_i915_file_private {
 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
 
 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
+#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_GPU_CACHE(dev))
 
 #define GT_FREQUENCY_MULTIPLIER 50
 
@@ -1946,7 +1949,7 @@ bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
 int __must_check i915_gem_init(struct drm_device *dev);
 int __must_check i915_gem_init_hw(struct drm_device *dev);
-void i915_gem_l3_remap(struct drm_device *dev);
+void i915_gem_l3_remap(struct drm_device *dev, int slice);
 void i915_gem_init_swizzling(struct drm_device *dev);
 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
 int __must_check i915_gpu_idle(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d00d24f7a976..21a3d69679ee 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4222,16 +4222,15 @@ i915_gem_idle(struct drm_device *dev)
         return 0;
 }
 
-void i915_gem_l3_remap(struct drm_device *dev)
+void i915_gem_l3_remap(struct drm_device *dev, int slice)
 {
         drm_i915_private_t *dev_priv = dev->dev_private;
+        u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
+        u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
         u32 misccpctl;
         int i;
 
-        if (!HAS_L3_GPU_CACHE(dev))
-                return;
-
-        if (!dev_priv->l3_parity.remap_info)
+        if (!HAS_L3_GPU_CACHE(dev) || !remap_info)
                 return;
 
         misccpctl = I915_READ(GEN7_MISCCPCTL);
@@ -4239,17 +4238,17 @@ void i915_gem_l3_remap(struct drm_device *dev)
         POSTING_READ(GEN7_MISCCPCTL);
 
         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
-                u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
-                if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
+                u32 remap = I915_READ(reg_base + i);
+                if (remap && remap != remap_info[i/4])
                         DRM_DEBUG("0x%x was already programmed to %x\n",
-                                  GEN7_L3LOG_BASE + i, remap);
-                if (remap && !dev_priv->l3_parity.remap_info[i/4])
+                                  reg_base + i, remap);
+                if (remap && !remap_info[i/4])
                         DRM_DEBUG_DRIVER("Clearing remapped register\n");
-                I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
+                I915_WRITE(reg_base + i, remap_info[i/4]);
         }
 
         /* Make sure all the writes land before disabling dop clock gating */
-        POSTING_READ(GEN7_L3LOG_BASE);
+        POSTING_READ(reg_base);
 
         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 }
@@ -4343,7 +4342,7 @@ int
 i915_gem_init_hw(struct drm_device *dev)
 {
         drm_i915_private_t *dev_priv = dev->dev_private;
-        int ret;
+        int ret, i;
 
         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
                 return -EIO;
@@ -4362,7 +4361,8 @@ i915_gem_init_hw(struct drm_device *dev)
                 I915_WRITE(GEN7_MSG_CTL, temp);
         }
 
-        i915_gem_l3_remap(dev);
+        for (i = 0; i < NUM_L3_SLICES(dev); i++)
+                i915_gem_l3_remap(dev, i);
 
         i915_gem_init_swizzling(dev);
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a610f5abcc41..60a7bac4fc3b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -888,9 +888,10 @@ static void ivybridge_parity_work(struct work_struct *work)
         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
                                                     l3_parity.error_work);
         u32 error_status, row, bank, subbank;
-        char *parity_event[5];
+        char *parity_event[6];
         uint32_t misccpctl;
         unsigned long flags;
+        uint8_t slice = 0;
 
         /* We must turn off DOP level clock gating to access the L3 registers.
          * In order to prevent a get/put style interface, acquire struct mutex
@@ -898,45 +899,64 @@ static void ivybridge_parity_work(struct work_struct *work)
          */
         mutex_lock(&dev_priv->dev->struct_mutex);
 
+        /* If we've screwed up tracking, just let the interrupt fire again */
+        if (WARN_ON(!dev_priv->l3_parity.which_slice))
+                goto out;
+
         misccpctl = I915_READ(GEN7_MISCCPCTL);
         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
         POSTING_READ(GEN7_MISCCPCTL);
 
-        error_status = I915_READ(GEN7_L3CDERRST1);
-        row = GEN7_PARITY_ERROR_ROW(error_status);
-        bank = GEN7_PARITY_ERROR_BANK(error_status);
-        subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
+        while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
+                u32 reg;
 
-        I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
-                                    GEN7_L3CDERRST1_ENABLE);
-        POSTING_READ(GEN7_L3CDERRST1);
+                slice--;
+                if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
+                        break;
 
-        I915_WRITE(GEN7_MISCCPCTL, misccpctl);
+                dev_priv->l3_parity.which_slice &= ~(1<<slice);
 
-        spin_lock_irqsave(&dev_priv->irq_lock, flags);
-        ilk_enable_gt_irq(dev_priv, GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
+                reg = GEN7_L3CDERRST1 + (slice * 0x200);