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authorPaulo Zanoni <paulo.r.zanoni@intel.com>2014-03-07 18:08:15 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-03-19 11:39:46 -0400
commit5d584b2eca96543568a8db8eba008f2dab784367 (patch)
tree4d52d0fb4bd986112faeeda285d33362a3e2d5b8 /drivers/gpu/drm/i915/i915_irq.c
parent7c8615d8f9faf7a33ad528a012e097631599207f (diff)
drm/i915: move pc8.irqs_disabled to pm.irqs_disabled
When other platforms add runtime PM support they will also need to disable interrupts, so move the variable to the runtime PM struct. Also notice that the longer-term goal is to completely kill the regsave struct, and I even have patches for that. v2: - Rebase. v3: - Rebase. Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c58
1 files changed, 29 insertions, 29 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c8e262fc750a..1c00751eca69 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -86,9 +86,9 @@ ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
86{ 86{
87 assert_spin_locked(&dev_priv->irq_lock); 87 assert_spin_locked(&dev_priv->irq_lock);
88 88
89 if (dev_priv->pc8.irqs_disabled) { 89 if (dev_priv->pm.irqs_disabled) {
90 WARN(1, "IRQs disabled\n"); 90 WARN(1, "IRQs disabled\n");
91 dev_priv->pc8.regsave.deimr &= ~mask; 91 dev_priv->pm.regsave.deimr &= ~mask;
92 return; 92 return;
93 } 93 }
94 94
@@ -104,9 +104,9 @@ ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
104{ 104{
105 assert_spin_locked(&dev_priv->irq_lock); 105 assert_spin_locked(&dev_priv->irq_lock);
106 106
107 if (dev_priv->pc8.irqs_disabled) { 107 if (dev_priv->pm.irqs_disabled) {
108 WARN(1, "IRQs disabled\n"); 108 WARN(1, "IRQs disabled\n");
109 dev_priv->pc8.regsave.deimr |= mask; 109 dev_priv->pm.regsave.deimr |= mask;
110 return; 110 return;
111 } 111 }
112 112
@@ -129,10 +129,10 @@ static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
129{ 129{
130 assert_spin_locked(&dev_priv->irq_lock); 130 assert_spin_locked(&dev_priv->irq_lock);
131 131
132 if (dev_priv->pc8.irqs_disabled) { 132 if (dev_priv->pm.irqs_disabled) {
133 WARN(1, "IRQs disabled\n"); 133 WARN(1, "IRQs disabled\n");
134 dev_priv->pc8.regsave.gtimr &= ~interrupt_mask; 134 dev_priv->pm.regsave.gtimr &= ~interrupt_mask;
135 dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask & 135 dev_priv->pm.regsave.gtimr |= (~enabled_irq_mask &
136 interrupt_mask); 136 interrupt_mask);
137 return; 137 return;
138 } 138 }
@@ -167,10 +167,10 @@ static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
167 167
168 assert_spin_locked(&dev_priv->irq_lock); 168 assert_spin_locked(&dev_priv->irq_lock);
169 169
170 if (dev_priv->pc8.irqs_disabled) { 170 if (dev_priv->pm.irqs_disabled) {
171 WARN(1, "IRQs disabled\n"); 171 WARN(1, "IRQs disabled\n");
172 dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask; 172 dev_priv->pm.regsave.gen6_pmimr &= ~interrupt_mask;
173 dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask & 173 dev_priv->pm.regsave.gen6_pmimr |= (~enabled_irq_mask &
174 interrupt_mask); 174 interrupt_mask);
175 return; 175 return;
176 } 176 }
@@ -313,11 +313,11 @@ static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
313 313
314 assert_spin_locked(&dev_priv->irq_lock); 314 assert_spin_locked(&dev_priv->irq_lock);
315 315
316 if (dev_priv->pc8.irqs_disabled && 316 if (dev_priv->pm.irqs_disabled &&
317 (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) { 317 (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
318 WARN(1, "IRQs disabled\n"); 318 WARN(1, "IRQs disabled\n");
319 dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask; 319 dev_priv->pm.regsave.sdeimr &= ~interrupt_mask;
320 dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask & 320 dev_priv->pm.regsave.sdeimr |= (~enabled_irq_mask &
321 interrupt_mask); 321 interrupt_mask);
322 return; 322 return;
323 } 323 }
@@ -4118,32 +4118,32 @@ void intel_hpd_init(struct drm_device *dev)
4118 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 4118 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4119} 4119}
4120 4120
4121/* Disable interrupts so we can allow Package C8+. */ 4121/* Disable interrupts so we can allow runtime PM. */
4122void hsw_pc8_disable_interrupts(struct drm_device *dev) 4122void hsw_runtime_pm_disable_interrupts(struct drm_device *dev)
4123{ 4123{
4124 struct drm_i915_private *dev_priv = dev->dev_private; 4124 struct drm_i915_private *dev_priv = dev->dev_private;
4125 unsigned long irqflags; 4125 unsigned long irqflags;
4126 4126
4127 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 4127 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4128 4128
4129 dev_priv->pc8.regsave.deimr = I915_READ(DEIMR); 4129 dev_priv->pm.regsave.deimr = I915_READ(DEIMR);
4130 dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR); 4130 dev_priv->pm.regsave.sdeimr = I915_READ(SDEIMR);
4131 dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR); 4131 dev_priv->pm.regsave.gtimr = I915_READ(GTIMR);
4132 dev_priv->pc8.regsave.gtier = I915_READ(GTIER); 4132 dev_priv->pm.regsave.gtier = I915_READ(GTIER);
4133 dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR); 4133 dev_priv->pm.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
4134 4134
4135 ironlake_disable_display_irq(dev_priv, 0xffffffff); 4135 ironlake_disable_display_irq(dev_priv, 0xffffffff);
4136 ibx_disable_display_interrupt(dev_priv, 0xffffffff); 4136 ibx_disable_display_interrupt(dev_priv, 0xffffffff);
4137 ilk_disable_gt_irq(dev_priv, 0xffffffff); 4137 ilk_disable_gt_irq(dev_priv, 0xffffffff);
4138 snb_disable_pm_irq(dev_priv, 0xffffffff); 4138 snb_disable_pm_irq(dev_priv, 0xffffffff);
4139 4139
4140 dev_priv->pc8.irqs_disabled = true; 4140 dev_priv->pm.irqs_disabled = true;
4141 4141
4142 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 4142 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4143} 4143}
4144 4144
4145/* Restore interrupts so we can recover from Package C8+. */ 4145/* Restore interrupts so we can recover from runtime PM. */
4146void hsw_pc8_restore_interrupts(struct drm_device *dev) 4146void hsw_runtime_pm_restore_interrupts(struct drm_device *dev)
4147{ 4147{
4148 struct drm_i915_private *dev_priv = dev->dev_private; 4148 struct drm_i915_private *dev_priv = dev->dev_private;
4149 unsigned long irqflags; 4149 unsigned long irqflags;
@@ -4163,13 +4163,13 @@ void hsw_pc8_restore_interrupts(struct drm_device *dev)
4163 val = I915_READ(GEN6_PMIMR); 4163 val = I915_READ(GEN6_PMIMR);
4164 WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val); 4164 WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val);
4165 4165
4166 dev_priv->pc8.irqs_disabled = false; 4166 dev_priv->pm.irqs_disabled = false;
4167 4167
4168 ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr); 4168 ironlake_enable_display_irq(dev_priv, ~dev_priv->pm.regsave.deimr);
4169 ibx_enable_display_interrupt(dev_priv, ~dev_priv->pc8.regsave.sdeimr); 4169 ibx_enable_display_interrupt(dev_priv, ~dev_priv->pm.regsave.sdeimr);
4170 ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr); 4170 ilk_enable_gt_irq(dev_priv, ~dev_priv->pm.regsave.gtimr);
4171 snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr); 4171 snb_enable_pm_irq(dev_priv, ~dev_priv->pm.regsave.gen6_pmimr);
4172 I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier); 4172 I915_WRITE(GTIER, dev_priv->pm.regsave.gtier);
4173 4173
4174 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 4174 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4175} 4175}