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authorAlan Cox <alan@linux.intel.com>2012-03-08 11:00:31 -0500
committerDave Airlie <airlied@redhat.com>2012-03-10 08:05:28 -0500
commit648a8e342c5a754bdc62f003d3af90507c1abfde (patch)
tree95dd76398a23ac3d6a662c7f71445aa22a89302a /drivers/gpu/drm/gma500/psb_drv.h
parent933315acb6e223d4da36cb0b95d18dcfa6323658 (diff)
gma500: now move the Oaktrail save state into its own structure
Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/gma500/psb_drv.h')
-rw-r--r--drivers/gpu/drm/gma500/psb_drv.h226
1 files changed, 118 insertions, 108 deletions
diff --git a/drivers/gpu/drm/gma500/psb_drv.h b/drivers/gpu/drm/gma500/psb_drv.h
index a84a9ec38bee..dee07e0d7c39 100644
--- a/drivers/gpu/drm/gma500/psb_drv.h
+++ b/drivers/gpu/drm/gma500/psb_drv.h
@@ -276,6 +276,123 @@ struct intel_gmbus {
276 u32 reg0; 276 u32 reg0;
277}; 277};
278 278
279/*
280 * Register save state. This is used to hold the context when the
281 * device is powered off. In the case of Oaktrail this can (but does not
282 * yet) include screen blank. Operations occuring during the save
283 * update the register cache instead.
284 */
285struct psb_state {
286 uint32_t saveDSPACNTR;
287 uint32_t saveDSPBCNTR;
288 uint32_t savePIPEACONF;
289 uint32_t savePIPEBCONF;
290 uint32_t savePIPEASRC;
291 uint32_t savePIPEBSRC;
292 uint32_t saveFPA0;
293 uint32_t saveFPA1;
294 uint32_t saveDPLL_A;
295 uint32_t saveDPLL_A_MD;
296 uint32_t saveHTOTAL_A;
297 uint32_t saveHBLANK_A;
298 uint32_t saveHSYNC_A;
299 uint32_t saveVTOTAL_A;
300 uint32_t saveVBLANK_A;
301 uint32_t saveVSYNC_A;
302 uint32_t saveDSPASTRIDE;
303 uint32_t saveDSPASIZE;
304 uint32_t saveDSPAPOS;
305 uint32_t saveDSPABASE;
306 uint32_t saveDSPASURF;
307 uint32_t saveDSPASTATUS;
308 uint32_t saveFPB0;
309 uint32_t saveFPB1;
310 uint32_t saveDPLL_B;
311 uint32_t saveDPLL_B_MD;
312 uint32_t saveHTOTAL_B;
313 uint32_t saveHBLANK_B;
314 uint32_t saveHSYNC_B;
315 uint32_t saveVTOTAL_B;
316 uint32_t saveVBLANK_B;
317 uint32_t saveVSYNC_B;
318 uint32_t saveDSPBSTRIDE;
319 uint32_t saveDSPBSIZE;
320 uint32_t saveDSPBPOS;
321 uint32_t saveDSPBBASE;
322 uint32_t saveDSPBSURF;
323 uint32_t saveDSPBSTATUS;
324 uint32_t saveVCLK_DIVISOR_VGA0;
325 uint32_t saveVCLK_DIVISOR_VGA1;
326 uint32_t saveVCLK_POST_DIV;
327 uint32_t saveVGACNTRL;
328 uint32_t saveADPA;
329 uint32_t saveLVDS;
330 uint32_t saveDVOA;
331 uint32_t saveDVOB;
332 uint32_t saveDVOC;
333 uint32_t savePP_ON;
334 uint32_t savePP_OFF;
335 uint32_t savePP_CONTROL;
336 uint32_t savePP_CYCLE;
337 uint32_t savePFIT_CONTROL;
338 uint32_t savePaletteA[256];
339 uint32_t savePaletteB[256];
340 uint32_t saveBLC_PWM_CTL2;
341 uint32_t saveBLC_PWM_CTL;
342 uint32_t saveCLOCKGATING;
343 uint32_t saveDSPARB;
344 uint32_t saveDSPATILEOFF;
345 uint32_t saveDSPBTILEOFF;
346 uint32_t saveDSPAADDR;
347 uint32_t saveDSPBADDR;
348 uint32_t savePFIT_AUTO_RATIOS;
349 uint32_t savePFIT_PGM_RATIOS;
350 uint32_t savePP_ON_DELAYS;
351 uint32_t savePP_OFF_DELAYS;
352 uint32_t savePP_DIVISOR;
353 uint32_t saveBSM;
354 uint32_t saveVBT;
355 uint32_t saveBCLRPAT_A;
356 uint32_t saveBCLRPAT_B;
357 uint32_t saveDSPALINOFF;
358 uint32_t saveDSPBLINOFF;
359 uint32_t savePERF_MODE;
360 uint32_t saveDSPFW1;
361 uint32_t saveDSPFW2;
362 uint32_t saveDSPFW3;
363 uint32_t saveDSPFW4;
364 uint32_t saveDSPFW5;
365 uint32_t saveDSPFW6;
366 uint32_t saveCHICKENBIT;
367 uint32_t saveDSPACURSOR_CTRL;
368 uint32_t saveDSPBCURSOR_CTRL;
369 uint32_t saveDSPACURSOR_BASE;
370 uint32_t saveDSPBCURSOR_BASE;
371 uint32_t saveDSPACURSOR_POS;
372 uint32_t saveDSPBCURSOR_POS;
373 uint32_t save_palette_a[256];
374 uint32_t save_palette_b[256];
375 uint32_t saveOV_OVADD;
376 uint32_t saveOV_OGAMC0;
377 uint32_t saveOV_OGAMC1;
378 uint32_t saveOV_OGAMC2;
379 uint32_t saveOV_OGAMC3;
380 uint32_t saveOV_OGAMC4;
381 uint32_t saveOV_OGAMC5;
382 uint32_t saveOVC_OVADD;
383 uint32_t saveOVC_OGAMC0;
384 uint32_t saveOVC_OGAMC1;
385 uint32_t saveOVC_OGAMC2;
386 uint32_t saveOVC_OGAMC3;
387 uint32_t saveOVC_OGAMC4;
388 uint32_t saveOVC_OGAMC5;
389
390 /* DPST register save */
391 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
392 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
393 uint32_t savePWM_CONTROL_LOGIC;
394};
395
279struct psb_ops; 396struct psb_ops;
280 397
281#define PSB_NUM_PIPE 3 398#define PSB_NUM_PIPE 3
@@ -403,118 +520,11 @@ struct drm_psb_private {
403 /* 520 /*
404 * Register state 521 * Register state
405 */ 522 */
406 uint32_t saveDSPACNTR; 523 struct psb_state regs;
407 uint32_t saveDSPBCNTR;
408 uint32_t savePIPEACONF;
409 uint32_t savePIPEBCONF;
410 uint32_t savePIPEASRC;
411 uint32_t savePIPEBSRC;
412 uint32_t saveFPA0;
413 uint32_t saveFPA1;
414 uint32_t saveDPLL_A;
415 uint32_t saveDPLL_A_MD;
416 uint32_t saveHTOTAL_A;
417 uint32_t saveHBLANK_A;
418 uint32_t saveHSYNC_A;
419 uint32_t saveVTOTAL_A;
420 uint32_t saveVBLANK_A;
421 uint32_t saveVSYNC_A;
422 uint32_t saveDSPASTRIDE;
423 uint32_t saveDSPASIZE;
424 uint32_t saveDSPAPOS;
425 uint32_t saveDSPABASE;
426 uint32_t saveDSPASURF;
427 uint32_t saveDSPASTATUS;
428 uint32_t saveFPB0;
429 uint32_t saveFPB1;
430 uint32_t saveDPLL_B;
431 uint32_t saveDPLL_B_MD;
432 uint32_t saveHTOTAL_B;
433 uint32_t saveHBLANK_B;
434 uint32_t saveHSYNC_B;
435 uint32_t saveVTOTAL_B;
436 uint32_t saveVBLANK_B;
437 uint32_t saveVSYNC_B;
438 uint32_t saveDSPBSTRIDE;
439 uint32_t saveDSPBSIZE;
440 uint32_t saveDSPBPOS;
441 uint32_t saveDSPBBASE;
442 uint32_t saveDSPBSURF;
443 uint32_t saveDSPBSTATUS;
444 uint32_t saveVCLK_DIVISOR_VGA0;
445 uint32_t saveVCLK_DIVISOR_VGA1;
446 uint32_t saveVCLK_POST_DIV;
447 uint32_t saveVGACNTRL;
448 uint32_t saveADPA;
449 uint32_t saveLVDS;
450 uint32_t saveDVOA;
451 uint32_t saveDVOB;
452 uint32_t saveDVOC;
453 uint32_t savePP_ON;
454 uint32_t savePP_OFF;
455 uint32_t savePP_CONTROL;
456 uint32_t savePP_CYCLE;
457 uint32_t savePFIT_CONTROL;
458 uint32_t savePaletteA[256];
459 uint32_t savePaletteB[256];
460 uint32_t saveBLC_PWM_CTL2;
461 uint32_t saveBLC_PWM_CTL;
462 uint32_t saveCLOCKGATING;
463 uint32_t saveDSPARB;
464 uint32_t saveDSPATILEOFF;
465 uint32_t saveDSPBTILEOFF;
466 uint32_t saveDSPAADDR;
467 uint32_t saveDSPBADDR;
468 uint32_t savePFIT_AUTO_RATIOS;
469 uint32_t savePFIT_PGM_RATIOS;
470 uint32_t savePP_ON_DELAYS;
471 uint32_t savePP_OFF_DELAYS;
472 uint32_t savePP_DIVISOR;
473 uint32_t saveBSM;
474 uint32_t saveVBT;
475 uint32_t saveBCLRPAT_A;
476 uint32_t saveBCLRPAT_B;
477 uint32_t saveDSPALINOFF;
478 uint32_t saveDSPBLINOFF;
479 uint32_t savePERF_MODE;
480 uint32_t saveDSPFW1;
481 uint32_t saveDSPFW2;
482 uint32_t saveDSPFW3;
483 uint32_t saveDSPFW4;
484 uint32_t saveDSPFW5;
485 uint32_t saveDSPFW6;
486 uint32_t saveCHICKENBIT;
487 uint32_t saveDSPACURSOR_CTRL;
488 uint32_t saveDSPBCURSOR_CTRL;
489 uint32_t saveDSPACURSOR_BASE;
490 uint32_t saveDSPBCURSOR_BASE;
491 uint32_t saveDSPACURSOR_POS;
492 uint32_t saveDSPBCURSOR_POS;
493 uint32_t save_palette_a[256];
494 uint32_t save_palette_b[256];
495 uint32_t saveOV_OVADD;
496 uint32_t saveOV_OGAMC0;
497 uint32_t saveOV_OGAMC1;
498 uint32_t saveOV_OGAMC2;
499 uint32_t saveOV_OGAMC3;
500 uint32_t saveOV_OGAMC4;
501 uint32_t saveOV_OGAMC5;
502 uint32_t saveOVC_OVADD;
503 uint32_t saveOVC_OGAMC0;
504 uint32_t saveOVC_OGAMC1;
505 uint32_t saveOVC_OGAMC2;
506 uint32_t saveOVC_OGAMC3;
507 uint32_t saveOVC_OGAMC4;
508 uint32_t saveOVC_OGAMC5;
509
510 /* MSI reg save */ 524 /* MSI reg save */
511 uint32_t msi_addr; 525 uint32_t msi_addr;
512 uint32_t msi_data; 526 uint32_t msi_data;
513 527
514 /* DPST register save */
515 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
516 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
517 uint32_t savePWM_CONTROL_LOGIC;
518 528
519 /* 529 /*
520 * LID-Switch 530 * LID-Switch
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