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authorAlan Cox <alan@linux.intel.com>2012-05-11 06:30:16 -0400
committerDave Airlie <airlied@redhat.com>2012-05-11 12:35:47 -0400
commit6256304ba35e7b7af3298c233f79b9b4168794dd (patch)
treefd61bd53b93cec81b66d40b634ef50bf64d3291a /drivers/gpu/drm/gma500/psb_drv.h
parenta373bedd7e70c1932f3f37d6858f437b69ef01c6 (diff)
gma500: introduce a structure describing each pipe
This starts the move away from lots of confused unions of per driver stuff inherited when we merged the drivers together. Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/gma500/psb_drv.h')
-rw-r--r--drivers/gpu/drm/gma500/psb_drv.h136
1 files changed, 31 insertions, 105 deletions
diff --git a/drivers/gpu/drm/gma500/psb_drv.h b/drivers/gpu/drm/gma500/psb_drv.h
index 309a6427584a..e25f9a124796 100644
--- a/drivers/gpu/drm/gma500/psb_drv.h
+++ b/drivers/gpu/drm/gma500/psb_drv.h
@@ -286,45 +286,37 @@ struct intel_gmbus {
286 * yet) include screen blank. Operations occuring during the save 286 * yet) include screen blank. Operations occuring during the save
287 * update the register cache instead. 287 * update the register cache instead.
288 */ 288 */
289
290/*
291 * Common status for pipes.
292 */
293struct psb_pipe {
294 u32 fp0;
295 u32 fp1;
296 u32 cntr;
297 u32 conf;
298 u32 src;
299 u32 dpll;
300 u32 dpll_md;
301 u32 htotal;
302 u32 hblank;
303 u32 hsync;
304 u32 vtotal;
305 u32 vblank;
306 u32 vsync;
307 u32 stride;
308 u32 size;
309 u32 pos;
310 u32 base;
311 u32 surf;
312 u32 addr;
313 u32 status;
314 u32 linoff;
315 u32 tileoff;
316 u32 palette[256];
317};
318
289struct psb_state { 319struct psb_state {
290 uint32_t saveDSPACNTR;
291 uint32_t saveDSPBCNTR;
292 uint32_t savePIPEACONF;
293 uint32_t savePIPEBCONF;
294 uint32_t savePIPEASRC;
295 uint32_t savePIPEBSRC;
296 uint32_t saveFPA0;
297 uint32_t saveFPA1;
298 uint32_t saveDPLL_A;
299 uint32_t saveDPLL_A_MD;
300 uint32_t saveHTOTAL_A;
301 uint32_t saveHBLANK_A;
302 uint32_t saveHSYNC_A;
303 uint32_t saveVTOTAL_A;
304 uint32_t saveVBLANK_A;
305 uint32_t saveVSYNC_A;
306 uint32_t saveDSPASTRIDE;
307 uint32_t saveDSPASIZE;
308 uint32_t saveDSPAPOS;
309 uint32_t saveDSPABASE;
310 uint32_t saveDSPASURF;
311 uint32_t saveDSPASTATUS;
312 uint32_t saveFPB0;
313 uint32_t saveFPB1;
314 uint32_t saveDPLL_B;
315 uint32_t saveDPLL_B_MD;
316 uint32_t saveHTOTAL_B;
317 uint32_t saveHBLANK_B;
318 uint32_t saveHSYNC_B;
319 uint32_t saveVTOTAL_B;
320 uint32_t saveVBLANK_B;
321 uint32_t saveVSYNC_B;
322 uint32_t saveDSPBSTRIDE;
323 uint32_t saveDSPBSIZE;
324 uint32_t saveDSPBPOS;
325 uint32_t saveDSPBBASE;
326 uint32_t saveDSPBSURF;
327 uint32_t saveDSPBSTATUS;
328 uint32_t saveVCLK_DIVISOR_VGA0; 320 uint32_t saveVCLK_DIVISOR_VGA0;
329 uint32_t saveVCLK_DIVISOR_VGA1; 321 uint32_t saveVCLK_DIVISOR_VGA1;
330 uint32_t saveVCLK_POST_DIV; 322 uint32_t saveVCLK_POST_DIV;
@@ -339,14 +331,8 @@ struct psb_state {
339 uint32_t savePP_CONTROL; 331 uint32_t savePP_CONTROL;
340 uint32_t savePP_CYCLE; 332 uint32_t savePP_CYCLE;
341 uint32_t savePFIT_CONTROL; 333 uint32_t savePFIT_CONTROL;
342 uint32_t savePaletteA[256];
343 uint32_t savePaletteB[256];
344 uint32_t saveCLOCKGATING; 334 uint32_t saveCLOCKGATING;
345 uint32_t saveDSPARB; 335 uint32_t saveDSPARB;
346 uint32_t saveDSPATILEOFF;
347 uint32_t saveDSPBTILEOFF;
348 uint32_t saveDSPAADDR;
349 uint32_t saveDSPBADDR;
350 uint32_t savePFIT_AUTO_RATIOS; 336 uint32_t savePFIT_AUTO_RATIOS;
351 uint32_t savePFIT_PGM_RATIOS; 337 uint32_t savePFIT_PGM_RATIOS;
352 uint32_t savePP_ON_DELAYS; 338 uint32_t savePP_ON_DELAYS;
@@ -354,8 +340,6 @@ struct psb_state {
354 uint32_t savePP_DIVISOR; 340 uint32_t savePP_DIVISOR;
355 uint32_t saveBCLRPAT_A; 341 uint32_t saveBCLRPAT_A;
356 uint32_t saveBCLRPAT_B; 342 uint32_t saveBCLRPAT_B;
357 uint32_t saveDSPALINOFF;
358 uint32_t saveDSPBLINOFF;
359 uint32_t savePERF_MODE; 343 uint32_t savePERF_MODE;
360 uint32_t saveDSPFW1; 344 uint32_t saveDSPFW1;
361 uint32_t saveDSPFW2; 345 uint32_t saveDSPFW2;
@@ -370,8 +354,6 @@ struct psb_state {
370 uint32_t saveDSPBCURSOR_BASE; 354 uint32_t saveDSPBCURSOR_BASE;
371 uint32_t saveDSPACURSOR_POS; 355 uint32_t saveDSPACURSOR_POS;
372 uint32_t saveDSPBCURSOR_POS; 356 uint32_t saveDSPBCURSOR_POS;
373 uint32_t save_palette_a[256];
374 uint32_t save_palette_b[256];
375 uint32_t saveOV_OVADD; 357 uint32_t saveOV_OVADD;
376 uint32_t saveOV_OGAMC0; 358 uint32_t saveOV_OGAMC0;
377 uint32_t saveOV_OGAMC1; 359 uint32_t saveOV_OGAMC1;
@@ -394,64 +376,7 @@ struct psb_state {
394}; 376};
395 377
396struct medfield_state { 378struct medfield_state {
397 uint32_t saveDPLL_A;
398 uint32_t saveFPA0;
399 uint32_t savePIPEACONF;
400 uint32_t saveHTOTAL_A;
401 uint32_t saveHBLANK_A;
402 uint32_t saveHSYNC_A;
403 uint32_t saveVTOTAL_A;
404 uint32_t saveVBLANK_A;
405 uint32_t saveVSYNC_A;
406 uint32_t savePIPEASRC;
407 uint32_t saveDSPASTRIDE;
408 uint32_t saveDSPALINOFF;
409 uint32_t saveDSPATILEOFF;
410 uint32_t saveDSPASIZE;
411 uint32_t saveDSPAPOS;
412 uint32_t saveDSPASURF;
413 uint32_t saveDSPACNTR;
414 uint32_t saveDSPASTATUS;
415 uint32_t save_palette_a[256];
416 uint32_t saveMIPI; 379 uint32_t saveMIPI;
417
418 uint32_t saveDPLL_B;
419 uint32_t saveFPB0;
420 uint32_t savePIPEBCONF;
421 uint32_t saveHTOTAL_B;
422 uint32_t saveHBLANK_B;
423 uint32_t saveHSYNC_B;
424 uint32_t saveVTOTAL_B;
425 uint32_t saveVBLANK_B;
426 uint32_t saveVSYNC_B;
427 uint32_t savePIPEBSRC;
428 uint32_t saveDSPBSTRIDE;
429 uint32_t saveDSPBLINOFF;
430 uint32_t saveDSPBTILEOFF;
431 uint32_t saveDSPBSIZE;
432 uint32_t saveDSPBPOS;
433 uint32_t saveDSPBSURF;
434 uint32_t saveDSPBCNTR;
435 uint32_t saveDSPBSTATUS;
436 uint32_t save_palette_b[256];
437
438 uint32_t savePIPECCONF;
439 uint32_t saveHTOTAL_C;
440 uint32_t saveHBLANK_C;
441 uint32_t saveHSYNC_C;
442 uint32_t saveVTOTAL_C;
443 uint32_t saveVBLANK_C;
444 uint32_t saveVSYNC_C;
445 uint32_t savePIPECSRC;
446 uint32_t saveDSPCSTRIDE;
447 uint32_t saveDSPCLINOFF;
448 uint32_t saveDSPCTILEOFF;
449 uint32_t saveDSPCSIZE;
450 uint32_t saveDSPCPOS;
451 uint32_t saveDSPCSURF;
452 uint32_t saveDSPCCNTR;
453 uint32_t saveDSPCSTATUS;
454 uint32_t save_palette_c[256];
455 uint32_t saveMIPI_C; 380 uint32_t saveMIPI_C;
456 381
457 uint32_t savePFIT_CONTROL; 382 uint32_t savePFIT_CONTROL;
@@ -480,6 +405,7 @@ struct cdv_state {
480}; 405};
481 406
482struct psb_save_area { 407struct psb_save_area {
408 struct psb_pipe pipe[3];
483 uint32_t saveBSM; 409 uint32_t saveBSM;
484 uint32_t saveVBT; 410 uint32_t saveVBT;
485 union { 411 union {