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authorAlan Cox <alan@linux.intel.com>2012-05-11 06:30:16 -0400
committerDave Airlie <airlied@redhat.com>2012-05-11 12:35:47 -0400
commit6256304ba35e7b7af3298c233f79b9b4168794dd (patch)
treefd61bd53b93cec81b66d40b634ef50bf64d3291a
parenta373bedd7e70c1932f3f37d6858f437b69ef01c6 (diff)
gma500: introduce a structure describing each pipe
This starts the move away from lots of confused unions of per driver stuff inherited when we merged the drivers together. Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/gma500/cdv_intel_display.c33
-rw-r--r--drivers/gpu/drm/gma500/mdfld_device.c177
-rw-r--r--drivers/gpu/drm/gma500/oaktrail_device.c72
-rw-r--r--drivers/gpu/drm/gma500/oaktrail_hdmi.c60
-rw-r--r--drivers/gpu/drm/gma500/psb_drv.h136
-rw-r--r--drivers/gpu/drm/gma500/psb_intel_display.c35
6 files changed, 173 insertions, 340 deletions
diff --git a/drivers/gpu/drm/gma500/cdv_intel_display.c b/drivers/gpu/drm/gma500/cdv_intel_display.c
index 2fab77854971..123ed5aa80c1 100644
--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
+++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
@@ -758,7 +758,7 @@ static void cdv_intel_crtc_load_lut(struct drm_crtc *crtc)
758 gma_power_end(dev); 758 gma_power_end(dev);
759 } else { 759 } else {
760 for (i = 0; i < 256; i++) { 760 for (i = 0; i < 256; i++) {
761 dev_priv->regs.psb.save_palette_a[i] = 761 dev_priv->regs.pipe[0].palette[i] =
762 ((psb_intel_crtc->lut_r[i] + 762 ((psb_intel_crtc->lut_r[i] +
763 psb_intel_crtc->lut_adj[i]) << 16) | 763 psb_intel_crtc->lut_adj[i]) << 16) |
764 ((psb_intel_crtc->lut_g[i] + 764 ((psb_intel_crtc->lut_g[i] +
@@ -1497,6 +1497,7 @@ static int cdv_intel_crtc_clock_get(struct drm_device *dev,
1497 struct cdv_intel_clock_t clock; 1497 struct cdv_intel_clock_t clock;
1498 bool is_lvds; 1498 bool is_lvds;
1499 struct drm_psb_private *dev_priv = dev->dev_private; 1499 struct drm_psb_private *dev_priv = dev->dev_private;
1500 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
1500 1501
1501 if (gma_power_begin(dev, false)) { 1502 if (gma_power_begin(dev, false)) {
1502 dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B); 1503 dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B);
@@ -1507,18 +1508,11 @@ static int cdv_intel_crtc_clock_get(struct drm_device *dev,
1507 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); 1508 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
1508 gma_power_end(dev); 1509 gma_power_end(dev);
1509 } else { 1510 } else {
1510 dpll = (pipe == 0) ? 1511 dpll = p->dpll;
1511 dev_priv->regs.psb.saveDPLL_A :
1512 dev_priv->regs.psb.saveDPLL_B;
1513
1514 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 1512 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1515 fp = (pipe == 0) ? 1513 fp = p->fp0;
1516 dev_priv->regs.psb.saveFPA0 :
1517 dev_priv->regs.psb.saveFPB0;
1518 else 1514 else
1519 fp = (pipe == 0) ? 1515 fp = p->fp1;
1520 dev_priv->regs.psb.saveFPA1 :
1521 dev_priv->regs.psb.saveFPB1;
1522 1516
1523 is_lvds = (pipe == 1) && 1517 is_lvds = (pipe == 1) &&
1524 (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN); 1518 (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN);
@@ -1582,6 +1576,7 @@ struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
1582 int vtot; 1576 int vtot;
1583 int vsync; 1577 int vsync;
1584 struct drm_psb_private *dev_priv = dev->dev_private; 1578 struct drm_psb_private *dev_priv = dev->dev_private;
1579 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
1585 1580
1586 if (gma_power_begin(dev, false)) { 1581 if (gma_power_begin(dev, false)) {
1587 htot = REG_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); 1582 htot = REG_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
@@ -1590,18 +1585,10 @@ struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
1590 vsync = REG_READ((pipe == 0) ? VSYNC_A : VSYNC_B); 1585 vsync = REG_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
1591 gma_power_end(dev); 1586 gma_power_end(dev);
1592 } else { 1587 } else {
1593 htot = (pipe == 0) ? 1588 htot = p->htotal;
1594 dev_priv->regs.psb.saveHTOTAL_A : 1589 hsync = p->hsync;
1595 dev_priv->regs.psb.saveHTOTAL_B; 1590 vtot = p->vtotal;
1596 hsync = (pipe == 0) ? 1591 vsync = p->vsync;
1597 dev_priv->regs.psb.saveHSYNC_A :
1598 dev_priv->regs.psb.saveHSYNC_B;
1599 vtot = (pipe == 0) ?
1600 dev_priv->regs.psb.saveVTOTAL_A :
1601 dev_priv->regs.psb.saveVTOTAL_B;
1602 vsync = (pipe == 0) ?
1603 dev_priv->regs.psb.saveVSYNC_A :
1604 dev_priv->regs.psb.saveVSYNC_B;
1605 } 1592 }
1606 1593
1607 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 1594 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
diff --git a/drivers/gpu/drm/gma500/mdfld_device.c b/drivers/gpu/drm/gma500/mdfld_device.c
index 717f4db28c3c..72686171b2f1 100644
--- a/drivers/gpu/drm/gma500/mdfld_device.c
+++ b/drivers/gpu/drm/gma500/mdfld_device.c
@@ -163,10 +163,11 @@ struct backlight_device *mdfld_get_backlight_device(void)
163 * 163 *
164 * Notes: FIXME_JLIU7 need to add the support for DPI MIPI & HDMI audio 164 * Notes: FIXME_JLIU7 need to add the support for DPI MIPI & HDMI audio
165 */ 165 */
166static int mdfld_save_display_registers(struct drm_device *dev, int pipe) 166static int mdfld_save_display_registers(struct drm_device *dev, int pipenum)
167{ 167{
168 struct drm_psb_private *dev_priv = dev->dev_private; 168 struct drm_psb_private *dev_priv = dev->dev_private;
169 struct medfield_state *regs = &dev_priv->regs.mdfld; 169 struct medfield_state *regs = &dev_priv->regs.mdfld;
170 struct psb_pipe *pipe = &dev_priv->regs.pipe[pipenum];
170 int i; 171 int i;
171 172
172 /* register */ 173 /* register */
@@ -192,28 +193,28 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe)
192 u32 palette_reg = PALETTE_A; 193 u32 palette_reg = PALETTE_A;
193 194
194 /* pointer to values */ 195 /* pointer to values */
195 u32 *dpll_val = &regs->saveDPLL_A; 196 u32 *dpll_val = &pipe->dpll;
196 u32 *fp_val = &regs->saveFPA0; 197 u32 *fp_val = &pipe->fp0;
197 u32 *pipeconf_val = &regs->savePIPEACONF; 198 u32 *pipeconf_val = &pipe->conf;
198 u32 *htot_val = &regs->saveHTOTAL_A; 199 u32 *htot_val = &pipe->htotal;
199 u32 *hblank_val = &regs->saveHBLANK_A; 200 u32 *hblank_val = &pipe->hblank;
200 u32 *hsync_val = &regs->saveHSYNC_A; 201 u32 *hsync_val = &pipe->hsync;
201 u32 *vtot_val = &regs->saveVTOTAL_A; 202 u32 *vtot_val = &pipe->vtotal;
202 u32 *vblank_val = &regs->saveVBLANK_A; 203 u32 *vblank_val = &pipe->vblank;
203 u32 *vsync_val = &regs->saveVSYNC_A; 204 u32 *vsync_val = &pipe->vsync;
204 u32 *pipesrc_val = &regs->savePIPEASRC; 205 u32 *pipesrc_val = &pipe->src;
205 u32 *dspstride_val = &regs->saveDSPASTRIDE; 206 u32 *dspstride_val = &pipe->stride;
206 u32 *dsplinoff_val = &regs->saveDSPALINOFF; 207 u32 *dsplinoff_val = &pipe->linoff;
207 u32 *dsptileoff_val = &regs->saveDSPATILEOFF; 208 u32 *dsptileoff_val = &pipe->tileoff;
208 u32 *dspsize_val = &regs->saveDSPASIZE; 209 u32 *dspsize_val = &pipe->size;
209 u32 *dsppos_val = &regs->saveDSPAPOS; 210 u32 *dsppos_val = &pipe->pos;
210 u32 *dspsurf_val = &regs->saveDSPASURF; 211 u32 *dspsurf_val = &pipe->surf;
211 u32 *mipi_val = &regs->saveMIPI; 212 u32 *mipi_val = &regs->saveMIPI;
212 u32 *dspcntr_val = &regs->saveDSPACNTR; 213 u32 *dspcntr_val = &pipe->cntr;
213 u32 *dspstatus_val = &regs->saveDSPASTATUS; 214 u32 *dspstatus_val = &pipe->status;
214 u32 *palette_val = regs->save_palette_a; 215 u32 *palette_val = pipe->palette;
215 216
216 switch (pipe) { 217 switch (pipenum) {
217 case 0: 218 case 0:
218 break; 219 break;
219 case 1: 220 case 1:
@@ -237,27 +238,6 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe)
237 dspcntr_reg = DSPBCNTR; 238 dspcntr_reg = DSPBCNTR;
238 dspstatus_reg = PIPEBSTAT; 239 dspstatus_reg = PIPEBSTAT;
239 palette_reg = PALETTE_B; 240 palette_reg = PALETTE_B;
240
241 /* values */
242 dpll_val = &regs->saveDPLL_B;
243 fp_val = &regs->saveFPB0;
244 pipeconf_val = &regs->savePIPEBCONF;
245 htot_val = &regs->saveHTOTAL_B;
246 hblank_val = &regs->saveHBLANK_B;
247 hsync_val = &regs->saveHSYNC_B;
248 vtot_val = &regs->saveVTOTAL_B;
249 vblank_val = &regs->saveVBLANK_B;
250 vsync_val = &regs->saveVSYNC_B;
251 pipesrc_val = &regs->savePIPEBSRC;
252 dspstride_val = &regs->saveDSPBSTRIDE;
253 dsplinoff_val = &regs->saveDSPBLINOFF;
254 dsptileoff_val = &regs->saveDSPBTILEOFF;
255 dspsize_val = &regs->saveDSPBSIZE;
256 dsppos_val = &regs->saveDSPBPOS;
257 dspsurf_val = &regs->saveDSPBSURF;
258 dspcntr_val = &regs->saveDSPBCNTR;
259 dspstatus_val = &regs->saveDSPBSTATUS;
260 palette_val = regs->save_palette_b;
261 break; 241 break;
262 case 2: 242 case 2:
263 /* register */ 243 /* register */
@@ -281,24 +261,7 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe)
281 palette_reg = PALETTE_C; 261 palette_reg = PALETTE_C;
282 262
283 /* pointer to values */ 263 /* pointer to values */
284 pipeconf_val = &regs->savePIPECCONF;
285 htot_val = &regs->saveHTOTAL_C;
286 hblank_val = &regs->saveHBLANK_C;
287 hsync_val = &regs->saveHSYNC_C;
288 vtot_val = &regs->saveVTOTAL_C;
289 vblank_val = &regs->saveVBLANK_C;
290 vsync_val = &regs->saveVSYNC_C;
291 pipesrc_val = &regs->savePIPECSRC;
292 dspstride_val = &regs->saveDSPCSTRIDE;
293 dsplinoff_val = &regs->saveDSPCLINOFF;
294 dsptileoff_val = &regs->saveDSPCTILEOFF;
295 dspsize_val = &regs->saveDSPCSIZE;
296 dsppos_val = &regs->saveDSPCPOS;
297 dspsurf_val = &regs->saveDSPCSURF;
298 mipi_val = &regs->saveMIPI_C; 264 mipi_val = &regs->saveMIPI_C;
299 dspcntr_val = &regs->saveDSPCCNTR;
300 dspstatus_val = &regs->saveDSPCSTATUS;
301 palette_val = regs->save_palette_c;
302 break; 265 break;
303 default: 266 default:
304 DRM_ERROR("%s, invalid pipe number.\n", __func__); 267 DRM_ERROR("%s, invalid pipe number.\n", __func__);
@@ -329,7 +292,7 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe)
329 for (i = 0; i < 256; i++) 292 for (i = 0; i < 256; i++)
330 palette_val[i] = PSB_RVDC32(palette_reg + (i << 2)); 293 palette_val[i] = PSB_RVDC32(palette_reg + (i << 2));
331 294
332 if (pipe == 1) { 295 if (pipenum == 1) {
333 regs->savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL); 296 regs->savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
334 regs->savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS); 297 regs->savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS);
335 298
@@ -349,7 +312,7 @@ static int mdfld_save_display_registers(struct drm_device *dev, int pipe)
349 * 312 *
350 * Notes: FIXME_JLIU7 need to add the support for DPI MIPI & HDMI audio 313 * Notes: FIXME_JLIU7 need to add the support for DPI MIPI & HDMI audio
351 */ 314 */
352static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) 315static int mdfld_restore_display_registers(struct drm_device *dev, int pipenum)
353{ 316{
354 /* To get panel out of ULPS mode. */ 317 /* To get panel out of ULPS mode. */
355 u32 temp = 0; 318 u32 temp = 0;
@@ -357,11 +320,12 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
357 struct drm_psb_private *dev_priv = dev->dev_private; 320 struct drm_psb_private *dev_priv = dev->dev_private;
358 struct mdfld_dsi_config *dsi_config = NULL; 321 struct mdfld_dsi_config *dsi_config = NULL;
359 struct medfield_state *regs = &dev_priv->regs.mdfld; 322 struct medfield_state *regs = &dev_priv->regs.mdfld;
323 struct psb_pipe *pipe = &dev_priv->regs.pipe[pipenum];
360 u32 i = 0; 324 u32 i = 0;
361 u32 dpll = 0; 325 u32 dpll = 0;
362 u32 timeout = 0; 326 u32 timeout = 0;
363 327
364 /* regester */ 328 /* register */
365 u32 dpll_reg = MRST_DPLL_A; 329 u32 dpll_reg = MRST_DPLL_A;
366 u32 fp_reg = MRST_FPA0; 330 u32 fp_reg = MRST_FPA0;
367 u32 pipeconf_reg = PIPEACONF; 331 u32 pipeconf_reg = PIPEACONF;
@@ -384,33 +348,34 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
384 u32 palette_reg = PALETTE_A; 348 u32 palette_reg = PALETTE_A;
385 349
386 /* values */ 350 /* values */
387 u32 dpll_val = regs->saveDPLL_A & ~DPLL_VCO_ENABLE; 351 u32 dpll_val = pipe->dpll;
388 u32 fp_val = regs->saveFPA0; 352 u32 fp_val = pipe->fp0;
389 u32 pipeconf_val = regs->savePIPEACONF; 353 u32 pipeconf_val = pipe->conf;
390 u32 htot_val = regs->saveHTOTAL_A; 354 u32 htot_val = pipe->htotal;
391 u32 hblank_val = regs->saveHBLANK_A; 355 u32 hblank_val = pipe->hblank;
392 u32 hsync_val = regs->saveHSYNC_A; 356 u32 hsync_val = pipe->hsync;
393 u32 vtot_val = regs->saveVTOTAL_A; 357 u32 vtot_val = pipe->vtotal;
394 u32 vblank_val = regs->saveVBLANK_A; 358 u32 vblank_val = pipe->vblank;
395 u32 vsync_val = regs->saveVSYNC_A; 359 u32 vsync_val = pipe->vsync;
396 u32 pipesrc_val = regs->savePIPEASRC; 360 u32 pipesrc_val = pipe->src;
397 u32 dspstride_val = regs->saveDSPASTRIDE; 361 u32 dspstride_val = pipe->stride;
398 u32 dsplinoff_val = regs->saveDSPALINOFF; 362 u32 dsplinoff_val = pipe->linoff;
399 u32 dsptileoff_val = regs->saveDSPATILEOFF; 363 u32 dsptileoff_val = pipe->tileoff;
400 u32 dspsize_val = regs->saveDSPASIZE; 364 u32 dspsize_val = pipe->size;
401 u32 dsppos_val = regs->saveDSPAPOS; 365 u32 dsppos_val = pipe->pos;
402 u32 dspsurf_val = regs->saveDSPASURF; 366 u32 dspsurf_val = pipe->surf;
403 u32 dspstatus_val = regs->saveDSPASTATUS; 367 u32 dspstatus_val = pipe->status;
404 u32 mipi_val = regs->saveMIPI; 368 u32 mipi_val = regs->saveMIPI;
405 u32 dspcntr_val = regs->saveDSPACNTR; 369 u32 dspcntr_val = pipe->cntr;
406 u32 *palette_val = regs->save_palette_a; 370 u32 *palette_val = pipe->palette;
407 371
408 switch (pipe) { 372 switch (pipenum) {
409 case 0: 373 case 0:
374 dpll_val &= ~DPLL_VCO_ENABLE;
410 dsi_config = dev_priv->dsi_configs[0]; 375 dsi_config = dev_priv->dsi_configs[0];
411 break; 376 break;
412 case 1: 377 case 1:
413 /* regester */ 378 /* register */
414 dpll_reg = MDFLD_DPLL_B; 379 dpll_reg = MDFLD_DPLL_B;
415 fp_reg = MDFLD_DPLL_DIV0; 380 fp_reg = MDFLD_DPLL_DIV0;
416 pipeconf_reg = PIPEBCONF; 381 pipeconf_reg = PIPEBCONF;
@@ -432,28 +397,10 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
432 palette_reg = PALETTE_B; 397 palette_reg = PALETTE_B;
433 398
434 /* values */ 399 /* values */
435 dpll_val = regs->saveDPLL_B & ~DPLL_VCO_ENABLE; 400 dpll_val &= ~DPLL_VCO_ENABLE;
436 fp_val = regs->saveFPB0;
437 pipeconf_val = regs->savePIPEBCONF;
438 htot_val = regs->saveHTOTAL_B;
439 hblank_val = regs->saveHBLANK_B;
440 hsync_val = regs->saveHSYNC_B;
441 vtot_val = regs->saveVTOTAL_B;
442 vblank_val = regs->saveVBLANK_B;
443 vsync_val = regs->saveVSYNC_B;
444 pipesrc_val = regs->savePIPEBSRC;
445 dspstride_val = regs->saveDSPBSTRIDE;
446 dsplinoff_val = regs->saveDSPBLINOFF;
447 dsptileoff_val = regs->saveDSPBTILEOFF;
448 dspsize_val = regs->saveDSPBSIZE;
449 dsppos_val = regs->saveDSPBPOS;
450 dspsurf_val = regs->saveDSPBSURF;
451 dspcntr_val = regs->saveDSPBCNTR;
452 dspstatus_val = regs->saveDSPBSTATUS;
453 palette_val = regs->save_palette_b;
454 break; 401 break;
455 case 2: 402 case 2:
456 /* regester */ 403 /* register */
457 pipeconf_reg = PIPECCONF; 404 pipeconf_reg = PIPECCONF;
458 htot_reg = HTOTAL_C; 405 htot_reg = HTOTAL_C;
459 hblank_reg = HBLANK_C; 406 hblank_reg = HBLANK_C;
@@ -474,25 +421,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
474 palette_reg = PALETTE_C; 421 palette_reg = PALETTE_C;
475 422
476 /* values */ 423 /* values */
477 pipeconf_val = regs->savePIPECCONF;
478 htot_val = regs->saveHTOTAL_C;
479 hblank_val = regs->saveHBLANK_C;
480 hsync_val = regs->saveHSYNC_C;
481 vtot_val = regs->saveVTOTAL_C;
482 vblank_val = regs->saveVBLANK_C;
483 vsync_val = regs->saveVSYNC_C;
484 pipesrc_val = regs->savePIPECSRC;
485 dspstride_val = regs->saveDSPCSTRIDE;
486 dsplinoff_val = regs->saveDSPCLINOFF;
487 dsptileoff_val = regs->saveDSPCTILEOFF;
488 dspsize_val = regs->saveDSPCSIZE;
489 dsppos_val = regs->saveDSPCPOS;
490 dspsurf_val = regs->saveDSPCSURF;
491 mipi_val = regs->saveMIPI_C; 424 mipi_val = regs->saveMIPI_C;
492 dspcntr_val = regs->saveDSPCCNTR;
493 dspstatus_val = regs->saveDSPCSTATUS;
494 palette_val = regs->save_palette_c;
495
496 dsi_config = dev_priv->dsi_configs[1]; 425 dsi_config = dev_priv->dsi_configs[1];
497 break; 426 break;
498 default: 427 default:
@@ -503,7 +432,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
503 /*make sure VGA plane is off. it initializes to on after reset!*/ 432 /*make sure VGA plane is off. it initializes to on after reset!*/
504 PSB_WVDC32(0x80000000, VGACNTRL); 433 PSB_WVDC32(0x80000000, VGACNTRL);
505 434
506 if (pipe == 1) { 435 if (pipenum == 1) {
507 PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, dpll_reg); 436 PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, dpll_reg);
508 PSB_RVDC32(dpll_reg); 437 PSB_RVDC32(dpll_reg);
509 438
@@ -564,7 +493,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
564 PSB_WVDC32(dsppos_val, dsppos_reg); 493 PSB_WVDC32(dsppos_val, dsppos_reg);
565 PSB_WVDC32(dspsurf_val, dspsurf_reg); 494 PSB_WVDC32(dspsurf_val, dspsurf_reg);
566 495
567 if (pipe == 1) { 496 if (pipenum == 1) {
568 /* restore palette (gamma) */ 497 /* restore palette (gamma) */
569 /*DRM_UDELAY(50000); */ 498 /*DRM_UDELAY(50000); */
570 for (i = 0; i < 256; i++) 499 for (i = 0; i < 256; i++)
@@ -588,7 +517,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe)
588 517
589 /*setup MIPI adapter + MIPI IP registers*/ 518 /*setup MIPI adapter + MIPI IP registers*/
590 if (dsi_config) 519 if (dsi_config)
591 mdfld_dsi_controller_init(dsi_config, pipe); 520 mdfld_dsi_controller_init(dsi_config, pipenum);
592 521
593 if (in_atomic() || in_interrupt()) 522 if (in_atomic() || in_interrupt())
594 mdelay(20); 523 mdelay(20);
diff --git a/drivers/gpu/drm/gma500/oaktrail_device.c b/drivers/gpu/drm/gma500/oaktrail_device.c
index 0bb74cc3ecf8..e0b3d49a619a 100644
--- a/drivers/gpu/drm/gma500/oaktrail_device.c
+++ b/drivers/gpu/drm/gma500/oaktrail_device.c
@@ -187,6 +187,7 @@ static int oaktrail_save_display_registers(struct drm_device *dev)
187{ 187{
188 struct drm_psb_private *dev_priv = dev->dev_private; 188 struct drm_psb_private *dev_priv = dev->dev_private;
189 struct psb_save_area *regs = &dev_priv->regs; 189 struct psb_save_area *regs = &dev_priv->regs;
190 struct psb_pipe *p = &regs->pipe[0];
190 int i; 191 int i;
191 u32 pp_stat; 192 u32 pp_stat;
192 193
@@ -201,24 +202,24 @@ static int oaktrail_save_display_registers(struct drm_device *dev)
201 regs->psb.saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT); 202 regs->psb.saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
202 203
203 /* Pipe & plane A info */ 204 /* Pipe & plane A info */
204 regs->psb.savePIPEACONF = PSB_RVDC32(PIPEACONF); 205 p->conf = PSB_RVDC32(PIPEACONF);
205 regs->psb.savePIPEASRC = PSB_RVDC32(PIPEASRC); 206 p->src = PSB_RVDC32(PIPEASRC);
206 regs->psb.saveFPA0 = PSB_RVDC32(MRST_FPA0); 207 p->fp0 = PSB_RVDC32(MRST_FPA0);
207 regs->psb.saveFPA1 = PSB_RVDC32(MRST_FPA1); 208 p->fp1 = PSB_RVDC32(MRST_FPA1);
208 regs->psb.saveDPLL_A = PSB_RVDC32(MRST_DPLL_A); 209 p->dpll = PSB_RVDC32(MRST_DPLL_A);
209 regs->psb.saveHTOTAL_A = PSB_RVDC32(HTOTAL_A); 210 p->htotal = PSB_RVDC32(HTOTAL_A);
210 regs->psb.saveHBLANK_A = PSB_RVDC32(HBLANK_A); 211 p->hblank = PSB_RVDC32(HBLANK_A);
211 regs->psb.saveHSYNC_A = PSB_RVDC32(HSYNC_A); 212 p->hsync = PSB_RVDC32(HSYNC_A);
212 regs->psb.saveVTOTAL_A = PSB_RVDC32(VTOTAL_A); 213 p->vtotal = PSB_RVDC32(VTOTAL_A);
213 regs->psb.saveVBLANK_A = PSB_RVDC32(VBLANK_A); 214 p->vblank = PSB_RVDC32(VBLANK_A);
214 regs->psb.saveVSYNC_A = PSB_RVDC32(VSYNC_A); 215 p->vsync = PSB_RVDC32(VSYNC_A);
215 regs->psb.saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A); 216 regs->psb.saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A);
216 regs->psb.saveDSPACNTR = PSB_RVDC32(DSPACNTR); 217 p->cntr = PSB_RVDC32(DSPACNTR);
217 regs->psb.saveDSPASTRIDE = PSB_RVDC32(DSPASTRIDE); 218 p->stride = PSB_RVDC32(DSPASTRIDE);
218 regs->psb.saveDSPAADDR = PSB_RVDC32(DSPABASE); 219 p->addr = PSB_RVDC32(DSPABASE);
219 regs->psb.saveDSPASURF = PSB_RVDC32(DSPASURF); 220 p->surf = PSB_RVDC32(DSPASURF);
220 regs->psb.saveDSPALINOFF = PSB_RVDC32(DSPALINOFF); 221 p->linoff = PSB_RVDC32(DSPALINOFF);
221 regs->psb.saveDSPATILEOFF = PSB_RVDC32(DSPATILEOFF); 222 p->tileoff = PSB_RVDC32(DSPATILEOFF);
222 223
223 /* Save cursor regs */ 224 /* Save cursor regs */
224 regs->psb.saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR); 225 regs->psb.saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR);
@@ -227,7 +228,7 @@ static int oaktrail_save_display_registers(struct drm_device *dev)
227 228
228 /* Save palette (gamma) */ 229 /* Save palette (gamma) */
229 for (i = 0; i < 256; i++) 230 for (i = 0; i < 256; i++)
230 regs->psb.save_palette_a[i] = PSB_RVDC32(PALETTE_A + (i << 2)); 231 p->palette[i] = PSB_RVDC32(PALETTE_A + (i << 2));
231 232
232 if (dev_priv->hdmi_priv) 233 if (dev_priv->hdmi_priv)
233 oaktrail_hdmi_save(dev); 234 oaktrail_hdmi_save(dev);
@@ -300,6 +301,7 @@ static int oaktrail_restore_display_registers(struct drm_device *dev)
300{ 301{
301 struct drm_psb_private *dev_priv = dev->dev_private; 302 struct drm_psb_private *dev_priv = dev->dev_private;
302 struct psb_save_area *regs = &dev_priv->regs; 303 struct psb_save_area *regs = &dev_priv->regs;
304 struct psb_pipe *p = &regs->pipe[0];
303 u32 pp_stat; 305 u32 pp_stat;
304 int i; 306 int i;
305 307
@@ -317,21 +319,21 @@ static int oaktrail_restore_display_registers(struct drm_device *dev)
317 PSB_WVDC32(0x80000000, VGACNTRL); 319 PSB_WVDC32(0x80000000, VGACNTRL);
318 320
319 /* set the plls */ 321 /* set the plls */
320 PSB_WVDC32(regs->psb.saveFPA0, MRST_FPA0); 322 PSB_WVDC32(p->fp0, MRST_FPA0);
321 PSB_WVDC32(regs->psb.saveFPA1, MRST_FPA1); 323 PSB_WVDC32(p->fp1, MRST_FPA1);
322 324
323 /* Actually enable it */ 325 /* Actually enable it */
324 PSB_WVDC32(regs->psb.saveDPLL_A, MRST_DPLL_A); 326 PSB_WVDC32(p->dpll, MRST_DPLL_A);
325 DRM_UDELAY(150); 327 DRM_UDELAY(150);
326 328
327 /* Restore mode */ 329 /* Restore mode */
328 PSB_WVDC32(regs->psb.saveHTOTAL_A, HTOTAL_A); 330 PSB_WVDC32(p->htotal, HTOTAL_A);
329 PSB_WVDC32(regs->psb.saveHBLANK_A, HBLANK_A); 331 PSB_WVDC32(p->hblank, HBLANK_A);
330 PSB_WVDC32(regs->psb.saveHSYNC_A, HSYNC_A); 332 PSB_WVDC32(p->hsync, HSYNC_A);
331 PSB_WVDC32(regs->psb.saveVTOTAL_A, VTOTAL_A); 333 PSB_WVDC32(p->vtotal, VTOTAL_A);
332 PSB_WVDC32(regs->psb.saveVBLANK_A, VBLANK_A); 334 PSB_WVDC32(p->vblank, VBLANK_A);
333 PSB_WVDC32(regs->psb.saveVSYNC_A, VSYNC_A); 335 PSB_WVDC32(p->vsync, VSYNC_A);
334 PSB_WVDC32(regs->psb.savePIPEASRC, PIPEASRC); 336 PSB_WVDC32(p->src, PIPEASRC);
335 PSB_WVDC32(regs->psb.saveBCLRPAT_A, BCLRPAT_A); 337 PSB_WVDC32(regs->psb.saveBCLRPAT_A, BCLRPAT_A);
336 338
337 /* Restore performance mode*/ 339 /* Restore performance mode*/
@@ -339,16 +341,16 @@ static int oaktrail_restore_display_registers(struct drm_device *dev)
339 341
340 /* Enable the pipe*/ 342 /* Enable the pipe*/
341 if (dev_priv->iLVDS_enable) 343 if (dev_priv->iLVDS_enable)
342 PSB_WVDC32(regs->psb.savePIPEACONF, PIPEACONF); 344 PSB_WVDC32(p->conf, PIPEACONF);
343 345
344 /* Set up the plane*/ 346 /* Set up the plane*/
345 PSB_WVDC32(regs->psb.saveDSPALINOFF, DSPALINOFF); 347 PSB_WVDC32(p->linoff, DSPALINOFF);
346 PSB_WVDC32(regs->psb.saveDSPASTRIDE, DSPASTRIDE); 348 PSB_WVDC32(p->stride, DSPASTRIDE);
347 PSB_WVDC32(regs->psb.saveDSPATILEOFF, DSPATILEOFF); 349 PSB_WVDC32(p->tileoff, DSPATILEOFF);
348 350
349 /* Enable the plane */ 351 /* Enable the plane */
350 PSB_WVDC32(regs->psb.saveDSPACNTR, DSPACNTR); 352 PSB_WVDC32(p->cntr, DSPACNTR);
351 PSB_WVDC32(regs->psb.saveDSPASURF, DSPASURF); 353 PSB_WVDC32(p->surf, DSPASURF);
352 354
353 /* Enable Cursor A */ 355 /* Enable Cursor A */
354 PSB_WVDC32(regs->psb.saveDSPACURSOR_CTRL, CURACNTR); 356 PSB_WVDC32(regs->psb.saveDSPACURSOR_CTRL, CURACNTR);
@@ -357,7 +359,7 @@ static int oaktrail_restore_display_registers(struct drm_device *dev)
357 359
358 /* Restore palette (gamma) */ 360 /* Restore palette (gamma) */
359 for (i = 0; i < 256; i++) 361 for (i = 0; i < 256; i++)
360 PSB_WVDC32(regs->psb.save_palette_a[i], PALETTE_A + (i << 2)); 362 PSB_WVDC32(p->palette[i], PALETTE_A + (i << 2));
361 363
362 if (dev_priv->hdmi_priv) 364 if (dev_priv->hdmi_priv)
363 oaktrail_hdmi_restore(dev); 365 oaktrail_hdmi_restore(dev);
diff --git a/drivers/gpu/drm/gma500/oaktrail_hdmi.c b/drivers/gpu/drm/gma500/oaktrail_hdmi.c
index 25956601191f..c10899c953b9 100644
--- a/drivers/gpu/drm/gma500/oaktrail_hdmi.c
+++ b/drivers/gpu/drm/gma500/oaktrail_hdmi.c
@@ -434,6 +434,7 @@ void oaktrail_hdmi_save(struct drm_device *dev)
434 struct drm_psb_private *dev_priv = dev->dev_private; 434 struct drm_psb_private *dev_priv = dev->dev_private;
435 struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; 435 struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
436 struct psb_state *regs = &dev_priv->regs.psb; 436 struct psb_state *regs = &dev_priv->regs.psb;
437 struct psb_pipe *pipeb = &dev_priv->regs.pipe[1];
437 int i; 438 int i;
438 439
439 /* dpll */ 440 /* dpll */
@@ -444,14 +445,14 @@ void oaktrail_hdmi_save(struct drm_device *dev)
444 hdmi_dev->saveDPLL_CLK_ENABLE = PSB_RVDC32(DPLL_CLK_ENABLE); 445 hdmi_dev->saveDPLL_CLK_ENABLE = PSB_RVDC32(DPLL_CLK_ENABLE);
445 446
446 /* pipe B */ 447 /* pipe B */
447 regs->savePIPEBCONF = PSB_RVDC32(PIPEBCONF); 448 pipeb->conf = PSB_RVDC32(PIPEBCONF);
448 regs->savePIPEBSRC = PSB_RVDC32(PIPEBSRC); 449 pipeb->src = PSB_RVDC32(PIPEBSRC);
449 regs->saveHTOTAL_B = PSB_RVDC32(HTOTAL_B); 450 pipeb->htotal = PSB_RVDC32(HTOTAL_B);
450 regs->saveHBLANK_B = PSB_RVDC32(HBLANK_B); 451 pipeb->hblank = PSB_RVDC32(HBLANK_B);
451 regs->saveHSYNC_B = PSB_RVDC32(HSYNC_B); 452 pipeb->hsync = PSB_RVDC32(HSYNC_B);
452 regs->saveVTOTAL_B = PSB_RVDC32(VTOTAL_B); 453 pipeb->vtotal = PSB_RVDC32(VTOTAL_B);
453 regs->saveVBLANK_B = PSB_RVDC32(VBLANK_B); 454 pipeb->vblank = PSB_RVDC32(VBLANK_B);
454 regs->saveVSYNC_B = PSB_RVDC32(VSYNC_B); 455 pipeb->vsync = PSB_RVDC32(VSYNC_B);
455 456
456 hdmi_dev->savePCH_PIPEBCONF = PSB_RVDC32(PCH_PIPEBCONF); 457 hdmi_dev->savePCH_PIPEBCONF = PSB_RVDC32(PCH_PIPEBCONF);
457 hdmi_dev->savePCH_PIPEBSRC = PSB_RVDC32(PCH_PIPEBSRC); 458 hdmi_dev->savePCH_PIPEBSRC = PSB_RVDC32(PCH_PIPEBSRC);
@@ -463,12 +464,12 @@ void oaktrail_hdmi_save(struct drm_device *dev)
463 hdmi_dev->savePCH_VSYNC_B = PSB_RVDC32(PCH_VSYNC_B); 464 hdmi_dev->savePCH_VSYNC_B = PSB_RVDC32(PCH_VSYNC_B);
464 465
465 /* plane */ 466 /* plane */
466 regs->saveDSPBCNTR = PSB_RVDC32(DSPBCNTR); 467 pipeb->cntr = PSB_RVDC32(DSPBCNTR);
467 regs->saveDSPBSTRIDE = PSB_RVDC32(DSPBSTRIDE); 468 pipeb->stride = PSB_RVDC32(DSPBSTRIDE);
468 regs->saveDSPBADDR = PSB_RVDC32(DSPBBASE); 469 pipeb->addr = PSB_RVDC32(DSPBBASE);
469 regs->saveDSPBSURF = PSB_RVDC32(DSPBSURF); 470 pipeb->surf = PSB_RVDC32(DSPBSURF);
470 regs->saveDSPBLINOFF = PSB_RVDC32(DSPBLINOFF); 471 pipeb->linoff = PSB_RVDC32(DSPBLINOFF);
471 regs->saveDSPBTILEOFF = PSB_RVDC32(DSPBTILEOFF); 472 pipeb->tileoff = PSB_RVDC32(DSPBTILEOFF);
472 473
473 /* cursor B */ 474 /* cursor B */
474 regs->saveDSPBCURSOR_CTRL = PSB_RVDC32(CURBCNTR); 475 regs->saveDSPBCURSOR_CTRL = PSB_RVDC32(CURBCNTR);
@@ -477,7 +478,7 @@ void oaktrail_hdmi_save(struct drm_device *dev)
477 478
478 /* save palette */ 479 /* save palette */
479 for (i = 0; i < 256; i++) 480 for (i = 0; i < 256; i++)
480 regs->save_palette_b[i] = PSB_RVDC32(PALETTE_B + (i << 2)); 481 pipeb->palette[i] = PSB_RVDC32(PALETTE_B + (i << 2));
481} 482}
482 483
483/* restore HDMI register state */ 484/* restore HDMI register state */
@@ -486,6 +487,7 @@ void oaktrail_hdmi_restore(struct drm_device *dev)
486 struct drm_psb_private *dev_priv = dev->dev_private; 487 struct drm_psb_private *dev_priv = dev->dev_private;
487 struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv; 488 struct oaktrail_hdmi_dev *hdmi_dev = dev_priv->hdmi_priv;
488 struct psb_state *regs = &dev_priv->regs.psb; 489 struct psb_state *regs = &dev_priv->regs.psb;
490 struct psb_pipe *pipeb = &dev_priv->regs.pipe[1];
489 int i; 491 int i;
490 492
491 /* dpll */ 493 /* dpll */
@@ -497,13 +499,13 @@ void oaktrail_hdmi_restore(struct drm_device *dev)
497 DRM_UDELAY(150); 499 DRM_UDELAY(150);
498 500
499 /* pipe */ 501 /* pipe */
500 PSB_WVDC32(regs->savePIPEBSRC, PIPEBSRC); 502 PSB_WVDC32(pipeb->src, PIPEBSRC);
501 PSB_WVDC32(regs->saveHTOTAL_B, HTOTAL_B); 503 PSB_WVDC32(pipeb->htotal, HTOTAL_B);
502 PSB_WVDC32(regs->saveHBLANK_B, HBLANK_B); 504 PSB_WVDC32(pipeb->hblank, HBLANK_B);
503 PSB_WVDC32(regs->saveHSYNC_B, HSYNC_B); 505 PSB_WVDC32(pipeb->hsync, HSYNC_B);
504 PSB_WVDC32(regs->saveVTOTAL_B, VTOTAL_B); 506 PSB_WVDC32(pipeb->vtotal, VTOTAL_B);
505 PSB_WVDC32(regs->saveVBLANK_B, VBLANK_B); 507 PSB_WVDC32(pipeb->vblank, VBLANK_B);
506 PSB_WVDC32(regs->saveVSYNC_B, VSYNC_B); 508 PSB_WVDC32(pipeb->vsync, VSYNC_B);
507 509
508 PSB_WVDC32(hdmi_dev->savePCH_PIPEBSRC, PCH_PIPEBSRC); 510 PSB_WVDC32(hdmi_dev->savePCH_PIPEBSRC, PCH_PIPEBSRC);
509 PSB_WVDC32(hdmi_dev->savePCH_HTOTAL_B, PCH_HTOTAL_B); 511 PSB_WVDC32(hdmi_dev->savePCH_HTOTAL_B, PCH_HTOTAL_B);
@@ -513,15 +515,15 @@ void oaktrail_hdmi_restore(struct drm_device *dev)
513 PSB_WVDC32(hdmi_dev->savePCH_VBLANK_B, PCH_VBLANK_B); 515 PSB_WVDC32(hdmi_dev->savePCH_VBLANK_B, PCH_VBLANK_B);
514 PSB_WVDC32(hdmi_dev->savePCH_VSYNC_B, PCH_VSYNC_B); 516 PSB_WVDC32(hdmi_dev->savePCH_VSYNC_B, PCH_VSYNC_B);
515 517
516 PSB_WVDC32(regs->savePIPEBCONF, PIPEBCONF); 518 PSB_WVDC32(pipeb->conf, PIPEBCONF);
517 PSB_WVDC32(hdmi_dev->savePCH_PIPEBCONF, PCH_PIPEBCONF); 519 PSB_WVDC32(hdmi_dev->savePCH_PIPEBCONF, PCH_PIPEBCONF);
518 520
519 /* plane */ 521 /* plane */
520 PSB_WVDC32(regs->saveDSPBLINOFF, DSPBLINOFF); 522 PSB_WVDC32(pipeb->linoff, DSPBLINOFF);
521 PSB_WVDC32(regs->saveDSPBSTRIDE, DSPBSTRIDE); 523 PSB_WVDC32(pipeb->stride, DSPBSTRIDE);
522 PSB_WVDC32(regs->saveDSPBTILEOFF, DSPBTILEOFF); 524 PSB_WVDC32(pipeb->tileoff, DSPBTILEOFF);
523 PSB_WVDC32(regs->saveDSPBCNTR, DSPBCNTR); 525 PSB_WVDC32(pipeb->cntr, DSPBCNTR);
524 PSB_WVDC32(regs->saveDSPBSURF, DSPBSURF); 526 PSB_WVDC32(pipeb->surf, DSPBSURF);
525 527
526 /* cursor B */ 528 /* cursor B */
527 PSB_WVDC32(regs->saveDSPBCURSOR_CTRL, CURBCNTR); 529 PSB_WVDC32(regs->saveDSPBCURSOR_CTRL, CURBCNTR);
@@ -530,5 +532,5 @@ void oaktrail_hdmi_restore(struct drm_device *dev)
530 532
531 /* restore palette */ 533 /* restore palette */
532 for (i = 0; i < 256; i++) 534 for (i = 0; i < 256; i++)
533 PSB_WVDC32(regs->save_palette_b[i], PALETTE_B + (i << 2)); 535 PSB_WVDC32(pipeb->palette[i], PALETTE_B + (i << 2));
534} 536}
diff --git a/drivers/gpu/drm/gma500/psb_drv.h b/drivers/gpu/drm/gma500/psb_drv.h
index 309a6427584a..e25f9a124796 100644
--- a/drivers/gpu/drm/gma500/psb_drv.h
+++ b/drivers/gpu/drm/gma500/psb_drv.h
@@ -286,45 +286,37 @@ struct intel_gmbus {
286 * yet) include screen blank. Operations occuring during the save 286 * yet) include screen blank. Operations occuring during the save
287 * update the register cache instead. 287 * update the register cache instead.
288 */ 288 */
289
290/*
291 * Common status for pipes.
292 */
293struct psb_pipe {
294 u32 fp0;
295 u32 fp1;
296 u32 cntr;
297 u32 conf;
298 u32 src;
299 u32 dpll;
300 u32 dpll_md;
301 u32 htotal;
302 u32 hblank;
303 u32 hsync;
304 u32 vtotal;
305 u32 vblank;
306 u32 vsync;
307 u32 stride;
308 u32 size;
309 u32 pos;
310 u32 base;
311 u32 surf;
312 u32 addr;
313 u32 status;
314 u32 linoff;
315 u32 tileoff;
316 u32 palette[256];
317};
318
289struct psb_state { 319struct psb_state {
290 uint32_t saveDSPACNTR;
291 uint32_t saveDSPBCNTR;
292 uint32_t savePIPEACONF;
293 uint32_t savePIPEBCONF;
294 uint32_t savePIPEASRC;
295 uint32_t savePIPEBSRC;
296 uint32_t saveFPA0;
297 uint32_t saveFPA1;
298 uint32_t saveDPLL_A;
299 uint32_t saveDPLL_A_MD;
300 uint32_t saveHTOTAL_A;
301 uint32_t saveHBLANK_A;
302 uint32_t saveHSYNC_A;
303 uint32_t saveVTOTAL_A;
304 uint32_t saveVBLANK_A;
305 uint32_t saveVSYNC_A;
306 uint32_t saveDSPASTRIDE;
307 uint32_t saveDSPASIZE;
308 uint32_t saveDSPAPOS;
309 uint32_t saveDSPABASE;
310 uint32_t saveDSPASURF;
311 uint32_t saveDSPASTATUS;
312 uint32_t saveFPB0;
313 uint32_t saveFPB1;
314 uint32_t saveDPLL_B;
315 uint32_t saveDPLL_B_MD;
316 uint32_t saveHTOTAL_B;
317 uint32_t saveHBLANK_B;
318 uint32_t saveHSYNC_B;
319 uint32_t saveVTOTAL_B;
320 uint32_t saveVBLANK_B;
321 uint32_t saveVSYNC_B;
322 uint32_t saveDSPBSTRIDE;
323 uint32_t saveDSPBSIZE;
324 uint32_t saveDSPBPOS;
325 uint32_t saveDSPBBASE;
326 uint32_t saveDSPBSURF;
327 uint32_t saveDSPBSTATUS;
328 uint32_t saveVCLK_DIVISOR_VGA0; 320 uint32_t saveVCLK_DIVISOR_VGA0;
329 uint32_t saveVCLK_DIVISOR_VGA1; 321 uint32_t saveVCLK_DIVISOR_VGA1;
330 uint32_t saveVCLK_POST_DIV; 322 uint32_t saveVCLK_POST_DIV;
@@ -339,14 +331,8 @@ struct psb_state {
339 uint32_t savePP_CONTROL; 331 uint32_t savePP_CONTROL;
340 uint32_t savePP_CYCLE; 332 uint32_t savePP_CYCLE;
341 uint32_t savePFIT_CONTROL; 333 uint32_t savePFIT_CONTROL;
342 uint32_t savePaletteA[256];
343 uint32_t savePaletteB[256];
344 uint32_t saveCLOCKGATING; 334 uint32_t saveCLOCKGATING;
345 uint32_t saveDSPARB; 335 uint32_t saveDSPARB;
346 uint32_t saveDSPATILEOFF;
347 uint32_t saveDSPBTILEOFF;
348 uint32_t saveDSPAADDR;
349 uint32_t saveDSPBADDR;
350 uint32_t savePFIT_AUTO_RATIOS; 336 uint32_t savePFIT_AUTO_RATIOS;
351 uint32_t savePFIT_PGM_RATIOS; 337 uint32_t savePFIT_PGM_RATIOS;
352 uint32_t savePP_ON_DELAYS; 338 uint32_t savePP_ON_DELAYS;
@@ -354,8 +340,6 @@ struct psb_state {
354 uint32_t savePP_DIVISOR; 340 uint32_t savePP_DIVISOR;
355 uint32_t saveBCLRPAT_A; 341 uint32_t saveBCLRPAT_A;
356 uint32_t saveBCLRPAT_B; 342 uint32_t saveBCLRPAT_B;
357 uint32_t saveDSPALINOFF;
358 uint32_t saveDSPBLINOFF;
359 uint32_t savePERF_MODE; 343 uint32_t savePERF_MODE;
360 uint32_t saveDSPFW1; 344 uint32_t saveDSPFW1;
361 uint32_t saveDSPFW2; 345 uint32_t saveDSPFW2;
@@ -370,8 +354,6 @@ struct psb_state {
370 uint32_t saveDSPBCURSOR_BASE; 354 uint32_t saveDSPBCURSOR_BASE;
371 uint32_t saveDSPACURSOR_POS; 355 uint32_t saveDSPACURSOR_POS;
372 uint32_t saveDSPBCURSOR_POS; 356 uint32_t saveDSPBCURSOR_POS;
373 uint32_t save_palette_a[256];
374 uint32_t save_palette_b[256];
375 uint32_t saveOV_OVADD; 357 uint32_t saveOV_OVADD;
376 uint32_t saveOV_OGAMC0; 358 uint32_t saveOV_OGAMC0;
377 uint32_t saveOV_OGAMC1; 359 uint32_t saveOV_OGAMC1;
@@ -394,64 +376,7 @@ struct psb_state {
394}; 376};
395 377
396struct medfield_state { 378struct medfield_state {
397 uint32_t saveDPLL_A;
398 uint32_t saveFPA0;
399 uint32_t savePIPEACONF;
400 uint32_t saveHTOTAL_A;
401 uint32_t saveHBLANK_A;
402 uint32_t saveHSYNC_A;
403 uint32_t saveVTOTAL_A;
404 uint32_t saveVBLANK_A;
405 uint32_t saveVSYNC_A;
406 uint32_t savePIPEASRC;
407 uint32_t saveDSPASTRIDE;
408 uint32_t saveDSPALINOFF;
409 uint32_t saveDSPATILEOFF;
410 uint32_t saveDSPASIZE;
411 uint32_t saveDSPAPOS;
412 uint32_t saveDSPASURF;
413 uint32_t saveDSPACNTR;
414 uint32_t saveDSPASTATUS;
415 uint32_t save_palette_a[256];
416 uint32_t saveMIPI; 379 uint32_t saveMIPI;
417
418 uint32_t saveDPLL_B;
419 uint32_t saveFPB0;
420 uint32_t savePIPEBCONF;
421 uint32_t saveHTOTAL_B;
422 uint32_t saveHBLANK_B;
423 uint32_t saveHSYNC_B;
424 uint32_t saveVTOTAL_B;
425 uint32_t saveVBLANK_B;
426 uint32_t saveVSYNC_B;
427 uint32_t savePIPEBSRC;
428 uint32_t saveDSPBSTRIDE;
429 uint32_t saveDSPBLINOFF;
430 uint32_t saveDSPBTILEOFF;
431 uint32_t saveDSPBSIZE;
432 uint32_t saveDSPBPOS;
433 uint32_t saveDSPBSURF;
434 uint32_t saveDSPBCNTR;
435 uint32_t saveDSPBSTATUS;
436 uint32_t save_palette_b[256];
437
438 uint32_t savePIPECCONF;
439 uint32_t saveHTOTAL_C;
440 uint32_t saveHBLANK_C;
441 uint32_t saveHSYNC_C;
442 uint32_t saveVTOTAL_C;
443 uint32_t saveVBLANK_C;
444 uint32_t saveVSYNC_C;
445 uint32_t savePIPECSRC;
446 uint32_t saveDSPCSTRIDE;
447 uint32_t saveDSPCLINOFF;
448 uint32_t saveDSPCTILEOFF;
449 uint32_t saveDSPCSIZE;
450 uint32_t saveDSPCPOS;
451 uint32_t saveDSPCSURF;
452 uint32_t saveDSPCCNTR;
453 uint32_t saveDSPCSTATUS;
454 uint32_t save_palette_c[256];
455 uint32_t saveMIPI_C; 380 uint32_t saveMIPI_C;
456 381
457 uint32_t savePFIT_CONTROL; 382 uint32_t savePFIT_CONTROL;
@@ -480,6 +405,7 @@ struct cdv_state {
480}; 405};
481 406
482struct psb_save_area { 407struct psb_save_area {
408 struct psb_pipe pipe[3];
483 uint32_t saveBSM; 409 uint32_t saveBSM;
484 uint32_t saveVBT; 410 uint32_t saveVBT;
485 union { 411 union {
diff --git a/drivers/gpu/drm/gma500/psb_intel_display.c b/drivers/gpu/drm/gma500/psb_intel_display.c
index 2616558457c8..2cda49dc3307 100644
--- a/drivers/gpu/drm/gma500/psb_intel_display.c
+++ b/drivers/gpu/drm/gma500/psb_intel_display.c
@@ -799,8 +799,7 @@ static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
799void psb_intel_crtc_load_lut(struct drm_crtc *crtc) 799void psb_intel_crtc_load_lut(struct drm_crtc *crtc)
800{ 800{
801 struct drm_device *dev = crtc->dev; 801 struct drm_device *dev = crtc->dev;
802 struct drm_psb_private *dev_priv = 802 struct drm_psb_private *dev_priv = dev->dev_private;
803 (struct drm_psb_private *)dev->dev_private;
804 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc); 803 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
805 int palreg = PALETTE_A; 804 int palreg = PALETTE_A;
806 int i; 805 int i;
@@ -836,7 +835,7 @@ void psb_intel_crtc_load_lut(struct drm_crtc *crtc)
836 gma_power_end(dev); 835 gma_power_end(dev);
837 } else { 836 } else {
838 for (i = 0; i < 256; i++) { 837 for (i = 0; i < 256; i++) {
839 dev_priv->regs.psb.save_palette_a[i] = 838 dev_priv->regs.pipe[0].palette[i] =
840 ((psb_intel_crtc->lut_r[i] + 839 ((psb_intel_crtc->lut_r[i] +
841 psb_intel_crtc->lut_adj[i]) << 16) | 840 psb_intel_crtc->lut_adj[i]) << 16) |
842 ((psb_intel_crtc->lut_g[i] + 841 ((psb_intel_crtc->lut_g[i] +
@@ -1121,6 +1120,7 @@ static int psb_intel_crtc_clock_get(struct drm_device *dev,
1121 struct psb_intel_clock_t clock; 1120 struct psb_intel_clock_t clock;
1122 bool is_lvds; 1121 bool is_lvds;
1123 struct drm_psb_private *dev_priv = dev->dev_private; 1122 struct drm_psb_private *dev_priv = dev->dev_private;
1123 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
1124 1124
1125 if (gma_power_begin(dev, false)) { 1125 if (gma_power_begin(dev, false)) {
1126 dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B); 1126 dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B);
@@ -1131,18 +1131,12 @@ static int psb_intel_crtc_clock_get(struct drm_device *dev,
1131 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); 1131 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
1132 gma_power_end(dev); 1132 gma_power_end(dev);
1133 } else { 1133 } else {
1134 dpll = (pipe == 0) ? 1134 dpll = p->dpll;
1135 dev_priv->regs.psb.saveDPLL_A :
1136 dev_priv->regs.psb.saveDPLL_B;
1137 1135
1138 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 1136 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1139 fp = (pipe == 0) ? 1137 fp = p->fp0;
1140 dev_priv->regs.psb.saveFPA0 :
1141 dev_priv->regs.psb.saveFPB0;
1142 else 1138 else
1143 fp = (pipe == 0) ? 1139 fp = p->fp1;
1144 dev_priv->regs.psb.saveFPA1 :
1145 dev_priv->regs.psb.saveFPB1;
1146 1140
1147 is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS & 1141 is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS &
1148 LVDS_PORT_EN); 1142 LVDS_PORT_EN);
@@ -1202,6 +1196,7 @@ struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
1202 int vtot; 1196 int vtot;
1203 int vsync; 1197 int vsync;
1204 struct drm_psb_private *dev_priv = dev->dev_private; 1198 struct drm_psb_private *dev_priv = dev->dev_private;
1199 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
1205 1200
1206 if (gma_power_begin(dev, false)) { 1201 if (gma_power_begin(dev, false)) {
1207 htot = REG_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); 1202 htot = REG_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
@@ -1210,18 +1205,10 @@ struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
1210 vsync = REG_READ((pipe == 0) ? VSYNC_A : VSYNC_B); 1205 vsync = REG_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
1211 gma_power_end(dev); 1206 gma_power_end(dev);
1212 } else { 1207 } else {
1213 htot = (pipe == 0) ? 1208 htot = p->htotal;
1214 dev_priv->regs.psb.saveHTOTAL_A : 1209 hsync = p->hsync;
1215 dev_priv->regs.psb.saveHTOTAL_B; 1210 vtot = p->vtotal;
1216 hsync = (pipe == 0) ? 1211 vsync = p->vsync;
1217 dev_priv->regs.psb.saveHSYNC_A :
1218 dev_priv->regs.psb.saveHSYNC_B;
1219 vtot = (pipe == 0) ?
1220 dev_priv->regs.psb.saveVTOTAL_A :
1221 dev_priv->regs.psb.saveVTOTAL_B;
1222 vsync = (pipe == 0) ?
1223 dev_priv->regs.psb.saveVSYNC_A :
1224 dev_priv->regs.psb.saveVSYNC_B;
1225 } 1212 }
1226 1213
1227 mode = kzalloc(sizeof(*mode), GFP_KERNEL); 1214 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-04 15:01:28 -0400