Merge tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Driver specific changes

Again, a lot of platforms have changes in here: pxa, samsung, omap,
at91, imx, ...

* tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (54 commits)
  ARM: sa1100: clean up of the clock support
  ARM: pxa: add dummy clock for sa1100-rtc
  RTC: sa1100: support sa1100, pxa and mmp soc families
  RTC: sa1100: remove redundant code of setting alarm
  RTC: sa1100: Clean out ost register
  Input: zylonite-wm97xx - replace IRQ_GPIO() with gpio_to_irq()
  pcmcia: pxa: replace IRQ_GPIO() with gpio_to_irq()
  ARM: EXYNOS: Modified files for SPI consolidation work
  ARM: S5P64X0: Enable SDHCI support
  ARM: S5P64X0: Add lookup of sdhci-s3c clocks using generic names
  ARM: S5P64X0: Add HSMMC setup for host Controller
  ARM: EXYNOS: Add USB OHCI support to ORIGEN board
  USB: Add Samsung Exynos OHCI diver
  ARM: EXYNOS: Add USB OHCI support to SMDKV310 board
  ARM: EXYNOS: Add USB OHCI device
  net: macb: fix build break with !CONFIG_OF
  i2c: tegra: Support DVC controller in device tree
  i2c: tegra: Add __devinit/exit to probe/remove
  net/at91_ether: use gpio_is_valid for phy IRQ line
  ARM: at91/net: add macb ethernet controller in 9g45/9g20 DT
  ...

3 files changed, 334 insertions, 51 deletions

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 5099681cf503..e3380137b05b 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -141,6 +141,12 @@ config GPIO_PL061
         help
           Say yes here to support the PrimeCell PL061 GPIO device
 
+config GPIO_PXA
+        bool "PXA GPIO support"
+        depends on ARCH_PXA || ARCH_MMP
+        help
+          Say yes here to support the PXA GPIO device
+
 config GPIO_XILINX
         bool "Xilinx GPIO support"
         depends on PPC_OF || MICROBLAZE
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 4e018d6a7639..8ef9e9abe970 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -40,7 +40,7 @@ obj-$(CONFIG_GPIO_PCA953X)	+= gpio-pca953x.o
 obj-$(CONFIG_GPIO_PCF857X)      += gpio-pcf857x.o
 obj-$(CONFIG_GPIO_PCH)          += gpio-pch.o
 obj-$(CONFIG_GPIO_PL061)        += gpio-pl061.o
-obj-$(CONFIG_PLAT_PXA)          += gpio-pxa.o
+obj-$(CONFIG_GPIO_PXA)          += gpio-pxa.o
 obj-$(CONFIG_GPIO_RDC321X)      += gpio-rdc321x.o
 obj-$(CONFIG_PLAT_SAMSUNG)      += gpio-samsung.o
 obj-$(CONFIG_ARCH_SA1100)       += gpio-sa1100.o
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index ee137712f9db..b2d3ee1d183a 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -11,14 +11,46 @@
  *  it under the terms of the GNU General Public License version 2 as
  *  published by the Free Software Foundation.
  */
+#include <linux/clk.h>
+#include <linux/err.h>
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/platform_device.h>
 #include <linux/syscore_ops.h>
 #include <linux/slab.h>
 
-#include <mach/gpio-pxa.h>
+/*
+ * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
+ * one set of registers. The register offsets are organized below:
+ *
+ *           GPLR    GPDR    GPSR    GPCR    GRER    GFER    GEDR
+ * BANK 0 - 0x0000  0x000C  0x0018  0x0024  0x0030  0x003C  0x0048
+ * BANK 1 - 0x0004  0x0010  0x001C  0x0028  0x0034  0x0040  0x004C
+ * BANK 2 - 0x0008  0x0014  0x0020  0x002C  0x0038  0x0044  0x0050
+ *
+ * BANK 3 - 0x0100  0x010C  0x0118  0x0124  0x0130  0x013C  0x0148
+ * BANK 4 - 0x0104  0x0110  0x011C  0x0128  0x0134  0x0140  0x014C
+ * BANK 5 - 0x0108  0x0114  0x0120  0x012C  0x0138  0x0144  0x0150
+ *
+ * NOTE:
+ *   BANK 3 is only available on PXA27x and later processors.
+ *   BANK 4 and 5 are only available on PXA935
+ */
+
+#define GPLR_OFFSET     0x00
+#define GPDR_OFFSET     0x0C
+#define GPSR_OFFSET     0x18
+#define GPCR_OFFSET     0x24
+#define GRER_OFFSET     0x30
+#define GFER_OFFSET     0x3C
+#define GEDR_OFFSET     0x48
+#define GAFR_OFFSET     0x54
+#define ED_MASK_OFFSET  0x9C    /* GPIO edge detection for AP side */
+
+#define BANK_OFF(n)     (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
 
 int pxa_last_gpio;
 
@@ -39,8 +71,20 @@ struct pxa_gpio_chip {
 #endif
 };
 
+enum {
+        PXA25X_GPIO = 0,
+        PXA26X_GPIO,
+        PXA27X_GPIO,
+        PXA3XX_GPIO,
+        PXA93X_GPIO,
+        MMP_GPIO = 0x10,
+        MMP2_GPIO,
+};
+
 static DEFINE_SPINLOCK(gpio_lock);
 static struct pxa_gpio_chip *pxa_gpio_chips;
+static int gpio_type;
+static void __iomem *gpio_reg_base;
 
 #define for_each_gpio_chip(i, c)                        \
         for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
@@ -55,6 +99,122 @@ static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
         return &pxa_gpio_chips[gpio_to_bank(gpio)];
 }
 
+static inline int gpio_is_pxa_type(int type)
+{
+        return (type & MMP_GPIO) == 0;
+}
+
+static inline int gpio_is_mmp_type(int type)
+{
+        return (type & MMP_GPIO) != 0;
+}
+
+/* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
+ * as well as their Alternate Function value being '1' for GPIO in GAFRx.
+ */
+static inline int __gpio_is_inverted(int gpio)
+{
+        if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
+                return 1;
+        return 0;
+}
+
+/*
+ * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
+ * function of a GPIO, and GPDRx cannot be altered once configured. It
+ * is attributed as "occupied" here (I know this terminology isn't
+ * accurate, you are welcome to propose a better one :-)
+ */
+static inline int __gpio_is_occupied(unsigned gpio)
+{
+        struct pxa_gpio_chip *pxachip;
+        void __iomem *base;
+        unsigned long gafr = 0, gpdr = 0;
+        int ret, af = 0, dir = 0;
+
+        pxachip = gpio_to_pxachip(gpio);
+        base = gpio_chip_base(&pxachip->chip);
+        gpdr = readl_relaxed(base + GPDR_OFFSET);
+
+        switch (gpio_type) {
+        case PXA25X_GPIO:
+        case PXA26X_GPIO:
+        case PXA27X_GPIO:
+                gafr = readl_relaxed(base + GAFR_OFFSET);
+                af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
+                dir = gpdr & GPIO_bit(gpio);
+
+                if (__gpio_is_inverted(gpio))
+                        ret = (af != 1) || (dir == 0);
+                else
+                        ret = (af != 0) || (dir != 0);
+                break;
+        default:
+                ret = gpdr & GPIO_bit(gpio);
+                break;
+        }
+        return ret;
+}
+
+#ifdef CONFIG_ARCH_PXA
+static inline int __pxa_gpio_to_irq(int gpio)
+{
+        if (gpio_is_pxa_type(gpio_type))
+                return PXA_GPIO_TO_IRQ(gpio);
+        return -1;
+}
+
+static inline int __pxa_irq_to_gpio(int irq)
+{
+        if (gpio_is_pxa_type(gpio_type))
+                return irq - PXA_GPIO_TO_IRQ(0);
+        return -1;
+}
+#else
+static inline int __pxa_gpio_to_irq(int gpio) { return -1; }
+static inline int __pxa_irq_to_gpio(int irq) { return -1; }
+#endif
+
+#ifdef CONFIG_ARCH_MMP
+static inline int __mmp_gpio_to_irq(int gpio)
+{
+        if (gpio_is_mmp_type(gpio_type))
+                return MMP_GPIO_TO_IRQ(gpio);
+        return -1;
+}
+
+static inline int __mmp_irq_to_gpio(int irq)
+{
+        if (gpio_is_mmp_type(gpio_type))
+                return irq - MMP_GPIO_TO_IRQ(0);
+        return -1;
+}
+#else
+static inline int __mmp_gpio_to_irq(int gpio) { return -1; }
+static inline int __mmp_irq_to_gpio(int irq) { return -1; }
+#endif
+
+static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+        int gpio, ret;
+
+        gpio = chip->base + offset;
+        ret = __pxa_gpio_to_irq(gpio);
+        if (ret >= 0)
+                return ret;
+        return __mmp_gpio_to_irq(gpio);
+}
+
+int pxa_irq_to_gpio(int irq)
+{
+        int ret;
+
+        ret = __pxa_irq_to_gpio(irq);
+        if (ret >= 0)
+                return ret;
+        return __mmp_irq_to_gpio(irq);
+}
+
 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 {
         void __iomem *base = gpio_chip_base(chip);
@@ -63,12 +223,12 @@ static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 
         spin_lock_irqsave(&gpio_lock, flags);
 
-        value = __raw_readl(base + GPDR_OFFSET);
+        value = readl_relaxed(base + GPDR_OFFSET);
         if (__gpio_is_inverted(chip->base + offset))
                 value |= mask;
         else
                 value &= ~mask;
-        __raw_writel(value, base + GPDR_OFFSET);
+        writel_relaxed(value, base + GPDR_OFFSET);
 
         spin_unlock_irqrestore(&gpio_lock, flags);
         return 0;
@@ -81,16 +241,16 @@ static int pxa_gpio_direction_output(struct gpio_chip *chip,
         uint32_t tmp, mask = 1 << offset;
         unsigned long flags;
 
-        __raw_writel(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
+        writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
 
         spin_lock_irqsave(&gpio_lock, flags);
 
-        tmp = __raw_readl(base + GPDR_OFFSET);
+        tmp = readl_relaxed(base + GPDR_OFFSET);
         if (__gpio_is_inverted(chip->base + offset))
                 tmp &= ~mask;
         else
                 tmp |= mask;
-        __raw_writel(tmp, base + GPDR_OFFSET);
+        writel_relaxed(tmp, base + GPDR_OFFSET);
 
         spin_unlock_irqrestore(&gpio_lock, flags);
         return 0;
@@ -98,16 +258,16 @@ static int pxa_gpio_direction_output(struct gpio_chip *chip,
 
 static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
-        return __raw_readl(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
+        return readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
 }
 
 static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 {
-        __raw_writel(1 << offset, gpio_chip_base(chip) +
+        writel_relaxed(1 << offset, gpio_chip_base(chip) +
                                 (value ? GPSR_OFFSET : GPCR_OFFSET));
 }
 
-static int __init pxa_init_gpio_chip(int gpio_end)
+static int __devinit pxa_init_gpio_chip(int gpio_end)
 {
         int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
         struct pxa_gpio_chip *chips;
@@ -122,7 +282,7 @@ static int __init pxa_init_gpio_chip(int gpio_end)
                 struct gpio_chip *c = &chips[i].chip;
 
                 sprintf(chips[i].label, "gpio-%d", i);
-                chips[i].regbase = GPIO_BANK(i);
+                chips[i].regbase = gpio_reg_base + BANK_OFF(i);
 
                 c->base  = gpio;
                 c->label = chips[i].label;
@@ -131,6 +291,7 @@ static int __init pxa_init_gpio_chip(int gpio_end)
                 c->direction_output = pxa_gpio_direction_output;
                 c->get = pxa_gpio_get;
                 c->set = pxa_gpio_set;
+                c->to_irq = pxa_gpio_to_irq;
 
                 /* number of GPIOs on last bank may be less than 32 */
                 c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
@@ -147,18 +308,18 @@ static inline void update_edge_detect(struct pxa_gpio_chip *c)
 {
         uint32_t grer, gfer;
 
-        grer = __raw_readl(c->regbase + GRER_OFFSET) & ~c->irq_mask;
-        gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~c->irq_mask;
+        grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
+        gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
         grer |= c->irq_edge_rise & c->irq_mask;
         gfer |= c->irq_edge_fall & c->irq_mask;
-        __raw_writel(grer, c->regbase + GRER_OFFSET);
-        __raw_writel(gfer, c->regbase + GFER_OFFSET);
+        writel_relaxed(grer, c->regbase + GRER_OFFSET);
+        writel_relaxed(gfer, c->regbase + GFER_OFFSET);
 }
 
 static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
 {
         struct pxa_gpio_chip *c;
-        int gpio = irq_to_gpio(d->irq);
+        int gpio = pxa_irq_to_gpio(d->irq);
         unsigned long gpdr, mask = GPIO_bit(gpio);
 
         c = gpio_to_pxachip(gpio);
@@ -176,12 +337,12 @@ static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
         }
 
-        gpdr = __raw_readl(c->regbase + GPDR_OFFSET);
+        gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
 
         if (__gpio_is_inverted(gpio))
-                __raw_writel(gpdr | mask,  c->regbase + GPDR_OFFSET);
+                writel_relaxed(gpdr | mask,  c->regbase + GPDR_OFFSET);
         else
-                __raw_writel(gpdr & ~mask, c->regbase + GPDR_OFFSET);
+                writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
 
         if (type & IRQ_TYPE_EDGE_RISING)
                 c->irq_edge_rise |= mask;
@@ -212,9 +373,9 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
                 for_each_gpio_chip(gpio, c) {
                         gpio_base = c->chip.base;
 
-                        gedr = __raw_readl(c->regbase + GEDR_OFFSET);
+                        gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
                         gedr = gedr & c->irq_mask;
-                        __raw_writel(gedr, c->regbase + GEDR_OFFSET);
+                        writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
 
                         n = find_first_bit(&gedr, BITS_PER_LONG);
                         while (n < BITS_PER_LONG) {
@@ -229,29 +390,29 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
 
 static void pxa_ack_muxed_gpio(struct irq_data *d)
 {
-        int gpio = irq_to_gpio(d->irq);
+        int gpio = pxa_irq_to_gpio(d->irq);
         struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
 
-        __raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
+        writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
 }
 
 static void pxa_mask_muxed_gpio(struct irq_data *d)
 {
-        int gpio = irq_to_gpio(d->irq);
+        int gpio = pxa_irq_to_gpio(d->irq);
         struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
         uint32_t grer, gfer;
 
         c->irq_mask &= ~GPIO_bit(gpio);
 
-        grer = __raw_readl(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
-        gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
-        __raw_writel(grer, c->regbase + GRER_OFFSET);
-        __raw_writel(gfer, c->regbase + GFER_OFFSET);
+        grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
+        gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
+        writel_relaxed(grer, c->regbase + GRER_OFFSET);
+        writel_relaxed(gfer, c->regbase + GFER_OFFSET);
 }
 
 static void pxa_unmask_muxed_gpio(struct irq_data *d)
 {
-        int gpio = irq_to_gpio(d->irq);
+        int gpio = pxa_irq_to_gpio(d->irq);
         struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
 
         c->irq_mask |= GPIO_bit(gpio);
@@ -266,34 +427,143 @@ static struct irq_chip pxa_muxed_gpio_chip = {
         .irq_set_type   = pxa_gpio_irq_type,
 };
 
-void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn)
+static int pxa_gpio_nums(void)
 {
-        struct pxa_gpio_chip *c;
-        int gpio, irq;
+        int count = 0;
+
+#ifdef CONFIG_ARCH_PXA
+        if (cpu_is_pxa25x()) {
+#ifdef CONFIG_CPU_PXA26x
+                count = 89;
+                gpio_type = PXA26X_GPIO;
+#elif defined(CONFIG_PXA25x)
+                count = 84;
+                gpio_type = PXA26X_GPIO;
+#endif /* CONFIG_CPU_PXA26x */
+        } else if (cpu_is_pxa27x()) {
+                count = 120;
+                gpio_type = PXA27X_GPIO;
+        } else if (cpu_is_pxa93x() || cpu_is_pxa95x()) {
+                count = 191;
+                gpio_type = PXA93X_GPIO;
+        } else if (cpu_is_pxa3xx()) {
+                count = 127;
+                gpio_type = PXA3XX_GPIO;
+        }
+#endif /* CONFIG_ARCH_PXA */
+
+#ifdef CONFIG_ARCH_MMP
+        if (cpu_is_pxa168() || cpu_is_pxa910()) {
+                count = 127;
+                gpio_type = MMP_GPIO;
+        } else if (cpu_is_mmp2()) {
+                count = 191;
+                gpio_type = MMP2_GPIO;
+        }
+#endif /* CONFIG_ARCH_MMP */
+        return count;
+}
 
-        pxa_last_gpio = end;
+static int __devinit pxa_gpio_probe(struct platform_device *pdev)
+{
+        struct pxa_gpio_chip *c;
+        struct resource *res;
+        struct clk *clk;
+        int gpio, irq, ret;
+        int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
+
+        pxa_last_gpio = pxa_gpio_nums();
+        if (!pxa_last_gpio)
+                return -EINVAL;
+
+        irq0 = platform_get_irq_byname(pdev, "gpio0");
+        irq1 = platform_get_irq_byname(pdev, "gpio1");
+        irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
+        if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
+                || (irq_mux <= 0))
+                return -EINVAL;
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res)
+                return -EINVAL;
+        gpio_reg_base = ioremap(res->start, resource_size(res));
+        if (!gpio_reg_base)
+                return -EINVAL;
+
+        if (irq0 > 0)
+                gpio_offset = 2;
+
+        clk = clk_get(&pdev->dev, NULL);
+        if (IS_ERR(clk)) {
+                dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
+                        PTR_ERR(clk));
+                iounmap(gpio_reg_base);
+                return PTR_ERR(clk);
+        }
+        ret = clk_prepare(clk);
+        if (ret) {
+                clk_put(clk);
+                iounmap(gpio_reg_base);
+                return ret;
+        }
+        ret = clk_enable(clk);
+        if (ret) {
+                clk_unprepare(clk);
+                clk_put(clk);
+                iounmap(gpio_reg_base);
+                return ret;
+        }
 
         /* Initialize GPIO chips */
-        pxa_init_gpio_chip(end);
+        pxa_init_gpio_chip(pxa_last_gpio);
 
         /* clear all GPIO edge detects */
         for_each_gpio_chip(gpio, c) {
-                __raw_writel(0, c->regbase + GFER_OFFSET);
-                __raw_writel(0, c->regbase + GRER_OFFSET);
-                __raw_writel(~0,c->regbase + GEDR_OFFSET);
+                writel_relaxed(0, c->regbase + GFER_OFFSET);
+                writel_relaxed(0, c->regbase + GRER_OFFSET);
+                writel_relaxed(~0,c->regbase + GEDR_OFFSET);
+                /* unmask GPIO edge detect for AP side */
+                if (gpio_is_mmp_type(gpio_type))
+                        writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
         }
 
-        for (irq  = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) {
+#ifdef CONFIG_ARCH_PXA
+        irq = gpio_to_irq(0);
+        irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
+                                 handle_edge_irq);
+        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+        irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);
+
+        irq = gpio_to_irq(1);
+        irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
+                                 handle_edge_irq);
+        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+        irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
+#endif
+
+        for (irq  = gpio_to_irq(gpio_offset);
+                irq <= gpio_to_irq(pxa_last_gpio); irq++) {
                 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
                                          handle_edge_irq);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
 
-        /* Install handler for GPIO>=2 edge detect interrupts */
-        irq_set_chained_handler(mux_irq, pxa_gpio_demux_handler);
-        pxa_muxed_gpio_chip.irq_set_wake = fn;
+        irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler);
+        return 0;
 }
 
+static struct platform_driver pxa_gpio_driver = {
+        .probe          = pxa_gpio_probe,
+        .driver         = {
+                .name   = "pxa-gpio",
+        },
+};
+
+static int __init pxa_gpio_init(void)
+{
+        return platform_driver_register(&pxa_gpio_driver);
+}
+postcore_initcall(pxa_gpio_init);
+
 #ifdef CONFIG_PM
 static int pxa_gpio_suspend(void)
 {
@@ -301,13 +571,13 @@ static int pxa_gpio_suspend(void)
         int gpio;
 
         for_each_gpio_chip(gpio, c) {
-                c->saved_gplr = __raw_readl(c->regbase + GPLR_OFFSET);
-                c->saved_gpdr = __raw_readl(c->regbase + GPDR_OFFSET);
-                c->saved_grer = __raw_readl(c->regbase + GRER_OFFSET);
-                c->saved_gfer = __raw_readl(c->regbase + GFER_OFFSET);
+                c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
+                c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
+                c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
+                c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
 
                 /* Clear GPIO transition detect bits */
-                __raw_writel(0xffffffff, c->regbase + GEDR_OFFSET);
+                writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
         }
         return 0;
 }
@@ -319,12 +589,12 @@ static void pxa_gpio_resume(void)
 
         for_each_gpio_chip(gpio, c) {
                 /* restore level with set/clear */
-                __raw_writel( c->saved_gplr, c->regbase + GPSR_OFFSET);
-                __raw_writel(~c->saved_gplr, c->regbase + GPCR_OFFSET);
+                writel_relaxed( c->saved_gplr, c->regbase + GPSR_OFFSET);
+                writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
 
-                __raw_writel(c->saved_grer, c->regbase + GRER_OFFSET);
-                __raw_writel(c->saved_gfer, c->regbase + GFER_OFFSET);
-                __raw_writel(c->saved_gpdr, c->regbase + GPDR_OFFSET);
+                writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
+                writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
+                writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
         }
 }
 #else
@@ -336,3 +606,10 @@ struct syscore_ops pxa_gpio_syscore_ops = {
         .suspend        = pxa_gpio_suspend,
         .resume         = pxa_gpio_resume,
 };
+
+static int __init pxa_gpio_sysinit(void)
+{
+        register_syscore_ops(&pxa_gpio_syscore_ops);
+        return 0;
+}
+postcore_initcall(pxa_gpio_sysinit);