Merge tag 'exynos-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc

Merge "Samsung exynos cpuidle update for v3.17" from Kukjin Kim:

- add callbacks exynos_suspend() and exynos_powered_up()
  for support cpuidle through mcpm
- skip exynos_cpuidle for exynos5420 because is uses
  cpuidle-big-liggle generic cpuidle driver
- add generic functions to calculate cpu number is used
  for pmu and this is required for exynos5420 multi-cluster
- add of_device_id structure for big.LITTLE cpuidle and
  add "samsung,exynos5420" compatible string for exynos5420

* tag 'exynos-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: EXYNOS: populate suspend and powered_up callbacks for mcpm
  ARM: EXYNOS: do not allow cpuidle registration for exynos5420
  cpuidle: big.LITTLE: init driver for exynos5420
  cpuidle: big.LITTLE: Add ARCH_EXYNOS entry in config
  ARM: EXYNOS: add generic function to calculate cpu number
  cpuidle: big.LITTLE: add of_device_id structure
  + Linux 3.16-rc5

Signed-off-by: Olof Johansson <olof@lixom.net>

12 files changed, 97 insertions, 69 deletions

diff --git a/drivers/clk/clk-s2mps11.c b/drivers/clk/clk-s2mps11.c
index 9b7b5859a420..3757e9e72d37 100644
--- a/drivers/clk/clk-s2mps11.c
+++ b/drivers/clk/clk-s2mps11.c
@@ -230,16 +230,13 @@ static int s2mps11_clk_probe(struct platform_device *pdev)
                         goto err_reg;
                 }
 
-                s2mps11_clk->lookup = devm_kzalloc(&pdev->dev,
-                                        sizeof(struct clk_lookup), GFP_KERNEL);
+                s2mps11_clk->lookup = clkdev_alloc(s2mps11_clk->clk,
+                                        s2mps11_name(s2mps11_clk), NULL);
                 if (!s2mps11_clk->lookup) {
                         ret = -ENOMEM;
                         goto err_lup;
                 }
 
-                s2mps11_clk->lookup->con_id = s2mps11_name(s2mps11_clk);
-                s2mps11_clk->lookup->clk = s2mps11_clk->clk;
-
                 clkdev_add(s2mps11_clk->lookup);
         }
 
diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c
index 12f3c0b64fcd..4c449b3170f6 100644
--- a/drivers/clk/qcom/mmcc-msm8960.c
+++ b/drivers/clk/qcom/mmcc-msm8960.c
@@ -1209,7 +1209,7 @@ static struct clk_branch rot_clk = {
 
 static u8 mmcc_pxo_hdmi_map[] = {
         [P_PXO]         = 0,
-        [P_HDMI_PLL]    = 2,
+        [P_HDMI_PLL]    = 3,
 };
 
 static const char *mmcc_pxo_hdmi[] = {
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 4f150c9dd38c..7f4a473a7ad7 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -925,21 +925,13 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
         GATE(CLK_RTC, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15,
                         0, 0),
         GATE(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0),
-        GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "div_pwm_isp",
-                        E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0),
-        GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp_pre",
-                        E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0),
-        GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp_pre",
-                        E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0),
-        GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp",
-                        E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0),
-        GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "sclk_pwm_isp",
+        GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "div_pwm_isp",
                         E4X12_GATE_IP_ISP, 0, 0, 0),
-        GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "sclk_spi0_isp",
+        GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "div_spi0_isp_pre",
                         E4X12_GATE_IP_ISP, 1, 0, 0),
-        GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "sclk_spi1_isp",
+        GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "div_spi1_isp_pre",
                         E4X12_GATE_IP_ISP, 2, 0, 0),
-        GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "sclk_uart_isp",
+        GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "div_uart_isp",
                         E4X12_GATE_IP_ISP, 3, 0, 0),
         GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0),
         GATE(CLK_PCM0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2,
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 1fad4c5e3f5d..184f64293b26 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -661,7 +661,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
         GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0),
         GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0),
         GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub",
-                        GATE_IP_DISP1, 2, 0, 0),
+                        GATE_IP_DISP1, 9, 0, 0),
         GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub",
                         GATE_IP_DISP1, 8, 0, 0),
         GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0),
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 9d7d7eed03fd..a4e6cc782e5c 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -631,7 +631,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
                         SRC_TOP4, 16, 1),
         MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
         MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
-        MUX(0, "mout_user_aclk333", mout_user_aclk333_p, SRC_TOP4, 28, 1),
+        MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
+                        SRC_TOP4, 28, 1),
 
         MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p,
                         SRC_TOP5, 0, 1),
@@ -684,7 +685,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
                         SRC_TOP11, 12, 1),
         MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
         MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
-        MUX(0, "mout_sw_aclk333", mout_sw_aclk333_p, SRC_TOP11, 28, 1),
+        MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
+                        SRC_TOP11, 28, 1),
 
         MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p,
                         SRC_TOP12, 4, 1),
@@ -890,8 +892,6 @@ static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = {
                         GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
         GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
                         GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
-        GATE(CLK_ACLK66_PERIC, "aclk66_peric", "mout_user_aclk66_peric",
-                        GATE_BUS_TOP, 11, CLK_IGNORE_UNUSED, 0),
         GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
                         GATE_BUS_TOP, 13, 0, 0),
         GATE(0, "aclk166", "mout_user_aclk166",
@@ -994,34 +994,61 @@ static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = {
                         SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
 
         /* PERIC Block */
-        GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_IP_PERIC, 0, 0, 0),
-        GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_IP_PERIC, 1, 0, 0),
-        GATE(CLK_UART2, "uart2", "aclk66_peric", GATE_IP_PERIC, 2, 0, 0),
-        GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_IP_PERIC, 3, 0, 0),
-        GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_IP_PERIC, 6, 0, 0),
-        GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_IP_PERIC, 7, 0, 0),
-        GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_IP_PERIC, 8, 0, 0),
-        GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_IP_PERIC, 9, 0, 0),
-        GATE(CLK_USI0, "usi0", "aclk66_peric", GATE_IP_PERIC, 10, 0, 0),
-        GATE(CLK_USI1, "usi1", "aclk66_peric", GATE_IP_PERIC, 11, 0, 0),
-        GATE(CLK_USI2, "usi2", "aclk66_peric", GATE_IP_PERIC, 12, 0, 0),
-        GATE(CLK_USI3, "usi3", "aclk66_peric", GATE_IP_PERIC, 13, 0, 0),
-        GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_IP_PERIC, 14, 0, 0),
-        GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_IP_PERIC, 15, 0, 0),
-        GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_IP_PERIC, 16, 0, 0),
-        GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_IP_PERIC, 17, 0, 0),
-        GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_IP_PERIC, 18, 0, 0),
-        GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_IP_PERIC, 20, 0, 0),
-        GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_IP_PERIC, 21, 0, 0),
-        GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_IP_PERIC, 22, 0, 0),
-        GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_IP_PERIC, 23, 0, 0),
-        GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_IP_PERIC, 24, 0, 0),
-        GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_IP_PERIC, 26, 0, 0),
-        GATE(CLK_USI4, "usi4", "aclk66_peric", GATE_IP_PERIC, 28, 0, 0),
-        GATE(CLK_USI5, "usi5", "aclk66_peric", GATE_IP_PERIC, 30, 0, 0),
-        GATE(CLK_USI6, "usi6", "aclk66_peric", GATE_IP_PERIC, 31, 0, 0),
-
-        GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0),
+        GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 0, 0, 0),
+        GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 1, 0, 0),
+        GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 2, 0, 0),
+        GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 3, 0, 0),
+        GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 6, 0, 0),
+        GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 7, 0, 0),
+        GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 8, 0, 0),
+        GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 9, 0, 0),
+        GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 10, 0, 0),
+        GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 11, 0, 0),
+        GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 12, 0, 0),
+        GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 13, 0, 0),
+        GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 14, 0, 0),
+        GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 15, 0, 0),
+        GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 16, 0, 0),
+        GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 17, 0, 0),
+        GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 18, 0, 0),
+        GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 20, 0, 0),
+        GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 21, 0, 0),
+        GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 22, 0, 0),
+        GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 23, 0, 0),
+        GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 24, 0, 0),
+        GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 26, 0, 0),
+        GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 28, 0, 0),
+        GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 30, 0, 0),
+        GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric",
+                        GATE_IP_PERIC, 31, 0, 0),
+
+        GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric",
+                        GATE_BUS_PERIC, 22, 0, 0),
 
         /* PERIS Block */
         GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
diff --git a/drivers/clk/samsung/clk-s3c2410.c b/drivers/clk/samsung/clk-s3c2410.c
index ba0716801db2..140f4733c02e 100644
--- a/drivers/clk/samsung/clk-s3c2410.c
+++ b/drivers/clk/samsung/clk-s3c2410.c
@@ -152,6 +152,11 @@ struct samsung_clock_alias s3c2410_common_aliases[] __initdata = {
         ALIAS(HCLK, NULL, "hclk"),
         ALIAS(MPLL, NULL, "mpll"),
         ALIAS(FCLK, NULL, "fclk"),
+        ALIAS(PCLK, NULL, "watchdog"),
+        ALIAS(PCLK_SDI, NULL, "sdi"),
+        ALIAS(HCLK_NAND, NULL, "nand"),
+        ALIAS(PCLK_I2S, NULL, "iis"),
+        ALIAS(PCLK_I2C, NULL, "i2c"),
 };
 
 /* S3C2410 specific clocks */
@@ -378,7 +383,7 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
         if (!np)
                 s3c2410_common_clk_register_fixed_ext(ctx, xti_f);
 
-        if (current_soc == 2410) {
+        if (current_soc == S3C2410) {
                 if (_get_rate("xti") == 12 * MHZ) {
                         s3c2410_plls[mpll].rate_table = pll_s3c2410_12mhz_tbl;
                         s3c2410_plls[upll].rate_table = pll_s3c2410_12mhz_tbl;
@@ -432,7 +437,7 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
                 samsung_clk_register_fixed_factor(ctx, s3c2410_ffactor,
                                 ARRAY_SIZE(s3c2410_ffactor));
                 samsung_clk_register_alias(ctx, s3c2410_aliases,
-                        ARRAY_SIZE(s3c2410_common_aliases));
+                        ARRAY_SIZE(s3c2410_aliases));
                 break;
         case S3C2440:
                 samsung_clk_register_mux(ctx, s3c2440_muxes,
diff --git a/drivers/clk/samsung/clk-s3c64xx.c b/drivers/clk/samsung/clk-s3c64xx.c
index efa16ee592c8..8889ff1c10fc 100644
--- a/drivers/clk/samsung/clk-s3c64xx.c
+++ b/drivers/clk/samsung/clk-s3c64xx.c
@@ -418,8 +418,10 @@ static struct samsung_clock_alias s3c64xx_clock_aliases[] = {
         ALIAS(SCLK_MMC2, "s3c-sdhci.2", "mmc_busclk.2"),
         ALIAS(SCLK_MMC1, "s3c-sdhci.1", "mmc_busclk.2"),
         ALIAS(SCLK_MMC0, "s3c-sdhci.0", "mmc_busclk.2"),
-        ALIAS(SCLK_SPI1, "s3c6410-spi.1", "spi-bus"),
-        ALIAS(SCLK_SPI0, "s3c6410-spi.0", "spi-bus"),
+        ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi_busclk0"),
+        ALIAS(SCLK_SPI1, "s3c6410-spi.1", "spi_busclk2"),
+        ALIAS(PCLK_SPI0, "s3c6410-spi.0", "spi_busclk0"),
+        ALIAS(SCLK_SPI0, "s3c6410-spi.0", "spi_busclk2"),
         ALIAS(SCLK_AUDIO1, "samsung-pcm.1", "audio-bus"),
         ALIAS(SCLK_AUDIO1, "samsung-i2s.1", "audio-bus"),
         ALIAS(SCLK_AUDIO0, "samsung-pcm.0", "audio-bus"),
diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c
index c2d204315546..bb5f387774e2 100644
--- a/drivers/clk/spear/spear3xx_clock.c
+++ b/drivers/clk/spear/spear3xx_clock.c
@@ -211,7 +211,7 @@ static inline void spear310_clk_init(void) { }
 /* array of all spear 320 clock lookups */
 #ifdef CONFIG_MACH_SPEAR320
 
-#define SPEAR320_CONTROL_REG            (soc_config_base + 0x0000)
+#define SPEAR320_CONTROL_REG            (soc_config_base + 0x0010)
 #define SPEAR320_EXT_CTRL_REG           (soc_config_base + 0x0018)
 
         #define SPEAR320_UARTX_PCLK_MASK                0x1
@@ -245,7 +245,8 @@ static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk",
         "ras_syn0_gclk", };
 static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", };
 
-static void __init spear320_clk_init(void __iomem *soc_config_base)
+static void __init spear320_clk_init(void __iomem *soc_config_base,
+                                     struct clk *ras_apb_clk)
 {
         struct clk *clk;
 
@@ -342,6 +343,8 @@ static void __init spear320_clk_init(void __iomem *soc_config_base)
                         SPEAR320_CONTROL_REG, UART1_PCLK_SHIFT, UART1_PCLK_MASK,
                         0, &_lock);
         clk_register_clkdev(clk, NULL, "a3000000.serial");
+        /* Enforce ras_apb_clk */
+        clk_set_parent(clk, ras_apb_clk);
 
         clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
                         ARRAY_SIZE(uartx_parents),
@@ -349,6 +352,8 @@ static void __init spear320_clk_init(void __iomem *soc_config_base)
                         SPEAR320_EXT_CTRL_REG, SPEAR320_UART2_PCLK_SHIFT,
                         SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
         clk_register_clkdev(clk, NULL, "a4000000.serial");
+        /* Enforce ras_apb_clk */
+        clk_set_parent(clk, ras_apb_clk);
 
         clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
                         ARRAY_SIZE(uartx_parents),
@@ -379,12 +384,12 @@ static void __init spear320_clk_init(void __iomem *soc_config_base)
         clk_register_clkdev(clk, NULL, "60100000.serial");
 }
 #else
-static inline void spear320_clk_init(void __iomem *soc_config_base) { }
+static inline void spear320_clk_init(void __iomem *sb, struct clk *rc) { }
 #endif
 
 void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base)
 {
-        struct clk *clk, *clk1;
+        struct clk *clk, *clk1, *ras_apb_clk;
 
         clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
                         32000);
@@ -613,6 +618,7 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
         clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB,
                         RAS_APB_CLK_ENB, 0, &_lock);
         clk_register_clkdev(clk, "ras_apb_clk", NULL);
+        ras_apb_clk = clk;
 
         clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0,
                         RAS_CLK_ENB, RAS_32K_CLK_ENB, 0, &_lock);
@@ -659,5 +665,5 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
         else if (of_machine_is_compatible("st,spear310"))
                 spear310_clk_init();
         else if (of_machine_is_compatible("st,spear320"))
-                spear320_clk_init(soc_config_base);
+                spear320_clk_init(soc_config_base, ras_apb_clk);
 }
diff --git a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
index 44cd27c5c401..670f90d629d7 100644
--- a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
+++ b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
@@ -29,7 +29,7 @@ static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev)
 
         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         reg = devm_ioremap_resource(&pdev->dev, r);
-        if (!reg)
+        if (IS_ERR(reg))
                 return PTR_ERR(reg);
 
         clk_parent = of_clk_get_parent_name(np, 0);
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
index 5428c9c547cd..72d97279eae1 100644
--- a/drivers/clk/ti/apll.c
+++ b/drivers/clk/ti/apll.c
@@ -77,13 +77,11 @@ static int dra7_apll_enable(struct clk_hw *hw)
         if (i == MAX_APLL_WAIT_TRIES) {
                 pr_warn("clock: %s failed transition to '%s'\n",
                         clk_name, (state) ? "locked" : "bypassed");
-        } else {
+                r = -EBUSY;
+        } else
                 pr_debug("clock: %s transition to '%s' in %d loops\n",
                          clk_name, (state) ? "locked" : "bypassed", i);
 
-                r = 0;
-        }
-
         return r;
 }
 
@@ -338,7 +336,7 @@ static void __init of_omap2_apll_setup(struct device_node *node)
         const char *parent_name;
         u32 val;
 
-        ad = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
+        ad = kzalloc(sizeof(*ad), GFP_KERNEL);
         clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
         init = kzalloc(sizeof(*init), GFP_KERNEL);
 
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index abd956d5f838..79791e1bf282 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -161,7 +161,8 @@ cleanup:
 }
 
 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
-        defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX)
+        defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
+        defined(CONFIG_SOC_AM43XX)
 /**
  * ti_clk_register_dpll_x2 - Registers a DPLLx2 clock
  * @node: device node for this clock
@@ -322,7 +323,7 @@ CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
                of_ti_omap4_dpll_x2_setup);
 #endif
 
-#ifdef CONFIG_SOC_AM33XX
+#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 static void __init of_ti_am3_dpll_x2_setup(struct device_node *node)
 {
         ti_clk_register_dpll_x2(node, &dpll_x2_ck_ops, NULL);
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
index 0197a478720c..e9d650e51287 100644
--- a/drivers/clk/ti/mux.c
+++ b/drivers/clk/ti/mux.c
@@ -160,7 +160,7 @@ static void of_mux_clk_setup(struct device_node *node)
         u8 clk_mux_flags = 0;
         u32 mask = 0;
         u32 shift = 0;
-        u32 flags = 0;
+        u32 flags = CLK_SET_RATE_NO_REPARENT;
 
         num_parents = of_clk_get_parent_count(node);
         if (num_parents < 2) {