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path: root/drivers/clk/spear/spear3xx_clock.c
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Diffstat (limited to 'drivers/clk/spear/spear3xx_clock.c')
-rw-r--r--drivers/clk/spear/spear3xx_clock.c16
1 files changed, 11 insertions, 5 deletions
diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c
index c2d204315546..bb5f387774e2 100644
--- a/drivers/clk/spear/spear3xx_clock.c
+++ b/drivers/clk/spear/spear3xx_clock.c
@@ -211,7 +211,7 @@ static inline void spear310_clk_init(void) { }
211/* array of all spear 320 clock lookups */ 211/* array of all spear 320 clock lookups */
212#ifdef CONFIG_MACH_SPEAR320 212#ifdef CONFIG_MACH_SPEAR320
213 213
214#define SPEAR320_CONTROL_REG (soc_config_base + 0x0000) 214#define SPEAR320_CONTROL_REG (soc_config_base + 0x0010)
215#define SPEAR320_EXT_CTRL_REG (soc_config_base + 0x0018) 215#define SPEAR320_EXT_CTRL_REG (soc_config_base + 0x0018)
216 216
217 #define SPEAR320_UARTX_PCLK_MASK 0x1 217 #define SPEAR320_UARTX_PCLK_MASK 0x1
@@ -245,7 +245,8 @@ static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk",
245 "ras_syn0_gclk", }; 245 "ras_syn0_gclk", };
246static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", }; 246static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", };
247 247
248static void __init spear320_clk_init(void __iomem *soc_config_base) 248static void __init spear320_clk_init(void __iomem *soc_config_base,
249 struct clk *ras_apb_clk)
249{ 250{
250 struct clk *clk; 251 struct clk *clk;
251 252
@@ -342,6 +343,8 @@ static void __init spear320_clk_init(void __iomem *soc_config_base)
342 SPEAR320_CONTROL_REG, UART1_PCLK_SHIFT, UART1_PCLK_MASK, 343 SPEAR320_CONTROL_REG, UART1_PCLK_SHIFT, UART1_PCLK_MASK,
343 0, &_lock); 344 0, &_lock);
344 clk_register_clkdev(clk, NULL, "a3000000.serial"); 345 clk_register_clkdev(clk, NULL, "a3000000.serial");
346 /* Enforce ras_apb_clk */
347 clk_set_parent(clk, ras_apb_clk);
345 348
346 clk = clk_register_mux(NULL, "uart2_clk", uartx_parents, 349 clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
347 ARRAY_SIZE(uartx_parents), 350 ARRAY_SIZE(uartx_parents),
@@ -349,6 +352,8 @@ static void __init spear320_clk_init(void __iomem *soc_config_base)
349 SPEAR320_EXT_CTRL_REG, SPEAR320_UART2_PCLK_SHIFT, 352 SPEAR320_EXT_CTRL_REG, SPEAR320_UART2_PCLK_SHIFT,
350 SPEAR320_UARTX_PCLK_MASK, 0, &_lock); 353 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
351 clk_register_clkdev(clk, NULL, "a4000000.serial"); 354 clk_register_clkdev(clk, NULL, "a4000000.serial");
355 /* Enforce ras_apb_clk */
356 clk_set_parent(clk, ras_apb_clk);
352 357
353 clk = clk_register_mux(NULL, "uart3_clk", uartx_parents, 358 clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
354 ARRAY_SIZE(uartx_parents), 359 ARRAY_SIZE(uartx_parents),
@@ -379,12 +384,12 @@ static void __init spear320_clk_init(void __iomem *soc_config_base)
379 clk_register_clkdev(clk, NULL, "60100000.serial"); 384 clk_register_clkdev(clk, NULL, "60100000.serial");
380} 385}
381#else 386#else
382static inline void spear320_clk_init(void __iomem *soc_config_base) { } 387static inline void spear320_clk_init(void __iomem *sb, struct clk *rc) { }
383#endif 388#endif
384 389
385void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base) 390void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base)
386{ 391{
387 struct clk *clk, *clk1; 392 struct clk *clk, *clk1, *ras_apb_clk;
388 393
389 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 394 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
390 32000); 395 32000);
@@ -613,6 +618,7 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
613 clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB, 618 clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB,
614 RAS_APB_CLK_ENB, 0, &_lock); 619 RAS_APB_CLK_ENB, 0, &_lock);
615 clk_register_clkdev(clk, "ras_apb_clk", NULL); 620 clk_register_clkdev(clk, "ras_apb_clk", NULL);
621 ras_apb_clk = clk;
616 622
617 clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0, 623 clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0,
618 RAS_CLK_ENB, RAS_32K_CLK_ENB, 0, &_lock); 624 RAS_CLK_ENB, RAS_32K_CLK_ENB, 0, &_lock);
@@ -659,5 +665,5 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
659 else if (of_machine_is_compatible("st,spear310")) 665 else if (of_machine_is_compatible("st,spear310"))
660 spear310_clk_init(); 666 spear310_clk_init();
661 else if (of_machine_is_compatible("st,spear320")) 667 else if (of_machine_is_compatible("st,spear320"))
662 spear320_clk_init(soc_config_base); 668 spear320_clk_init(soc_config_base, ras_apb_clk);
663} 669}