clk: qcom: Add support for MSM8660's global clock controller (GCC)

Add a driver for the global clock controller found on MSM8660
based platforms. This should allow most non-multimedia device
drivers to probe and control their clocks.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>

3 files changed, 2828 insertions, 0 deletions

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 7b582dd5cd08..995bcfa021a4 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -4,6 +4,14 @@ config COMMON_CLK_QCOM
         select REGMAP_MMIO
         select RESET_CONTROLLER
 
+config MSM_GCC_8660
+        tristate "MSM8660 Global Clock Controller"
+        depends on COMMON_CLK_QCOM
+        help
+          Support for the global clock controller on msm8660 devices.
+          Say Y if you want to use peripheral devices such as UART, SPI,
+          i2c, USB, SD/eMMC, etc.
+
 config MSM_GCC_8960
         tristate "MSM8960 Global Clock Controller"
         depends on COMMON_CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index e00cb848a1ae..190d38433202 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -7,6 +7,7 @@ clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-rcg2.o
 clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-branch.o
 clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += reset.o
 
+obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
 obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
 obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
 obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm8660.c
new file mode 100644
index 000000000000..bc0b7f1fcfbe
--- /dev/null
+++ b/drivers/clk/qcom/gcc-msm8660.c
@@ -0,0 +1,2819 @@
+/*
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/clock/qcom,gcc-msm8660.h>
+#include <dt-bindings/reset/qcom,gcc-msm8660.h>
+
+#include "clk-regmap.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "reset.h"
+
+static struct clk_pll pll8 = {
+        .l_reg = 0x3144,
+        .m_reg = 0x3148,
+        .n_reg = 0x314c,
+        .config_reg = 0x3154,
+        .mode_reg = 0x3140,
+        .status_reg = 0x3158,
+        .status_bit = 16,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "pll8",
+                .parent_names = (const char *[]){ "pxo" },
+                .num_parents = 1,
+                .ops = &clk_pll_ops,
+        },
+};
+
+static struct clk_regmap pll8_vote = {
+        .enable_reg = 0x34c0,
+        .enable_mask = BIT(8),
+        .hw.init = &(struct clk_init_data){
+                .name = "pll8_vote",
+                .parent_names = (const char *[]){ "pll8" },
+                .num_parents = 1,
+                .ops = &clk_pll_vote_ops,
+        },
+};
+
+#define P_PXO   0
+#define P_PLL8  1
+#define P_CXO   2
+
+static const u8 gcc_pxo_pll8_map[] = {
+        [P_PXO]         = 0,
+        [P_PLL8]        = 3,
+};
+
+static const char *gcc_pxo_pll8[] = {
+        "pxo",
+        "pll8_vote",
+};
+
+static const u8 gcc_pxo_pll8_cxo_map[] = {
+        [P_PXO]         = 0,
+        [P_PLL8]        = 3,
+        [P_CXO]         = 5,
+};
+
+static const char *gcc_pxo_pll8_cxo[] = {
+        "pxo",
+        "pll8_vote",
+        "cxo",
+};
+
+static struct freq_tbl clk_tbl_gsbi_uart[] = {
+        {  1843200, P_PLL8, 2,  6, 625 },
+        {  3686400, P_PLL8, 2, 12, 625 },
+        {  7372800, P_PLL8, 2, 24, 625 },
+        { 14745600, P_PLL8, 2, 48, 625 },
+        { 16000000, P_PLL8, 4,  1,   6 },
+        { 24000000, P_PLL8, 4,  1,   4 },
+        { 32000000, P_PLL8, 4,  1,   3 },
+        { 40000000, P_PLL8, 1,  5,  48 },
+        { 46400000, P_PLL8, 1, 29, 240 },
+        { 48000000, P_PLL8, 4,  1,   2 },
+        { 51200000, P_PLL8, 1,  2,  15 },
+        { 56000000, P_PLL8, 1,  7,  48 },
+        { 58982400, P_PLL8, 1, 96, 625 },
+        { 64000000, P_PLL8, 2,  1,   3 },
+        { }
+};
+
+static struct clk_rcg gsbi1_uart_src = {
+        .ns_reg = 0x29d4,
+        .md_reg = 0x29d0,
+        .mn = {
+                .mnctr_en_bit = 8,
+                .mnctr_reset_bit = 7,
+                .mnctr_mode_shift = 5,
+                .n_val_shift = 16,
+                .m_val_shift = 16,
+                .width = 16,
+        },
+        .p = {
+                .pre_div_shift = 3,
+                .pre_div_width = 2,
+        },
+        .s = {
+                .src_sel_shift = 0,
+                .parent_map = gcc_pxo_pll8_map,
+        },
+        .freq_tbl = clk_tbl_gsbi_uart,
+        .clkr = {
+                .enable_reg = 0x29d4,
+                .enable_mask = BIT(11),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gsbi1_uart_src",
+                        .parent_names = gcc_pxo_pll8,
+                        .num_parents = 2,
+                        .ops = &clk_rcg_ops,
+                        .flags = CLK_SET_PARENT_GATE,
+                },
+        },
+};
+
+static struct clk_branch gsbi1_uart_clk = {
+        .halt_reg = 0x2fcc,
+        .halt_bit = 10,
+        .clkr = {
+                .enable_reg = 0x29d4,
+                .enable_mask = BIT(9),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gsbi1_uart_clk",
+                        .parent_names = (const char *[]){
+                                "gsbi1_uart_src",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_branch_ops,
+                        .flags = CLK_SET_RATE_PARENT,
+                },
+        },
+};
+
+static struct clk_rcg gsbi2_uart_src = {
+        .ns_reg = 0x29f4,
+        .md_reg = 0x29f0,
+        .mn = {
+                .mnctr_en_bit = 8,