diff options
author | Olof Johansson <olof@lixom.net> | 2013-12-26 13:33:05 -0500 |
---|---|---|
committer | Olof Johansson <olof@lixom.net> | 2013-12-26 13:33:05 -0500 |
commit | e7d248f0e0f93b86c56466ede82c46234f622615 (patch) | |
tree | 36adb8e2ff0b4cc570334372389f82a73e352002 /drivers/clk/tegra/clk-periph.c | |
parent | 1c7af42fe579b5cf8c942319cbed38801305dda4 (diff) | |
parent | 8a0a1af30cbf56b41220a02e34835022c4d72f41 (diff) |
Merge tag 'tegra-for-3.14-dmas-resets-rework' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/cleanup
From Stephen Warren:
ARM: tegra: implement common DMA and resets DT bindings
This series converts the Tegra DTs and drivers to use the common/
standard DMA and reset bindings, rather than custom bindings. It also
adds complete documentation for the Tegra clock bindings without
actually changing any binding definitions.
This conversion relies on a few sets of patches in branches from outside
the Tegra tree:
1) A patch to add an DMA channel request API which allows deferred probe
to be implemented.
2) A patch to implement a common part of the of_xlate function for DMA
controllers.
3) Some ASoC patches (which in turn rely on (1) above), which support
deferred probe during DMA channel allocation.
4) The Tegra clock driver changes for 3.14.
Consequently, this branch is based on a merge of all of those external
branches.
In turn, this branch is or will be pulled into a few places that either
rely on features introduced here, or would otherwise conflict with the
patches:
a) Tegra's own for-3.14/powergate and for-4.14/dt branches, to avoid
conflicts.
b) The DRM tree, which introduces new code that relies on the reset
controller framework introduced in this branch, and to avoid
conflicts.
* tag 'tegra-for-3.14-dmas-resets-rework' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (30 commits)
spi: tegra: checking for ERR_PTR instead of NULL
ASoC: tegra: update module reset list for Tegra124
clk: tegra: remove bogus PCIE_XCLK
clk: tegra: remove legacy reset APIs
ARM: tegra: remove legacy DMA entries from DT
ARM: tegra: remove legacy clock entries from DT
USB: EHCI: tegra: use reset framework
Input: tegra-kbc - use reset framework
serial: tegra: convert to standard DMA DT bindings
serial: tegra: use reset framework
spi: tegra: convert to standard DMA DT bindings
spi: tegra: use reset framework
staging: nvec: use reset framework
i2c: tegra: use reset framework
ASoC: tegra: convert to standard DMA DT bindings
ASoC: tegra: allocate AHUB FIFO during probe() not startup()
ASoC: tegra: call pm_runtime APIs around register accesses
ASoC: tegra: use reset framework
dma: tegra: register as an OF DMA controller
dma: tegra: use reset framework
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'drivers/clk/tegra/clk-periph.c')
-rw-r--r-- | drivers/clk/tegra/clk-periph.c | 40 |
1 files changed, 0 insertions, 40 deletions
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c index d62b396863c1..c534043c0481 100644 --- a/drivers/clk/tegra/clk-periph.c +++ b/drivers/clk/tegra/clk-periph.c | |||
@@ -111,46 +111,6 @@ static void clk_periph_disable(struct clk_hw *hw) | |||
111 | gate_ops->disable(gate_hw); | 111 | gate_ops->disable(gate_hw); |
112 | } | 112 | } |
113 | 113 | ||
114 | void tegra_periph_reset_deassert(struct clk *c) | ||
115 | { | ||
116 | struct clk_hw *hw = __clk_get_hw(c); | ||
117 | struct tegra_clk_periph *periph = to_clk_periph(hw); | ||
118 | struct tegra_clk_periph_gate *gate; | ||
119 | |||
120 | if (periph->magic != TEGRA_CLK_PERIPH_MAGIC) { | ||
121 | gate = to_clk_periph_gate(hw); | ||
122 | if (gate->magic != TEGRA_CLK_PERIPH_GATE_MAGIC) { | ||
123 | WARN_ON(1); | ||
124 | return; | ||
125 | } | ||
126 | } else { | ||
127 | gate = &periph->gate; | ||
128 | } | ||
129 | |||
130 | tegra_periph_reset(gate, 0); | ||
131 | } | ||
132 | EXPORT_SYMBOL(tegra_periph_reset_deassert); | ||
133 | |||
134 | void tegra_periph_reset_assert(struct clk *c) | ||
135 | { | ||
136 | struct clk_hw *hw = __clk_get_hw(c); | ||
137 | struct tegra_clk_periph *periph = to_clk_periph(hw); | ||
138 | struct tegra_clk_periph_gate *gate; | ||
139 | |||
140 | if (periph->magic != TEGRA_CLK_PERIPH_MAGIC) { | ||
141 | gate = to_clk_periph_gate(hw); | ||
142 | if (gate->magic != TEGRA_CLK_PERIPH_GATE_MAGIC) { | ||
143 | WARN_ON(1); | ||
144 | return; | ||
145 | } | ||
146 | } else { | ||
147 | gate = &periph->gate; | ||
148 | } | ||
149 | |||
150 | tegra_periph_reset(gate, 1); | ||
151 | } | ||
152 | EXPORT_SYMBOL(tegra_periph_reset_assert); | ||
153 | |||
154 | const struct clk_ops tegra_clk_periph_ops = { | 114 | const struct clk_ops tegra_clk_periph_ops = { |
155 | .get_parent = clk_periph_get_parent, | 115 | .get_parent = clk_periph_get_parent, |
156 | .set_parent = clk_periph_set_parent, | 116 | .set_parent = clk_periph_set_parent, |