Merge tag 'tegra-for-3.14-dmas-resets-rework' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/cleanup

From Stephen Warren:
ARM: tegra: implement common DMA and resets DT bindings

This series converts the Tegra DTs and drivers to use the common/
standard DMA and reset bindings, rather than custom bindings. It also
adds complete documentation for the Tegra clock bindings without
actually changing any binding definitions.

This conversion relies on a few sets of patches in branches from outside
the Tegra tree:

1) A patch to add an DMA channel request API which allows deferred probe
   to be implemented.

2) A patch to implement a common part of the of_xlate function for DMA
   controllers.

3) Some ASoC patches (which in turn rely on (1) above), which support
   deferred probe during DMA channel allocation.

4) The Tegra clock driver changes for 3.14.

Consequently, this branch is based on a merge of all of those external
branches.

In turn, this branch is or will be pulled into a few places that either
rely on features introduced here, or would otherwise conflict with the
patches:

a) Tegra's own for-3.14/powergate and for-4.14/dt branches, to avoid
   conflicts.

b) The DRM tree, which introduces new code that relies on the reset
   controller framework introduced in this branch, and to avoid
   conflicts.

* tag 'tegra-for-3.14-dmas-resets-rework' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (30 commits)
  spi: tegra: checking for ERR_PTR instead of NULL
  ASoC: tegra: update module reset list for Tegra124
  clk: tegra: remove bogus PCIE_XCLK
  clk: tegra: remove legacy reset APIs
  ARM: tegra: remove legacy DMA entries from DT
  ARM: tegra: remove legacy clock entries from DT
  USB: EHCI: tegra: use reset framework
  Input: tegra-kbc - use reset framework
  serial: tegra: convert to standard DMA DT bindings
  serial: tegra: use reset framework
  spi: tegra: convert to standard DMA DT bindings
  spi: tegra: use reset framework
  staging: nvec: use reset framework
  i2c: tegra: use reset framework
  ASoC: tegra: convert to standard DMA DT bindings
  ASoC: tegra: allocate AHUB FIFO during probe() not startup()
  ASoC: tegra: call pm_runtime APIs around register accesses
  ASoC: tegra: use reset framework
  dma: tegra: register as an OF DMA controller
  dma: tegra: use reset framework
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>

8 files changed, 57 insertions, 82 deletions

diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
index f38f33e3c65d..507015314827 100644
--- a/drivers/clk/tegra/clk-periph-gate.c
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -36,8 +36,6 @@ static DEFINE_SPINLOCK(periph_ref_lock);
 
 #define read_rst(gate) \
         readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
-#define write_rst_set(val, gate) \
-        writel_relaxed(val, gate->clk_base + (gate->regs->rst_set_reg))
 #define write_rst_clr(val, gate) \
         writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
 
@@ -123,26 +121,6 @@ static void clk_periph_disable(struct clk_hw *hw)
         spin_unlock_irqrestore(&periph_ref_lock, flags);
 }
 
-void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert)
-{
-        if (gate->flags & TEGRA_PERIPH_NO_RESET)
-                return;
-
-        if (assert) {
-                /*
-                 * If peripheral is in the APB bus then read the APB bus to
-                 * flush the write operation in apb bus. This will avoid the
-                 * peripheral access after disabling clock
-                 */
-                if (gate->flags & TEGRA_PERIPH_ON_APB)
-                        tegra_read_chipid();
-
-                write_rst_set(periph_clk_to_bit(gate), gate);
-        } else {
-                write_rst_clr(periph_clk_to_bit(gate), gate);
-        }
-}
-
 const struct clk_ops tegra_clk_periph_gate_ops = {
         .is_enabled = clk_periph_is_enabled,
         .enable = clk_periph_enable,
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index d62b396863c1..c534043c0481 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -111,46 +111,6 @@ static void clk_periph_disable(struct clk_hw *hw)
         gate_ops->disable(gate_hw);
 }
 
-void tegra_periph_reset_deassert(struct clk *c)
-{
-        struct clk_hw *hw = __clk_get_hw(c);
-        struct tegra_clk_periph *periph = to_clk_periph(hw);
-        struct tegra_clk_periph_gate *gate;
-
-        if (periph->magic != TEGRA_CLK_PERIPH_MAGIC) {
-                gate = to_clk_periph_gate(hw);
-                if (gate->magic != TEGRA_CLK_PERIPH_GATE_MAGIC) {
-                        WARN_ON(1);
-                        return;
-                }
-        } else {
-                gate = &periph->gate;
-        }
-
-        tegra_periph_reset(gate, 0);
-}
-EXPORT_SYMBOL(tegra_periph_reset_deassert);
-
-void tegra_periph_reset_assert(struct clk *c)
-{
-        struct clk_hw *hw = __clk_get_hw(c);
-        struct tegra_clk_periph *periph = to_clk_periph(hw);
-        struct tegra_clk_periph_gate *gate;
-
-        if (periph->magic != TEGRA_CLK_PERIPH_MAGIC) {
-                gate = to_clk_periph_gate(hw);
-                if (gate->magic != TEGRA_CLK_PERIPH_GATE_MAGIC) {
-                        WARN_ON(1);
-                        return;
-                }
-        } else {
-                gate = &periph->gate;
-        }
-
-        tegra_periph_reset(gate, 1);
-}
-EXPORT_SYMBOL(tegra_periph_reset_assert);
-
 const struct clk_ops tegra_clk_periph_ops = {
         .get_parent = clk_periph_get_parent,
         .set_parent = clk_periph_set_parent,
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 29b912582e3d..90d9d25f2228 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1460,7 +1460,8 @@ static void __init tegra114_clock_init(struct device_node *np)
                 return;
         }
 
-        clks = tegra_clk_init(TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_PERIPH_BANKS);
+        clks = tegra_clk_init(clk_base, TEGRA114_CLK_CLK_MAX,
+                                TEGRA114_CLK_PERIPH_BANKS);
         if (!clks)
                 return;
 
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 0ef4485e9b0a..aff86b5bc745 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1398,7 +1398,7 @@ static void __init tegra124_clock_init(struct device_node *np)
                 return;
         }
 
-        clks = tegra_clk_init(TEGRA124_CLK_CLK_MAX, 6);
+        clks = tegra_clk_init(clk_base, TEGRA124_CLK_CLK_MAX, 6);
         if (!clks)
                 return;
 
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index b3b7204acfe7..dbace152b2fa 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -468,7 +468,6 @@ static struct tegra_devclk devclks[] __initdata = {
         { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_ISP },
         { .con_id = "pex", .dt_id = TEGRA20_CLK_PEX },
         { .con_id = "afi", .dt_id = TEGRA20_CLK_AFI },
-        { .con_id = "pcie_xclk", .dt_id = TEGRA20_CLK_PCIE_XCLK },
         { .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 },
         { .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 },
         { .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K },
@@ -834,11 +833,6 @@ static void __init tegra20_periph_clk_init(void)
                                     periph_clk_enb_refcnt);
         clks[TEGRA20_CLK_PEX] = clk;
 
-        /* pcie_xclk */
-        clk = tegra_clk_register_periph_gate("pcie_xclk", "clk_m", 0, clk_base,
-                                    0, 74, periph_clk_enb_refcnt);
-        clks[TEGRA20_CLK_PCIE_XCLK] = clk;
-
         /* cdev1 */
         clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT,
                                       26000000);
@@ -1109,7 +1103,8 @@ static void __init tegra20_clock_init(struct device_node *np)
                 BUG();
         }
 
-        clks = tegra_clk_init(TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_PERIPH_BANKS);
+        clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX,
+                                TEGRA20_CLK_PERIPH_BANKS);
         if (!clks)
                 return;
 
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index dcb6843b3a89..8b10c38b6e3c 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -649,7 +649,6 @@ static struct tegra_devclk devclks[] __initdata = {
         { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_ISP },
         { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },
         { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },
-        { .con_id = "pciex", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIEX },
         { .con_id = "fuse", .dt_id = TEGRA30_CLK_FUSE },
         { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
         { .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },
@@ -1150,11 +1149,6 @@ static void __init tegra30_periph_clk_init(void)
                                     periph_clk_enb_refcnt);
         clks[TEGRA30_CLK_AFI] = clk;
 
-        /* pciex */
-        clk = tegra_clk_register_periph_gate("pciex", "pll_e", 0, clk_base, 0,
-                                    74, periph_clk_enb_refcnt);
-        clks[TEGRA30_CLK_PCIEX] = clk;
-
         /* emc */
         clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
                                ARRAY_SIZE(mux_pllmcp_clkm),
@@ -1395,7 +1389,6 @@ static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
         TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "nvavp", "bsea"),
         TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL),
         TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"),
-        TEGRA_CLK_DUPLICATE(TEGRA30_CLK_PCIEX, "tegra_pcie", "pciex"),
         TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"),
         TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL), /* MUST be the last entry */
 };
@@ -1427,7 +1420,8 @@ static void __init tegra30_clock_init(struct device_node *np)
                 BUG();
         }
 
-        clks = tegra_clk_init(TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_PERIPH_BANKS);
+        clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX,
+                                TEGRA30_CLK_PERIPH_BANKS);
         if (!clks)
                 return;
 
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index a12a5f5107ec..c0a7d7723510 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -18,6 +18,8 @@
 #include <linux/clk-provider.h>
 #include <linux/of.h>
 #include <linux/clk/tegra.h>
+#include <linux/reset-controller.h>
+#include <linux/tegra-soc.h>
 
 #include "clk.h"
 
@@ -121,6 +123,35 @@ static struct tegra_clk_periph_regs periph_regs[] = {
         },
 };
 
+static void __iomem *clk_base;
+
+static int tegra_clk_rst_assert(struct reset_controller_dev *rcdev,
+                unsigned long id)
+{
+        /*
+         * If peripheral is on the APB bus then we must read the APB bus to
+         * flush the write operation in apb bus. This will avoid peripheral
+         * access after disabling clock. Since the reset driver has no
+         * knowledge of which reset IDs represent which devices, simply do
+         * this all the time.
+         */
+        tegra_read_chipid();
+
+        writel_relaxed(BIT(id % 32),
+                        clk_base + periph_regs[id / 32].rst_set_reg);
+
+        return 0;
+}
+
+static int tegra_clk_rst_deassert(struct reset_controller_dev *rcdev,
+                unsigned long id)
+{
+        writel_relaxed(BIT(id % 32),
+                        clk_base + periph_regs[id / 32].rst_clr_reg);
+
+        return 0;
+}
+
 struct tegra_clk_periph_regs *get_reg_bank(int clkid)
 {
         int reg_bank = clkid / 32;
@@ -133,8 +164,10 @@ struct tegra_clk_periph_regs *get_reg_bank(int clkid)
         }
 }
 
-struct clk ** __init tegra_clk_init(int num, int banks)
+struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks)
 {
+        clk_base = regs;
+
         if (WARN_ON(banks > ARRAY_SIZE(periph_regs)))
                 return NULL;
 
@@ -203,6 +236,17 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
         }
 }
 
+static struct reset_control_ops rst_ops = {
+        .assert = tegra_clk_rst_assert,
+        .deassert = tegra_clk_rst_deassert,
+};
+
+static struct reset_controller_dev rst_ctlr = {
+        .ops = &rst_ops,
+        .owner = THIS_MODULE,
+        .of_reset_n_cells = 1,
+};
+
 void __init tegra_add_of_provider(struct device_node *np)
 {
         int i;
@@ -220,6 +264,10 @@ void __init tegra_add_of_provider(struct device_node *np)
         clk_data.clks = clks;
         clk_data.clk_num = clk_num;
         of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
+        rst_ctlr.of_node = np;
+        rst_ctlr.nr_resets = clk_num * 32;
+        reset_controller_register(&rst_ctlr);
 }
 
 void __init tegra_register_devclks(struct tegra_devclk *dev_clks, int num)
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 40fb011233c0..16ec8d6bb87f 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -393,7 +393,6 @@ struct tegra_clk_periph_gate {
 #define TEGRA_PERIPH_NO_DIV BIT(4)
 #define TEGRA_PERIPH_NO_GATE BIT(5)
 
-void tegra_periph_reset(struct tegra_clk_periph_gate *gate, bool assert);
 extern const struct clk_ops tegra_clk_periph_gate_ops;
 struct clk *tegra_clk_register_periph_gate(const char *name,
                 const char *parent_name, u8 gate_flags, void __iomem *clk_base,
@@ -597,7 +596,7 @@ void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
                 struct clk *clks[], int clk_max);
 
 struct tegra_clk_periph_regs *get_reg_bank(int clkid);
-struct clk **tegra_clk_init(int num, int periph_banks);
+struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks);
 
 struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk);