Merge tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux

Pull clock framework updates from Mike Turquette:
 "The clock framework changes for 3.17 are mostly additions of new clock
  drivers and fixes/enhancements to existing clock drivers.  There are
  also some non-critical fixes and improvements to the framework core.

  Changes to the clock framework core include:
   - improvements to printks on errors
   - flattening the previously hierarchal structure of per-clock entries
     in debugfs
   - allow per-clock debugfs entries that are specific to a particular
     clock driver
   - configure initial clock parent and/or initial clock rate from
     Device Tree
   - several feature enhancements to the composite clock type
   - misc fixes

  New clock drivers added include:
   - TI Palmas PMIC
   - Allwinner A23 SoC
   - Qualcomm APQ8084 and IPQ8064 SoCs
   - Rockchip rk3188, rk3066 and rk3288 SoCs
   - STMicroelectronics STiH407 SoC
   - Cirrus Logic CLPS711X SoC

  Many fixes, feature enhancements and further clock tree support for
  existing clock drivers also were merged, such as Samsung's "ARMCLK
  down" power saving feature for their Exynos4 & Exynos5 SoCs"

* tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
  clk: Add missing of_clk_set_defaults export
  clk: checking wrong variable in __set_clk_parents()
  clk: Propagate any error return from debug_init()
  clk: clps711x: Add DT bindings documentation
  clk: Add CLPS711X clk driver
  clk: st: Use round to closest divider flag
  clk: st: Update frequency tables for fs660c32 and fs432c65
  clk: st: STiH407: Support for clockgenA9
  clk: st: STiH407: Support for clockgenD0/D2/D3
  clk: st: STiH407: Support for clockgenC0
  clk: st: Add quadfs reset handling
  clk: st: Add polarity bit indication
  clk: st: STiH407: Support for clockgenA0
  clk: st: STiH407: Support for A9 MUX Clocks
  clk: st: STiH407: Support for Flexgen Clocks
  clk: st: Adds Flexgen clock binding
  clk: st: Remove uncessary (void *) cast
  clk: st: use static const for clkgen_pll_data tables
  clk: st: use static const for stm_fs tables
  clk: st: Update ST clock binding documentation
  ...

1 files changed, 3 insertions, 3 deletions

diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index 65894f7687ed..4daa5977793a 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -742,19 +742,19 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
         clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
                         0, &_lock);
-        clk_register_clkdev(clk, NULL, "dw_pcie.0");
+        clk_register_clkdev(clk, NULL, "b1000000.pcie");
         clk_register_clkdev(clk, NULL, "b1000000.ahci");
 
         clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
                         0, &_lock);
-        clk_register_clkdev(clk, NULL, "dw_pcie.1");
+        clk_register_clkdev(clk, NULL, "b1800000.pcie");
         clk_register_clkdev(clk, NULL, "b1800000.ahci");
 
         clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
                         SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
                         0, &_lock);
-        clk_register_clkdev(clk, NULL, "dw_pcie.2");
+        clk_register_clkdev(clk, NULL, "b4000000.pcie");
         clk_register_clkdev(clk, NULL, "b4000000.ahci");
 
         clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,