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-rw-r--r--Documentation/devicetree/bindings/arm/samsung/pmu.txt30
-rw-r--r--Documentation/devicetree/bindings/clock/clk-palmas-clk32kg-clocks.txt35
-rw-r--r--Documentation/devicetree/bindings/clock/clock-bindings.txt36
-rw-r--r--Documentation/devicetree/bindings/clock/clps711x-clock.txt19
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc.txt2
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,mmcc.txt2
-rw-r--r--Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt61
-rw-r--r--Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt61
-rw-r--r--Documentation/devicetree/bindings/clock/rockchip.txt3
-rw-r--r--Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt28
-rw-r--r--Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt6
-rw-r--r--Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt17
-rw-r--r--Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt8
-rw-r--r--Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt34
-rw-r--r--Documentation/devicetree/bindings/clock/st/st,clkgen.txt59
-rw-r--r--Documentation/devicetree/bindings/clock/st/st,flexgen.txt119
-rw-r--r--Documentation/devicetree/bindings/clock/st/st,quadfs.txt15
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi.txt7
-rw-r--r--MAINTAINERS7
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi10
-rw-r--r--arch/arm/boot/dts/exynos4x12.dtsi7
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi3
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi3
-rw-r--r--arch/arm/mach-rockchip/Kconfig1
-rw-r--r--drivers/base/platform.c5
-rw-r--r--drivers/clk/Kconfig7
-rw-r--r--drivers/clk/Makefile5
-rw-r--r--drivers/clk/at91/clk-main.c1
-rw-r--r--drivers/clk/clk-clps711x.c192
-rw-r--r--drivers/clk/clk-composite.c79
-rw-r--r--drivers/clk/clk-conf.c144
-rw-r--r--drivers/clk/clk-palmas.c307
-rw-r--r--drivers/clk/clk-ppc-corenet.c2
-rw-r--r--drivers/clk/clk-s2mps11.c33
-rw-r--r--drivers/clk/clk.c134
-rw-r--r--drivers/clk/clkdev.c5
-rw-r--r--drivers/clk/qcom/Kconfig25
-rw-r--r--drivers/clk/qcom/Makefile3
-rw-r--r--drivers/clk/qcom/clk-pll.c15
-rw-r--r--drivers/clk/qcom/clk-pll.h2
-rw-r--r--drivers/clk/qcom/clk-rcg.c51
-rw-r--r--drivers/clk/qcom/clk-rcg.h1
-rw-r--r--drivers/clk/qcom/common.c39
-rw-r--r--drivers/clk/qcom/common.h6
-rw-r--r--drivers/clk/qcom/gcc-apq8084.c3611
-rw-r--r--drivers/clk/qcom/gcc-ipq806x.c2424
-rw-r--r--drivers/clk/qcom/gcc-msm8960.c583
-rw-r--r--drivers/clk/qcom/mmcc-apq8084.c3352
-rw-r--r--drivers/clk/qcom/mmcc-msm8960.c526
-rw-r--r--drivers/clk/qcom/mmcc-msm8974.c10
-rw-r--r--drivers/clk/rockchip/Makefile6
-rw-r--r--drivers/clk/rockchip/clk-pll.c431
-rw-r--r--drivers/clk/rockchip/clk-rk3188.c672
-rw-r--r--drivers/clk/rockchip/clk-rk3288.c717
-rw-r--r--drivers/clk/rockchip/clk.c244
-rw-r--r--drivers/clk/rockchip/clk.h347
-rw-r--r--drivers/clk/rockchip/softrst.c118
-rw-r--r--drivers/clk/samsung/Makefile1
-rw-r--r--drivers/clk/samsung/clk-exynos-clkout.c153
-rw-r--r--drivers/clk/samsung/clk-exynos3250.c43
-rw-r--r--drivers/clk/samsung/clk-exynos4.c231
-rw-r--r--drivers/clk/samsung/clk-exynos5250.c4
-rw-r--r--drivers/clk/samsung/clk-exynos5260.c2
-rw-r--r--drivers/clk/samsung/clk-exynos5410.c2
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c61
-rw-r--r--drivers/clk/samsung/clk-exynos5440.c4
-rw-r--r--drivers/clk/samsung/clk-s3c2410.c2
-rw-r--r--drivers/clk/samsung/clk-s3c2412.c2
-rw-r--r--drivers/clk/samsung/clk-s3c2443.c2
-rw-r--r--drivers/clk/samsung/clk-s3c64xx.c2
-rw-r--r--drivers/clk/samsung/clk.c21
-rw-r--r--drivers/clk/samsung/clk.h4
-rw-r--r--drivers/clk/spear/spear1310_clock.c6
-rw-r--r--drivers/clk/spear/spear1340_clock.c2
-rw-r--r--drivers/clk/st/Makefile2
-rw-r--r--drivers/clk/st/clk-flexgen.c331
-rw-r--r--drivers/clk/st/clkgen-fsyn.c223
-rw-r--r--drivers/clk/st/clkgen-mux.c12
-rw-r--r--drivers/clk/st/clkgen-pll.c94
-rw-r--r--drivers/clk/sunxi/Makefile4
-rw-r--r--drivers/clk/sunxi/clk-a20-gmac.c2
-rw-r--r--drivers/clk/sunxi/clk-factors.c2
-rw-r--r--drivers/clk/sunxi/clk-factors.h1
-rw-r--r--drivers/clk/sunxi/clk-sun6i-apb0-gates.c76
-rw-r--r--drivers/clk/sunxi/clk-sun6i-apb0.c2
-rw-r--r--drivers/clk/sunxi/clk-sun6i-ar100.c4
-rw-r--r--drivers/clk/sunxi/clk-sun8i-apb0.c68
-rw-r--r--drivers/clk/sunxi/clk-sunxi.c129
-rw-r--r--drivers/clk/tegra/clk-pll.c19
-rw-r--r--drivers/clk/tegra/clk-tegra-periph.c4
-rw-r--r--drivers/clk/tegra/clk-tegra114.c31
-rw-r--r--drivers/clk/tegra/clk-tegra124.c10
-rw-r--r--drivers/clk/tegra/clk.c6
-rw-r--r--drivers/clk/ti/clk-7xx.c11
-rw-r--r--drivers/i2c/i2c-core.c5
-rw-r--r--drivers/spi/spi.c5
-rw-r--r--include/dt-bindings/clock/clps711x-clock.h27
-rw-r--r--include/dt-bindings/clock/exynos4.h25
-rw-r--r--include/dt-bindings/clock/exynos5250.h2
-rw-r--r--include/dt-bindings/clock/exynos5420.h2
-rw-r--r--include/dt-bindings/clock/exynos5440.h2
-rw-r--r--include/dt-bindings/clock/qcom,gcc-apq8084.h351
-rw-r--r--include/dt-bindings/clock/qcom,gcc-ipq806x.h293
-rw-r--r--include/dt-bindings/clock/qcom,gcc-msm8960.h11
-rw-r--r--include/dt-bindings/clock/qcom,mmcc-apq8084.h183
-rw-r--r--include/dt-bindings/clock/qcom,mmcc-msm8960.h8
-rw-r--r--include/dt-bindings/clock/rk3066a-cru.h35
-rw-r--r--include/dt-bindings/clock/rk3188-cru-common.h249
-rw-r--r--include/dt-bindings/clock/rk3188-cru.h51
-rw-r--r--include/dt-bindings/clock/rk3288-cru.h278
-rw-r--r--include/dt-bindings/mfd/palmas.h18
-rw-r--r--include/dt-bindings/reset/qcom,gcc-apq8084.h109
-rw-r--r--include/dt-bindings/reset/qcom,gcc-ipq806x.h132
-rw-r--r--include/dt-bindings/reset/qcom,gcc-msm8960.h16
-rw-r--r--include/dt-bindings/reset/qcom,mmcc-apq8084.h64
-rw-r--r--include/dt-bindings/reset/qcom,mmcc-msm8960.h8
-rw-r--r--include/linux/clk-provider.h5
-rw-r--r--include/linux/clk/clk-conf.h20
118 files changed, 17745 insertions, 397 deletions
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 2a4ab046a8a1..f9865e77e0b0 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -12,8 +12,38 @@ Properties:
12 12
13 - reg : offset and length of the register set. 13 - reg : offset and length of the register set.
14 14
15 - #clock-cells : must be <1>, since PMU requires once cell as clock specifier.
16 The single specifier cell is used as index to list of clocks
17 provided by PMU, which is currently:
18 0 : SoC clock output (CLKOUT pin)
19
20 - clock-names : list of clock names for particular CLKOUT mux inputs in
21 following format:
22 "clkoutN", where N is a decimal number corresponding to
23 CLKOUT mux control bits value for given input, e.g.
24 "clkout0", "clkout7", "clkout15".
25
26 - clocks : list of phandles and specifiers to all input clocks listed in
27 clock-names property.
28
15Example : 29Example :
16pmu_system_controller: system-controller@10040000 { 30pmu_system_controller: system-controller@10040000 {
17 compatible = "samsung,exynos5250-pmu", "syscon"; 31 compatible = "samsung,exynos5250-pmu", "syscon";
18 reg = <0x10040000 0x5000>; 32 reg = <0x10040000 0x5000>;
33 #clock-cells = <1>;
34 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
35 "clkout4", "clkout8", "clkout9";
36 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
37 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
38 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
39 <&clock CLK_XUSBXTI>;
40};
41
42Example of clock consumer :
43
44usb3503: usb3503@08 {
45 /* ... */
46 clock-names = "refclk";
47 clocks = <&pmu_system_controller 0>;
48 /* ... */
19}; 49};
diff --git a/Documentation/devicetree/bindings/clock/clk-palmas-clk32kg-clocks.txt b/Documentation/devicetree/bindings/clock/clk-palmas-clk32kg-clocks.txt
new file mode 100644
index 000000000000..4208886d834a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-palmas-clk32kg-clocks.txt
@@ -0,0 +1,35 @@
1* Palmas 32KHz clocks *
2
3Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO.
4
5This binding uses the common clock binding ./clock-bindings.txt.
6
7Required properties:
8- compatible : "ti,palmas-clk32kg" for clk32kg clock
9 "ti,palmas-clk32kgaudio" for clk32kgaudio clock
10- #clock-cells : shall be set to 0.
11
12Optional property:
13- ti,external-sleep-control: The external enable input pins controlled the
14 enable/disable of clocks. The external enable input pins ENABLE1,
15 ENABLE2 and NSLEEP. The valid values for the external pins are:
16 PALMAS_EXT_CONTROL_PIN_ENABLE1 for ENABLE1 pin
17 PALMAS_EXT_CONTROL_PIN_ENABLE2 for ENABLE2 pin
18 PALMAS_EXT_CONTROL_PIN_NSLEEP for NSLEEP pin
19 Option 0 or missing this property means the clock is enabled/disabled
20 via register access and these pins do not have any control.
21 The macros of external control pins for DTS is defined at
22 dt-bindings/mfd/palmas.h
23
24Example:
25 #include <dt-bindings/mfd/palmas.h>
26 ...
27 palmas: tps65913@58 {
28 ...
29 clk32kg: palmas_clk32k@0 {
30 compatible = "ti,palmas-clk32kg";
31 #clock-cells = <0>;
32 ti,external-sleep-control = <PALMAS_EXT_CONTROL_PIN_NSLEEP>;
33 };
34 ...
35 };
diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt b/Documentation/devicetree/bindings/clock/clock-bindings.txt
index f15787817d6b..06fc6d541c89 100644
--- a/Documentation/devicetree/bindings/clock/clock-bindings.txt
+++ b/Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -131,3 +131,39 @@ clock signal, and a UART.
131 ("pll" and "pll-switched"). 131 ("pll" and "pll-switched").
132* The UART has its baud clock connected the external oscillator and its 132* The UART has its baud clock connected the external oscillator and its
133 register clock connected to the PLL clock (the "pll-switched" signal) 133 register clock connected to the PLL clock (the "pll-switched" signal)
134
135==Assigned clock parents and rates==
136
137Some platforms may require initial configuration of default parent clocks
138and clock frequencies. Such a configuration can be specified in a device tree
139node through assigned-clocks, assigned-clock-parents and assigned-clock-rates
140properties. The assigned-clock-parents property should contain a list of parent
141clocks in form of phandle and clock specifier pairs, the assigned-clock-parents
142property the list of assigned clock frequency values - corresponding to clocks
143listed in the assigned-clocks property.
144
145To skip setting parent or rate of a clock its corresponding entry should be
146set to 0, or can be omitted if it is not followed by any non-zero entry.
147
148 uart@a000 {
149 compatible = "fsl,imx-uart";
150 reg = <0xa000 0x1000>;
151 ...
152 clocks = <&osc 0>, <&pll 1>;
153 clock-names = "baud", "register";
154
155 assigned-clocks = <&clkcon 0>, <&pll 2>;
156 assigned-clock-parents = <&pll 2>;
157 assigned-clock-rates = <0>, <460800>;
158 };
159
160In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and
161the <&pll 2> clock is assigned a frequency value of 460800 Hz.
162
163Configuring a clock's parent and rate through the device node that consumes
164the clock can be done only for clocks that have a single user. Specifying
165conflicting parent or rate configuration in multiple consumer nodes for
166a shared clock is forbidden.
167
168Configuration of common clocks, which affect multiple consumer devices can
169be similarly specified in the clock provider node.
diff --git a/Documentation/devicetree/bindings/clock/clps711x-clock.txt b/Documentation/devicetree/bindings/clock/clps711x-clock.txt
new file mode 100644
index 000000000000..ce5a7476f05d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clps711x-clock.txt
@@ -0,0 +1,19 @@
1* Clock bindings for the Cirrus Logic CLPS711X CPUs
2
3Required properties:
4- compatible : Shall contain "cirrus,clps711x-clk".
5- reg : Address of the internal register set.
6- startup-frequency: Factory set CPU startup frequency in HZ.
7- #clock-cells : Should be <1>.
8
9The clock consumer should specify the desired clock by having the clock
10ID in its "clocks" phandle cell. See include/dt-bindings/clock/clps711x-clock.h
11for the full list of CLPS711X clock IDs.
12
13Example:
14 clks: clks@80000000 {
15 #clock-cells = <1>;
16 compatible = "cirrus,ep7312-clk", "cirrus,clps711x-clk";
17 reg = <0x80000000 0xc000>;
18 startup-frequency = <73728000>;
19 };
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 9cfcb4f2bc97..aba3d254e037 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -5,6 +5,8 @@ Required properties :
5- compatible : shall contain only one of the following: 5- compatible : shall contain only one of the following:
6 6
7 "qcom,gcc-apq8064" 7 "qcom,gcc-apq8064"
8 "qcom,gcc-apq8084"
9 "qcom,gcc-ipq8064"
8 "qcom,gcc-msm8660" 10 "qcom,gcc-msm8660"
9 "qcom,gcc-msm8960" 11 "qcom,gcc-msm8960"
10 "qcom,gcc-msm8974" 12 "qcom,gcc-msm8974"
diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
index d572e9964c54..29ebf84d25af 100644
--- a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
@@ -4,6 +4,8 @@ Qualcomm Multimedia Clock & Reset Controller Binding
4Required properties : 4Required properties :
5- compatible : shall contain only one of the following: 5- compatible : shall contain only one of the following:
6 6
7 "qcom,mmcc-apq8064"
8 "qcom,mmcc-apq8084"
7 "qcom,mmcc-msm8660" 9 "qcom,mmcc-msm8660"
8 "qcom,mmcc-msm8960" 10 "qcom,mmcc-msm8960"
9 "qcom,mmcc-msm8974" 11 "qcom,mmcc-msm8974"
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt
new file mode 100644
index 000000000000..0c2bf5eba43e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt
@@ -0,0 +1,61 @@
1* Rockchip RK3188/RK3066 Clock and Reset Unit
2
3The RK3188/RK3066 clock controller generates and supplies clock to various
4controllers within the SoC and also implements a reset controller for SoC
5peripherals.
6
7Required Properties:
8
9- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
10 "rockchip,rk3066a-cru"
11- reg: physical base address of the controller and length of memory mapped
12 region.
13- #clock-cells: should be 1.
14- #reset-cells: should be 1.
15
16Optional Properties:
17
18- rockchip,grf: phandle to the syscon managing the "general register files"
19 If missing pll rates are not changable, due to the missing pll lock status.
20
21Each clock is assigned an identifier and client nodes can use this identifier
22to specify the clock which they consume. All available clocks are defined as
23preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
24dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
25Similar macros exist for the reset sources in these files.
26
27External clocks:
28
29There are several clocks that are generated outside the SoC. It is expected
30that they are defined using standard clock bindings with following
31clock-output-names:
32 - "xin24m" - crystal input - required,
33 - "xin32k" - rtc clock - optional,
34 - "xin27m" - 27mhz crystal input on rk3066 - optional,
35 - "ext_hsadc" - external HSADC clock - optional,
36 - "ext_cif0" - external camera clock - optional,
37 - "ext_rmii" - external RMII clock - optional,
38 - "ext_jtag" - externalJTAG clock - optional
39
40Example: Clock controller node:
41
42 cru: cru@20000000 {
43 compatible = "rockchip,rk3188-cru";
44 reg = <0x20000000 0x1000>;
45 rockchip,grf = <&grf>;
46
47 #clock-cells = <1>;
48 #reset-cells = <1>;
49 };
50
51Example: UART controller node that consumes the clock generated by the clock
52 controller:
53
54 uart0: serial@10124000 {
55 compatible = "snps,dw-apb-uart";
56 reg = <0x10124000 0x400>;
57 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
58 reg-shift = <2>;
59 reg-io-width = <1>;
60 clocks = <&cru SCLK_UART0>;
61 };
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt
new file mode 100644
index 000000000000..c9fbb76573e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt
@@ -0,0 +1,61 @@
1* Rockchip RK3288 Clock and Reset Unit
2
3The RK3288 clock controller generates and supplies clock to various
4controllers within the SoC and also implements a reset controller for SoC
5peripherals.
6
7Required Properties:
8
9- compatible: should be "rockchip,rk3288-cru"
10- reg: physical base address of the controller and length of memory mapped
11 region.
12- #clock-cells: should be 1.
13- #reset-cells: should be 1.
14
15Optional Properties:
16
17- rockchip,grf: phandle to the syscon managing the "general register files"
18 If missing pll rates are not changable, due to the missing pll lock status.
19
20Each clock is assigned an identifier and client nodes can use this identifier
21to specify the clock which they consume. All available clocks are defined as
22preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
23used in device tree sources. Similar macros exist for the reset sources in
24these files.
25
26External clocks:
27
28There are several clocks that are generated outside the SoC. It is expected
29that they are defined using standard clock bindings with following
30clock-output-names:
31 - "xin24m" - crystal input - required,
32 - "xin32k" - rtc clock - optional,
33 - "ext_i2s" - external I2S clock - optional,
34 - "ext_hsadc" - external HSADC clock - optional,
35 - "ext_edp_24m" - external display port clock - optional,
36 - "ext_vip" - external VIP clock - optional,
37 - "ext_isp" - external ISP clock - optional,
38 - "ext_jtag" - external JTAG clock - optional
39
40Example: Clock controller node:
41
42 cru: cru@20000000 {
43 compatible = "rockchip,rk3188-cru";
44 reg = <0x20000000 0x1000>;
45 rockchip,grf = <&grf>;
46
47 #clock-cells = <1>;
48 #reset-cells = <1>;
49 };
50
51Example: UART controller node that consumes the clock generated by the clock
52 controller:
53
54 uart0: serial@10124000 {
55 compatible = "snps,dw-apb-uart";
56 reg = <0x10124000 0x400>;
57 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
58 reg-shift = <2>;
59 reg-io-width = <1>;
60 clocks = <&cru SCLK_UART0>;
61 };
diff --git a/Documentation/devicetree/bindings/clock/rockchip.txt b/Documentation/devicetree/bindings/clock/rockchip.txt
index a891c823ed44..22f6769e5d4a 100644
--- a/Documentation/devicetree/bindings/clock/rockchip.txt
+++ b/Documentation/devicetree/bindings/clock/rockchip.txt
@@ -6,6 +6,9 @@ This binding uses the common clock binding[1].
6 6
7== Gate clocks == 7== Gate clocks ==
8 8
9These bindings are deprecated!
10Please use the soc specific CRU bindings instead.
11
9The gate registers form a continuos block which makes the dt node 12The gate registers form a continuos block which makes the dt node
10structure a matter of taste, as either all gates can be put into 13structure a matter of taste, as either all gates can be put into
11one gate clock spanning all registers or they can be divided into 14one gate clock spanning all registers or they can be divided into
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
index ae56315fcec5..6247652044a0 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
@@ -24,26 +24,26 @@ Required properties:
24 24
25Example: 25Example:
26 26
27 clockgenA@fd345000 { 27 clockgen-a@fd345000 {
28 reg = <0xfd345000 0xb50>; 28 reg = <0xfd345000 0xb50>;
29 29
30 CLK_M_A1_DIV1: CLK_M_A1_DIV1 { 30 clk_m_a1_div1: clk-m-a1-div1 {
31 #clock-cells = <1>; 31 #clock-cells = <1>;
32 compatible = "st,clkgena-divmux-c32-odf1", 32 compatible = "st,clkgena-divmux-c32-odf1",
33 "st,clkgena-divmux"; 33 "st,clkgena-divmux";
34 34
35 clocks = <&CLK_M_A1_OSC_PREDIV>, 35 clocks = <&clk_m_a1_osc_prediv>,
36 <&CLK_M_A1_PLL0 1>, /* PLL0 PHI1 */ 36 <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
37 <&CLK_M_A1_PLL1 1>; /* PLL1 PHI1 */ 37 <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
38 38
39 clock-output-names = "CLK_M_RX_ICN_TS", 39 clock-output-names = "clk-m-rx-icn-ts",
40 "CLK_M_RX_ICN_VDP_0", 40 "clk-m-rx-icn-vdp-0",
41 "", /* Unused */ 41 "", /* unused */
42 "CLK_M_PRV_T1_BUS", 42 "clk-m-prv-t1-bus",
43 "CLK_M_ICN_REG_12", 43 "clk-m-icn-reg-12",
44 "CLK_M_ICN_REG_10", 44 "clk-m-icn-reg-10",
45 "", /* Unused */ 45 "", /* unused */
46 "CLK_M_ICN_ST231"; 46 "clk-m-icn-st231";
47 }; 47 };
48 }; 48 };
49 49
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
index 943e0808e212..f1fa91c68768 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
@@ -17,7 +17,7 @@ Required properties:
17 "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux" 17 "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux"
18 "st,stih415-clkgen-a9-mux", "st,clkgen-mux" 18 "st,stih415-clkgen-a9-mux", "st,clkgen-mux"
19 "st,stih416-clkgen-a9-mux", "st,clkgen-mux" 19 "st,stih416-clkgen-a9-mux", "st,clkgen-mux"
20 20 "st,stih407-clkgen-a9-mux", "st,clkgen-mux"
21 21
22- #clock-cells : from common clock binding; shall be set to 0. 22- #clock-cells : from common clock binding; shall be set to 0.
23 23
@@ -27,10 +27,10 @@ Required properties:
27 27
28Example: 28Example:
29 29
30 CLK_M_HVA: CLK_M_HVA { 30 clk_m_hva: clk-m-hva@fd690868 {
31 #clock-cells = <0>; 31 #clock-cells = <0>;
32 compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux"; 32 compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
33 reg = <0xfd690868 4>; 33 reg = <0xfd690868 4>;
34 34
35 clocks = <&CLOCKGEN_F 1>, <&CLK_M_A1_DIV0 3>; 35 clocks = <&clockgen_f 1>, <&clk_m_a1_div0 3>;
36 }; 36 };
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
index 81eb3855ab92..efb51cf0c845 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
@@ -19,11 +19,14 @@ Required properties:
19 "st,stih415-plls-c32-ddr", "st,clkgen-plls-c32" 19 "st,stih415-plls-c32-ddr", "st,clkgen-plls-c32"
20 "st,stih416-plls-c32-a9", "st,clkgen-plls-c32" 20 "st,stih416-plls-c32-a9", "st,clkgen-plls-c32"
21 "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32" 21 "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
22 "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
23 "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
24 "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
25 "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
22 26
23 "st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32" 27 "st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
24 "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32" 28 "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
25 29
26
27- #clock-cells : From common clock binding; shall be set to 1. 30- #clock-cells : From common clock binding; shall be set to 1.
28 31
29- clocks : From common clock binding 32- clocks : From common clock binding
@@ -32,17 +35,17 @@ Required properties:
32 35
33Example: 36Example:
34 37
35 clockgenA@fee62000 { 38 clockgen-a@fee62000 {
36 reg = <0xfee62000 0xb48>; 39 reg = <0xfee62000 0xb48>;
37 40
38 CLK_S_A0_PLL: CLK_S_A0_PLL { 41 clk_s_a0_pll: clk-s-a0-pll {
39 #clock-cells = <1>; 42 #clock-cells = <1>;
40 compatible = "st,clkgena-plls-c65"; 43 compatible = "st,clkgena-plls-c65";
41 44
42 clocks = <&CLK_SYSIN>; 45 clocks = <&clk_sysin>;
43 46
44 clock-output-names = "CLK_S_A0_PLL0_HS", 47 clock-output-names = "clk-s-a0-pll0-hs",
45 "CLK_S_A0_PLL0_LS", 48 "clk-s-a0-pll0-ls",
46 "CLK_S_A0_PLL1"; 49 "clk-s-a0-pll1";
47 }; 50 };
48 }; 51 };
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
index 566c9d79ed32..604766c2619e 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
@@ -20,17 +20,17 @@ Required properties:
20 20
21Example: 21Example:
22 22
23 clockgenA@fd345000 { 23 clockgen-a@fd345000 {
24 reg = <0xfd345000 0xb50>; 24 reg = <0xfd345000 0xb50>;
25 25
26 CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV { 26 clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
27 #clock-cells = <0>; 27 #clock-cells = <0>;
28 compatible = "st,clkgena-prediv-c32", 28 compatible = "st,clkgena-prediv-c32",
29 "st,clkgena-prediv"; 29 "st,clkgena-prediv";
30 30
31 clocks = <&CLK_SYSIN>; 31 clocks = <&clk_sysin>;
32 32
33 clock-output-names = "CLK_M_A2_OSC_PREDIV"; 33 clock-output-names = "clk-m-a2-osc-prediv";
34 }; 34 };
35 }; 35 };
36 36
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
index 4e3ff28b04c3..109b3eddcb17 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
@@ -32,22 +32,30 @@ Required properties:
32 32
33Example: 33Example:
34 34
35 CLOCKGEN_C_VCC: CLOCKGEN_C_VCC { 35 clockgen_c_vcc: clockgen-c-vcc@0xfe8308ac {
36 #clock-cells = <1>; 36 #clock-cells = <1>;
37 compatible = "st,stih416-clkgenc", "st,clkgen-vcc"; 37 compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
38 reg = <0xfe8308ac 12>; 38 reg = <0xfe8308ac 12>;
39 39
40 clocks = <&CLK_S_VCC_HD>, <&CLOCKGEN_C 1>, 40 clocks = <&clk_s_vcc_hd>,
41 <&CLK_S_TMDS_FROMPHY>, <&CLOCKGEN_C 2>; 41 <&clockgen_c 1>,
42 42 <&clk_s_tmds_fromphy>,
43 clock-output-names = 43 <&clockgen_c 2>;
44 "CLK_S_PIX_HDMI", "CLK_S_PIX_DVO", 44
45 "CLK_S_OUT_DVO", "CLK_S_PIX_HD", 45 clock-output-names = "clk-s-pix-hdmi",
46 "CLK_S_HDDAC", "CLK_S_DENC", 46 "clk-s-pix-dvo",
47 "CLK_S_SDDAC", "CLK_S_PIX_MAIN", 47 "clk-s-out-dvo",
48 "CLK_S_PIX_AUX", "CLK_S_STFE_FRC_0", 48 "clk-s-pix-hd",
49 "CLK_S_REF_MCRU", "CLK_S_SLAVE_MCRU", 49 "clk-s-hddac",
50 "CLK_S_TMDS_HDMI", "CLK_S_HDMI_REJECT_PLL", 50 "clk-s-denc",
51 "CLK_S_THSENS"; 51 "clk-s-sddac",
52 "clk-s-pix-main",
53 "clk-s-pix-aux",
54 "clk-s-stfe-frc-0",
55 "clk-s-ref-mcru",
56 "clk-s-slave-mcru",
57 "clk-s-tmds-hdmi",
58 "clk-s-hdmi-reject-pll",
59 "clk-s-thsens";
52 }; 60 };
53 61
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
index 49ec5ae18b5b..78978f1f5158 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
@@ -24,60 +24,77 @@ address is common of all subnode.
24 quadfs_node { 24 quadfs_node {
25 ... 25 ...
26 }; 26 };
27
28 mux_node {
29 ...
30 };
31
32 vcc_node {
33 ...
34 };
35
36 flexgen_node {
37 ...
38 };
27 ... 39 ...
28 }; 40 };
29 41
30This binding uses the common clock binding[1]. 42This binding uses the common clock binding[1].
31Each subnode should use the binding discribe in [2]..[4] 43Each subnode should use the binding discribe in [2]..[7]
32 44
33[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 45[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
34[2] Documentation/devicetree/bindings/clock/st,quadfs.txt 46[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
35[3] Documentation/devicetree/bindings/clock/st,quadfs.txt 47[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
36[4] Documentation/devicetree/bindings/clock/st,quadfs.txt 48[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
49[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
50[6] Documentation/devicetree/bindings/clock/st,vcc.txt
51[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
52[8] Documentation/devicetree/bindings/clock/st,flexgen.txt
53
37 54
38Required properties: 55Required properties:
39- reg : A Base address and length of the register set. 56- reg : A Base address and length of the register set.
40 57
41Example: 58Example:
42 59
43 clockgenA@fee62000 { 60 clockgen-a@fee62000 {
44 61
45 reg = <0xfee62000 0xb48>; 62 reg = <0xfee62000 0xb48>;
46 63
47 CLK_S_A0_PLL: CLK_S_A0_PLL { 64 clk_s_a0_pll: clk-s-a0-pll {
48 #clock-cells = <1>; 65 #clock-cells = <1>;
49 compatible = "st,clkgena-plls-c65"; 66 compatible = "st,clkgena-plls-c65";
50 67
51 clocks = <&CLK_SYSIN>; 68 clocks = <&clk-sysin>;
52 69
53 clock-output-names = "CLK_S_A0_PLL0_HS", 70 clock-output-names = "clk-s-a0-pll0-hs",
54 "CLK_S_A0_PLL0_LS", 71 "clk-s-a0-pll0-ls",
55 "CLK_S_A0_PLL1"; 72 "clk-s-a0-pll1";
56 }; 73 };
57 74
58 CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV { 75 clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
59 #clock-cells = <0>; 76 #clock-cells = <0>;
60 compatible = "st,clkgena-prediv-c65", 77 compatible = "st,clkgena-prediv-c65",
61 "st,clkgena-prediv"; 78 "st,clkgena-prediv";
62 79
63 clocks = <&CLK_SYSIN>; 80 clocks = <&clk_sysin>;
64 81
65 clock-output-names = "CLK_S_A0_OSC_PREDIV"; 82 clock-output-names = "clk-s-a0-osc-prediv";
66 }; 83 };
67 84
68 CLK_S_A0_HS: CLK_S_A0_HS { 85 clk_s_a0_hs: clk-s-a0-hs {
69 #clock-cells = <1>; 86 #clock-cells = <1>;
70 compatible = "st,clkgena-divmux-c65-hs", 87 compatible = "st,clkgena-divmux-c65-hs",
71 "st,clkgena-divmux"; 88 "st,clkgena-divmux";
72 89
73 clocks = <&CLK_S_A0_OSC_PREDIV>, 90 clocks = <&clk-s_a0_osc_prediv>,
74 <&CLK_S_A0_PLL 0>, /* PLL0 HS */ 91 <&clk-s_a0_pll 0>, /* pll0 hs */
75 <&CLK_S_A0_PLL 2>; /* PLL1 */ 92 <&clk-s_a0_pll 2>; /* pll1 */
76 93
77 clock-output-names = "CLK_S_FDMA_0", 94 clock-output-names = "clk-s-fdma-0",
78 "CLK_S_FDMA_1", 95 "clk-s-fdma-1",
79 ""; /* CLK_S_JIT_SENSE */ 96 ""; /* clk-s-jit-sense */
80 /* Fourth output unused */ 97 /* fourth output unused */
81 }; 98 };
82 }; 99 };
83 100
diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
new file mode 100644
index 000000000000..1d3ace088172
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
@@ -0,0 +1,119 @@
1Binding for a type of flexgen structure found on certain
2STMicroelectronics consumer electronics SoC devices
3
4This structure includes:
5- a clock cross bar (represented by a mux element)
6- a pre and final dividers (represented by a divider and gate elements)
7
8Flexgen structure is a part of Clockgen[1].
9
10Please find an example below:
11
12 Clockgen block diagram
13 -------------------------------------------------------------------
14 | Flexgen stucture |
15 | --------------------------------------------- |
16 | | ------- -------- -------- | |
17clk_sysin | | | | | | | | |
18---|-----------------|-->| | | | | | | |
19 | | | | | | | | | | |
20 | | ------- | | | |Pre | |Final | | |
21 | | |PLL0 | | | | |Dividers| |Dividers| | |
22 | |->| | | | | | x32 | | x32 | | |
23 | | | odf_0|----|-->| | | | | | | |
24 | | | | | | | | | | | | |
25 | | | | | | | | | | | | |
26 | | | | | | | | | | | | |
27 | | | | | | | | | | | | |
28 | | ------- | | | | | | | | |
29 | | | | | | | | | | |
30 | | ------- | | Clock | | | | | | |
31 | | |PLL1 | | | | | | | | | |
32 | |->| | | | Cross | | | | | | |
33 | | | odf_0|----|-->| | | | | | CLK_DIV[31:0]
34 | | | | | | Bar |====>| |====>| |===|=========>
35 | | | | | | | | | | | | |
36 | | | | | | | | | | | | |
37 | | | | | | | | | | | | |
38 | | ------- | | | | | | | | |
39 | | | | | | | | | | |
40 | | ------- | | | | | | | | |
41 | | |QUADFS | | | | | | | | | |
42 | |->| ch0|----|-->| | | | | | | |
43 | | | | | | | | | | | |
44 | | ch1|----|-->| | | | | | | |
45 | | | | | | | | | | | |
46 | | ch2|----|-->| | | DIV | | DIV | | |
47 | | | | | | | 1 to | | 1 to | | |
48 | | ch3|----|-->| | | 1024 | | 64 | | |
49 | ------- | | | | | | | | |
50 | | ------- -------- -------- | |
51 | -------------------------------------------- |
52 | |
53 -------------------------------------------------------------------
54
55This binding uses the common clock binding[2].
56
57[1] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
58[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
59
60Required properties:
61- compatible : shall be:
62 "st,flexgen"
63
64- #clock-cells : from common clock binding; shall be set to 1 (multiple clock
65 outputs).
66
67- clocks : must be set to the parent's phandle. it's could be output clocks of
68 a quadsfs or/and a pll or/and clk_sysin (up to 7 clocks)
69
70- clock-output-names : List of strings used to name the clock outputs.
71
72Example:
73
74 clk_s_c0_flexgen: clk-s-c0-flexgen {
75
76 #clock-cells = <1>;
77 compatible = "st,flexgen";
78
79 clocks = <&clk_s_c0_pll0 0>,
80 <&clk_s_c0_pll1 0>,
81 <&clk_s_c0_quadfs 0>,
82 <&clk_s_c0_quadfs 1>,
83 <&clk_s_c0_quadfs 2>,
84 <&clk_s_c0_quadfs 3>,
85 <&clk_sysin>;
86
87 clock-output-names = "clk-icn-gpu",
88 "clk-fdma",
89 "clk-nand",
90 "clk-hva",
91 "clk-proc-stfe",
92 "clk-proc-tp",
93 "clk-rx-icn-dmu",
94 "clk-rx-icn-hva",
95 "clk-icn-cpu",
96 "clk-tx-icn-dmu",
97 "clk-mmc-0",
98 "clk-mmc-1",
99 "clk-jpegdec",
100 "clk-ext2fa9",
101 "clk-ic-bdisp-0",
102 "clk-ic-bdisp-1",
103 "clk-pp-dmu",
104 "clk-vid-dmu",
105 "clk-dss-lpc",
106 "clk-st231-aud-0",
107 "clk-st231-gp-1",
108 "clk-st231-dmu",
109 "clk-icn-lmi",
110 "clk-tx-icn-disp-1",
111 "clk-icn-sbc",
112 "clk-stfe-frc2",
113 "clk-eth-phy",
114 "clk-eth-ref-phyclk",
115 "clk-flash-promip",
116 "clk-main-disp",
117 "clk-aux-disp",
118 "clk-compo-dvp";
119 };
diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
index ec86d62ca283..cedeb9cc8208 100644
--- a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
@@ -15,6 +15,9 @@ Required properties:
15 "st,stih416-quadfs432", "st,quadfs" 15 "st,stih416-quadfs432", "st,quadfs"
16 "st,stih416-quadfs660-E", "st,quadfs" 16 "st,stih416-quadfs660-E", "st,quadfs"
17 "st,stih416-quadfs660-F", "st,quadfs" 17 "st,stih416-quadfs660-F", "st,quadfs"
18 "st,stih407-quadfs660-C", "st,quadfs"
19 "st,stih407-quadfs660-D", "st,quadfs"
20
18 21
19- #clock-cells : from common clock binding; shall be set to 1. 22- #clock-cells : from common clock binding; shall be set to 1.
20 23
@@ -32,14 +35,14 @@ Required properties:
32 35
33Example: 36Example:
34 37
35 CLOCKGEN_E: CLOCKGEN_E { 38 clockgen_e: clockgen-e@fd3208bc {
36 #clock-cells = <1>; 39 #clock-cells = <1>;
37 compatible = "st,stih416-quadfs660-E", "st,quadfs"; 40 compatible = "st,stih416-quadfs660-E", "st,quadfs";
38 reg = <0xfd3208bc 0xB0>; 41 reg = <0xfd3208bc 0xB0>;
39 42
40 clocks = <&CLK_SYSIN>; 43 clocks = <&clk_sysin>;
41 clock-output-names = "CLK_M_PIX_MDTP_0", 44 clock-output-names = "clk-m-pix-mdtp-0",
42 "CLK_M_PIX_MDTP_1", 45 "clk-m-pix-mdtp-1",
43 "CLK_M_PIX_MDTP_2", 46 "clk-m-pix-mdtp-2",
44 "CLK_M_MPELPC"; 47 "clk-m-mpelpc";
45 }; 48 };
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index b9ec668bfe62..d3a5c3c6d677 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -9,11 +9,13 @@ Required properties:
9 "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator 9 "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
10 "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4 10 "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
11 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31 11 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
12 "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock 13 "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
13 "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock 14 "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
14 "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31 15 "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
15 "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock 16 "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
16 "allwinner,sun4i-a10-axi-clk" - for the AXI clock 17 "allwinner,sun4i-a10-axi-clk" - for the AXI clock
18 "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
17 "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates 19 "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
18 "allwinner,sun4i-a10-ahb-clk" - for the AHB clock 20 "allwinner,sun4i-a10-ahb-clk" - for the AHB clock
19 "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10 21 "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
@@ -23,13 +25,16 @@ Required properties:
23 "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31 25 "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
24 "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31 26 "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
25 "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 27 "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
28 "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
26 "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock 29 "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
27 "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31 30 "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
31 "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
28 "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10 32 "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
29 "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13 33 "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
30 "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s 34 "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
31 "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31 35 "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
32 "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20 36 "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
37 "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
33 "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock 38 "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
34 "allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing 39 "allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
35 "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10 40 "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
@@ -37,8 +42,10 @@ Required properties:
37 "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s 42 "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
38 "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31 43 "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
39 "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20 44 "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
45 "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
40 "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31 46 "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
41 "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 47 "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
48 "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
42 "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks 49 "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
43 "allwinner,sun7i-a20-out-clk" - for the external output clocks 50 "allwinner,sun7i-a20-out-clk" - for the external output clocks
44 "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31 51 "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
diff --git a/MAINTAINERS b/MAINTAINERS
index f167eb17b5e4..e4cf1f63f487 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9057,6 +9057,13 @@ L: linux-pm@vger.kernel.org
9057S: Supported 9057S: Supported
9058F: drivers/thermal/ti-soc-thermal/ 9058F: drivers/thermal/ti-soc-thermal/
9059 9059
9060TI CLOCK DRIVER
9061M: Tero Kristo <t-kristo@ti.com>
9062L: linux-omap@vger.kernel.org
9063S: Maintained
9064F: drivers/clk/ti/
9065F: include/linux/clk/ti.h
9066
9060TI FLASH MEDIA INTERFACE DRIVER 9067TI FLASH MEDIA INTERFACE DRIVER
9061M: Alex Dubov <oakad@yahoo.com> 9068M: Alex Dubov <oakad@yahoo.com>
9062S: Maintained 9069S: Maintained
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index ee3001f38821..97ea7a9b1f62 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -31,6 +31,16 @@
31 pinctrl2 = &pinctrl_2; 31 pinctrl2 = &pinctrl_2;
32 }; 32 };
33 33
34 pmu_system_controller: system-controller@10020000 {
35 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
36 "clkout4", "clkout8", "clkout9";
37 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
38 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
39 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
40 <&clock CLK_XUSBXTI>;
41 #clock-cells = <1>;
42 };
43
34 sysram@02020000 { 44 sysram@02020000 {
35 compatible = "mmio-sram"; 45 compatible = "mmio-sram";
36 reg = <0x02020000 0x20000>; 46 reg = <0x02020000 0x20000>;
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index c5a943df1cd7..de1f9c77b589 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -139,6 +139,13 @@
139 139
140 pmu_system_controller: system-controller@10020000 { 140 pmu_system_controller: system-controller@10020000 {
141 compatible = "samsung,exynos4212-pmu", "syscon"; 141 compatible = "samsung,exynos4212-pmu", "syscon";
142 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
143 "clkout4", "clkout8", "clkout9";
144 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
145 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
146 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
147 <&clock CLK_XUSBXTI>;
148 #clock-cells = <1>;
142 }; 149 };
143 150
144 g2d@10800000 { 151 g2d@10800000 {
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 834fb5a5306f..492e1eff37bd 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -191,6 +191,9 @@
191 pmu_system_controller: system-controller@10040000 { 191 pmu_system_controller: system-controller@10040000 {
192 compatible = "samsung,exynos5250-pmu", "syscon"; 192 compatible = "samsung,exynos5250-pmu", "syscon";
193 reg = <0x10040000 0x5000>; 193 reg = <0x10040000 0x5000>;
194 clock-names = "clkout16";
195 clocks = <&clock CLK_FIN_PLL>;
196 #clock-cells = <1>;
194 }; 197 };
195 198
196 sysreg_system_controller: syscon@10050000 { 199 sysreg_system_controller: syscon@10050000 {
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 15957227ffda..a40a5c2b5a4f 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -727,6 +727,9 @@
727 pmu_system_controller: system-controller@10040000 { 727 pmu_system_controller: system-controller@10040000 {
728 compatible = "samsung,exynos5420-pmu", "syscon"; 728 compatible = "samsung,exynos5420-pmu", "syscon";
729 reg = <0x10040000 0x5000>; 729 reg = <0x10040000 0x5000>;
730 clock-names = "clkout16";
731 clocks = <&clock CLK_FIN_PLL>;
732 #clock-cells = <1>;
730 }; 733 };
731 734
732 sysreg_system_controller: syscon@10050000 { 735 sysreg_system_controller: syscon@10050000 {
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 1caee6d548b8..e4564c259ed1 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -2,6 +2,7 @@ config ARCH_ROCKCHIP
2 bool "Rockchip RK2928 and RK3xxx SOCs" if ARCH_MULTI_V7 2 bool "Rockchip RK2928 and RK3xxx SOCs" if ARCH_MULTI_V7
3 select PINCTRL 3 select PINCTRL
4 select PINCTRL_ROCKCHIP 4 select PINCTRL_ROCKCHIP
5 select ARCH_HAS_RESET_CONTROLLER
5 select ARCH_REQUIRE_GPIOLIB 6 select ARCH_REQUIRE_GPIOLIB
6 select ARM_GIC 7 select ARM_GIC
7 select CACHE_L2X0 8 select CACHE_L2X0
diff --git a/drivers/base/platform.c b/drivers/base/platform.c
index eee48c49f5de..00f2208949d1 100644
--- a/drivers/base/platform.c
+++ b/drivers/base/platform.c
@@ -23,6 +23,7 @@
23#include <linux/pm_runtime.h> 23#include <linux/pm_runtime.h>
24#include <linux/idr.h> 24#include <linux/idr.h>
25#include <linux/acpi.h> 25#include <linux/acpi.h>
26#include <linux/clk/clk-conf.h>
26 27
27#include "base.h" 28#include "base.h"
28#include "power/power.h" 29#include "power/power.h"
@@ -499,6 +500,10 @@ static int platform_drv_probe(struct device *_dev)
499 struct platform_device *dev = to_platform_device(_dev); 500 struct platform_device *dev = to_platform_device(_dev);
500 int ret; 501 int ret;
501 502
503 ret = of_clk_set_defaults(_dev->of_node, false);
504 if (ret < 0)
505 return ret;
506
502 acpi_dev_pm_attach(_dev, true); 507 acpi_dev_pm_attach(_dev, true);
503 508
504 ret = drv->probe(dev); 509 ret = drv->probe(dev);
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9f9c5ae5359b..cfd3af7b2cbd 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -102,6 +102,13 @@ config COMMON_CLK_KEYSTONE
102 Supports clock drivers for Keystone based SOCs. These SOCs have local 102 Supports clock drivers for Keystone based SOCs. These SOCs have local
103 a power sleep control module that gate the clock to the IPs and PLLs. 103 a power sleep control module that gate the clock to the IPs and PLLs.
104 104
105config COMMON_CLK_PALMAS
106 tristate "Clock driver for TI Palmas devices"
107 depends on MFD_PALMAS
108 ---help---
109 This driver supports TI Palmas devices 32KHz output KG and KG_AUDIO
110 using common clock framework.
111
105source "drivers/clk/qcom/Kconfig" 112source "drivers/clk/qcom/Kconfig"
106 113
107endmenu 114endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 567f10259029..f537a0b1f798 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -9,12 +9,16 @@ obj-$(CONFIG_COMMON_CLK) += clk-gate.o
9obj-$(CONFIG_COMMON_CLK) += clk-mux.o 9obj-$(CONFIG_COMMON_CLK) += clk-mux.o
10obj-$(CONFIG_COMMON_CLK) += clk-composite.o 10obj-$(CONFIG_COMMON_CLK) += clk-composite.o
11obj-$(CONFIG_COMMON_CLK) += clk-fractional-divider.o 11obj-$(CONFIG_COMMON_CLK) += clk-fractional-divider.o
12ifeq ($(CONFIG_OF), y)
13obj-$(CONFIG_COMMON_CLK) += clk-conf.o
14endif
12 15
13# hardware specific clock types 16# hardware specific clock types
14# please keep this section sorted lexicographically by file/directory path name 17# please keep this section sorted lexicographically by file/directory path name
15obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o 18obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
16obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o 19obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o
17obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o 20obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
21obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o
18obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o 22obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
19obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o 23obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
20obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o 24obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
@@ -22,6 +26,7 @@ obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
22obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o 26obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
23obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o 27obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
24obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o 28obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
29obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o
25obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o 30obj-$(CONFIG_CLK_PPC_CORENET) += clk-ppc-corenet.o
26obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o 31obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o
27obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o 32obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o
diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
index 733306131b99..59fa3cc96c9e 100644
--- a/drivers/clk/at91/clk-main.c
+++ b/drivers/clk/at91/clk-main.c
@@ -388,6 +388,7 @@ static unsigned long clk_main_recalc_rate(struct at91_pmc *pmc,
388 if (parent_rate) 388 if (parent_rate)
389 return parent_rate; 389 return parent_rate;
390 390
391 pr_warn("Main crystal frequency not set, using approximate value\n");
391 tmp = pmc_read(pmc, AT91_CKGR_MCFR); 392 tmp = pmc_read(pmc, AT91_CKGR_MCFR);
392 if (!(tmp & AT91_PMC_MAINRDY)) 393 if (!(tmp & AT91_PMC_MAINRDY))
393 return 0; 394 return 0;
diff --git a/drivers/clk/clk-clps711x.c b/drivers/clk/clk-clps711x.c
new file mode 100644
index 000000000000..715eec1a9902
--- /dev/null
+++ b/drivers/clk/clk-clps711x.c
@@ -0,0 +1,192 @@
1/*
2 * Cirrus Logic CLPS711X CLK driver
3 *
4 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/clk.h>
13#include <linux/clk-provider.h>
14#include <linux/clkdev.h>
15#include <linux/io.h>
16#include <linux/ioport.h>
17#include <linux/of_address.h>
18#include <linux/slab.h>
19#include <linux/mfd/syscon/clps711x.h>
20
21#include <dt-bindings/clock/clps711x-clock.h>
22
23#define CLPS711X_SYSCON1 (0x0100)
24#define CLPS711X_SYSCON2 (0x1100)
25#define CLPS711X_SYSFLG2 (CLPS711X_SYSCON2 + SYSFLG_OFFSET)
26#define CLPS711X_PLLR (0xa5a8)
27
28#define CLPS711X_EXT_FREQ (13000000)
29#define CLPS711X_OSC_FREQ (3686400)
30
31static const struct clk_div_table spi_div_table[] = {
32 { .val = 0, .div = 32, },
33 { .val = 1, .div = 8, },
34 { .val = 2, .div = 2, },
35 { .val = 3, .div = 1, },
36};
37
38static const struct clk_div_table timer_div_table[] = {
39 { .val = 0, .div = 256, },
40 { .val = 1, .div = 1, },
41};
42
43struct clps711x_clk {
44 struct clk_onecell_data clk_data;
45 spinlock_t lock;
46 struct clk *clks[CLPS711X_CLK_MAX];
47};
48
49static struct clps711x_clk * __init _clps711x_clk_init(void __iomem *base,
50 u32 fref)
51{
52 u32 tmp, f_cpu, f_pll, f_bus, f_tim, f_pwm, f_spi;
53 struct clps711x_clk *clps711x_clk;
54 unsigned i;
55
56 if (!base)
57 return ERR_PTR(-ENOMEM);
58
59 clps711x_clk = kzalloc(sizeof(*clps711x_clk), GFP_KERNEL);
60 if (!clps711x_clk)
61 return ERR_PTR(-ENOMEM);
62
63 spin_lock_init(&clps711x_clk->lock);
64
65 /* Read PLL multiplier value and sanity check */
66 tmp = readl(base + CLPS711X_PLLR) >> 24;
67 if (((tmp >= 10) && (tmp <= 50)) || !fref)
68 f_pll = DIV_ROUND_UP(CLPS711X_OSC_FREQ * tmp, 2);
69 else
70 f_pll = fref;
71
72 tmp = readl(base + CLPS711X_SYSFLG2);
73 if (tmp & SYSFLG2_CKMODE) {
74 f_cpu = CLPS711X_EXT_FREQ;
75 f_bus = CLPS711X_EXT_FREQ;
76 f_spi = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 96);
77 f_pll = 0;
78 f_pwm = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 128);
79 } else {
80 f_cpu = f_pll;
81 if (f_cpu > 36864000)
82 f_bus = DIV_ROUND_UP(f_cpu, 2);
83 else
84 f_bus = 36864000 / 2;
85 f_spi = DIV_ROUND_CLOSEST(f_cpu, 576);
86 f_pwm = DIV_ROUND_CLOSEST(f_cpu, 768);
87 }
88
89 if (tmp & SYSFLG2_CKMODE) {
90 if (readl(base + CLPS711X_SYSCON2) & SYSCON2_OSTB)
91 f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 26);
92 else
93 f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 24);
94 } else
95 f_tim = DIV_ROUND_CLOSEST(f_cpu, 144);
96
97 tmp = readl(base + CLPS711X_SYSCON1);
98 /* Timer1 in free running mode.
99 * Counter will wrap around to 0xffff when it underflows
100 * and will continue to count down.
101 */
102 tmp &= ~(SYSCON1_TC1M | SYSCON1_TC1S);
103 /* Timer2 in prescale mode.
104 * Value writen is automatically re-loaded when
105 * the counter underflows.
106 */
107 tmp |= SYSCON1_TC2M | SYSCON1_TC2S;
108 writel(tmp, base + CLPS711X_SYSCON1);
109
110 clps711x_clk->clks[CLPS711X_CLK_DUMMY] =
111 clk_register_fixed_rate(NULL, "dummy", NULL, CLK_IS_ROOT, 0);
112 clps711x_clk->clks[CLPS711X_CLK_CPU] =
113 clk_register_fixed_rate(NULL, "cpu", NULL, CLK_IS_ROOT, f_cpu);
114 clps711x_clk->clks[CLPS711X_CLK_BUS] =
115 clk_register_fixed_rate(NULL, "bus", NULL, CLK_IS_ROOT, f_bus);
116 clps711x_clk->clks[CLPS711X_CLK_PLL] =
117 clk_register_fixed_rate(NULL, "pll", NULL, CLK_IS_ROOT, f_pll);
118 clps711x_clk->clks[CLPS711X_CLK_TIMERREF] =
119 clk_register_fixed_rate(NULL, "timer_ref", NULL, CLK_IS_ROOT,
120 f_tim);
121 clps711x_clk->clks[CLPS711X_CLK_TIMER1] =
122 clk_register_divider_table(NULL, "timer1", "timer_ref", 0,
123 base + CLPS711X_SYSCON1, 5, 1, 0,
124 timer_div_table, &clps711x_clk->lock);
125 clps711x_clk->clks[CLPS711X_CLK_TIMER2] =
126 clk_register_divider_table(NULL, "timer2", "timer_ref", 0,
127 base + CLPS711X_SYSCON1, 7, 1, 0,
128 timer_div_table, &clps711x_clk->lock);
129 clps711x_clk->clks[CLPS711X_CLK_PWM] =
130 clk_register_fixed_rate(NULL, "pwm", NULL, CLK_IS_ROOT, f_pwm);
131 clps711x_clk->clks[CLPS711X_CLK_SPIREF] =
132 clk_register_fixed_rate(NULL, "spi_ref", NULL, CLK_IS_ROOT,
133 f_spi);
134 clps711x_clk->clks[CLPS711X_CLK_SPI] =
135 clk_register_divider_table(NULL, "spi", "spi_ref", 0,
136 base + CLPS711X_SYSCON1, 16, 2, 0,
137 spi_div_table, &clps711x_clk->lock);
138 clps711x_clk->clks[CLPS711X_CLK_UART] =
139 clk_register_fixed_factor(NULL, "uart", "bus", 0, 1, 10);
140 clps711x_clk->clks[CLPS711X_CLK_TICK] =
141 clk_register_fixed_rate(NULL, "tick", NULL, CLK_IS_ROOT, 64);
142
143 for (i = 0; i < CLPS711X_CLK_MAX; i++)
144 if (IS_ERR(clps711x_clk->clks[i]))
145 pr_err("clk %i: register failed with %ld\n",
146 i, PTR_ERR(clps711x_clk->clks[i]));
147
148 return clps711x_clk;
149}
150
151void __init clps711x_clk_init(void __iomem *base)
152{
153 struct clps711x_clk *clps711x_clk;
154
155 clps711x_clk = _clps711x_clk_init(base, 73728000);
156
157 BUG_ON(IS_ERR(clps711x_clk));
158
159 /* Clocksource */
160 clk_register_clkdev(clps711x_clk->clks[CLPS711X_CLK_TIMER1],
161 NULL, "clps711x-timer.0");
162 clk_register_clkdev(clps711x_clk->clks[CLPS711X_CLK_TIMER2],
163 NULL, "clps711x-timer.1");
164
165 /* Drivers */
166 clk_register_clkdev(clps711x_clk->clks[CLPS711X_CLK_PWM],
167 NULL, "clps711x-pwm");
168 clk_register_clkdev(clps711x_clk->clks[CLPS711X_CLK_UART],
169 NULL, "clps711x-uart.0");
170 clk_register_clkdev(clps711x_clk->clks[CLPS711X_CLK_UART],
171 NULL, "clps711x-uart.1");
172}
173
174#ifdef CONFIG_OF
175static void __init clps711x_clk_init_dt(struct device_node *np)
176{
177 void __iomem *base = of_iomap(np, 0);
178 struct clps711x_clk *clps711x_clk;
179 u32 fref = 0;
180
181 WARN_ON(of_property_read_u32(np, "startup-frequency", &fref));
182
183 clps711x_clk = _clps711x_clk_init(base, fref);
184 BUG_ON(IS_ERR(clps711x_clk));
185
186 clps711x_clk->clk_data.clks = clps711x_clk->clks;
187 clps711x_clk->clk_data.clk_num = CLPS711X_CLK_MAX;
188 of_clk_add_provider(np, of_clk_src_onecell_get,
189 &clps711x_clk->clk_data);
190}
191CLK_OF_DECLARE(clps711x, "cirrus,clps711x-clk", clps711x_clk_init_dt);
192#endif
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index 57a078e06efe..b9355daf8065 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -64,11 +64,56 @@ static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate,
64 const struct clk_ops *mux_ops = composite->mux_ops; 64 const struct clk_ops *mux_ops = composite->mux_ops;
65 struct clk_hw *rate_hw = composite->rate_hw; 65 struct clk_hw *rate_hw = composite->rate_hw;
66 struct clk_hw *mux_hw = composite->mux_hw; 66 struct clk_hw *mux_hw = composite->mux_hw;
67 struct clk *parent;
68 unsigned long parent_rate;
69 long tmp_rate, best_rate = 0;
70 unsigned long rate_diff;
71 unsigned long best_rate_diff = ULONG_MAX;
72 int i;
67 73
68 if (rate_hw && rate_ops && rate_ops->determine_rate) { 74 if (rate_hw && rate_ops && rate_ops->determine_rate) {
69 rate_hw->clk = hw->clk; 75 rate_hw->clk = hw->clk;
70 return rate_ops->determine_rate(rate_hw, rate, best_parent_rate, 76 return rate_ops->determine_rate(rate_hw, rate, best_parent_rate,
71 best_parent_p); 77 best_parent_p);
78 } else if (rate_hw && rate_ops && rate_ops->round_rate &&
79 mux_hw && mux_ops && mux_ops->set_parent) {
80 *best_parent_p = NULL;
81
82 if (__clk_get_flags(hw->clk) & CLK_SET_RATE_NO_REPARENT) {
83 *best_parent_p = clk_get_parent(mux_hw->clk);
84 *best_parent_rate = __clk_get_rate(*best_parent_p);
85
86 return rate_ops->round_rate(rate_hw, rate,
87 best_parent_rate);
88 }
89
90 for (i = 0; i < __clk_get_num_parents(mux_hw->clk); i++) {
91 parent = clk_get_parent_by_index(mux_hw->clk, i);
92 if (!parent)
93 continue;
94
95 parent_rate = __clk_get_rate(parent);
96
97 tmp_rate = rate_ops->round_rate(rate_hw, rate,
98 &parent_rate);
99 if (tmp_rate < 0)
100 continue;
101
102 rate_diff = abs(rate - tmp_rate);
103
104 if (!rate_diff || !*best_parent_p
105 || best_rate_diff > rate_diff) {
106 *best_parent_p = parent;
107 *best_parent_rate = parent_rate;
108 best_rate_diff = rate_diff;
109 best_rate = tmp_rate;
110 }
111
112 if (!rate_diff)
113 return rate;
114 }
115
116 return best_rate;
72 } else if (mux_hw && mux_ops && mux_ops->determine_rate) { 117 } else if (mux_hw && mux_ops && mux_ops->determine_rate) {
73 mux_hw->clk = hw->clk; 118 mux_hw->clk = hw->clk;
74 return mux_ops->determine_rate(mux_hw, rate, best_parent_rate, 119 return mux_ops->determine_rate(mux_hw, rate, best_parent_rate,
@@ -162,7 +207,7 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
162 clk_composite_ops = &composite->ops; 207 clk_composite_ops = &composite->ops;
163 208
164 if (mux_hw && mux_ops) { 209 if (mux_hw && mux_ops) {
165 if (!mux_ops->get_parent || !mux_ops->set_parent) { 210 if (!mux_ops->get_parent) {
166 clk = ERR_PTR(-EINVAL); 211 clk = ERR_PTR(-EINVAL);
167 goto err; 212 goto err;
168 } 213 }
@@ -170,7 +215,8 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
170 composite->mux_hw = mux_hw; 215 composite->mux_hw = mux_hw;
171 composite->mux_ops = mux_ops; 216 composite->mux_ops = mux_ops;
172 clk_composite_ops->get_parent = clk_composite_get_parent; 217 clk_composite_ops->get_parent = clk_composite_get_parent;
173 clk_composite_ops->set_parent = clk_composite_set_parent; 218 if (mux_ops->set_parent)
219 clk_composite_ops->set_parent = clk_composite_set_parent;
174 if (mux_ops->determine_rate) 220 if (mux_ops->determine_rate)
175 clk_composite_ops->determine_rate = clk_composite_determine_rate; 221 clk_composite_ops->determine_rate = clk_composite_determine_rate;
176 } 222 }
@@ -180,24 +226,27 @@ struct clk *clk_register_composite(struct device *dev, const char *name,
180 clk = ERR_PTR(-EINVAL); 226 clk = ERR_PTR(-EINVAL);
181 goto err; 227 goto err;
182 } 228 }
229 clk_composite_ops->recalc_rate = clk_composite_recalc_rate;
183 230
184 /* .round_rate is a prerequisite for .set_rate */ 231 if (rate_ops->determine_rate)
185 if (rate_ops->round_rate) { 232 clk_composite_ops->determine_rate =
186 clk_composite_ops->round_rate = clk_composite_round_rate; 233 clk_composite_determine_rate;
187 if (rate_ops->set_rate) { 234 else if (rate_ops->round_rate)
188 clk_composite_ops->set_rate = clk_composite_set_rate; 235 clk_composite_ops->round_rate =
189 } 236 clk_composite_round_rate;
190 } else { 237
191 WARN(rate_ops->set_rate, 238 /* .set_rate requires either .round_rate or .determine_rate */
192 "%s: missing round_rate op is required\n", 239 if (rate_ops->set_rate) {
193 __func__); 240 if (rate_ops->determine_rate || rate_ops->round_rate)
241 clk_composite_ops->set_rate =
242 clk_composite_set_rate;
243 else
244 WARN(1, "%s: missing round_rate op is required\n",
245 __func__);
194 } 246 }
195 247
196 composite->rate_hw = rate_hw; 248 composite->rate_hw = rate_hw;
197 composite->rate_ops = rate_ops; 249 composite->rate_ops = rate_ops;
198 clk_composite_ops->recalc_rate = clk_composite_recalc_rate;
199 if (rate_ops->determine_rate)
200 clk_composite_ops->determine_rate = clk_composite_determine_rate;
201 } 250 }
202 251
203 if (gate_hw && gate_ops) { 252 if (gate_hw && gate_ops) {
diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c
new file mode 100644
index 000000000000..aad4796aa3ed
--- /dev/null
+++ b/drivers/clk/clk-conf.c
@@ -0,0 +1,144 @@
1/*
2 * Copyright (C) 2014 Samsung Electronics Co., Ltd.
3 * Sylwester Nawrocki <s.nawrocki@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
11#include <linux/clk-provider.h>
12#include <linux/clk/clk-conf.h>
13#include <linux/device.h>
14#include <linux/of.h>
15#include <linux/printk.h>
16#include "clk.h"
17
18static int __set_clk_parents(struct device_node *node, bool clk_supplier)
19{
20 struct of_phandle_args clkspec;
21 int index, rc, num_parents;
22 struct clk *clk, *pclk;
23
24 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents",
25 "#clock-cells");
26 if (num_parents == -EINVAL)
27 pr_err("clk: invalid value of clock-parents property at %s\n",
28 node->full_name);
29
30 for (index = 0; index < num_parents; index++) {
31 rc = of_parse_phandle_with_args(node, "assigned-clock-parents",
32 "#clock-cells", index, &clkspec);
33 if (rc < 0) {
34 /* skip empty (null) phandles */
35 if (rc == -ENOENT)
36 continue;
37 else
38 return rc;
39 }
40 if (clkspec.np == node && !clk_supplier)
41 return 0;
42 pclk = of_clk_get_by_clkspec(&clkspec);
43 if (IS_ERR(pclk)) {
44 pr_warn("clk: couldn't get parent clock %d for %s\n",
45 index, node->full_name);
46 return PTR_ERR(pclk);
47 }
48
49 rc = of_parse_phandle_with_args(node, "assigned-clocks",
50 "#clock-cells", index, &clkspec);
51 if (rc < 0)
52 goto err;
53 if (clkspec.np == node && !clk_supplier) {
54 rc = 0;
55 goto err;
56 }
57 clk = of_clk_get_by_clkspec(&clkspec);
58 if (IS_ERR(clk)) {
59 pr_warn("clk: couldn't get parent clock %d for %s\n",
60 index, node->full_name);
61 rc = PTR_ERR(clk);
62 goto err;
63 }
64
65 rc = clk_set_parent(clk, pclk);
66 if (rc < 0)
67 pr_err("clk: failed to reparent %s to %s: %d\n",
68 __clk_get_name(clk), __clk_get_name(pclk), rc);
69 clk_put(clk);
70 clk_put(pclk);
71 }
72 return 0;
73err:
74 clk_put(pclk);
75 return rc;
76}
77
78static int __set_clk_rates(struct device_node *node, bool clk_supplier)
79{
80 struct of_phandle_args clkspec;
81 struct property *prop;
82 const __be32 *cur;
83 int rc, index = 0;
84 struct clk *clk;
85 u32 rate;
86
87 of_property_for_each_u32(node, "assigned-clock-rates", prop, cur, rate) {
88 if (rate) {
89 rc = of_parse_phandle_with_args(node, "assigned-clocks",
90 "#clock-cells", index, &clkspec);
91 if (rc < 0) {
92 /* skip empty (null) phandles */
93 if (rc == -ENOENT)
94 continue;
95 else
96 return rc;
97 }
98 if (clkspec.np == node && !clk_supplier)
99 return 0;
100
101 clk = of_clk_get_by_clkspec(&clkspec);
102 if (IS_ERR(clk)) {
103 pr_warn("clk: couldn't get clock %d for %s\n",
104 index, node->full_name);
105 return PTR_ERR(clk);
106 }
107
108 rc = clk_set_rate(clk, rate);
109 if (rc < 0)
110 pr_err("clk: couldn't set %s clock rate: %d\n",
111 __clk_get_name(clk), rc);
112 clk_put(clk);
113 }
114 index++;
115 }
116 return 0;
117}
118
119/**
120 * of_clk_set_defaults() - parse and set assigned clocks configuration
121 * @node: device node to apply clock settings for
122 * @clk_supplier: true if clocks supplied by @node should also be considered
123 *
124 * This function parses 'assigned-{clocks/clock-parents/clock-rates}' properties
125 * and sets any specified clock parents and rates. The @clk_supplier argument
126 * should be set to true if @node may be also a clock supplier of any clock
127 * listed in its 'assigned-clocks' or 'assigned-clock-parents' properties.
128 * If @clk_supplier is false the function exits returnning 0 as soon as it
129 * determines the @node is also a supplier of any of the clocks.
130 */
131int of_clk_set_defaults(struct device_node *node, bool clk_supplier)
132{
133 int rc;
134
135 if (!node)
136 return 0;
137
138 rc = __set_clk_parents(node, clk_supplier);
139 if (rc < 0)
140 return rc;
141
142 return __set_clk_rates(node, clk_supplier);
143}
144EXPORT_SYMBOL_GPL(of_clk_set_defaults);
diff --git a/drivers/clk/clk-palmas.c b/drivers/clk/clk-palmas.c
new file mode 100644
index 000000000000..781630e1372b
--- /dev/null
+++ b/drivers/clk/clk-palmas.c
@@ -0,0 +1,307 @@
1/*
2 * Clock driver for Palmas device.
3 *
4 * Copyright (c) 2013, NVIDIA Corporation.
5 * Copyright (c) 2013-2014 Texas Instruments, Inc.
6 *
7 * Author: Laxman Dewangan <ldewangan@nvidia.com>
8 * Peter Ujfalusi <peter.ujfalusi@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation version 2.
13 *
14 * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
15 * whether express or implied; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 */
19
20#include <linux/clk.h>
21#include <linux/clkdev.h>
22#include <linux/clk-provider.h>
23#include <linux/mfd/palmas.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/platform_device.h>
28#include <linux/slab.h>
29
30#define PALMAS_CLOCK_DT_EXT_CONTROL_ENABLE1 1
31#define PALMAS_CLOCK_DT_EXT_CONTROL_ENABLE2 2
32#define PALMAS_CLOCK_DT_EXT_CONTROL_NSLEEP 3
33
34struct palmas_clk32k_desc {
35 const char *clk_name;
36 unsigned int control_reg;
37 unsigned int enable_mask;
38 unsigned int sleep_mask;
39 unsigned int sleep_reqstr_id;
40 int delay;
41};
42
43struct palmas_clock_info {
44 struct device *dev;
45 struct clk *clk;
46 struct clk_hw hw;
47 struct palmas *palmas;
48 struct palmas_clk32k_desc *clk_desc;
49 int ext_control_pin;
50};
51
52static inline struct palmas_clock_info *to_palmas_clks_info(struct clk_hw *hw)
53{
54 return container_of(hw, struct palmas_clock_info, hw);
55}
56
57static unsigned long palmas_clks_recalc_rate(struct clk_hw *hw,
58 unsigned long parent_rate)
59{
60 return 32768;
61}
62
63static int palmas_clks_prepare(struct clk_hw *hw)
64{
65 struct palmas_clock_info *cinfo = to_palmas_clks_info(hw);
66 int ret;
67
68 ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE,
69 cinfo->clk_desc->control_reg,
70 cinfo->clk_desc->enable_mask,
71 cinfo->clk_desc->enable_mask);
72 if (ret < 0)
73 dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n",
74 cinfo->clk_desc->control_reg, ret);
75 else if (cinfo->clk_desc->delay)
76 udelay(cinfo->clk_desc->delay);
77
78 return ret;
79}
80
81static void palmas_clks_unprepare(struct clk_hw *hw)
82{
83 struct palmas_clock_info *cinfo = to_palmas_clks_info(hw);
84 int ret;
85
86 /*
87 * Clock can be disabled through external pin if it is externally
88 * controlled.
89 */
90 if (cinfo->ext_control_pin)
91 return;
92
93 ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE,
94 cinfo->clk_desc->control_reg,
95 cinfo->clk_desc->enable_mask, 0);
96 if (ret < 0)
97 dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n",
98 cinfo->clk_desc->control_reg, ret);
99}
100
101static int palmas_clks_is_prepared(struct clk_hw *hw)
102{
103 struct palmas_clock_info *cinfo = to_palmas_clks_info(hw);
104 int ret;
105 u32 val;
106
107 if (cinfo->ext_control_pin)
108 return 1;
109
110 ret = palmas_read(cinfo->palmas, PALMAS_RESOURCE_BASE,
111 cinfo->clk_desc->control_reg, &val);
112 if (ret < 0) {
113 dev_err(cinfo->dev, "Reg 0x%02x read failed, %d\n",
114 cinfo->clk_desc->control_reg, ret);
115 return ret;
116 }
117 return !!(val & cinfo->clk_desc->enable_mask);
118}
119
120static struct clk_ops palmas_clks_ops = {
121 .prepare = palmas_clks_prepare,
122 .unprepare = palmas_clks_unprepare,
123 .is_prepared = palmas_clks_is_prepared,
124 .recalc_rate = palmas_clks_recalc_rate,
125};
126
127struct palmas_clks_of_match_data {
128 struct clk_init_data init;
129 struct palmas_clk32k_desc desc;
130};
131
132static struct palmas_clks_of_match_data palmas_of_clk32kg = {
133 .init = {
134 .name = "clk32kg",
135 .ops = &palmas_clks_ops,
136 .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
137 },
138 .desc = {
139 .clk_name = "clk32kg",
140 .control_reg = PALMAS_CLK32KG_CTRL,
141 .enable_mask = PALMAS_CLK32KG_CTRL_MODE_ACTIVE,
142 .sleep_mask = PALMAS_CLK32KG_CTRL_MODE_SLEEP,
143 .sleep_reqstr_id = PALMAS_EXTERNAL_REQSTR_ID_CLK32KG,
144 .delay = 200,
145 },
146};
147
148static struct palmas_clks_of_match_data palmas_of_clk32kgaudio = {
149 .init = {
150 .name = "clk32kgaudio",
151 .ops = &palmas_clks_ops,
152 .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
153 },
154 .desc = {
155 .clk_name = "clk32kgaudio",
156 .control_reg = PALMAS_CLK32KGAUDIO_CTRL,
157 .enable_mask = PALMAS_CLK32KG_CTRL_MODE_ACTIVE,
158 .sleep_mask = PALMAS_CLK32KG_CTRL_MODE_SLEEP,
159 .sleep_reqstr_id = PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO,
160 .delay = 200,
161 },
162};
163
164static struct of_device_id palmas_clks_of_match[] = {
165 {
166 .compatible = "ti,palmas-clk32kg",
167 .data = &palmas_of_clk32kg,
168 },
169 {
170 .compatible = "ti,palmas-clk32kgaudio",
171 .data = &palmas_of_clk32kgaudio,
172 },
173 { },
174};
175MODULE_DEVICE_TABLE(of, palmas_clks_of_match);
176
177static void palmas_clks_get_clk_data(struct platform_device *pdev,
178 struct palmas_clock_info *cinfo)
179{
180 struct device_node *node = pdev->dev.of_node;
181 unsigned int prop;
182 int ret;
183
184 ret = of_property_read_u32(node, "ti,external-sleep-control",
185 &prop);
186 if (ret)
187 return;
188
189 switch (prop) {
190 case PALMAS_CLOCK_DT_EXT_CONTROL_ENABLE1:
191 prop = PALMAS_EXT_CONTROL_ENABLE1;
192 break;
193 case PALMAS_CLOCK_DT_EXT_CONTROL_ENABLE2:
194 prop = PALMAS_EXT_CONTROL_ENABLE2;
195 break;
196 case PALMAS_CLOCK_DT_EXT_CONTROL_NSLEEP:
197 prop = PALMAS_EXT_CONTROL_NSLEEP;
198 break;
199 default:
200 dev_warn(&pdev->dev, "%s: Invalid ext control option: %u\n",
201 node->name, prop);
202 prop = 0;
203 break;
204 }
205 cinfo->ext_control_pin = prop;
206}
207
208static int palmas_clks_init_configure(struct palmas_clock_info *cinfo)
209{
210 int ret;
211
212 ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE,
213 cinfo->clk_desc->control_reg,
214 cinfo->clk_desc->sleep_mask, 0);
215 if (ret < 0) {
216 dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n",
217 cinfo->clk_desc->control_reg, ret);
218 return ret;
219 }
220
221 if (cinfo->ext_control_pin) {
222 ret = clk_prepare(cinfo->clk);
223 if (ret < 0) {
224 dev_err(cinfo->dev, "Clock prep failed, %d\n", ret);
225 return ret;
226 }
227
228 ret = palmas_ext_control_req_config(cinfo->palmas,
229 cinfo->clk_desc->sleep_reqstr_id,
230 cinfo->ext_control_pin, true);
231 if (ret < 0) {
232 dev_err(cinfo->dev, "Ext config for %s failed, %d\n",
233 cinfo->clk_desc->clk_name, ret);
234 return ret;
235 }
236 }
237
238 return ret;
239}
240static int palmas_clks_probe(struct platform_device *pdev)
241{
242 struct palmas *palmas = dev_get_drvdata(pdev->dev.parent);
243 struct device_node *node = pdev->dev.of_node;
244 struct palmas_clks_of_match_data *match_data;
245 const struct of_device_id *match;
246 struct palmas_clock_info *cinfo;
247 struct clk *clk;
248 int ret;
249
250 match = of_match_device(palmas_clks_of_match, &pdev->dev);
251 match_data = (struct palmas_clks_of_match_data *)match->data;
252
253 cinfo = devm_kzalloc(&pdev->dev, sizeof(*cinfo), GFP_KERNEL);
254 if (!cinfo)
255 return -ENOMEM;
256
257 palmas_clks_get_clk_data(pdev, cinfo);
258 platform_set_drvdata(pdev, cinfo);
259
260 cinfo->dev = &pdev->dev;
261 cinfo->palmas = palmas;
262
263 cinfo->clk_desc = &match_data->desc;
264 cinfo->hw.init = &match_data->init;
265 clk = devm_clk_register(&pdev->dev, &cinfo->hw);
266 if (IS_ERR(clk)) {
267 ret = PTR_ERR(clk);
268 dev_err(&pdev->dev, "Fail to register clock %s, %d\n",
269 match_data->desc.clk_name, ret);
270 return ret;
271 }
272
273 cinfo->clk = clk;
274 ret = palmas_clks_init_configure(cinfo);
275 if (ret < 0) {
276 dev_err(&pdev->dev, "Clock config failed, %d\n", ret);
277 return ret;
278 }
279
280 ret = of_clk_add_provider(node, of_clk_src_simple_get, cinfo->clk);
281 if (ret < 0)
282 dev_err(&pdev->dev, "Fail to add clock driver, %d\n", ret);
283 return ret;
284}
285
286static int palmas_clks_remove(struct platform_device *pdev)
287{
288 of_clk_del_provider(pdev->dev.of_node);
289 return 0;
290}
291
292static struct platform_driver palmas_clks_driver = {
293 .driver = {
294 .name = "palmas-clk",
295 .owner = THIS_MODULE,
296 .of_match_table = palmas_clks_of_match,
297 },
298 .probe = palmas_clks_probe,
299 .remove = palmas_clks_remove,
300};
301
302module_platform_driver(palmas_clks_driver);
303
304MODULE_DESCRIPTION("Clock driver for Palmas Series Devices");
305MODULE_ALIAS("platform:palmas-clk");
306MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
307MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-ppc-corenet.c
index 8b284be4efa4..8e58edfeeb37 100644
--- a/drivers/clk/clk-ppc-corenet.c
+++ b/drivers/clk/clk-ppc-corenet.c
@@ -291,7 +291,7 @@ static const struct of_device_id ppc_clk_ids[] __initconst = {
291 {} 291 {}
292}; 292};
293 293
294static struct platform_driver ppc_corenet_clk_driver = { 294static struct platform_driver ppc_corenet_clk_driver __initdata = {
295 .driver = { 295 .driver = {
296 .name = "ppc_corenet_clock", 296 .name = "ppc_corenet_clock",
297 .owner = THIS_MODULE, 297 .owner = THIS_MODULE,
diff --git a/drivers/clk/clk-s2mps11.c b/drivers/clk/clk-s2mps11.c
index 3757e9e72d37..b7797fb12e12 100644
--- a/drivers/clk/clk-s2mps11.c
+++ b/drivers/clk/clk-s2mps11.c
@@ -46,7 +46,6 @@ struct s2mps11_clk {
46 struct clk *clk; 46 struct clk *clk;
47 struct clk_lookup *lookup; 47 struct clk_lookup *lookup;
48 u32 mask; 48 u32 mask;
49 bool enabled;
50 unsigned int reg; 49 unsigned int reg;
51}; 50};
52 51
@@ -63,8 +62,6 @@ static int s2mps11_clk_prepare(struct clk_hw *hw)
63 ret = regmap_update_bits(s2mps11->iodev->regmap_pmic, 62 ret = regmap_update_bits(s2mps11->iodev->regmap_pmic,
64 s2mps11->reg, 63 s2mps11->reg,
65 s2mps11->mask, s2mps11->mask); 64 s2mps11->mask, s2mps11->mask);
66 if (!ret)
67 s2mps11->enabled = true;
68 65
69 return ret; 66 return ret;
70} 67}
@@ -76,32 +73,32 @@ static void s2mps11_clk_unprepare(struct clk_hw *hw)
76 73
77 ret = regmap_update_bits(s2mps11->iodev->regmap_pmic, s2mps11->reg, 74 ret = regmap_update_bits(s2mps11->iodev->regmap_pmic, s2mps11->reg,
78 s2mps11->mask, ~s2mps11->mask); 75 s2mps11->mask, ~s2mps11->mask);
79
80 if (!ret)
81 s2mps11->enabled = false;
82} 76}
83 77
84static int s2mps11_clk_is_enabled(struct clk_hw *hw) 78static int s2mps11_clk_is_prepared(struct clk_hw *hw)
85{ 79{
80 int ret;
81 u32 val;
86 struct s2mps11_clk *s2mps11 = to_s2mps11_clk(hw); 82 struct s2mps11_clk *s2mps11 = to_s2mps11_clk(hw);
87 83
88 return s2mps11->enabled; 84 ret = regmap_read(s2mps11->iodev->regmap_pmic,
85 s2mps11->reg, &val);
86 if (ret < 0)
87 return -EINVAL;
88
89 return val & s2mps11->mask;
89} 90}
90 91
91static unsigned long s2mps11_clk_recalc_rate(struct clk_hw *hw, 92static unsigned long s2mps11_clk_recalc_rate(struct clk_hw *hw,
92 unsigned long parent_rate) 93 unsigned long parent_rate)
93{ 94{
94 struct s2mps11_clk *s2mps11 = to_s2mps11_clk(hw); 95 return 32768;
95 if (s2mps11->enabled)
96 return 32768;
97 else
98 return 0;
99} 96}
100 97
101static struct clk_ops s2mps11_clk_ops = { 98static struct clk_ops s2mps11_clk_ops = {
102 .prepare = s2mps11_clk_prepare, 99 .prepare = s2mps11_clk_prepare,
103 .unprepare = s2mps11_clk_unprepare, 100 .unprepare = s2mps11_clk_unprepare,
104 .is_enabled = s2mps11_clk_is_enabled, 101 .is_prepared = s2mps11_clk_is_prepared,
105 .recalc_rate = s2mps11_clk_recalc_rate, 102 .recalc_rate = s2mps11_clk_recalc_rate,
106}; 103};
107 104
@@ -169,7 +166,6 @@ static int s2mps11_clk_probe(struct platform_device *pdev)
169 unsigned int s2mps11_reg; 166 unsigned int s2mps11_reg;
170 struct clk_init_data *clks_init; 167 struct clk_init_data *clks_init;
171 int i, ret = 0; 168 int i, ret = 0;
172 u32 val;
173 169
174 s2mps11_clks = devm_kzalloc(&pdev->dev, sizeof(*s2mps11_clk) * 170 s2mps11_clks = devm_kzalloc(&pdev->dev, sizeof(*s2mps11_clk) *
175 S2MPS11_CLKS_NUM, GFP_KERNEL); 171 S2MPS11_CLKS_NUM, GFP_KERNEL);
@@ -214,13 +210,6 @@ static int s2mps11_clk_probe(struct platform_device *pdev)
214 s2mps11_clk->mask = 1 << i; 210 s2mps11_clk->mask = 1 << i;
215 s2mps11_clk->reg = s2mps11_reg; 211 s2mps11_clk->reg = s2mps11_reg;
216 212
217 ret = regmap_read(s2mps11_clk->iodev->regmap_pmic,
218 s2mps11_clk->reg, &val);
219 if (ret < 0)
220 goto err_reg;
221
222 s2mps11_clk->enabled = val & s2mps11_clk->mask;
223
224 s2mps11_clk->clk = devm_clk_register(&pdev->dev, 213 s2mps11_clk->clk = devm_clk_register(&pdev->dev,
225 &s2mps11_clk->hw); 214 &s2mps11_clk->hw);
226 if (IS_ERR(s2mps11_clk->clk)) { 215 if (IS_ERR(s2mps11_clk->clk)) {
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 8b73edef151d..b76fa69b44cb 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -10,6 +10,7 @@
10 */ 10 */
11 11
12#include <linux/clk-private.h> 12#include <linux/clk-private.h>
13#include <linux/clk/clk-conf.h>
13#include <linux/module.h> 14#include <linux/module.h>
14#include <linux/mutex.h> 15#include <linux/mutex.h>
15#include <linux/spinlock.h> 16#include <linux/spinlock.h>
@@ -98,9 +99,19 @@ static void clk_enable_unlock(unsigned long flags)
98#include <linux/debugfs.h> 99#include <linux/debugfs.h>
99 100
100static struct dentry *rootdir; 101static struct dentry *rootdir;
101static struct dentry *orphandir;
102static int inited = 0; 102static int inited = 0;
103 103
104static struct hlist_head *all_lists[] = {
105 &clk_root_list,
106 &clk_orphan_list,
107 NULL,
108};
109
110static struct hlist_head *orphan_list[] = {
111 &clk_orphan_list,
112 NULL,
113};
114
104static void clk_summary_show_one(struct seq_file *s, struct clk *c, int level) 115static void clk_summary_show_one(struct seq_file *s, struct clk *c, int level)
105{ 116{
106 if (!c) 117 if (!c)
@@ -130,17 +141,16 @@ static void clk_summary_show_subtree(struct seq_file *s, struct clk *c,
130static int clk_summary_show(struct seq_file *s, void *data) 141static int clk_summary_show(struct seq_file *s, void *data)
131{ 142{
132 struct clk *c; 143 struct clk *c;
144 struct hlist_head **lists = (struct hlist_head **)s->private;
133 145
134 seq_puts(s, " clock enable_cnt prepare_cnt rate accuracy\n"); 146 seq_puts(s, " clock enable_cnt prepare_cnt rate accuracy\n");
135 seq_puts(s, "--------------------------------------------------------------------------------\n"); 147 seq_puts(s, "--------------------------------------------------------------------------------\n");
136 148
137 clk_prepare_lock(); 149 clk_prepare_lock();
138 150
139 hlist_for_each_entry(c, &clk_root_list, child_node) 151 for (; *lists; lists++)
140 clk_summary_show_subtree(s, c, 0); 152 hlist_for_each_entry(c, *lists, child_node)
141 153 clk_summary_show_subtree(s, c, 0);
142 hlist_for_each_entry(c, &clk_orphan_list, child_node)
143 clk_summary_show_subtree(s, c, 0);
144 154
145 clk_prepare_unlock(); 155 clk_prepare_unlock();
146 156
@@ -193,21 +203,19 @@ static int clk_dump(struct seq_file *s, void *data)
193{ 203{
194 struct clk *c; 204 struct clk *c;
195 bool first_node = true; 205 bool first_node = true;
206 struct hlist_head **lists = (struct hlist_head **)s->private;
196 207
197 seq_printf(s, "{"); 208 seq_printf(s, "{");
198 209
199 clk_prepare_lock(); 210 clk_prepare_lock();
200 211
201 hlist_for_each_entry(c, &clk_root_list, child_node) { 212 for (; *lists; lists++) {
202 if (!first_node) 213 hlist_for_each_entry(c, *lists, child_node) {
203 seq_printf(s, ","); 214 if (!first_node)
204 first_node = false; 215 seq_puts(s, ",");
205 clk_dump_subtree(s, c, 0); 216 first_node = false;
206 } 217 clk_dump_subtree(s, c, 0);
207 218 }
208 hlist_for_each_entry(c, &clk_orphan_list, child_node) {
209 seq_printf(s, ",");
210 clk_dump_subtree(s, c, 0);
211 } 219 }
212 220
213 clk_prepare_unlock(); 221 clk_prepare_unlock();
@@ -276,9 +284,11 @@ static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry)
276 if (!d) 284 if (!d)
277 goto err_out; 285 goto err_out;
278 286
279 if (clk->ops->debug_init) 287 if (clk->ops->debug_init) {
280 if (clk->ops->debug_init(clk->hw, clk->dentry)) 288 ret = clk->ops->debug_init(clk->hw, clk->dentry);
289 if (ret)
281 goto err_out; 290 goto err_out;
291 }
282 292
283 ret = 0; 293 ret = 0;
284 goto out; 294 goto out;
@@ -305,7 +315,7 @@ static int clk_debug_create_subtree(struct clk *clk, struct dentry *pdentry)
305 goto out; 315 goto out;
306 316
307 hlist_for_each_entry(child, &clk->children, child_node) 317 hlist_for_each_entry(child, &clk->children, child_node)
308 clk_debug_create_subtree(child, clk->dentry); 318 clk_debug_create_subtree(child, pdentry);
309 319
310 ret = 0; 320 ret = 0;
311out: 321out:
@@ -325,31 +335,12 @@ out:
325 */ 335 */
326static int clk_debug_register(struct clk *clk) 336static int clk_debug_register(struct clk *clk)
327{ 337{
328 struct clk *parent;
329 struct dentry *pdentry;
330 int ret = 0; 338 int ret = 0;
331 339
332 if (!inited) 340 if (!inited)
333 goto out; 341 goto out;
334 342
335 parent = clk->parent; 343 ret = clk_debug_create_subtree(clk, rootdir);
336
337 /*
338 * Check to see if a clk is a root clk. Also check that it is
339 * safe to add this clk to debugfs
340 */
341 if (!parent)
342 if (clk->flags & CLK_IS_ROOT)
343 pdentry = rootdir;
344 else
345 pdentry = orphandir;
346 else
347 if (parent->dentry)
348 pdentry = parent->dentry;
349 else
350 goto out;
351
352 ret = clk_debug_create_subtree(clk, pdentry);
353 344
354out: 345out:
355 return ret; 346 return ret;
@@ -370,38 +361,17 @@ static void clk_debug_unregister(struct clk *clk)
370 debugfs_remove_recursive(clk->dentry); 361 debugfs_remove_recursive(clk->dentry);
371} 362}
372 363
373/** 364struct dentry *clk_debugfs_add_file(struct clk *clk, char *name, umode_t mode,
374 * clk_debug_reparent - reparent clk node in the debugfs clk tree 365 void *data, const struct file_operations *fops)
375 * @clk: the clk being reparented
376 * @new_parent: the new clk parent, may be NULL
377 *
378 * Rename clk entry in the debugfs clk tree if debugfs has been
379 * initialized. Otherwise it bails out early since the debugfs clk tree
380 * will be created lazily by clk_debug_init as part of a late_initcall.
381 *
382 * Caller must hold prepare_lock.
383 */
384static void clk_debug_reparent(struct clk *clk, struct clk *new_parent)
385{ 366{
386 struct dentry *d; 367 struct dentry *d = NULL;
387 struct dentry *new_parent_d;
388
389 if (!inited)
390 return;
391 368
392 if (new_parent) 369 if (clk->dentry)
393 new_parent_d = new_parent->dentry; 370 d = debugfs_create_file(name, mode, clk->dentry, data, fops);
394 else
395 new_parent_d = orphandir;
396 371
397 d = debugfs_rename(clk->dentry->d_parent, clk->dentry, 372 return d;
398 new_parent_d, clk->name);
399 if (d)
400 clk->dentry = d;
401 else
402 pr_debug("%s: failed to rename debugfs entry for %s\n",
403 __func__, clk->name);
404} 373}
374EXPORT_SYMBOL_GPL(clk_debugfs_add_file);
405 375
406/** 376/**
407 * clk_debug_init - lazily create the debugfs clk tree visualization 377 * clk_debug_init - lazily create the debugfs clk tree visualization
@@ -425,19 +395,24 @@ static int __init clk_debug_init(void)
425 if (!rootdir) 395 if (!rootdir)
426 return -ENOMEM; 396 return -ENOMEM;
427 397
428 d = debugfs_create_file("clk_summary", S_IRUGO, rootdir, NULL, 398 d = debugfs_create_file("clk_summary", S_IRUGO, rootdir, &all_lists,
429 &clk_summary_fops); 399 &clk_summary_fops);
430 if (!d) 400 if (!d)
431 return -ENOMEM; 401 return -ENOMEM;
432 402
433 d = debugfs_create_file("clk_dump", S_IRUGO, rootdir, NULL, 403 d = debugfs_create_file("clk_dump", S_IRUGO, rootdir, &all_lists,
434 &clk_dump_fops); 404 &clk_dump_fops);
435 if (!d) 405 if (!d)
436 return -ENOMEM; 406 return -ENOMEM;
437 407
438 orphandir = debugfs_create_dir("orphans", rootdir); 408 d = debugfs_create_file("clk_orphan_summary", S_IRUGO, rootdir,
409 &orphan_list, &clk_summary_fops);
410 if (!d)
411 return -ENOMEM;
439 412
440 if (!orphandir) 413 d = debugfs_create_file("clk_orphan_dump", S_IRUGO, rootdir,
414 &orphan_list, &clk_dump_fops);
415 if (!d)
441 return -ENOMEM; 416 return -ENOMEM;
442 417
443 clk_prepare_lock(); 418 clk_prepare_lock();
@@ -446,7 +421,7 @@ static int __init clk_debug_init(void)
446 clk_debug_create_subtree(clk, rootdir); 421 clk_debug_create_subtree(clk, rootdir);
447 422
448 hlist_for_each_entry(clk, &clk_orphan_list, child_node) 423 hlist_for_each_entry(clk, &clk_orphan_list, child_node)
449 clk_debug_create_subtree(clk, orphandir); 424 clk_debug_create_subtree(clk, rootdir);
450 425
451 inited = 1; 426 inited = 1;
452 427
@@ -1284,9 +1259,6 @@ static void __clk_set_parent_after(struct clk *clk, struct clk *parent,
1284 clk_disable(old_parent); 1259 clk_disable(old_parent);
1285 __clk_unprepare(old_parent); 1260 __clk_unprepare(old_parent);
1286 } 1261 }
1287
1288 /* update debugfs with new clk tree topology */
1289 clk_debug_reparent(clk, parent);
1290} 1262}
1291 1263
1292static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index) 1264static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index)
@@ -1683,7 +1655,6 @@ out:
1683void __clk_reparent(struct clk *clk, struct clk *new_parent) 1655void __clk_reparent(struct clk *clk, struct clk *new_parent)
1684{ 1656{
1685 clk_reparent(clk, new_parent); 1657 clk_reparent(clk, new_parent);
1686 clk_debug_reparent(clk, new_parent);
1687 __clk_recalc_accuracies(clk); 1658 __clk_recalc_accuracies(clk);
1688 __clk_recalc_rates(clk, POST_RATE_CHANGE); 1659 __clk_recalc_rates(clk, POST_RATE_CHANGE);
1689} 1660}
@@ -2414,6 +2385,7 @@ int of_clk_add_provider(struct device_node *np,
2414 void *data) 2385 void *data)
2415{ 2386{
2416 struct of_clk_provider *cp; 2387 struct of_clk_provider *cp;
2388 int ret;
2417 2389
2418 cp = kzalloc(sizeof(struct of_clk_provider), GFP_KERNEL); 2390 cp = kzalloc(sizeof(struct of_clk_provider), GFP_KERNEL);
2419 if (!cp) 2391 if (!cp)
@@ -2428,7 +2400,11 @@ int of_clk_add_provider(struct device_node *np,
2428 mutex_unlock(&of_clk_mutex); 2400 mutex_unlock(&of_clk_mutex);
2429 pr_debug("Added clock from %s\n", np->full_name); 2401 pr_debug("Added clock from %s\n", np->full_name);
2430 2402
2431 return 0; 2403 ret = of_clk_set_defaults(np, true);
2404 if (ret < 0)
2405 of_clk_del_provider(np);
2406
2407 return ret;
2432} 2408}
2433EXPORT_SYMBOL_GPL(of_clk_add_provider); 2409EXPORT_SYMBOL_GPL(of_clk_add_provider);
2434 2410
@@ -2605,7 +2581,10 @@ void __init of_clk_init(const struct of_device_id *matches)
2605 list_for_each_entry_safe(clk_provider, next, 2581 list_for_each_entry_safe(clk_provider, next,
2606 &clk_provider_list, node) { 2582 &clk_provider_list, node) {
2607 if (force || parent_ready(clk_provider->np)) { 2583 if (force || parent_ready(clk_provider->np)) {
2584
2608 clk_provider->clk_init_cb(clk_provider->np); 2585 clk_provider->clk_init_cb(clk_provider->np);
2586 of_clk_set_defaults(clk_provider->np, true);
2587
2609 list_del(&clk_provider->node); 2588 list_del(&clk_provider->node);
2610 kfree(clk_provider); 2589 kfree(clk_provider);
2611 is_init_done = true; 2590 is_init_done = true;
@@ -2620,7 +2599,6 @@ void __init of_clk_init(const struct of_device_id *matches)
2620 */ 2599 */
2621 if (!is_init_done) 2600 if (!is_init_done)
2622 force = true; 2601 force = true;
2623
2624 } 2602 }
2625} 2603}
2626#endif 2604#endif
diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index f890b901c6bc..da4bda8b7fc7 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -101,8 +101,9 @@ struct clk *of_clk_get_by_name(struct device_node *np, const char *name)
101 if (!IS_ERR(clk)) 101 if (!IS_ERR(clk))
102 break; 102 break;
103 else if (name && index >= 0) { 103 else if (name && index >= 0) {
104 pr_err("ERROR: could not get clock %s:%s(%i)\n", 104 if (PTR_ERR(clk) != -EPROBE_DEFER)
105 np->full_name, name ? name : "", index); 105 pr_err("ERROR: could not get clock %s:%s(%i)\n",
106 np->full_name, name ? name : "", index);
106 return clk; 107 return clk;
107 } 108 }
108 109
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 7f696b7d4422..1107351ed346 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -4,6 +4,31 @@ config COMMON_CLK_QCOM
4 select REGMAP_MMIO 4 select REGMAP_MMIO
5 select RESET_CONTROLLER 5 select RESET_CONTROLLER
6 6
7config APQ_GCC_8084
8 tristate "APQ8084 Global Clock Controller"
9 depends on COMMON_CLK_QCOM
10 help
11 Support for the global clock controller on apq8084 devices.
12 Say Y if you want to use peripheral devices such as UART, SPI,
13 i2c, USB, SD/eMMC, SATA, PCIe, etc.
14
15config APQ_MMCC_8084
16 tristate "APQ8084 Multimedia Clock Controller"
17 select APQ_GCC_8084
18 depends on COMMON_CLK_QCOM
19 help
20 Support for the multimedia clock controller on apq8084 devices.
21 Say Y if you want to support multimedia devices such as display,
22 graphics, video encode/decode, camera, etc.
23
24config IPQ_GCC_806X
25 tristate "IPQ806x Global Clock Controller"
26 depends on COMMON_CLK_QCOM
27 help
28 Support for the global clock controller on ipq806x devices.
29 Say Y if you want to use peripheral devices such as UART, SPI,
30 i2c, USB, SD/eMMC, etc.
31
7config MSM_GCC_8660 32config MSM_GCC_8660
8 tristate "MSM8660 Global Clock Controller" 33 tristate "MSM8660 Global Clock Controller"
9 depends on COMMON_CLK_QCOM 34 depends on COMMON_CLK_QCOM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 689e05bf4f95..783cfb24faa4 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -8,6 +8,9 @@ clk-qcom-y += clk-rcg2.o
8clk-qcom-y += clk-branch.o 8clk-qcom-y += clk-branch.o
9clk-qcom-y += reset.o 9clk-qcom-y += reset.o
10 10
11obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
12obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
13obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
11obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o 14obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o
12obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o 15obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
13obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o 16obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
diff --git a/drivers/clk/qcom/clk-pll.c b/drivers/clk/qcom/clk-pll.c
index 0f927c538613..9db03d3b1657 100644
--- a/drivers/clk/qcom/clk-pll.c
+++ b/drivers/clk/qcom/clk-pll.c
@@ -166,7 +166,7 @@ const struct clk_ops clk_pll_vote_ops = {
166EXPORT_SYMBOL_GPL(clk_pll_vote_ops); 166EXPORT_SYMBOL_GPL(clk_pll_vote_ops);
167 167
168static void 168static void
169clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap) 169clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap, u8 lock_count)
170{ 170{
171 u32 val; 171 u32 val;
172 u32 mask; 172 u32 mask;
@@ -175,7 +175,7 @@ clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap)
175 regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_RESET, 0); 175 regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_RESET, 0);
176 176
177 /* Program bias count and lock count */ 177 /* Program bias count and lock count */
178 val = 1 << PLL_BIAS_COUNT_SHIFT; 178 val = 1 << PLL_BIAS_COUNT_SHIFT | lock_count << PLL_LOCK_COUNT_SHIFT;
179 mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT; 179 mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
180 mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT; 180 mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
181 regmap_update_bits(regmap, pll->mode_reg, mask, val); 181 regmap_update_bits(regmap, pll->mode_reg, mask, val);
@@ -212,11 +212,20 @@ static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,
212 regmap_update_bits(regmap, pll->config_reg, mask, val); 212 regmap_update_bits(regmap, pll->config_reg, mask, val);
213} 213}
214 214
215void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
216 const struct pll_config *config, bool fsm_mode)
217{
218 clk_pll_configure(pll, regmap, config);
219 if (fsm_mode)
220 clk_pll_set_fsm_mode(pll, regmap, 8);
221}
222EXPORT_SYMBOL_GPL(clk_pll_configure_sr);
223
215void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap, 224void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
216 const struct pll_config *config, bool fsm_mode) 225 const struct pll_config *config, bool fsm_mode)
217{ 226{
218 clk_pll_configure(pll, regmap, config); 227 clk_pll_configure(pll, regmap, config);
219 if (fsm_mode) 228 if (fsm_mode)
220 clk_pll_set_fsm_mode(pll, regmap); 229 clk_pll_set_fsm_mode(pll, regmap, 0);
221} 230}
222EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp); 231EXPORT_SYMBOL_GPL(clk_pll_configure_sr_hpm_lp);
diff --git a/drivers/clk/qcom/clk-pll.h b/drivers/clk/qcom/clk-pll.h
index 0775a99ca768..3003e9962472 100644
--- a/drivers/clk/qcom/clk-pll.h
+++ b/drivers/clk/qcom/clk-pll.h
@@ -60,6 +60,8 @@ struct pll_config {
60 u32 aux_output_mask; 60 u32 aux_output_mask;
61}; 61};
62 62
63void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,
64 const struct pll_config *config, bool fsm_mode);
63void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap, 65void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,
64 const struct pll_config *config, bool fsm_mode); 66 const struct pll_config *config, bool fsm_mode);
65 67
diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c
index abfc2b675aea..b638c5846dbf 100644
--- a/drivers/clk/qcom/clk-rcg.c
+++ b/drivers/clk/qcom/clk-rcg.c
@@ -417,20 +417,25 @@ static long clk_dyn_rcg_determine_rate(struct clk_hw *hw, unsigned long rate,
417 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p); 417 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p);
418} 418}
419 419
420static int clk_rcg_set_rate(struct clk_hw *hw, unsigned long rate, 420static long clk_rcg_bypass_determine_rate(struct clk_hw *hw, unsigned long rate,
421 unsigned long parent_rate) 421 unsigned long *p_rate, struct clk **p)
422{ 422{
423 struct clk_rcg *rcg = to_clk_rcg(hw); 423 struct clk_rcg *rcg = to_clk_rcg(hw);
424 const struct freq_tbl *f; 424 const struct freq_tbl *f = rcg->freq_tbl;
425
426 *p = clk_get_parent_by_index(hw->clk, f->src);
427 *p_rate = __clk_round_rate(*p, rate);
428
429 return *p_rate;
430}
431
432static int __clk_rcg_set_rate(struct clk_rcg *rcg, const struct freq_tbl *f)
433{
425 u32 ns, md, ctl; 434 u32 ns, md, ctl;
426 struct mn *mn = &rcg->mn; 435 struct mn *mn = &rcg->mn;
427 u32 mask = 0; 436 u32 mask = 0;
428 unsigned int reset_reg; 437 unsigned int reset_reg;
429 438
430 f = find_freq(rcg->freq_tbl, rate);
431 if (!f)
432 return -EINVAL;
433
434 if (rcg->mn.reset_in_cc) 439 if (rcg->mn.reset_in_cc)
435 reset_reg = rcg->clkr.enable_reg; 440 reset_reg = rcg->clkr.enable_reg;
436 else 441 else
@@ -466,6 +471,27 @@ static int clk_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
466 return 0; 471 return 0;
467} 472}
468 473
474static int clk_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
475 unsigned long parent_rate)
476{
477 struct clk_rcg *rcg = to_clk_rcg(hw);
478 const struct freq_tbl *f;
479
480 f = find_freq(rcg->freq_tbl, rate);
481 if (!f)
482 return -EINVAL;
483
484 return __clk_rcg_set_rate(rcg, f);
485}
486
487static int clk_rcg_bypass_set_rate(struct clk_hw *hw, unsigned long rate,
488 unsigned long parent_rate)
489{
490 struct clk_rcg *rcg = to_clk_rcg(hw);
491
492 return __clk_rcg_set_rate(rcg, rcg->freq_tbl);
493}
494
469static int __clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate) 495static int __clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate)
470{ 496{
471 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw); 497 struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
@@ -503,6 +529,17 @@ const struct clk_ops clk_rcg_ops = {
503}; 529};
504EXPORT_SYMBOL_GPL(clk_rcg_ops); 530EXPORT_SYMBOL_GPL(clk_rcg_ops);
505 531
532const struct clk_ops clk_rcg_bypass_ops = {
533 .enable = clk_enable_regmap,
534 .disable = clk_disable_regmap,
535 .get_parent = clk_rcg_get_parent,
536 .set_parent = clk_rcg_set_parent,
537 .recalc_rate = clk_rcg_recalc_rate,
538 .determine_rate = clk_rcg_bypass_determine_rate,
539 .set_rate = clk_rcg_bypass_set_rate,
540};
541EXPORT_SYMBOL_GPL(clk_rcg_bypass_ops);
542
506const struct clk_ops clk_dyn_rcg_ops = { 543const struct clk_ops clk_dyn_rcg_ops = {
507 .enable = clk_enable_regmap, 544 .enable = clk_enable_regmap,
508 .is_enabled = clk_is_enabled_regmap, 545 .is_enabled = clk_is_enabled_regmap,
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index b9ec11dfd1b4..ba0523cefd2e 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -95,6 +95,7 @@ struct clk_rcg {
95}; 95};
96 96
97extern const struct clk_ops clk_rcg_ops; 97extern const struct clk_ops clk_rcg_ops;
98extern const struct clk_ops clk_rcg_bypass_ops;
98 99
99#define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr) 100#define to_clk_rcg(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg, clkr)
100 101
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index 9b5a1cfc6b91..eeb3eea01f4c 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -27,30 +27,35 @@ struct qcom_cc {
27 struct clk *clks[]; 27 struct clk *clks[];
28}; 28};
29 29
30int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc) 30struct regmap *
31qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc)
31{ 32{
32 void __iomem *base; 33 void __iomem *base;
33 struct resource *res; 34 struct resource *res;
35 struct device *dev = &pdev->dev;
36
37 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
38 base = devm_ioremap_resource(dev, res);
39 if (IS_ERR(base))
40 return ERR_CAST(base);
41
42 return devm_regmap_init_mmio(dev, base, desc->config);
43}
44EXPORT_SYMBOL_GPL(qcom_cc_map);
45
46int qcom_cc_really_probe(struct platform_device *pdev,
47 const struct qcom_cc_desc *desc, struct regmap *regmap)
48{
34 int i, ret; 49 int i, ret;
35 struct device *dev = &pdev->dev; 50 struct device *dev = &pdev->dev;
36 struct clk *clk; 51 struct clk *clk;
37 struct clk_onecell_data *data; 52 struct clk_onecell_data *data;
38 struct clk **clks; 53 struct clk **clks;
39 struct regmap *regmap;
40 struct qcom_reset_controller *reset; 54 struct qcom_reset_controller *reset;
41 struct qcom_cc *cc; 55 struct qcom_cc *cc;
42 size_t num_clks = desc->num_clks; 56 size_t num_clks = desc->num_clks;
43 struct clk_regmap **rclks = desc->clks; 57 struct clk_regmap **rclks = desc->clks;
44 58
45 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
46 base = devm_ioremap_resource(dev, res);
47 if (IS_ERR(base))
48 return PTR_ERR(base);
49
50 regmap = devm_regmap_init_mmio(dev, base, desc->config);
51 if (IS_ERR(regmap))
52 return PTR_ERR(regmap);
53
54 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks, 59 cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
55 GFP_KERNEL); 60 GFP_KERNEL);
56 if (!cc) 61 if (!cc)
@@ -91,6 +96,18 @@ int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
91 96
92 return ret; 97 return ret;
93} 98}
99EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
100
101int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
102{
103 struct regmap *regmap;
104
105 regmap = qcom_cc_map(pdev, desc);
106 if (IS_ERR(regmap))
107 return PTR_ERR(regmap);
108
109 return qcom_cc_really_probe(pdev, desc, regmap);
110}
94EXPORT_SYMBOL_GPL(qcom_cc_probe); 111EXPORT_SYMBOL_GPL(qcom_cc_probe);
95 112
96void qcom_cc_remove(struct platform_device *pdev) 113void qcom_cc_remove(struct platform_device *pdev)
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
index 2c3cfc860348..2765e9d3da97 100644
--- a/drivers/clk/qcom/common.h
+++ b/drivers/clk/qcom/common.h
@@ -17,6 +17,7 @@ struct platform_device;
17struct regmap_config; 17struct regmap_config;
18struct clk_regmap; 18struct clk_regmap;
19struct qcom_reset_map; 19struct qcom_reset_map;
20struct regmap;
20 21
21struct qcom_cc_desc { 22struct qcom_cc_desc {
22 const struct regmap_config *config; 23 const struct regmap_config *config;
@@ -26,6 +27,11 @@ struct qcom_cc_desc {
26 size_t num_resets; 27 size_t num_resets;
27}; 28};
28 29
30extern struct regmap *qcom_cc_map(struct platform_device *pdev,
31 const struct qcom_cc_desc *desc);
32extern int qcom_cc_really_probe(struct platform_device *pdev,
33 const struct qcom_cc_desc *desc,
34 struct regmap *regmap);
29extern int qcom_cc_probe(struct platform_device *pdev, 35extern int qcom_cc_probe(struct platform_device *pdev,
30 const struct qcom_cc_desc *desc); 36 const struct qcom_cc_desc *desc);
31 37
diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
new file mode 100644
index 000000000000..ee52eb1c838a
--- /dev/null
+++ b/drivers/clk/qcom/gcc-apq8084.c
@@ -0,0 +1,3611 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/clk-provider.h>
22#include <linux/regmap.h>
23#include <linux/reset-controller.h>
24
25#include <dt-bindings/clock/qcom,gcc-apq8084.h>
26#include <dt-bindings/reset/qcom,gcc-apq8084.h>
27
28#include "common.h"
29#include "clk-regmap.h"
30#include "clk-pll.h"
31#include "clk-rcg.h"
32#include "clk-branch.h"
33#include "reset.h"
34
35#define P_XO 0
36#define P_GPLL0 1
37#define P_GPLL1 1
38#define P_GPLL4 2
39#define P_PCIE_0_1_PIPE_CLK 1
40#define P_SATA_ASIC0_CLK 1
41#define P_SATA_RX_CLK 1
42#define P_SLEEP_CLK 1
43
44static const u8 gcc_xo_gpll0_map[] = {
45 [P_XO] = 0,
46 [P_GPLL0] = 1,
47};
48
49static const char *gcc_xo_gpll0[] = {
50 "xo",
51 "gpll0_vote",
52};
53
54static const u8 gcc_xo_gpll0_gpll4_map[] = {
55 [P_XO] = 0,
56 [P_GPLL0] = 1,
57 [P_GPLL4] = 5,
58};
59
60static const char *gcc_xo_gpll0_gpll4[] = {
61 "xo",
62 "gpll0_vote",
63 "gpll4_vote",
64};
65
66static const u8 gcc_xo_sata_asic0_map[] = {
67 [P_XO] = 0,
68 [P_SATA_ASIC0_CLK] = 2,
69};
70
71static const char *gcc_xo_sata_asic0[] = {
72 "xo",
73 "sata_asic0_clk",
74};
75
76static const u8 gcc_xo_sata_rx_map[] = {
77 [P_XO] = 0,
78 [P_SATA_RX_CLK] = 2,
79};
80
81static const char *gcc_xo_sata_rx[] = {
82 "xo",
83 "sata_rx_clk",
84};
85
86static const u8 gcc_xo_pcie_map[] = {
87 [P_XO] = 0,
88 [P_PCIE_0_1_PIPE_CLK] = 2,
89};
90
91static const char *gcc_xo_pcie[] = {
92 "xo",
93 "pcie_pipe",
94};
95
96static const u8 gcc_xo_pcie_sleep_map[] = {
97 [P_XO] = 0,
98 [P_SLEEP_CLK] = 6,
99};
100
101static const char *gcc_xo_pcie_sleep[] = {
102 "xo",
103 "sleep_clk_src",
104};
105
106#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
107
108static struct clk_pll gpll0 = {
109 .l_reg = 0x0004,
110 .m_reg = 0x0008,
111 .n_reg = 0x000c,
112 .config_reg = 0x0014,
113 .mode_reg = 0x0000,
114 .status_reg = 0x001c,
115 .status_bit = 17,
116 .clkr.hw.init = &(struct clk_init_data){
117 .name = "gpll0",
118 .parent_names = (const char *[]){ "xo" },
119 .num_parents = 1,
120 .ops = &clk_pll_ops,
121 },
122};
123
124static struct clk_regmap gpll0_vote = {
125 .enable_reg = 0x1480,
126 .enable_mask = BIT(0),
127 .hw.init = &(struct clk_init_data){
128 .name = "gpll0_vote",
129 .parent_names = (const char *[]){ "gpll0" },
130 .num_parents = 1,
131 .ops = &clk_pll_vote_ops,
132 },
133};
134
135static struct clk_rcg2 config_noc_clk_src = {
136 .cmd_rcgr = 0x0150,
137 .hid_width = 5,
138 .parent_map = gcc_xo_gpll0_map,
139 .clkr.hw.init = &(struct clk_init_data){
140 .name = "config_noc_clk_src",
141 .parent_names = gcc_xo_gpll0,
142 .num_parents = 2,
143 .ops = &clk_rcg2_ops,
144 },
145};
146
147static struct clk_rcg2 periph_noc_clk_src = {
148 .cmd_rcgr = 0x0190,
149 .hid_width = 5,
150 .parent_map = gcc_xo_gpll0_map,
151 .clkr.hw.init = &(struct clk_init_data){
152 .name = "periph_noc_clk_src",
153 .parent_names = gcc_xo_gpll0,
154 .num_parents = 2,
155 .ops = &clk_rcg2_ops,
156 },
157};
158
159static struct clk_rcg2 system_noc_clk_src = {
160 .cmd_rcgr = 0x0120,
161 .hid_width = 5,
162 .parent_map = gcc_xo_gpll0_map,
163 .clkr.hw.init = &(struct clk_init_data){
164 .name = "system_noc_clk_src",
165 .parent_names = gcc_xo_gpll0,
166 .num_parents = 2,
167 .ops = &clk_rcg2_ops,
168 },
169};
170
171static struct clk_pll gpll1 = {
172 .l_reg = 0x0044,
173 .m_reg = 0x0048,
174 .n_reg = 0x004c,
175 .config_reg = 0x0054,
176 .mode_reg = 0x0040,
177 .status_reg = 0x005c,
178 .status_bit = 17,
179 .clkr.hw.init = &(struct clk_init_data){
180 .name = "gpll1",
181 .parent_names = (const char *[]){ "xo" },
182 .num_parents = 1,
183 .ops = &clk_pll_ops,
184 },
185};
186
187static struct clk_regmap gpll1_vote = {
188 .enable_reg = 0x1480,
189 .enable_mask = BIT(1),
190 .hw.init = &(struct clk_init_data){
191 .name = "gpll1_vote",
192 .parent_names = (const char *[]){ "gpll1" },
193 .num_parents = 1,
194 .ops = &clk_pll_vote_ops,
195 },
196};
197
198static struct clk_pll gpll4 = {
199 .l_reg = 0x1dc4,
200 .m_reg = 0x1dc8,
201 .n_reg = 0x1dcc,
202 .config_reg = 0x1dd4,
203 .mode_reg = 0x1dc0,
204 .status_reg = 0x1ddc,
205 .status_bit = 17,
206 .clkr.hw.init = &(struct clk_init_data){
207 .name = "gpll4",
208 .parent_names = (const char *[]){ "xo" },
209 .num_parents = 1,
210 .ops = &clk_pll_ops,
211 },
212};
213
214static struct clk_regmap gpll4_vote = {
215 .enable_reg = 0x1480,
216 .enable_mask = BIT(4),
217 .hw.init = &(struct clk_init_data){
218 .name = "gpll4_vote",
219 .parent_names = (const char *[]){ "gpll4" },
220 .num_parents = 1,
221 .ops = &clk_pll_vote_ops,
222 },
223};
224
225static const struct freq_tbl ftbl_gcc_ufs_axi_clk[] = {
226 F(100000000, P_GPLL0, 6, 0, 0),
227 F(200000000, P_GPLL0, 3, 0, 0),
228 F(240000000, P_GPLL0, 2.5, 0, 0),
229 { }
230};
231
232static struct clk_rcg2 ufs_axi_clk_src = {
233 .cmd_rcgr = 0x1d64,
234 .mnd_width = 8,
235 .hid_width = 5,
236 .parent_map = gcc_xo_gpll0_map,
237 .freq_tbl = ftbl_gcc_ufs_axi_clk,
238 .clkr.hw.init = &(struct clk_init_data){
239 .name = "ufs_axi_clk_src",
240 .parent_names = gcc_xo_gpll0,
241 .num_parents = 2,
242 .ops = &clk_rcg2_ops,
243 },
244};
245
246static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = {
247 F(125000000, P_GPLL0, 1, 5, 24),
248 { }
249};
250
251static struct clk_rcg2 usb30_master_clk_src = {
252 .cmd_rcgr = 0x03d4,
253 .mnd_width = 8,
254 .hid_width = 5,
255 .parent_map = gcc_xo_gpll0_map,
256 .freq_tbl = ftbl_gcc_usb30_master_clk,
257 .clkr.hw.init = &(struct clk_init_data){
258 .name = "usb30_master_clk_src",
259 .parent_names = gcc_xo_gpll0,
260 .num_parents = 2,
261 .ops = &clk_rcg2_ops,
262 },
263};
264
265static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk[] = {
266 F(125000000, P_GPLL0, 1, 5, 24),
267 { }
268};
269
270static struct clk_rcg2 usb30_sec_master_clk_src = {
271 .cmd_rcgr = 0x1bd4,
272 .mnd_width = 8,
273 .hid_width = 5,
274 .parent_map = gcc_xo_gpll0_map,
275 .freq_tbl = ftbl_gcc_usb30_sec_master_clk,
276 .clkr.hw.init = &(struct clk_init_data){
277 .name = "usb30_sec_master_clk_src",
278 .parent_names = gcc_xo_gpll0,
279 .num_parents = 2,
280 .ops = &clk_rcg2_ops,
281 },
282};
283
284static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
285 .halt_reg = 0x1bd0,
286 .clkr = {
287 .enable_reg = 0x1bd0,
288 .enable_mask = BIT(0),
289 .hw.init = &(struct clk_init_data){
290 .name = "gcc_usb30_sec_mock_utmi_clk",
291 .parent_names = (const char *[]){
292 "usb30_sec_mock_utmi_clk_src",
293 },
294 .num_parents = 1,
295 .flags = CLK_SET_RATE_PARENT,
296 .ops = &clk_branch2_ops,
297 },
298 },
299};
300
301static struct clk_branch gcc_usb30_sec_sleep_clk = {
302 .halt_reg = 0x1bcc,
303 .clkr = {
304 .enable_reg = 0x1bcc,
305 .enable_mask = BIT(0),
306 .hw.init = &(struct clk_init_data){
307 .name = "gcc_usb30_sec_sleep_clk",
308 .parent_names = (const char *[]){
309 "sleep_clk_src",
310 },
311 .num_parents = 1,
312 .flags = CLK_SET_RATE_PARENT,
313 .ops = &clk_branch2_ops,
314 },
315 },
316};
317
318static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = {
319 F(19200000, P_XO, 1, 0, 0),
320 F(50000000, P_GPLL0, 12, 0, 0),
321 { }
322};
323
324static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
325 .cmd_rcgr = 0x0660,
326 .hid_width = 5,
327 .parent_map = gcc_xo_gpll0_map,
328 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
329 .clkr.hw.init = &(struct clk_init_data){
330 .name = "blsp1_qup1_i2c_apps_clk_src",
331 .parent_names = gcc_xo_gpll0,
332 .num_parents = 2,
333 .ops = &clk_rcg2_ops,
334 },
335};
336
337static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = {
338 F(960000, P_XO, 10, 1, 2),
339 F(4800000, P_XO, 4, 0, 0),
340 F(9600000, P_XO, 2, 0, 0),
341 F(15000000, P_GPLL0, 10, 1, 4),
342 F(19200000, P_XO, 1, 0, 0),
343 F(25000000, P_GPLL0, 12, 1, 2),
344 F(50000000, P_GPLL0, 12, 0, 0),
345 { }
346};
347
348static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
349 .cmd_rcgr = 0x064c,
350 .mnd_width = 8,
351 .hid_width = 5,
352 .parent_map = gcc_xo_gpll0_map,
353 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
354 .clkr.hw.init = &(struct clk_init_data){
355 .name = "blsp1_qup1_spi_apps_clk_src",
356 .parent_names = gcc_xo_gpll0,
357 .num_parents = 2,
358 .ops = &clk_rcg2_ops,
359 },
360};
361
362static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
363 .cmd_rcgr = 0x06e0,
364 .hid_width = 5,
365 .parent_map = gcc_xo_gpll0_map,
366 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
367 .clkr.hw.init = &(struct clk_init_data){
368 .name = "blsp1_qup2_i2c_apps_clk_src",
369 .parent_names = gcc_xo_gpll0,
370 .num_parents = 2,
371 .ops = &clk_rcg2_ops,
372 },
373};
374
375static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
376 .cmd_rcgr = 0x06cc,
377 .mnd_width = 8,
378 .hid_width = 5,
379 .parent_map = gcc_xo_gpll0_map,
380 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
381 .clkr.hw.init = &(struct clk_init_data){
382 .name = "blsp1_qup2_spi_apps_clk_src",
383 .parent_names = gcc_xo_gpll0,
384 .num_parents = 2,
385 .ops = &clk_rcg2_ops,
386 },
387};
388
389static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
390 .cmd_rcgr = 0x0760,
391 .hid_width = 5,
392 .parent_map = gcc_xo_gpll0_map,
393 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
394 .clkr.hw.init = &(struct clk_init_data){
395 .name = "blsp1_qup3_i2c_apps_clk_src",
396 .parent_names = gcc_xo_gpll0,
397 .num_parents = 2,
398 .ops = &clk_rcg2_ops,
399 },
400};
401
402static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
403 .cmd_rcgr = 0x074c,
404 .mnd_width = 8,
405 .hid_width = 5,
406 .parent_map = gcc_xo_gpll0_map,
407 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
408 .clkr.hw.init = &(struct clk_init_data){
409 .name = "blsp1_qup3_spi_apps_clk_src",
410 .parent_names = gcc_xo_gpll0,
411 .num_parents = 2,
412 .ops = &clk_rcg2_ops,
413 },
414};
415
416static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
417 .cmd_rcgr = 0x07e0,
418 .hid_width = 5,
419 .parent_map = gcc_xo_gpll0_map,
420 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
421 .clkr.hw.init = &(struct clk_init_data){
422 .name = "blsp1_qup4_i2c_apps_clk_src",
423 .parent_names = gcc_xo_gpll0,
424 .num_parents = 2,
425 .ops = &clk_rcg2_ops,
426 },
427};
428
429static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
430 .cmd_rcgr = 0x07cc,
431 .mnd_width = 8,
432 .hid_width = 5,
433 .parent_map = gcc_xo_gpll0_map,
434 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
435 .clkr.hw.init = &(struct clk_init_data){
436 .name = "blsp1_qup4_spi_apps_clk_src",
437 .parent_names = gcc_xo_gpll0,
438 .num_parents = 2,
439 .ops = &clk_rcg2_ops,
440 },
441};
442
443static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
444 .cmd_rcgr = 0x0860,
445 .hid_width = 5,
446 .parent_map = gcc_xo_gpll0_map,
447 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
448 .clkr.hw.init = &(struct clk_init_data){
449 .name = "blsp1_qup5_i2c_apps_clk_src",
450 .parent_names = gcc_xo_gpll0,
451 .num_parents = 2,
452 .ops = &clk_rcg2_ops,
453 },
454};
455
456static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
457 .cmd_rcgr = 0x084c,
458 .mnd_width = 8,
459 .hid_width = 5,
460 .parent_map = gcc_xo_gpll0_map,
461 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
462 .clkr.hw.init = &(struct clk_init_data){
463 .name = "blsp1_qup5_spi_apps_clk_src",
464 .parent_names = gcc_xo_gpll0,
465 .num_parents = 2,
466 .ops = &clk_rcg2_ops,
467 },
468};
469
470static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
471 .cmd_rcgr = 0x08e0,
472 .hid_width = 5,
473 .parent_map = gcc_xo_gpll0_map,
474 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
475 .clkr.hw.init = &(struct clk_init_data){
476 .name = "blsp1_qup6_i2c_apps_clk_src",
477 .parent_names = gcc_xo_gpll0,
478 .num_parents = 2,
479 .ops = &clk_rcg2_ops,
480 },
481};
482
483static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
484 .cmd_rcgr = 0x08cc,
485 .mnd_width = 8,
486 .hid_width = 5,
487 .parent_map = gcc_xo_gpll0_map,
488 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
489 .clkr.hw.init = &(struct clk_init_data){
490 .name = "blsp1_qup6_spi_apps_clk_src",
491 .parent_names = gcc_xo_gpll0,
492 .num_parents = 2,
493 .ops = &clk_rcg2_ops,
494 },
495};
496
497static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = {
498 F(3686400, P_GPLL0, 1, 96, 15625),
499 F(7372800, P_GPLL0, 1, 192, 15625),
500 F(14745600, P_GPLL0, 1, 384, 15625),
501 F(16000000, P_GPLL0, 5, 2, 15),
502 F(19200000, P_XO, 1, 0, 0),
503 F(24000000, P_GPLL0, 5, 1, 5),
504 F(32000000, P_GPLL0, 1, 4, 75),
505 F(40000000, P_GPLL0, 15, 0, 0),
506 F(46400000, P_GPLL0, 1, 29, 375),
507 F(48000000, P_GPLL0, 12.5, 0, 0),
508 F(51200000, P_GPLL0, 1, 32, 375),
509 F(56000000, P_GPLL0, 1, 7, 75),
510 F(58982400, P_GPLL0, 1, 1536, 15625),
511 F(60000000, P_GPLL0, 10, 0, 0),
512 F(63160000, P_GPLL0, 9.5, 0, 0),
513 { }
514};
515
516static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
517 .cmd_rcgr = 0x068c,
518 .mnd_width = 16,
519 .hid_width = 5,
520 .parent_map = gcc_xo_gpll0_map,
521 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
522 .clkr.hw.init = &(struct clk_init_data){
523 .name = "blsp1_uart1_apps_clk_src",
524 .parent_names = gcc_xo_gpll0,
525 .num_parents = 2,
526 .ops = &clk_rcg2_ops,
527 },
528};
529
530static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
531 .cmd_rcgr = 0x070c,
532 .mnd_width = 16,
533 .hid_width = 5,
534 .parent_map = gcc_xo_gpll0_map,
535 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
536 .clkr.hw.init = &(struct clk_init_data){
537 .name = "blsp1_uart2_apps_clk_src",
538 .parent_names = gcc_xo_gpll0,
539 .num_parents = 2,
540 .ops = &clk_rcg2_ops,
541 },
542};
543
544static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
545 .cmd_rcgr = 0x078c,
546 .mnd_width = 16,
547 .hid_width = 5,
548 .parent_map = gcc_xo_gpll0_map,
549 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
550 .clkr.hw.init = &(struct clk_init_data){
551 .name = "blsp1_uart3_apps_clk_src",
552 .parent_names = gcc_xo_gpll0,
553 .num_parents = 2,
554 .ops = &clk_rcg2_ops,
555 },
556};
557
558static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
559 .cmd_rcgr = 0x080c,
560 .mnd_width = 16,
561 .hid_width = 5,
562 .parent_map = gcc_xo_gpll0_map,
563 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
564 .clkr.hw.init = &(struct clk_init_data){
565 .name = "blsp1_uart4_apps_clk_src",
566 .parent_names = gcc_xo_gpll0,
567 .num_parents = 2,
568 .ops = &clk_rcg2_ops,
569 },
570};
571
572static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
573 .cmd_rcgr = 0x088c,
574 .mnd_width = 16,
575 .hid_width = 5,
576 .parent_map = gcc_xo_gpll0_map,
577 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
578 .clkr.hw.init = &(struct clk_init_data){
579 .name = "blsp1_uart5_apps_clk_src",
580 .parent_names = gcc_xo_gpll0,
581 .num_parents = 2,
582 .ops = &clk_rcg2_ops,
583 },
584};
585
586static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
587 .cmd_rcgr = 0x090c,
588 .mnd_width = 16,
589 .hid_width = 5,
590 .parent_map = gcc_xo_gpll0_map,
591 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
592 .clkr.hw.init = &(struct clk_init_data){
593 .name = "blsp1_uart6_apps_clk_src",
594 .parent_names = gcc_xo_gpll0,
595 .num_parents = 2,
596 .ops = &clk_rcg2_ops,
597 },
598};
599
600static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
601 .cmd_rcgr = 0x09a0,
602 .hid_width = 5,
603 .parent_map = gcc_xo_gpll0_map,
604 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
605 .clkr.hw.init = &(struct clk_init_data){
606 .name = "blsp2_qup1_i2c_apps_clk_src",
607 .parent_names = gcc_xo_gpll0,
608 .num_parents = 2,
609 .ops = &clk_rcg2_ops,
610 },
611};
612
613static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
614 .cmd_rcgr = 0x098c,
615 .mnd_width = 8,
616 .hid_width = 5,
617 .parent_map = gcc_xo_gpll0_map,
618 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
619 .clkr.hw.init = &(struct clk_init_data){
620 .name = "blsp2_qup1_spi_apps_clk_src",
621 .parent_names = gcc_xo_gpll0,
622 .num_parents = 2,
623 .ops = &clk_rcg2_ops,
624 },
625};
626
627static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
628 .cmd_rcgr = 0x0a20,
629 .hid_width = 5,
630 .parent_map = gcc_xo_gpll0_map,
631 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
632 .clkr.hw.init = &(struct clk_init_data){
633 .name = "blsp2_qup2_i2c_apps_clk_src",
634 .parent_names = gcc_xo_gpll0,
635 .num_parents = 2,
636 .ops = &clk_rcg2_ops,
637 },
638};
639
640static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
641 .cmd_rcgr = 0x0a0c,
642 .mnd_width = 8,
643 .hid_width = 5,
644 .parent_map = gcc_xo_gpll0_map,
645 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
646 .clkr.hw.init = &(struct clk_init_data){
647 .name = "blsp2_qup2_spi_apps_clk_src",
648 .parent_names = gcc_xo_gpll0,
649 .num_parents = 2,
650 .ops = &clk_rcg2_ops,
651 },
652};
653
654static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
655 .cmd_rcgr = 0x0aa0,
656 .hid_width = 5,
657 .parent_map = gcc_xo_gpll0_map,
658 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
659 .clkr.hw.init = &(struct clk_init_data){
660 .name = "blsp2_qup3_i2c_apps_clk_src",
661 .parent_names = gcc_xo_gpll0,
662 .num_parents = 2,
663 .ops = &clk_rcg2_ops,
664 },
665};
666
667static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
668 .cmd_rcgr = 0x0a8c,
669 .mnd_width = 8,
670 .hid_width = 5,
671 .parent_map = gcc_xo_gpll0_map,
672 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
673 .clkr.hw.init = &(struct clk_init_data){
674 .name = "blsp2_qup3_spi_apps_clk_src",
675 .parent_names = gcc_xo_gpll0,
676 .num_parents = 2,
677 .ops = &clk_rcg2_ops,
678 },
679};
680
681static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
682 .cmd_rcgr = 0x0b20,
683 .hid_width = 5,
684 .parent_map = gcc_xo_gpll0_map,
685 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
686 .clkr.hw.init = &(struct clk_init_data){
687 .name = "blsp2_qup4_i2c_apps_clk_src",
688 .parent_names = gcc_xo_gpll0,
689 .num_parents = 2,
690 .ops = &clk_rcg2_ops,
691 },
692};
693
694static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
695 .cmd_rcgr = 0x0b0c,
696 .mnd_width = 8,
697 .hid_width = 5,
698 .parent_map = gcc_xo_gpll0_map,
699 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
700 .clkr.hw.init = &(struct clk_init_data){
701 .name = "blsp2_qup4_spi_apps_clk_src",
702 .parent_names = gcc_xo_gpll0,
703 .num_parents = 2,
704 .ops = &clk_rcg2_ops,
705 },
706};
707
708static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
709 .cmd_rcgr = 0x0ba0,
710 .hid_width = 5,
711 .parent_map = gcc_xo_gpll0_map,
712 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
713 .clkr.hw.init = &(struct clk_init_data){
714 .name = "blsp2_qup5_i2c_apps_clk_src",
715 .parent_names = gcc_xo_gpll0,
716 .num_parents = 2,
717 .ops = &clk_rcg2_ops,
718 },
719};
720
721static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
722 .cmd_rcgr = 0x0b8c,
723 .mnd_width = 8,
724 .hid_width = 5,
725 .parent_map = gcc_xo_gpll0_map,
726 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
727 .clkr.hw.init = &(struct clk_init_data){
728 .name = "blsp2_qup5_spi_apps_clk_src",
729 .parent_names = gcc_xo_gpll0,
730 .num_parents = 2,
731 .ops = &clk_rcg2_ops,
732 },
733};
734
735static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
736 .cmd_rcgr = 0x0c20,
737 .hid_width = 5,
738 .parent_map = gcc_xo_gpll0_map,
739 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
740 .clkr.hw.init = &(struct clk_init_data){
741 .name = "blsp2_qup6_i2c_apps_clk_src",
742 .parent_names = gcc_xo_gpll0,
743 .num_parents = 2,
744 .ops = &clk_rcg2_ops,
745 },
746};
747
748static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
749 .cmd_rcgr = 0x0c0c,
750 .mnd_width = 8,
751 .hid_width = 5,
752 .parent_map = gcc_xo_gpll0_map,
753 .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
754 .clkr.hw.init = &(struct clk_init_data){
755 .name = "blsp2_qup6_spi_apps_clk_src",
756 .parent_names = gcc_xo_gpll0,
757 .num_parents = 2,
758 .ops = &clk_rcg2_ops,
759 },
760};
761
762static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
763 .cmd_rcgr = 0x09cc,
764 .mnd_width = 16,
765 .hid_width = 5,
766 .parent_map = gcc_xo_gpll0_map,
767 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
768 .clkr.hw.init = &(struct clk_init_data){
769 .name = "blsp2_uart1_apps_clk_src",
770 .parent_names = gcc_xo_gpll0,
771 .num_parents = 2,
772 .ops = &clk_rcg2_ops,
773 },
774};
775
776static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
777 .cmd_rcgr = 0x0a4c,
778 .mnd_width = 16,
779 .hid_width = 5,
780 .parent_map = gcc_xo_gpll0_map,
781 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
782 .clkr.hw.init = &(struct clk_init_data){
783 .name = "blsp2_uart2_apps_clk_src",
784 .parent_names = gcc_xo_gpll0,
785 .num_parents = 2,
786 .ops = &clk_rcg2_ops,
787 },
788};
789
790static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
791 .cmd_rcgr = 0x0acc,
792 .mnd_width = 16,
793 .hid_width = 5,
794 .parent_map = gcc_xo_gpll0_map,
795 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
796 .clkr.hw.init = &(struct clk_init_data){
797 .name = "blsp2_uart3_apps_clk_src",
798 .parent_names = gcc_xo_gpll0,
799 .num_parents = 2,
800 .ops = &clk_rcg2_ops,
801 },
802};
803
804static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
805 .cmd_rcgr = 0x0b4c,
806 .mnd_width = 16,
807 .hid_width = 5,
808 .parent_map = gcc_xo_gpll0_map,
809 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
810 .clkr.hw.init = &(struct clk_init_data){
811 .name = "blsp2_uart4_apps_clk_src",
812 .parent_names = gcc_xo_gpll0,
813 .num_parents = 2,
814 .ops = &clk_rcg2_ops,
815 },
816};
817
818static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
819 .cmd_rcgr = 0x0bcc,
820 .mnd_width = 16,
821 .hid_width = 5,
822 .parent_map = gcc_xo_gpll0_map,
823 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
824 .clkr.hw.init = &(struct clk_init_data){
825 .name = "blsp2_uart5_apps_clk_src",
826 .parent_names = gcc_xo_gpll0,
827 .num_parents = 2,
828 .ops = &clk_rcg2_ops,
829 },
830};
831
832static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
833 .cmd_rcgr = 0x0c4c,
834 .mnd_width = 16,
835 .hid_width = 5,
836 .parent_map = gcc_xo_gpll0_map,
837 .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
838 .clkr.hw.init = &(struct clk_init_data){
839 .name = "blsp2_uart6_apps_clk_src",
840 .parent_names = gcc_xo_gpll0,
841 .num_parents = 2,
842 .ops = &clk_rcg2_ops,
843 },
844};
845
846static const struct freq_tbl ftbl_gcc_ce1_clk[] = {
847 F(50000000, P_GPLL0, 12, 0, 0),
848 F(85710000, P_GPLL0, 7, 0, 0),
849 F(100000000, P_GPLL0, 6, 0, 0),
850 F(171430000, P_GPLL0, 3.5, 0, 0),
851 { }
852};
853
854static struct clk_rcg2 ce1_clk_src = {
855 .cmd_rcgr = 0x1050,
856 .hid_width = 5,
857 .parent_map = gcc_xo_gpll0_map,
858 .freq_tbl = ftbl_gcc_ce1_clk,
859 .clkr.hw.init = &(struct clk_init_data){
860 .name = "ce1_clk_src",
861 .parent_names = gcc_xo_gpll0,
862 .num_parents = 2,
863 .ops = &clk_rcg2_ops,
864 },
865};
866
867static const struct freq_tbl ftbl_gcc_ce2_clk[] = {
868 F(50000000, P_GPLL0, 12, 0, 0),
869 F(85710000, P_GPLL0, 7, 0, 0),
870 F(100000000, P_GPLL0, 6, 0, 0),
871 F(171430000, P_GPLL0, 3.5, 0, 0),
872 { }
873};
874
875static struct clk_rcg2 ce2_clk_src = {
876 .cmd_rcgr = 0x1090,
877 .hid_width = 5,
878 .parent_map = gcc_xo_gpll0_map,
879 .freq_tbl = ftbl_gcc_ce2_clk,
880 .clkr.hw.init = &(struct clk_init_data){
881 .name = "ce2_clk_src",
882 .parent_names = gcc_xo_gpll0,
883 .num_parents = 2,
884 .ops = &clk_rcg2_ops,
885 },
886};
887
888static const struct freq_tbl ftbl_gcc_ce3_clk[] = {
889 F(50000000, P_GPLL0, 12, 0, 0),
890 F(85710000, P_GPLL0, 7, 0, 0),
891 F(100000000, P_GPLL0, 6, 0, 0),
892 F(171430000, P_GPLL0, 3.5, 0, 0),
893 { }
894};
895
896static struct clk_rcg2 ce3_clk_src = {
897 .cmd_rcgr = 0x1d10,
898 .hid_width = 5,
899 .parent_map = gcc_xo_gpll0_map,
900 .freq_tbl = ftbl_gcc_ce3_clk,
901 .clkr.hw.init = &(struct clk_init_data){
902 .name = "ce3_clk_src",
903 .parent_names = gcc_xo_gpll0,
904 .num_parents = 2,
905 .ops = &clk_rcg2_ops,
906 },
907};
908
909static const struct freq_tbl ftbl_gcc_gp_clk[] = {
910 F(19200000, P_XO, 1, 0, 0),
911 F(100000000, P_GPLL0, 6, 0, 0),
912 F(200000000, P_GPLL0, 3, 0, 0),
913 { }
914};
915
916static struct clk_rcg2 gp1_clk_src = {
917 .cmd_rcgr = 0x1904,
918 .mnd_width = 8,
919 .hid_width = 5,
920 .parent_map = gcc_xo_gpll0_map,
921 .freq_tbl = ftbl_gcc_gp_clk,
922 .clkr.hw.init = &(struct clk_init_data){
923 .name = "gp1_clk_src",
924 .parent_names = gcc_xo_gpll0,
925 .num_parents = 2,
926 .ops = &clk_rcg2_ops,
927 },
928};
929
930static struct clk_rcg2 gp2_clk_src = {
931 .cmd_rcgr = 0x1944,
932 .mnd_width = 8,
933 .hid_width = 5,
934 .parent_map = gcc_xo_gpll0_map,
935 .freq_tbl = ftbl_gcc_gp_clk,
936 .clkr.hw.init = &(struct clk_init_data){
937 .name = "gp2_clk_src",
938 .parent_names = gcc_xo_gpll0,
939 .num_parents = 2,
940 .ops = &clk_rcg2_ops,
941 },
942};
943
944static struct clk_rcg2 gp3_clk_src = {
945 .cmd_rcgr = 0x1984,
946 .mnd_width = 8,
947 .hid_width = 5,
948 .parent_map = gcc_xo_gpll0_map,
949 .freq_tbl = ftbl_gcc_gp_clk,
950 .clkr.hw.init = &(struct clk_init_data){
951 .name = "gp3_clk_src",
952 .parent_names = gcc_xo_gpll0,
953 .num_parents = 2,
954 .ops = &clk_rcg2_ops,
955 },
956};
957
958static const struct freq_tbl ftbl_gcc_pcie_0_1_aux_clk[] = {
959 F(1010000, P_XO, 1, 1, 19),
960 { }
961};
962
963static struct clk_rcg2 pcie_0_aux_clk_src = {
964 .cmd_rcgr = 0x1b2c,
965 .mnd_width = 16,
966 .hid_width = 5,
967 .parent_map = gcc_xo_pcie_sleep_map,
968 .freq_tbl = ftbl_gcc_pcie_0_1_aux_clk,
969 .clkr.hw.init = &(struct clk_init_data){
970 .name = "pcie_0_aux_clk_src",
971 .parent_names = gcc_xo_pcie_sleep,
972 .num_parents = 2,
973 .ops = &clk_rcg2_ops,
974 },
975};
976
977static struct clk_rcg2 pcie_1_aux_clk_src = {
978 .cmd_rcgr = 0x1bac,
979 .mnd_width = 16,
980 .hid_width = 5,
981 .parent_map = gcc_xo_pcie_sleep_map,
982 .freq_tbl = ftbl_gcc_pcie_0_1_aux_clk,
983 .clkr.hw.init = &(struct clk_init_data){
984 .name = "pcie_1_aux_clk_src",
985 .parent_names = gcc_xo_pcie_sleep,
986 .num_parents = 2,
987 .ops = &clk_rcg2_ops,
988 },
989};
990
991static const struct freq_tbl ftbl_gcc_pcie_0_1_pipe_clk[] = {
992 F(125000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0),
993 F(250000000, P_PCIE_0_1_PIPE_CLK, 1, 0, 0),
994 { }
995};
996
997static struct clk_rcg2 pcie_0_pipe_clk_src = {
998 .cmd_rcgr = 0x1b18,
999 .hid_width = 5,
1000 .parent_map = gcc_xo_pcie_map,
1001 .freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk,
1002 .clkr.hw.init = &(struct clk_init_data){
1003 .name = "pcie_0_pipe_clk_src",
1004 .parent_names = gcc_xo_pcie,
1005 .num_parents = 2,
1006 .ops = &clk_rcg2_ops,
1007 },
1008};
1009
1010static struct clk_rcg2 pcie_1_pipe_clk_src = {
1011 .cmd_rcgr = 0x1b98,
1012 .hid_width = 5,
1013 .parent_map = gcc_xo_pcie_map,
1014 .freq_tbl = ftbl_gcc_pcie_0_1_pipe_clk,
1015 .clkr.hw.init = &(struct clk_init_data){
1016 .name = "pcie_1_pipe_clk_src",
1017 .parent_names = gcc_xo_pcie,
1018 .num_parents = 2,
1019 .ops = &clk_rcg2_ops,
1020 },
1021};
1022
1023static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
1024 F(60000000, P_GPLL0, 10, 0, 0),
1025 { }
1026};
1027
1028static struct clk_rcg2 pdm2_clk_src = {
1029 .cmd_rcgr = 0x0cd0,
1030 .hid_width = 5,
1031 .parent_map = gcc_xo_gpll0_map,
1032 .freq_tbl = ftbl_gcc_pdm2_clk,
1033 .clkr.hw.init = &(struct clk_init_data){
1034 .name = "pdm2_clk_src",
1035 .parent_names = gcc_xo_gpll0,
1036 .num_parents = 2,
1037 .ops = &clk_rcg2_ops,
1038 },
1039};
1040
1041static const struct freq_tbl ftbl_gcc_sata_asic0_clk[] = {
1042 F(75000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1043 F(150000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1044 F(300000000, P_SATA_ASIC0_CLK, 1, 0, 0),
1045 { }
1046};
1047
1048static struct clk_rcg2 sata_asic0_clk_src = {
1049 .cmd_rcgr = 0x1c94,
1050 .hid_width = 5,
1051 .parent_map = gcc_xo_sata_asic0_map,
1052 .freq_tbl = ftbl_gcc_sata_asic0_clk,
1053 .clkr.hw.init = &(struct clk_init_data){
1054 .name = "sata_asic0_clk_src",
1055 .parent_names = gcc_xo_sata_asic0,
1056 .num_parents = 2,
1057 .ops = &clk_rcg2_ops,
1058 },
1059};
1060
1061static const struct freq_tbl ftbl_gcc_sata_pmalive_clk[] = {
1062 F(19200000, P_XO, 1, 0, 0),
1063 F(50000000, P_GPLL0, 12, 0, 0),
1064 F(100000000, P_GPLL0, 6, 0, 0),
1065 { }
1066};
1067
1068static struct clk_rcg2 sata_pmalive_clk_src = {
1069 .cmd_rcgr = 0x1c80,
1070 .hid_width = 5,
1071 .parent_map = gcc_xo_gpll0_map,
1072 .freq_tbl = ftbl_gcc_sata_pmalive_clk,
1073 .clkr.hw.init = &(struct clk_init_data){
1074 .name = "sata_pmalive_clk_src",
1075 .parent_names = gcc_xo_gpll0,
1076 .num_parents = 2,
1077 .ops = &clk_rcg2_ops,
1078 },
1079};
1080
1081static const struct freq_tbl ftbl_gcc_sata_rx_clk[] = {
1082 F(75000000, P_SATA_RX_CLK, 1, 0, 0),
1083 F(150000000, P_SATA_RX_CLK, 1, 0, 0),
1084 F(300000000, P_SATA_RX_CLK, 1, 0, 0),
1085 { }
1086};
1087
1088static struct clk_rcg2 sata_rx_clk_src = {
1089 .cmd_rcgr = 0x1ca8,
1090 .hid_width = 5,
1091 .parent_map = gcc_xo_sata_rx_map,
1092 .freq_tbl = ftbl_gcc_sata_rx_clk,
1093 .clkr.hw.init = &(struct clk_init_data){
1094 .name = "sata_rx_clk_src",
1095 .parent_names = gcc_xo_sata_rx,
1096 .num_parents = 2,
1097 .ops = &clk_rcg2_ops,
1098 },
1099};
1100
1101static const struct freq_tbl ftbl_gcc_sata_rx_oob_clk[] = {
1102 F(100000000, P_GPLL0, 6, 0, 0),
1103 { }
1104};
1105
1106static struct clk_rcg2 sata_rx_oob_clk_src = {
1107 .cmd_rcgr = 0x1c5c,
1108 .hid_width = 5,
1109 .parent_map = gcc_xo_gpll0_map,
1110 .freq_tbl = ftbl_gcc_sata_rx_oob_clk,
1111 .clkr.hw.init = &(struct clk_init_data){
1112 .name = "sata_rx_oob_clk_src",
1113 .parent_names = gcc_xo_gpll0,
1114 .num_parents = 2,
1115 .ops = &clk_rcg2_ops,
1116 },
1117};
1118
1119static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = {
1120 F(144000, P_XO, 16, 3, 25),
1121 F(400000, P_XO, 12, 1, 4),
1122 F(20000000, P_GPLL0, 15, 1, 2),
1123 F(25000000, P_GPLL0, 12, 1, 2),
1124 F(50000000, P_GPLL0, 12, 0, 0),
1125 F(100000000, P_GPLL0, 6, 0, 0),
1126 F(192000000, P_GPLL4, 4, 0, 0),
1127 F(200000000, P_GPLL0, 3, 0, 0),
1128 F(384000000, P_GPLL4, 2, 0, 0),
1129 { }
1130};
1131
1132static struct clk_rcg2 sdcc1_apps_clk_src = {
1133 .cmd_rcgr = 0x04d0,
1134 .mnd_width = 8,
1135 .hid_width = 5,
1136 .parent_map = gcc_xo_gpll0_gpll4_map,
1137 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1138 .clkr.hw.init = &(struct clk_init_data){
1139 .name = "sdcc1_apps_clk_src",
1140 .parent_names = gcc_xo_gpll0_gpll4,
1141 .num_parents = 3,
1142 .ops = &clk_rcg2_ops,
1143 },
1144};
1145
1146static struct clk_rcg2 sdcc2_apps_clk_src = {
1147 .cmd_rcgr = 0x0510,
1148 .mnd_width = 8,
1149 .hid_width = 5,
1150 .parent_map = gcc_xo_gpll0_map,
1151 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1152 .clkr.hw.init = &(struct clk_init_data){
1153 .name = "sdcc2_apps_clk_src",
1154 .parent_names = gcc_xo_gpll0,
1155 .num_parents = 2,
1156 .ops = &clk_rcg2_ops,
1157 },
1158};
1159
1160static struct clk_rcg2 sdcc3_apps_clk_src = {
1161 .cmd_rcgr = 0x0550,
1162 .mnd_width = 8,
1163 .hid_width = 5,
1164 .parent_map = gcc_xo_gpll0_map,
1165 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1166 .clkr.hw.init = &(struct clk_init_data){
1167 .name = "sdcc3_apps_clk_src",
1168 .parent_names = gcc_xo_gpll0,
1169 .num_parents = 2,
1170 .ops = &clk_rcg2_ops,
1171 },
1172};
1173
1174static struct clk_rcg2 sdcc4_apps_clk_src = {
1175 .cmd_rcgr = 0x0590,
1176 .mnd_width = 8,
1177 .hid_width = 5,
1178 .parent_map = gcc_xo_gpll0_map,
1179 .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
1180 .clkr.hw.init = &(struct clk_init_data){
1181 .name = "sdcc4_apps_clk_src",
1182 .parent_names = gcc_xo_gpll0,
1183 .num_parents = 2,
1184 .ops = &clk_rcg2_ops,
1185 },
1186};
1187
1188static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = {
1189 F(105000, P_XO, 2, 1, 91),
1190 { }
1191};
1192
1193static struct clk_rcg2 tsif_ref_clk_src = {
1194 .cmd_rcgr = 0x0d90,
1195 .mnd_width = 8,
1196 .hid_width = 5,
1197 .parent_map = gcc_xo_gpll0_map,
1198 .freq_tbl = ftbl_gcc_tsif_ref_clk,
1199 .clkr.hw.init = &(struct clk_init_data){
1200 .name = "tsif_ref_clk_src",
1201 .parent_names = gcc_xo_gpll0,
1202 .num_parents = 2,
1203 .ops = &clk_rcg2_ops,
1204 },
1205};
1206
1207static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
1208 F(60000000, P_GPLL0, 10, 0, 0),
1209 { }
1210};
1211
1212static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1213 .cmd_rcgr = 0x03e8,
1214 .hid_width = 5,
1215 .parent_map = gcc_xo_gpll0_map,
1216 .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
1217 .clkr.hw.init = &(struct clk_init_data){
1218 .name = "usb30_mock_utmi_clk_src",
1219 .parent_names = gcc_xo_gpll0,
1220 .num_parents = 2,
1221 .ops = &clk_rcg2_ops,
1222 },
1223};
1224
1225static const struct freq_tbl ftbl_gcc_usb30_sec_mock_utmi_clk[] = {
1226 F(125000000, P_GPLL0, 1, 5, 24),
1227 { }
1228};
1229
1230static struct clk_rcg2 usb30_sec_mock_utmi_clk_src = {
1231 .cmd_rcgr = 0x1be8,
1232 .hid_width = 5,
1233 .parent_map = gcc_xo_gpll0_map,
1234 .freq_tbl = ftbl_gcc_usb30_sec_mock_utmi_clk,
1235 .clkr.hw.init = &(struct clk_init_data){
1236 .name = "usb30_sec_mock_utmi_clk_src",
1237 .parent_names = gcc_xo_gpll0,
1238 .num_parents = 2,
1239 .ops = &clk_rcg2_ops,
1240 },
1241};
1242
1243static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1244 F(75000000, P_GPLL0, 8, 0, 0),
1245 { }
1246};
1247
1248static struct clk_rcg2 usb_hs_system_clk_src = {
1249 .cmd_rcgr = 0x0490,
1250 .hid_width = 5,
1251 .parent_map = gcc_xo_gpll0_map,
1252 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1253 .clkr.hw.init = &(struct clk_init_data){
1254 .name = "usb_hs_system_clk_src",
1255 .parent_names = gcc_xo_gpll0,
1256 .num_parents = 2,
1257 .ops = &clk_rcg2_ops,
1258 },
1259};
1260
1261static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
1262 F(480000000, P_GPLL1, 1, 0, 0),
1263 { }
1264};
1265
1266static u8 usb_hsic_clk_src_map[] = {
1267 [P_XO] = 0,
1268 [P_GPLL1] = 4,
1269};
1270
1271static struct clk_rcg2 usb_hsic_clk_src = {
1272 .cmd_rcgr = 0x0440,
1273 .hid_width = 5,
1274 .parent_map = usb_hsic_clk_src_map,
1275 .freq_tbl = ftbl_gcc_usb_hsic_clk,
1276 .clkr.hw.init = &(struct clk_init_data){
1277 .name = "usb_hsic_clk_src",
1278 .parent_names = (const char *[]){
1279 "xo",
1280 "gpll1_vote",
1281 },
1282 .num_parents = 2,
1283 .ops = &clk_rcg2_ops,
1284 },
1285};
1286
1287static const struct freq_tbl ftbl_gcc_usb_hsic_ahb_clk_src[] = {
1288 F(60000000, P_GPLL1, 8, 0, 0),
1289 { }
1290};
1291
1292static struct clk_rcg2 usb_hsic_ahb_clk_src = {
1293 .cmd_rcgr = 0x046c,
1294 .mnd_width = 8,
1295 .hid_width = 5,
1296 .parent_map = usb_hsic_clk_src_map,
1297 .freq_tbl = ftbl_gcc_usb_hsic_ahb_clk_src,
1298 .clkr.hw.init = &(struct clk_init_data){
1299 .name = "usb_hsic_ahb_clk_src",
1300 .parent_names = (const char *[]){
1301 "xo",
1302 "gpll1_vote",
1303 },
1304 .num_parents = 2,
1305 .ops = &clk_rcg2_ops,
1306 },
1307};
1308
1309static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
1310 F(9600000, P_XO, 2, 0, 0),
1311 { }
1312};
1313
1314static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
1315 .cmd_rcgr = 0x0458,
1316 .hid_width = 5,
1317 .parent_map = gcc_xo_gpll0_map,
1318 .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
1319 .clkr.hw.init = &(struct clk_init_data){
1320 .name = "usb_hsic_io_cal_clk_src",
1321 .parent_names = gcc_xo_gpll0,
1322 .num_parents = 1,
1323 .ops = &clk_rcg2_ops,
1324 },
1325};
1326
1327static struct clk_branch gcc_usb_hsic_mock_utmi_clk = {
1328 .halt_reg = 0x1f14,
1329 .clkr = {
1330 .enable_reg = 0x1f14,
1331 .enable_mask = BIT(0),
1332 .hw.init = &(struct clk_init_data){
1333 .name = "gcc_usb_hsic_mock_utmi_clk",
1334 .parent_names = (const char *[]){
1335 "usb_hsic_mock_utmi_clk_src",
1336 },
1337 .num_parents = 1,
1338 .flags = CLK_SET_RATE_PARENT,
1339 .ops = &clk_branch2_ops,
1340 },
1341 },
1342};
1343
1344static const struct freq_tbl ftbl_gcc_usb_hsic_mock_utmi_clk[] = {
1345 F(60000000, P_GPLL0, 10, 0, 0),
1346 { }
1347};
1348
1349static struct clk_rcg2 usb_hsic_mock_utmi_clk_src = {
1350 .cmd_rcgr = 0x1f00,
1351 .hid_width = 5,
1352 .parent_map = gcc_xo_gpll0_map,
1353 .freq_tbl = ftbl_gcc_usb_hsic_mock_utmi_clk,
1354 .clkr.hw.init = &(struct clk_init_data){
1355 .name = "usb_hsic_mock_utmi_clk_src",
1356 .parent_names = gcc_xo_gpll0,
1357 .num_parents = 1,
1358 .ops = &clk_rcg2_ops,
1359 },
1360};
1361
1362static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
1363 F(75000000, P_GPLL0, 8, 0, 0),
1364 { }
1365};
1366
1367static struct clk_rcg2 usb_hsic_system_clk_src = {
1368 .cmd_rcgr = 0x041c,
1369 .hid_width = 5,
1370 .parent_map = gcc_xo_gpll0_map,
1371 .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
1372 .clkr.hw.init = &(struct clk_init_data){
1373 .name = "usb_hsic_system_clk_src",
1374 .parent_names = gcc_xo_gpll0,
1375 .num_parents = 2,
1376 .ops = &clk_rcg2_ops,
1377 },
1378};
1379
1380static struct clk_branch gcc_bam_dma_ahb_clk = {
1381 .halt_reg = 0x0d44,
1382 .halt_check = BRANCH_HALT_VOTED,
1383 .clkr = {
1384 .enable_reg = 0x1484,
1385 .enable_mask = BIT(12),
1386 .hw.init = &(struct clk_init_data){
1387 .name = "gcc_bam_dma_ahb_clk",
1388 .parent_names = (const char *[]){
1389 "periph_noc_clk_src",
1390 },
1391 .num_parents = 1,
1392 .ops = &clk_branch2_ops,
1393 },
1394 },
1395};
1396
1397static struct clk_branch gcc_blsp1_ahb_clk = {
1398 .halt_reg = 0x05c4,
1399 .halt_check = BRANCH_HALT_VOTED,
1400 .clkr = {
1401 .enable_reg = 0x1484,
1402 .enable_mask = BIT(17),
1403 .hw.init = &(struct clk_init_data){
1404 .name = "gcc_blsp1_ahb_clk",
1405 .parent_names = (const char *[]){
1406 "periph_noc_clk_src",
1407 },
1408 .num_parents = 1,
1409 .ops = &clk_branch2_ops,
1410 },
1411 },
1412};
1413
1414static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1415 .halt_reg = 0x0648,
1416 .clkr = {
1417 .enable_reg = 0x0648,
1418 .enable_mask = BIT(0),
1419 .hw.init = &(struct clk_init_data){
1420 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1421 .parent_names = (const char *[]){
1422 "blsp1_qup1_i2c_apps_clk_src",
1423 },
1424 .num_parents = 1,
1425 .flags = CLK_SET_RATE_PARENT,
1426 .ops = &clk_branch2_ops,
1427 },
1428 },
1429};
1430
1431static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1432 .halt_reg = 0x0644,
1433 .clkr = {
1434 .enable_reg = 0x0644,
1435 .enable_mask = BIT(0),
1436 .hw.init = &(struct clk_init_data){
1437 .name = "gcc_blsp1_qup1_spi_apps_clk",
1438 .parent_names = (const char *[]){
1439 "blsp1_qup1_spi_apps_clk_src",
1440 },
1441 .num_parents = 1,
1442 .flags = CLK_SET_RATE_PARENT,
1443 .ops = &clk_branch2_ops,
1444 },
1445 },
1446};
1447
1448static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1449 .halt_reg = 0x06c8,
1450 .clkr = {
1451 .enable_reg = 0x06c8,
1452 .enable_mask = BIT(0),
1453 .hw.init = &(struct clk_init_data){
1454 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1455 .parent_names = (const char *[]){
1456 "blsp1_qup2_i2c_apps_clk_src",
1457 },
1458 .num_parents = 1,
1459 .flags = CLK_SET_RATE_PARENT,
1460 .ops = &clk_branch2_ops,
1461 },
1462 },
1463};
1464
1465static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1466 .halt_reg = 0x06c4,
1467 .clkr = {
1468 .enable_reg = 0x06c4,
1469 .enable_mask = BIT(0),
1470 .hw.init = &(struct clk_init_data){
1471 .name = "gcc_blsp1_qup2_spi_apps_clk",
1472 .parent_names = (const char *[]){
1473 "blsp1_qup2_spi_apps_clk_src",
1474 },
1475 .num_parents = 1,
1476 .flags = CLK_SET_RATE_PARENT,
1477 .ops = &clk_branch2_ops,
1478 },
1479 },
1480};
1481
1482static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1483 .halt_reg = 0x0748,
1484 .clkr = {
1485 .enable_reg = 0x0748,
1486 .enable_mask = BIT(0),
1487 .hw.init = &(struct clk_init_data){
1488 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1489 .parent_names = (const char *[]){
1490 "blsp1_qup3_i2c_apps_clk_src",
1491 },
1492 .num_parents = 1,
1493 .flags = CLK_SET_RATE_PARENT,
1494 .ops = &clk_branch2_ops,
1495 },
1496 },
1497};
1498
1499static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1500 .halt_reg = 0x0744,
1501 .clkr = {
1502 .enable_reg = 0x0744,
1503 .enable_mask = BIT(0),
1504 .hw.init = &(struct clk_init_data){
1505 .name = "gcc_blsp1_qup3_spi_apps_clk",
1506 .parent_names = (const char *[]){
1507 "blsp1_qup3_spi_apps_clk_src",
1508 },
1509 .num_parents = 1,
1510 .flags = CLK_SET_RATE_PARENT,
1511 .ops = &clk_branch2_ops,
1512 },
1513 },
1514};
1515
1516static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1517 .halt_reg = 0x07c8,
1518 .clkr = {
1519 .enable_reg = 0x07c8,
1520 .enable_mask = BIT(0),
1521 .hw.init = &(struct clk_init_data){
1522 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1523 .parent_names = (const char *[]){
1524 "blsp1_qup4_i2c_apps_clk_src",
1525 },
1526 .num_parents = 1,
1527 .flags = CLK_SET_RATE_PARENT,
1528 .ops = &clk_branch2_ops,
1529 },
1530 },
1531};
1532
1533static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1534 .halt_reg = 0x07c4,
1535 .clkr = {
1536 .enable_reg = 0x07c4,
1537 .enable_mask = BIT(0),
1538 .hw.init = &(struct clk_init_data){
1539 .name = "gcc_blsp1_qup4_spi_apps_clk",
1540 .parent_names = (const char *[]){
1541 "blsp1_qup4_spi_apps_clk_src",
1542 },
1543 .num_parents = 1,
1544 .flags = CLK_SET_RATE_PARENT,
1545 .ops = &clk_branch2_ops,
1546 },
1547 },
1548};
1549
1550static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1551 .halt_reg = 0x0848,
1552 .clkr = {
1553 .enable_reg = 0x0848,
1554 .enable_mask = BIT(0),
1555 .hw.init = &(struct clk_init_data){
1556 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1557 .parent_names = (const char *[]){
1558 "blsp1_qup5_i2c_apps_clk_src",
1559 },
1560 .num_parents = 1,
1561 .flags = CLK_SET_RATE_PARENT,
1562 .ops = &clk_branch2_ops,
1563 },
1564 },
1565};
1566
1567static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1568 .halt_reg = 0x0844,
1569 .clkr = {
1570 .enable_reg = 0x0844,
1571 .enable_mask = BIT(0),
1572 .hw.init = &(struct clk_init_data){
1573 .name = "gcc_blsp1_qup5_spi_apps_clk",
1574 .parent_names = (const char *[]){
1575 "blsp1_qup5_spi_apps_clk_src",
1576 },
1577 .num_parents = 1,
1578 .flags = CLK_SET_RATE_PARENT,
1579 .ops = &clk_branch2_ops,
1580 },
1581 },
1582};
1583
1584static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1585 .halt_reg = 0x08c8,
1586 .clkr = {
1587 .enable_reg = 0x08c8,
1588 .enable_mask = BIT(0),
1589 .hw.init = &(struct clk_init_data){
1590 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1591 .parent_names = (const char *[]){
1592 "blsp1_qup6_i2c_apps_clk_src",
1593 },
1594 .num_parents = 1,
1595 .flags = CLK_SET_RATE_PARENT,
1596 .ops = &clk_branch2_ops,
1597 },
1598 },
1599};
1600
1601static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1602 .halt_reg = 0x08c4,
1603 .clkr = {
1604 .enable_reg = 0x08c4,
1605 .enable_mask = BIT(0),
1606 .hw.init = &(struct clk_init_data){
1607 .name = "gcc_blsp1_qup6_spi_apps_clk",
1608 .parent_names = (const char *[]){
1609 "blsp1_qup6_spi_apps_clk_src",
1610 },
1611 .num_parents = 1,
1612 .flags = CLK_SET_RATE_PARENT,
1613 .ops = &clk_branch2_ops,
1614 },
1615 },
1616};
1617
1618static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1619 .halt_reg = 0x0684,
1620 .clkr = {
1621 .enable_reg = 0x0684,
1622 .enable_mask = BIT(0),
1623 .hw.init = &(struct clk_init_data){
1624 .name = "gcc_blsp1_uart1_apps_clk",
1625 .parent_names = (const char *[]){
1626 "blsp1_uart1_apps_clk_src",
1627 },
1628 .num_parents = 1,
1629 .flags = CLK_SET_RATE_PARENT,
1630 .ops = &clk_branch2_ops,
1631 },
1632 },
1633};
1634
1635static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1636 .halt_reg = 0x0704,
1637 .clkr = {
1638 .enable_reg = 0x0704,
1639 .enable_mask = BIT(0),
1640 .hw.init = &(struct clk_init_data){
1641 .name = "gcc_blsp1_uart2_apps_clk",
1642 .parent_names = (const char *[]){
1643 "blsp1_uart2_apps_clk_src",
1644 },
1645 .num_parents = 1,
1646 .flags = CLK_SET_RATE_PARENT,
1647 .ops = &clk_branch2_ops,
1648 },
1649 },
1650};
1651
1652static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1653 .halt_reg = 0x0784,
1654 .clkr = {
1655 .enable_reg = 0x0784,
1656 .enable_mask = BIT(0),
1657 .hw.init = &(struct clk_init_data){
1658 .name = "gcc_blsp1_uart3_apps_clk",
1659 .parent_names = (const char *[]){
1660 "blsp1_uart3_apps_clk_src",
1661 },
1662 .num_parents = 1,
1663 .flags = CLK_SET_RATE_PARENT,
1664 .ops = &clk_branch2_ops,
1665 },
1666 },
1667};
1668
1669static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1670 .halt_reg = 0x0804,
1671 .clkr = {
1672 .enable_reg = 0x0804,
1673 .enable_mask = BIT(0),
1674 .hw.init = &(struct clk_init_data){
1675 .name = "gcc_blsp1_uart4_apps_clk",
1676 .parent_names = (const char *[]){
1677 "blsp1_uart4_apps_clk_src",
1678 },
1679 .num_parents = 1,
1680 .flags = CLK_SET_RATE_PARENT,
1681 .ops = &clk_branch2_ops,
1682 },
1683 },
1684};
1685
1686static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1687 .halt_reg = 0x0884,
1688 .clkr = {
1689 .enable_reg = 0x0884,
1690 .enable_mask = BIT(0),
1691 .hw.init = &(struct clk_init_data){
1692 .name = "gcc_blsp1_uart5_apps_clk",
1693 .parent_names = (const char *[]){
1694 "blsp1_uart5_apps_clk_src",
1695 },
1696 .num_parents = 1,
1697 .flags = CLK_SET_RATE_PARENT,
1698 .ops = &clk_branch2_ops,
1699 },
1700 },
1701};
1702
1703static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1704 .halt_reg = 0x0904,
1705 .clkr = {
1706 .enable_reg = 0x0904,
1707 .enable_mask = BIT(0),
1708 .hw.init = &(struct clk_init_data){
1709 .name = "gcc_blsp1_uart6_apps_clk",
1710 .parent_names = (const char *[]){
1711 "blsp1_uart6_apps_clk_src",
1712 },
1713 .num_parents = 1,
1714 .flags = CLK_SET_RATE_PARENT,
1715 .ops = &clk_branch2_ops,
1716 },
1717 },
1718};
1719
1720static struct clk_branch gcc_blsp2_ahb_clk = {
1721 .halt_reg = 0x0944,
1722 .halt_check = BRANCH_HALT_VOTED,
1723 .clkr = {
1724 .enable_reg = 0x1484,
1725 .enable_mask = BIT(15),
1726 .hw.init = &(struct clk_init_data){
1727 .name = "gcc_blsp2_ahb_clk",
1728 .parent_names = (const char *[]){
1729 "periph_noc_clk_src",
1730 },
1731 .num_parents = 1,
1732 .ops = &clk_branch2_ops,
1733 },
1734 },
1735};
1736
1737static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1738 .halt_reg = 0x0988,
1739 .clkr = {
1740 .enable_reg = 0x0988,
1741 .enable_mask = BIT(0),
1742 .hw.init = &(struct clk_init_data){
1743 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1744 .parent_names = (const char *[]){
1745 "blsp2_qup1_i2c_apps_clk_src",
1746 },
1747 .num_parents = 1,
1748 .flags = CLK_SET_RATE_PARENT,
1749 .ops = &clk_branch2_ops,
1750 },
1751 },
1752};
1753
1754static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1755 .halt_reg = 0x0984,
1756 .clkr = {
1757 .enable_reg = 0x0984,
1758 .enable_mask = BIT(0),
1759 .hw.init = &(struct clk_init_data){
1760 .name = "gcc_blsp2_qup1_spi_apps_clk",
1761 .parent_names = (const char *[]){
1762 "blsp2_qup1_spi_apps_clk_src",
1763 },
1764 .num_parents = 1,
1765 .flags = CLK_SET_RATE_PARENT,
1766 .ops = &clk_branch2_ops,
1767 },
1768 },
1769};
1770
1771static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1772 .halt_reg = 0x0a08,
1773 .clkr = {
1774 .enable_reg = 0x0a08,
1775 .enable_mask = BIT(0),
1776 .hw.init = &(struct clk_init_data){
1777 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1778 .parent_names = (const char *[]){
1779 "blsp2_qup2_i2c_apps_clk_src",
1780 },
1781 .num_parents = 1,
1782 .flags = CLK_SET_RATE_PARENT,
1783 .ops = &clk_branch2_ops,
1784 },
1785 },
1786};
1787
1788static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1789 .halt_reg = 0x0a04,
1790 .clkr = {
1791 .enable_reg = 0x0a04,
1792 .enable_mask = BIT(0),
1793 .hw.init = &(struct clk_init_data){
1794 .name = "gcc_blsp2_qup2_spi_apps_clk",
1795 .parent_names = (const char *[]){
1796 "blsp2_qup2_spi_apps_clk_src",
1797 },
1798 .num_parents = 1,
1799 .flags = CLK_SET_RATE_PARENT,
1800 .ops = &clk_branch2_ops,
1801 },
1802 },
1803};
1804
1805static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1806 .halt_reg = 0x0a88,
1807 .clkr = {
1808 .enable_reg = 0x0a88,
1809 .enable_mask = BIT(0),
1810 .hw.init = &(struct clk_init_data){
1811 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1812 .parent_names = (const char *[]){
1813 "blsp2_qup3_i2c_apps_clk_src",
1814 },
1815 .num_parents = 1,
1816 .flags = CLK_SET_RATE_PARENT,
1817 .ops = &clk_branch2_ops,
1818 },
1819 },
1820};
1821
1822static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1823 .halt_reg = 0x0a84,
1824 .clkr = {
1825 .enable_reg = 0x0a84,
1826 .enable_mask = BIT(0),
1827 .hw.init = &(struct clk_init_data){
1828 .name = "gcc_blsp2_qup3_spi_apps_clk",
1829 .parent_names = (const char *[]){
1830 "blsp2_qup3_spi_apps_clk_src",
1831 },
1832 .num_parents = 1,
1833 .flags = CLK_SET_RATE_PARENT,
1834 .ops = &clk_branch2_ops,
1835 },
1836 },
1837};
1838
1839static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1840 .halt_reg = 0x0b08,
1841 .clkr = {
1842 .enable_reg = 0x0b08,
1843 .enable_mask = BIT(0),
1844 .hw.init = &(struct clk_init_data){
1845 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1846 .parent_names = (const char *[]){
1847 "blsp2_qup4_i2c_apps_clk_src",
1848 },
1849 .num_parents = 1,
1850 .flags = CLK_SET_RATE_PARENT,
1851 .ops = &clk_branch2_ops,
1852 },
1853 },
1854};
1855
1856static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1857 .halt_reg = 0x0b04,
1858 .clkr = {
1859 .enable_reg = 0x0b04,
1860 .enable_mask = BIT(0),
1861 .hw.init = &(struct clk_init_data){
1862 .name = "gcc_blsp2_qup4_spi_apps_clk",
1863 .parent_names = (const char *[]){
1864 "blsp2_qup4_spi_apps_clk_src",
1865 },
1866 .num_parents = 1,
1867 .flags = CLK_SET_RATE_PARENT,
1868 .ops = &clk_branch2_ops,
1869 },
1870 },
1871};
1872
1873static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1874 .halt_reg = 0x0b88,
1875 .clkr = {
1876 .enable_reg = 0x0b88,
1877 .enable_mask = BIT(0),
1878 .hw.init = &(struct clk_init_data){
1879 .name = "gcc_blsp2_qup5_i2c_apps_clk",
1880 .parent_names = (const char *[]){
1881 "blsp2_qup5_i2c_apps_clk_src",
1882 },
1883 .num_parents = 1,
1884 .flags = CLK_SET_RATE_PARENT,
1885 .ops = &clk_branch2_ops,
1886 },
1887 },
1888};
1889
1890static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1891 .halt_reg = 0x0b84,
1892 .clkr = {
1893 .enable_reg = 0x0b84,
1894 .enable_mask = BIT(0),
1895 .hw.init = &(struct clk_init_data){
1896 .name = "gcc_blsp2_qup5_spi_apps_clk",
1897 .parent_names = (const char *[]){
1898 "blsp2_qup5_spi_apps_clk_src",
1899 },
1900 .num_parents = 1,
1901 .flags = CLK_SET_RATE_PARENT,
1902 .ops = &clk_branch2_ops,
1903 },
1904 },
1905};
1906
1907static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1908 .halt_reg = 0x0c08,
1909 .clkr = {
1910 .enable_reg = 0x0c08,
1911 .enable_mask = BIT(0),
1912 .hw.init = &(struct clk_init_data){
1913 .name = "gcc_blsp2_qup6_i2c_apps_clk",
1914 .parent_names = (const char *[]){
1915 "blsp2_qup6_i2c_apps_clk_src",
1916 },
1917 .num_parents = 1,
1918 .flags = CLK_SET_RATE_PARENT,
1919 .ops = &clk_branch2_ops,
1920 },
1921 },
1922};
1923
1924static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1925 .halt_reg = 0x0c04,
1926 .clkr = {
1927 .enable_reg = 0x0c04,
1928 .enable_mask = BIT(0),
1929 .hw.init = &(struct clk_init_data){
1930 .name = "gcc_blsp2_qup6_spi_apps_clk",
1931 .parent_names = (const char *[]){
1932 "blsp2_qup6_spi_apps_clk_src",
1933 },
1934 .num_parents = 1,
1935 .flags = CLK_SET_RATE_PARENT,
1936 .ops = &clk_branch2_ops,
1937 },
1938 },
1939};
1940
1941static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1942 .halt_reg = 0x09c4,
1943 .clkr = {
1944 .enable_reg = 0x09c4,
1945 .enable_mask = BIT(0),
1946 .hw.init = &(struct clk_init_data){
1947 .name = "gcc_blsp2_uart1_apps_clk",
1948 .parent_names = (const char *[]){
1949 "blsp2_uart1_apps_clk_src",
1950 },
1951 .num_parents = 1,
1952 .flags = CLK_SET_RATE_PARENT,
1953 .ops = &clk_branch2_ops,
1954 },
1955 },
1956};
1957
1958static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1959 .halt_reg = 0x0a44,
1960 .clkr = {
1961 .enable_reg = 0x0a44,
1962 .enable_mask = BIT(0),
1963 .hw.init = &(struct clk_init_data){
1964 .name = "gcc_blsp2_uart2_apps_clk",
1965 .parent_names = (const char *[]){
1966 "blsp2_uart2_apps_clk_src",
1967 },
1968 .num_parents = 1,
1969 .flags = CLK_SET_RATE_PARENT,
1970 .ops = &clk_branch2_ops,
1971 },
1972 },
1973};
1974
1975static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1976 .halt_reg = 0x0ac4,
1977 .clkr = {
1978 .enable_reg = 0x0ac4,
1979 .enable_mask = BIT(0),
1980 .hw.init = &(struct clk_init_data){
1981 .name = "gcc_blsp2_uart3_apps_clk",
1982 .parent_names = (const char *[]){
1983 "blsp2_uart3_apps_clk_src",
1984 },
1985 .num_parents = 1,
1986 .flags = CLK_SET_RATE_PARENT,
1987 .ops = &clk_branch2_ops,
1988 },
1989 },
1990};
1991
1992static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1993 .halt_reg = 0x0b44,
1994 .clkr = {
1995 .enable_reg = 0x0b44,
1996 .enable_mask = BIT(0),
1997 .hw.init = &(struct clk_init_data){
1998 .name = "gcc_blsp2_uart4_apps_clk",
1999 .parent_names = (const char *[]){
2000 "blsp2_uart4_apps_clk_src",
2001 },
2002 .num_parents = 1,
2003 .flags = CLK_SET_RATE_PARENT,
2004 .ops = &clk_branch2_ops,
2005 },
2006 },
2007};
2008
2009static struct clk_branch gcc_blsp2_uart5_apps_clk = {
2010 .halt_reg = 0x0bc4,
2011 .clkr = {
2012 .enable_reg = 0x0bc4,
2013 .enable_mask = BIT(0),
2014 .hw.init = &(struct clk_init_data){
2015 .name = "gcc_blsp2_uart5_apps_clk",
2016 .parent_names = (const char *[]){
2017 "blsp2_uart5_apps_clk_src",
2018 },
2019 .num_parents = 1,
2020 .flags = CLK_SET_RATE_PARENT,
2021 .ops = &clk_branch2_ops,
2022 },
2023 },
2024};
2025
2026static struct clk_branch gcc_blsp2_uart6_apps_clk = {
2027 .halt_reg = 0x0c44,
2028 .clkr = {
2029 .enable_reg = 0x0c44,
2030 .enable_mask = BIT(0),
2031 .hw.init = &(struct clk_init_data){
2032 .name = "gcc_blsp2_uart6_apps_clk",
2033 .parent_names = (const char *[]){
2034 "blsp2_uart6_apps_clk_src",
2035 },
2036 .num_parents = 1,
2037 .flags = CLK_SET_RATE_PARENT,
2038 .ops = &clk_branch2_ops,
2039 },
2040 },
2041};
2042
2043static struct clk_branch gcc_boot_rom_ahb_clk = {
2044 .halt_reg = 0x0e04,
2045 .halt_check = BRANCH_HALT_VOTED,
2046 .clkr = {
2047 .enable_reg = 0x1484,
2048 .enable_mask = BIT(10),
2049 .hw.init = &(struct clk_init_data){
2050 .name = "gcc_boot_rom_ahb_clk",
2051 .parent_names = (const char *[]){
2052 "config_noc_clk_src",
2053 },
2054 .num_parents = 1,
2055 .ops = &clk_branch2_ops,
2056 },
2057 },
2058};
2059
2060static struct clk_branch gcc_ce1_ahb_clk = {
2061 .halt_reg = 0x104c,
2062 .halt_check = BRANCH_HALT_VOTED,
2063 .clkr = {
2064 .enable_reg = 0x1484,
2065 .enable_mask = BIT(3),
2066 .hw.init = &(struct clk_init_data){
2067 .name = "gcc_ce1_ahb_clk",
2068 .parent_names = (const char *[]){
2069 "config_noc_clk_src",
2070 },
2071 .num_parents = 1,
2072 .ops = &clk_branch2_ops,
2073 },
2074 },
2075};
2076
2077static struct clk_branch gcc_ce1_axi_clk = {
2078 .halt_reg = 0x1048,
2079 .halt_check = BRANCH_HALT_VOTED,
2080 .clkr = {
2081 .enable_reg = 0x1484,
2082 .enable_mask = BIT(4),
2083 .hw.init = &(struct clk_init_data){
2084 .name = "gcc_ce1_axi_clk",
2085 .parent_names = (const char *[]){
2086 "system_noc_clk_src",
2087 },
2088 .num_parents = 1,
2089 .ops = &clk_branch2_ops,
2090 },
2091 },
2092};
2093
2094static struct clk_branch gcc_ce1_clk = {
2095 .halt_reg = 0x1050,
2096 .halt_check = BRANCH_HALT_VOTED,
2097 .clkr = {
2098 .enable_reg = 0x1484,
2099 .enable_mask = BIT(5),
2100 .hw.init = &(struct clk_init_data){
2101 .name = "gcc_ce1_clk",
2102 .parent_names = (const char *[]){
2103 "ce1_clk_src",
2104 },
2105 .num_parents = 1,
2106 .ops = &clk_branch2_ops,
2107 },
2108 },
2109};
2110
2111static struct clk_branch gcc_ce2_ahb_clk = {
2112 .halt_reg = 0x108c,
2113 .halt_check = BRANCH_HALT_VOTED,
2114 .clkr = {
2115 .enable_reg = 0x1484,
2116 .enable_mask = BIT(0),
2117 .hw.init = &(struct clk_init_data){
2118 .name = "gcc_ce2_ahb_clk",
2119 .parent_names = (const char *[]){
2120 "config_noc_clk_src",
2121 },
2122 .num_parents = 1,
2123 .ops = &clk_branch2_ops,
2124 },
2125 },
2126};
2127
2128static struct clk_branch gcc_ce2_axi_clk = {
2129 .halt_reg = 0x1088,
2130 .halt_check = BRANCH_HALT_VOTED,
2131 .clkr = {
2132 .enable_reg = 0x1484,
2133 .enable_mask = BIT(1),
2134 .hw.init = &(struct clk_init_data){
2135 .name = "gcc_ce2_axi_clk",
2136 .parent_names = (const char *[]){
2137 "system_noc_clk_src",
2138 },
2139 .num_parents = 1,
2140 .ops = &clk_branch2_ops,
2141 },
2142 },
2143};
2144
2145static struct clk_branch gcc_ce2_clk = {
2146 .halt_reg = 0x1090,
2147 .halt_check = BRANCH_HALT_VOTED,
2148 .clkr = {
2149 .enable_reg = 0x1484,
2150 .enable_mask = BIT(2),
2151 .hw.init = &(struct clk_init_data){
2152 .name = "gcc_ce2_clk",
2153 .parent_names = (const char *[]){
2154 "ce2_clk_src",
2155 },
2156 .num_parents = 1,
2157 .flags = CLK_SET_RATE_PARENT,
2158 .ops = &clk_branch2_ops,
2159 },
2160 },
2161};
2162
2163static struct clk_branch gcc_ce3_ahb_clk = {
2164 .halt_reg = 0x1d0c,
2165 .halt_check = BRANCH_HALT_VOTED,
2166 .clkr = {
2167 .enable_reg = 0x1d0c,
2168 .enable_mask = BIT(0),
2169 .hw.init = &(struct clk_init_data){
2170 .name = "gcc_ce3_ahb_clk",
2171 .parent_names = (const char *[]){
2172 "config_noc_clk_src",
2173 },
2174 .num_parents = 1,
2175 .ops = &clk_branch2_ops,
2176 },
2177 },
2178};
2179
2180static struct clk_branch gcc_ce3_axi_clk = {
2181 .halt_reg = 0x1088,
2182 .halt_check = BRANCH_HALT_VOTED,
2183 .clkr = {
2184 .enable_reg = 0x1d08,
2185 .enable_mask = BIT(0),
2186 .hw.init = &(struct clk_init_data){
2187 .name = "gcc_ce3_axi_clk",
2188 .parent_names = (const char *[]){
2189 "system_noc_clk_src",
2190 },
2191 .num_parents = 1,
2192 .ops = &clk_branch2_ops,
2193 },
2194 },
2195};
2196
2197static struct clk_branch gcc_ce3_clk = {
2198 .halt_reg = 0x1090,
2199 .halt_check = BRANCH_HALT_VOTED,
2200 .clkr = {
2201 .enable_reg = 0x1d04,
2202 .enable_mask = BIT(0),
2203 .hw.init = &(struct clk_init_data){
2204 .name = "gcc_ce3_clk",
2205 .parent_names = (const char *[]){
2206 "ce3_clk_src",
2207 },
2208 .num_parents = 1,
2209 .flags = CLK_SET_RATE_PARENT,
2210 .ops = &clk_branch2_ops,
2211 },
2212 },
2213};
2214
2215static struct clk_branch gcc_gp1_clk = {
2216 .halt_reg = 0x1900,
2217 .clkr = {
2218 .enable_reg = 0x1900,
2219 .enable_mask = BIT(0),
2220 .hw.init = &(struct clk_init_data){
2221 .name = "gcc_gp1_clk",
2222 .parent_names = (const char *[]){
2223 "gp1_clk_src",
2224 },
2225 .num_parents = 1,
2226 .flags = CLK_SET_RATE_PARENT,
2227 .ops = &clk_branch2_ops,
2228 },
2229 },
2230};
2231
2232static struct clk_branch gcc_gp2_clk = {
2233 .halt_reg = 0x1940,
2234 .clkr = {
2235 .enable_reg = 0x1940,
2236 .enable_mask = BIT(0),
2237 .hw.init = &(struct clk_init_data){
2238 .name = "gcc_gp2_clk",
2239 .parent_names = (const char *[]){
2240 "gp2_clk_src",
2241 },
2242 .num_parents = 1,
2243 .flags = CLK_SET_RATE_PARENT,
2244 .ops = &clk_branch2_ops,
2245 },
2246 },
2247};
2248
2249static struct clk_branch gcc_gp3_clk = {
2250 .halt_reg = 0x1980,
2251 .clkr = {
2252 .enable_reg = 0x1980,
2253 .enable_mask = BIT(0),
2254 .hw.init = &(struct clk_init_data){
2255 .name = "gcc_gp3_clk",
2256 .parent_names = (const char *[]){
2257 "gp3_clk_src",
2258 },
2259 .num_parents = 1,
2260 .flags = CLK_SET_RATE_PARENT,
2261 .ops = &clk_branch2_ops,
2262 },
2263 },
2264};
2265
2266static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = {
2267 .halt_reg = 0x0248,
2268 .clkr = {
2269 .enable_reg = 0x0248,
2270 .enable_mask = BIT(0),
2271 .hw.init = &(struct clk_init_data){
2272 .name = "gcc_ocmem_noc_cfg_ahb_clk",
2273 .parent_names = (const char *[]){
2274 "config_noc_clk_src",
2275 },
2276 .num_parents = 1,
2277 .ops = &clk_branch2_ops,
2278 },
2279 },
2280};
2281
2282static struct clk_branch gcc_pcie_0_aux_clk = {
2283 .halt_reg = 0x1b10,
2284 .clkr = {
2285 .enable_reg = 0x1b10,
2286 .enable_mask = BIT(0),
2287 .hw.init = &(struct clk_init_data){
2288 .name = "gcc_pcie_0_aux_clk",
2289 .parent_names = (const char *[]){
2290 "pcie_0_aux_clk_src",
2291 },
2292 .num_parents = 1,
2293 .flags = CLK_SET_RATE_PARENT,
2294 .ops = &clk_branch2_ops,
2295 },
2296 },
2297};
2298
2299static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2300 .halt_reg = 0x1b0c,
2301 .clkr = {
2302 .enable_reg = 0x1b0c,
2303 .enable_mask = BIT(0),
2304 .hw.init = &(struct clk_init_data){
2305 .name = "gcc_pcie_0_cfg_ahb_clk",
2306 .parent_names = (const char *[]){
2307 "config_noc_clk_src",
2308 },
2309 .num_parents = 1,
2310 .flags = CLK_SET_RATE_PARENT,
2311 .ops = &clk_branch2_ops,
2312 },
2313 },
2314};
2315
2316static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2317 .halt_reg = 0x1b08,
2318 .clkr = {
2319 .enable_reg = 0x1b08,
2320 .enable_mask = BIT(0),
2321 .hw.init = &(struct clk_init_data){
2322 .name = "gcc_pcie_0_mstr_axi_clk",
2323 .parent_names = (const char *[]){
2324 "config_noc_clk_src",
2325 },
2326 .num_parents = 1,
2327 .flags = CLK_SET_RATE_PARENT,
2328 .ops = &clk_branch2_ops,
2329 },
2330 },
2331};
2332
2333static struct clk_branch gcc_pcie_0_pipe_clk = {
2334 .halt_reg = 0x1b14,
2335 .clkr = {
2336 .enable_reg = 0x1b14,
2337 .enable_mask = BIT(0),
2338 .hw.init = &(struct clk_init_data){
2339 .name = "gcc_pcie_0_pipe_clk",
2340 .parent_names = (const char *[]){
2341 "pcie_0_pipe_clk_src",
2342 },
2343 .num_parents = 1,
2344 .flags = CLK_SET_RATE_PARENT,
2345 .ops = &clk_branch2_ops,
2346 },
2347 },
2348};
2349
2350static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2351 .halt_reg = 0x1b04,
2352 .clkr = {
2353 .enable_reg = 0x1b04,
2354 .enable_mask = BIT(0),
2355 .hw.init = &(struct clk_init_data){
2356 .name = "gcc_pcie_0_slv_axi_clk",
2357 .parent_names = (const char *[]){
2358 "config_noc_clk_src",
2359 },
2360 .num_parents = 1,
2361 .flags = CLK_SET_RATE_PARENT,
2362 .ops = &clk_branch2_ops,
2363 },
2364 },
2365};
2366
2367static struct clk_branch gcc_pcie_1_aux_clk = {
2368 .halt_reg = 0x1b90,
2369 .clkr = {
2370 .enable_reg = 0x1b90,
2371 .enable_mask = BIT(0),
2372 .hw.init = &(struct clk_init_data){
2373 .name = "gcc_pcie_1_aux_clk",
2374 .parent_names = (const char *[]){
2375 "pcie_1_aux_clk_src",
2376 },
2377 .num_parents = 1,
2378 .flags = CLK_SET_RATE_PARENT,
2379 .ops = &clk_branch2_ops,
2380 },
2381 },
2382};
2383
2384static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2385 .halt_reg = 0x1b8c,
2386 .clkr = {
2387 .enable_reg = 0x1b8c,
2388 .enable_mask = BIT(0),
2389 .hw.init = &(struct clk_init_data){
2390 .name = "gcc_pcie_1_cfg_ahb_clk",
2391 .parent_names = (const char *[]){
2392 "config_noc_clk_src",
2393 },
2394 .num_parents = 1,
2395 .flags = CLK_SET_RATE_PARENT,
2396 .ops = &clk_branch2_ops,
2397 },
2398 },
2399};
2400
2401static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2402 .halt_reg = 0x1b88,
2403 .clkr = {
2404 .enable_reg = 0x1b88,
2405 .enable_mask = BIT(0),
2406 .hw.init = &(struct clk_init_data){
2407 .name = "gcc_pcie_1_mstr_axi_clk",
2408 .parent_names = (const char *[]){
2409 "config_noc_clk_src",
2410 },
2411 .num_parents = 1,
2412 .flags = CLK_SET_RATE_PARENT,
2413 .ops = &clk_branch2_ops,
2414 },
2415 },
2416};
2417
2418static struct clk_branch gcc_pcie_1_pipe_clk = {
2419 .halt_reg = 0x1b94,
2420 .clkr = {
2421 .enable_reg = 0x1b94,
2422 .enable_mask = BIT(0),
2423 .hw.init = &(struct clk_init_data){
2424 .name = "gcc_pcie_1_pipe_clk",
2425 .parent_names = (const char *[]){
2426 "pcie_1_pipe_clk_src",
2427 },
2428 .num_parents = 1,
2429 .flags = CLK_SET_RATE_PARENT,
2430 .ops = &clk_branch2_ops,
2431 },
2432 },
2433};
2434
2435static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2436 .halt_reg = 0x1b84,
2437 .clkr = {
2438 .enable_reg = 0x1b84,
2439 .enable_mask = BIT(0),
2440 .hw.init = &(struct clk_init_data){
2441 .name = "gcc_pcie_1_slv_axi_clk",
2442 .parent_names = (const char *[]){
2443 "config_noc_clk_src",
2444 },
2445 .num_parents = 1,
2446 .flags = CLK_SET_RATE_PARENT,
2447 .ops = &clk_branch2_ops,
2448 },
2449 },
2450};
2451
2452static struct clk_branch gcc_pdm2_clk = {
2453 .halt_reg = 0x0ccc,
2454 .clkr = {
2455 .enable_reg = 0x0ccc,
2456 .enable_mask = BIT(0),
2457 .hw.init = &(struct clk_init_data){
2458 .name = "gcc_pdm2_clk",
2459 .parent_names = (const char *[]){
2460 "pdm2_clk_src",
2461 },
2462 .num_parents = 1,
2463 .flags = CLK_SET_RATE_PARENT,
2464 .ops = &clk_branch2_ops,
2465 },
2466 },
2467};
2468
2469static struct clk_branch gcc_pdm_ahb_clk = {
2470 .halt_reg = 0x0cc4,
2471 .clkr = {
2472 .enable_reg = 0x0cc4,
2473 .enable_mask = BIT(0),
2474 .hw.init = &(struct clk_init_data){
2475 .name = "gcc_pdm_ahb_clk",
2476 .parent_names = (const char *[]){
2477 "periph_noc_clk_src",
2478 },
2479 .num_parents = 1,
2480 .ops = &clk_branch2_ops,
2481 },
2482 },
2483};
2484
2485static struct clk_branch gcc_periph_noc_usb_hsic_ahb_clk = {
2486 .halt_reg = 0x01a4,
2487 .clkr = {
2488 .enable_reg = 0x01a4,
2489 .enable_mask = BIT(0),
2490 .hw.init = &(struct clk_init_data){
2491 .name = "gcc_periph_noc_usb_hsic_ahb_clk",
2492 .parent_names = (const char *[]){
2493 "usb_hsic_ahb_clk_src",
2494 },
2495 .num_parents = 1,
2496 .flags = CLK_SET_RATE_PARENT,
2497 .ops = &clk_branch2_ops,
2498 },
2499 },
2500};
2501
2502static struct clk_branch gcc_prng_ahb_clk = {
2503 .halt_reg = 0x0d04,
2504 .halt_check = BRANCH_HALT_VOTED,
2505 .clkr = {
2506 .enable_reg = 0x1484,
2507 .enable_mask = BIT(13),
2508 .hw.init = &(struct clk_init_data){
2509 .name = "gcc_prng_ahb_clk",
2510 .parent_names = (const char *[]){
2511 "periph_noc_clk_src",
2512 },
2513 .num_parents = 1,
2514 .ops = &clk_branch2_ops,
2515 },
2516 },
2517};
2518
2519static struct clk_branch gcc_sata_asic0_clk = {
2520 .halt_reg = 0x1c54,
2521 .clkr = {
2522 .enable_reg = 0x1c54,
2523 .enable_mask = BIT(0),
2524 .hw.init = &(struct clk_init_data){
2525 .name = "gcc_sata_asic0_clk",
2526 .parent_names = (const char *[]){
2527 "sata_asic0_clk_src",
2528 },
2529 .num_parents = 1,
2530 .flags = CLK_SET_RATE_PARENT,
2531 .ops = &clk_branch2_ops,
2532 },
2533 },
2534};
2535
2536static struct clk_branch gcc_sata_axi_clk = {
2537 .halt_reg = 0x1c44,
2538 .clkr = {
2539 .enable_reg = 0x1c44,
2540 .enable_mask = BIT(0),
2541 .hw.init = &(struct clk_init_data){
2542 .name = "gcc_sata_axi_clk",
2543 .parent_names = (const char *[]){
2544 "config_noc_clk_src",
2545 },
2546 .num_parents = 1,
2547 .flags = CLK_SET_RATE_PARENT,
2548 .ops = &clk_branch2_ops,
2549 },
2550 },
2551};
2552
2553static struct clk_branch gcc_sata_cfg_ahb_clk = {
2554 .halt_reg = 0x1c48,
2555 .clkr = {
2556 .enable_reg = 0x1c48,
2557 .enable_mask = BIT(0),
2558 .hw.init = &(struct clk_init_data){
2559 .name = "gcc_sata_cfg_ahb_clk",
2560 .parent_names = (const char *[]){
2561 "config_noc_clk_src",
2562 },
2563 .num_parents = 1,
2564 .flags = CLK_SET_RATE_PARENT,
2565 .ops = &clk_branch2_ops,
2566 },
2567 },
2568};
2569
2570static struct clk_branch gcc_sata_pmalive_clk = {
2571 .halt_reg = 0x1c50,
2572 .clkr = {
2573 .enable_reg = 0x1c50,
2574 .enable_mask = BIT(0),
2575 .hw.init = &(struct clk_init_data){
2576 .name = "gcc_sata_pmalive_clk",
2577 .parent_names = (const char *[]){
2578 "sata_pmalive_clk_src",
2579 },
2580 .num_parents = 1,
2581 .flags = CLK_SET_RATE_PARENT,
2582 .ops = &clk_branch2_ops,
2583 },
2584 },
2585};
2586
2587static struct clk_branch gcc_sata_rx_clk = {
2588 .halt_reg = 0x1c58,
2589 .clkr = {
2590 .enable_reg = 0x1c58,
2591 .enable_mask = BIT(0),
2592 .hw.init = &(struct clk_init_data){
2593 .name = "gcc_sata_rx_clk",
2594 .parent_names = (const char *[]){
2595 "sata_rx_clk_src",
2596 },
2597 .num_parents = 1,
2598 .flags = CLK_SET_RATE_PARENT,
2599 .ops = &clk_branch2_ops,
2600 },
2601 },
2602};
2603
2604static struct clk_branch gcc_sata_rx_oob_clk = {
2605 .halt_reg = 0x1c4c,
2606 .clkr = {
2607 .enable_reg = 0x1c4c,
2608 .enable_mask = BIT(0),
2609 .hw.init = &(struct clk_init_data){
2610 .name = "gcc_sata_rx_oob_clk",
2611 .parent_names = (const char *[]){
2612 "sata_rx_oob_clk_src",
2613 },
2614 .num_parents = 1,
2615 .flags = CLK_SET_RATE_PARENT,
2616 .ops = &clk_branch2_ops,
2617 },
2618 },
2619};
2620
2621static struct clk_branch gcc_sdcc1_ahb_clk = {
2622 .halt_reg = 0x04c8,
2623 .clkr = {
2624 .enable_reg = 0x04c8,
2625 .enable_mask = BIT(0),
2626 .hw.init = &(struct clk_init_data){
2627 .name = "gcc_sdcc1_ahb_clk",
2628 .parent_names = (const char *[]){
2629 "periph_noc_clk_src",
2630 },
2631 .num_parents = 1,
2632 .ops = &clk_branch2_ops,
2633 },
2634 },
2635};
2636
2637static struct clk_branch gcc_sdcc1_apps_clk = {
2638 .halt_reg = 0x04c4,
2639 .clkr = {
2640 .enable_reg = 0x04c4,
2641 .enable_mask = BIT(0),
2642 .hw.init = &(struct clk_init_data){
2643 .name = "gcc_sdcc1_apps_clk",
2644 .parent_names = (const char *[]){
2645 "sdcc1_apps_clk_src",
2646 },
2647 .num_parents = 1,
2648 .flags = CLK_SET_RATE_PARENT,
2649 .ops = &clk_branch2_ops,
2650 },
2651 },
2652};
2653
2654static struct clk_branch gcc_sdcc1_cdccal_ff_clk = {
2655 .halt_reg = 0x04e8,
2656 .clkr = {
2657 .enable_reg = 0x04e8,
2658 .enable_mask = BIT(0),
2659 .hw.init = &(struct clk_init_data){
2660 .name = "gcc_sdcc1_cdccal_ff_clk",
2661 .parent_names = (const char *[]){
2662 "xo"
2663 },
2664 .num_parents = 1,
2665 .ops = &clk_branch2_ops,
2666 },
2667 },
2668};
2669
2670static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = {
2671 .halt_reg = 0x04e4,
2672 .clkr = {
2673 .enable_reg = 0x04e4,
2674 .enable_mask = BIT(0),
2675 .hw.init = &(struct clk_init_data){
2676 .name = "gcc_sdcc1_cdccal_sleep_clk",
2677 .parent_names = (const char *[]){
2678 "sleep_clk_src"
2679 },
2680 .num_parents = 1,
2681 .ops = &clk_branch2_ops,
2682 },
2683 },
2684};
2685
2686static struct clk_branch gcc_sdcc2_ahb_clk = {
2687 .halt_reg = 0x0508,
2688 .clkr = {
2689 .enable_reg = 0x0508,
2690 .enable_mask = BIT(0),
2691 .hw.init = &(struct clk_init_data){
2692 .name = "gcc_sdcc2_ahb_clk",
2693 .parent_names = (const char *[]){
2694 "periph_noc_clk_src",
2695 },
2696 .num_parents = 1,
2697 .ops = &clk_branch2_ops,
2698 },
2699 },
2700};
2701
2702static struct clk_branch gcc_sdcc2_apps_clk = {
2703 .halt_reg = 0x0504,
2704 .clkr = {
2705 .enable_reg = 0x0504,
2706 .enable_mask = BIT(0),
2707 .hw.init = &(struct clk_init_data){
2708 .name = "gcc_sdcc2_apps_clk",
2709 .parent_names = (const char *[]){
2710 "sdcc2_apps_clk_src",
2711 },
2712 .num_parents = 1,
2713 .flags = CLK_SET_RATE_PARENT,
2714 .ops = &clk_branch2_ops,
2715 },
2716 },
2717};
2718
2719static struct clk_branch gcc_sdcc3_ahb_clk = {
2720 .halt_reg = 0x0548,
2721 .clkr = {
2722 .enable_reg = 0x0548,
2723 .enable_mask = BIT(0),
2724 .hw.init = &(struct clk_init_data){
2725 .name = "gcc_sdcc3_ahb_clk",
2726 .parent_names = (const char *[]){
2727 "periph_noc_clk_src",
2728 },
2729 .num_parents = 1,
2730 .ops = &clk_branch2_ops,
2731 },
2732 },
2733};
2734
2735static struct clk_branch gcc_sdcc3_apps_clk = {
2736 .halt_reg = 0x0544,
2737 .clkr = {
2738 .enable_reg = 0x0544,
2739 .enable_mask = BIT(0),
2740 .hw.init = &(struct clk_init_data){
2741 .name = "gcc_sdcc3_apps_clk",
2742 .parent_names = (const char *[]){
2743 "sdcc3_apps_clk_src",
2744 },
2745 .num_parents = 1,
2746 .flags = CLK_SET_RATE_PARENT,
2747 .ops = &clk_branch2_ops,
2748 },
2749 },
2750};
2751
2752static struct clk_branch gcc_sdcc4_ahb_clk = {
2753 .halt_reg = 0x0588,
2754 .clkr = {
2755 .enable_reg = 0x0588,
2756 .enable_mask = BIT(0),
2757 .hw.init = &(struct clk_init_data){
2758 .name = "gcc_sdcc4_ahb_clk",
2759 .parent_names = (const char *[]){
2760 "periph_noc_clk_src",
2761 },
2762 .num_parents = 1,
2763 .ops = &clk_branch2_ops,
2764 },
2765 },
2766};
2767
2768static struct clk_branch gcc_sdcc4_apps_clk = {
2769 .halt_reg = 0x0584,
2770 .clkr = {
2771 .enable_reg = 0x0584,
2772 .enable_mask = BIT(0),
2773 .hw.init = &(struct clk_init_data){
2774 .name = "gcc_sdcc4_apps_clk",
2775 .parent_names = (const char *[]){
2776 "sdcc4_apps_clk_src",
2777 },
2778 .num_parents = 1,
2779 .flags = CLK_SET_RATE_PARENT,
2780 .ops = &clk_branch2_ops,
2781 },
2782 },
2783};
2784
2785static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
2786 .halt_reg = 0x013c,
2787 .clkr = {
2788 .enable_reg = 0x013c,
2789 .enable_mask = BIT(0),
2790 .hw.init = &(struct clk_init_data){
2791 .name = "gcc_sys_noc_ufs_axi_clk",
2792 .parent_names = (const char *[]){
2793 "ufs_axi_clk_src",
2794 },
2795 .num_parents = 1,
2796 .flags = CLK_SET_RATE_PARENT,
2797 .ops = &clk_branch2_ops,
2798 },
2799 },
2800};
2801
2802static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
2803 .halt_reg = 0x0108,
2804 .clkr = {
2805 .enable_reg = 0x0108,
2806 .enable_mask = BIT(0),
2807 .hw.init = &(struct clk_init_data){
2808 .name = "gcc_sys_noc_usb3_axi_clk",
2809 .parent_names = (const char *[]){
2810 "usb30_master_clk_src",
2811 },
2812 .num_parents = 1,
2813 .flags = CLK_SET_RATE_PARENT,
2814 .ops = &clk_branch2_ops,
2815 },
2816 },
2817};
2818
2819static struct clk_branch gcc_sys_noc_usb3_sec_axi_clk = {
2820 .halt_reg = 0x0138,
2821 .clkr = {
2822 .enable_reg = 0x0138,
2823 .enable_mask = BIT(0),
2824 .hw.init = &(struct clk_init_data){
2825 .name = "gcc_sys_noc_usb3_sec_axi_clk",
2826 .parent_names = (const char *[]){
2827 "usb30_sec_master_clk_src",
2828 },
2829 .num_parents = 1,
2830 .flags = CLK_SET_RATE_PARENT,
2831 .ops = &clk_branch2_ops,
2832 },
2833 },
2834};
2835
2836static struct clk_branch gcc_tsif_ahb_clk = {
2837 .halt_reg = 0x0d84,
2838 .clkr = {
2839 .enable_reg = 0x0d84,
2840 .enable_mask = BIT(0),
2841 .hw.init = &(struct clk_init_data){
2842 .name = "gcc_tsif_ahb_clk",
2843 .parent_names = (const char *[]){
2844 "periph_noc_clk_src",
2845 },
2846 .num_parents = 1,
2847 .ops = &clk_branch2_ops,
2848 },
2849 },
2850};
2851
2852static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2853 .halt_reg = 0x0d8c,
2854 .clkr = {
2855 .enable_reg = 0x0d8c,
2856 .enable_mask = BIT(0),
2857 .hw.init = &(struct clk_init_data){
2858 .name = "gcc_tsif_inactivity_timers_clk",
2859 .parent_names = (const char *[]){
2860 "sleep_clk_src",
2861 },
2862 .num_parents = 1,
2863 .flags = CLK_SET_RATE_PARENT,
2864 .ops = &clk_branch2_ops,
2865 },
2866 },
2867};
2868
2869static struct clk_branch gcc_tsif_ref_clk = {
2870 .halt_reg = 0x0d88,
2871 .clkr = {
2872 .enable_reg = 0x0d88,
2873 .enable_mask = BIT(0),
2874 .hw.init = &(struct clk_init_data){
2875 .name = "gcc_tsif_ref_clk",
2876 .parent_names = (const char *[]){
2877 "tsif_ref_clk_src",
2878 },
2879 .num_parents = 1,
2880 .flags = CLK_SET_RATE_PARENT,
2881 .ops = &clk_branch2_ops,
2882 },
2883 },
2884};
2885
2886static struct clk_branch gcc_ufs_ahb_clk = {
2887 .halt_reg = 0x1d48,
2888 .clkr = {
2889 .enable_reg = 0x1d48,
2890 .enable_mask = BIT(0),
2891 .hw.init = &(struct clk_init_data){
2892 .name = "gcc_ufs_ahb_clk",
2893 .parent_names = (const char *[]){
2894 "config_noc_clk_src",
2895 },
2896 .num_parents = 1,
2897 .flags = CLK_SET_RATE_PARENT,
2898 .ops = &clk_branch2_ops,
2899 },
2900 },
2901};
2902
2903static struct clk_branch gcc_ufs_axi_clk = {
2904 .halt_reg = 0x1d44,
2905 .clkr = {
2906 .enable_reg = 0x1d44,
2907 .enable_mask = BIT(0),
2908 .hw.init = &(struct clk_init_data){
2909 .name = "gcc_ufs_axi_clk",
2910 .parent_names = (const char *[]){
2911 "ufs_axi_clk_src",
2912 },
2913 .num_parents = 1,
2914 .flags = CLK_SET_RATE_PARENT,
2915 .ops = &clk_branch2_ops,
2916 },
2917 },
2918};
2919
2920static struct clk_branch gcc_ufs_rx_cfg_clk = {
2921 .halt_reg = 0x1d50,
2922 .clkr = {
2923 .enable_reg = 0x1d50,
2924 .enable_mask = BIT(0),
2925 .hw.init = &(struct clk_init_data){
2926 .name = "gcc_ufs_rx_cfg_clk",
2927 .parent_names = (const char *[]){
2928 "ufs_axi_clk_src",
2929 },
2930 .num_parents = 1,
2931 .flags = CLK_SET_RATE_PARENT,
2932 .ops = &clk_branch2_ops,
2933 },
2934 },
2935};
2936
2937static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2938 .halt_reg = 0x1d5c,
2939 .clkr = {
2940 .enable_reg = 0x1d5c,
2941 .enable_mask = BIT(0),
2942 .hw.init = &(struct clk_init_data){
2943 .name = "gcc_ufs_rx_symbol_0_clk",
2944 .parent_names = (const char *[]){
2945 "ufs_rx_symbol_0_clk_src",
2946 },
2947 .num_parents = 1,
2948 .flags = CLK_SET_RATE_PARENT,
2949 .ops = &clk_branch2_ops,
2950 },
2951 },
2952};
2953
2954static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2955 .halt_reg = 0x1d60,
2956 .clkr = {
2957 .enable_reg = 0x1d60,
2958 .enable_mask = BIT(0),
2959 .hw.init = &(struct clk_init_data){
2960 .name = "gcc_ufs_rx_symbol_1_clk",
2961 .parent_names = (const char *[]){
2962 "ufs_rx_symbol_1_clk_src",
2963 },
2964 .num_parents = 1,
2965 .flags = CLK_SET_RATE_PARENT,
2966 .ops = &clk_branch2_ops,
2967 },
2968 },
2969};
2970
2971static struct clk_branch gcc_ufs_tx_cfg_clk = {
2972 .halt_reg = 0x1d4c,
2973 .clkr = {
2974 .enable_reg = 0x1d4c,
2975 .enable_mask = BIT(0),
2976 .hw.init = &(struct clk_init_data){
2977 .name = "gcc_ufs_tx_cfg_clk",
2978 .parent_names = (const char *[]){
2979 "ufs_axi_clk_src",
2980 },
2981 .num_parents = 1,
2982 .flags = CLK_SET_RATE_PARENT,
2983 .ops = &clk_branch2_ops,
2984 },
2985 },
2986};
2987
2988static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2989 .halt_reg = 0x1d54,
2990 .clkr = {
2991 .enable_reg = 0x1d54,
2992 .enable_mask = BIT(0),
2993 .hw.init = &(struct clk_init_data){
2994 .name = "gcc_ufs_tx_symbol_0_clk",
2995 .parent_names = (const char *[]){
2996 "ufs_tx_symbol_0_clk_src",
2997 },
2998 .num_parents = 1,
2999 .flags = CLK_SET_RATE_PARENT,
3000 .ops = &clk_branch2_ops,
3001 },
3002 },
3003};
3004
3005static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
3006 .halt_reg = 0x1d58,
3007 .clkr = {
3008 .enable_reg = 0x1d58,
3009 .enable_mask = BIT(0),
3010 .hw.init = &(struct clk_init_data){
3011 .name = "gcc_ufs_tx_symbol_1_clk",
3012 .parent_names = (const char *[]){
3013 "ufs_tx_symbol_1_clk_src",
3014 },
3015 .num_parents = 1,
3016 .flags = CLK_SET_RATE_PARENT,
3017 .ops = &clk_branch2_ops,
3018 },
3019 },
3020};
3021
3022static struct clk_branch gcc_usb2a_phy_sleep_clk = {
3023 .halt_reg = 0x04ac,
3024 .clkr = {
3025 .enable_reg = 0x04ac,
3026 .enable_mask = BIT(0),
3027 .hw.init = &(struct clk_init_data){
3028 .name = "gcc_usb2a_phy_sleep_clk",
3029 .parent_names = (const char *[]){
3030 "sleep_clk_src",
3031 },
3032 .num_parents = 1,
3033 .ops = &clk_branch2_ops,
3034 },
3035 },
3036};
3037
3038static struct clk_branch gcc_usb2b_phy_sleep_clk = {
3039 .halt_reg = 0x04b4,
3040 .clkr = {
3041 .enable_reg = 0x04b4,
3042 .enable_mask = BIT(0),
3043 .hw.init = &(struct clk_init_data){
3044 .name = "gcc_usb2b_phy_sleep_clk",
3045 .parent_names = (const char *[]){
3046 "sleep_clk_src",
3047 },
3048 .num_parents = 1,
3049 .ops = &clk_branch2_ops,
3050 },
3051 },
3052};
3053
3054static struct clk_branch gcc_usb30_master_clk = {
3055 .halt_reg = 0x03c8,
3056 .clkr = {
3057 .enable_reg = 0x03c8,
3058 .enable_mask = BIT(0),
3059 .hw.init = &(struct clk_init_data){
3060 .name = "gcc_usb30_master_clk",
3061 .parent_names = (const char *[]){
3062 "usb30_master_clk_src",
3063 },
3064 .num_parents = 1,
3065 .flags = CLK_SET_RATE_PARENT,
3066 .ops = &clk_branch2_ops,
3067 },
3068 },
3069};
3070
3071static struct clk_branch gcc_usb30_sec_master_clk = {
3072 .halt_reg = 0x1bc8,
3073 .clkr = {
3074 .enable_reg = 0x1bc8,
3075 .enable_mask = BIT(0),
3076 .hw.init = &(struct clk_init_data){
3077 .name = "gcc_usb30_sec_master_clk",
3078 .parent_names = (const char *[]){
3079 "usb30_sec_master_clk_src",
3080 },
3081 .num_parents = 1,
3082 .flags = CLK_SET_RATE_PARENT,
3083 .ops = &clk_branch2_ops,
3084 },
3085 },
3086};
3087
3088static struct clk_branch gcc_usb30_mock_utmi_clk = {
3089 .halt_reg = 0x03d0,
3090 .clkr = {
3091 .enable_reg = 0x03d0,
3092 .enable_mask = BIT(0),
3093 .hw.init = &(struct clk_init_data){
3094 .name = "gcc_usb30_mock_utmi_clk",
3095 .parent_names = (const char *[]){
3096 "usb30_mock_utmi_clk_src",
3097 },
3098 .num_parents = 1,
3099 .flags = CLK_SET_RATE_PARENT,
3100 .ops = &clk_branch2_ops,
3101 },
3102 },
3103};
3104
3105static struct clk_branch gcc_usb30_sleep_clk = {
3106 .halt_reg = 0x03cc,
3107 .clkr = {
3108 .enable_reg = 0x03cc,
3109 .enable_mask = BIT(0),
3110 .hw.init = &(struct clk_init_data){
3111 .name = "gcc_usb30_sleep_clk",
3112 .parent_names = (const char *[]){
3113 "sleep_clk_src",
3114 },
3115 .num_parents = 1,
3116 .ops = &clk_branch2_ops,
3117 },
3118 },
3119};
3120
3121static struct clk_branch gcc_usb_hs_ahb_clk = {
3122 .halt_reg = 0x0488,
3123 .clkr = {
3124 .enable_reg = 0x0488,
3125 .enable_mask = BIT(0),
3126 .hw.init = &(struct clk_init_data){
3127 .name = "gcc_usb_hs_ahb_clk",
3128 .parent_names = (const char *[]){
3129 "periph_noc_clk_src",
3130 },
3131 .num_parents = 1,
3132 .ops = &clk_branch2_ops,
3133 },
3134 },
3135};
3136
3137static struct clk_branch gcc_usb_hs_inactivity_timers_clk = {
3138 .halt_reg = 0x048c,
3139 .clkr = {
3140 .enable_reg = 0x048c,
3141 .enable_mask = BIT(0),
3142 .hw.init = &(struct clk_init_data){
3143 .name = "gcc_usb_hs_inactivity_timers_clk",
3144 .parent_names = (const char *[]){
3145 "sleep_clk_src",
3146 },
3147 .num_parents = 1,
3148 .flags = CLK_SET_RATE_PARENT,
3149 .ops = &clk_branch2_ops,
3150 },
3151 },
3152};
3153
3154static struct clk_branch gcc_usb_hs_system_clk = {
3155 .halt_reg = 0x0484,
3156 .clkr = {
3157 .enable_reg = 0x0484,
3158 .enable_mask = BIT(0),
3159 .hw.init = &(struct clk_init_data){
3160 .name = "gcc_usb_hs_system_clk",
3161 .parent_names = (const char *[]){
3162 "usb_hs_system_clk_src",
3163 },
3164 .num_parents = 1,
3165 .flags = CLK_SET_RATE_PARENT,
3166 .ops = &clk_branch2_ops,
3167 },
3168 },
3169};
3170
3171static struct clk_branch gcc_usb_hsic_ahb_clk = {
3172 .halt_reg = 0x0408,
3173 .clkr = {
3174 .enable_reg = 0x0408,
3175 .enable_mask = BIT(0),
3176 .hw.init = &(struct clk_init_data){
3177 .name = "gcc_usb_hsic_ahb_clk",
3178 .parent_names = (const char *[]){
3179 "periph_noc_clk_src",
3180 },
3181 .num_parents = 1,
3182 .ops = &clk_branch2_ops,
3183 },
3184 },
3185};
3186
3187static struct clk_branch gcc_usb_hsic_clk = {
3188 .halt_reg = 0x0410,
3189 .clkr = {
3190 .enable_reg = 0x0410,
3191 .enable_mask = BIT(0),
3192 .hw.init = &(struct clk_init_data){
3193 .name = "gcc_usb_hsic_clk",
3194 .parent_names = (const char *[]){
3195 "usb_hsic_clk_src",
3196 },
3197 .num_parents = 1,
3198 .flags = CLK_SET_RATE_PARENT,
3199 .ops = &clk_branch2_ops,
3200 },
3201 },
3202};
3203
3204static struct clk_branch gcc_usb_hsic_io_cal_clk = {
3205 .halt_reg = 0x0414,
3206 .clkr = {
3207 .enable_reg = 0x0414,
3208 .enable_mask = BIT(0),
3209 .hw.init = &(struct clk_init_data){
3210 .name = "gcc_usb_hsic_io_cal_clk",
3211 .parent_names = (const char *[]){
3212 "usb_hsic_io_cal_clk_src",
3213 },
3214 .num_parents = 1,
3215 .flags = CLK_SET_RATE_PARENT,
3216 .ops = &clk_branch2_ops,
3217 },
3218 },
3219};
3220
3221static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = {
3222 .halt_reg = 0x0418,
3223 .clkr = {
3224 .enable_reg = 0x0418,
3225 .enable_mask = BIT(0),
3226 .hw.init = &(struct clk_init_data){
3227 .name = "gcc_usb_hsic_io_cal_sleep_clk",
3228 .parent_names = (const char *[]){
3229 "sleep_clk_src",
3230 },
3231 .num_parents = 1,
3232 .ops = &clk_branch2_ops,
3233 },
3234 },
3235};
3236
3237static struct clk_branch gcc_usb_hsic_system_clk = {
3238 .halt_reg = 0x040c,
3239 .clkr = {
3240 .enable_reg = 0x040c,
3241 .enable_mask = BIT(0),
3242 .hw.init = &(struct clk_init_data){
3243 .name = "gcc_usb_hsic_system_clk",
3244 .parent_names = (const char *[]){
3245 "usb_hsic_system_clk_src",
3246 },
3247 .num_parents = 1,
3248 .flags = CLK_SET_RATE_PARENT,
3249 .ops = &clk_branch2_ops,
3250 },
3251 },
3252};
3253
3254static struct clk_regmap *gcc_apq8084_clocks[] = {
3255 [GPLL0] = &gpll0.clkr,
3256 [GPLL0_VOTE] = &gpll0_vote,
3257 [GPLL1] = &gpll1.clkr,
3258 [GPLL1_VOTE] = &gpll1_vote,
3259 [GPLL4] = &gpll4.clkr,
3260 [GPLL4_VOTE] = &gpll4_vote,
3261 [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
3262 [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
3263 [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
3264 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
3265 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
3266 [USB30_SEC_MASTER_CLK_SRC] = &usb30_sec_master_clk_src.clkr,
3267 [USB_HSIC_AHB_CLK_SRC] = &usb_hsic_ahb_clk_src.clkr,
3268 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3269 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3270 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3271 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3272 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3273 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3274 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3275 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3276 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3277 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3278 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3279 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3280 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3281 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3282 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
3283 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
3284 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
3285 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
3286 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3287 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3288 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3289 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3290 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3291 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3292 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
3293 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
3294 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
3295 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
3296 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
3297 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
3298 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3299 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3300 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
3301 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
3302 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
3303 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
3304 [CE1_CLK_SRC] = &ce1_clk_src.clkr,
3305 [CE2_CLK_SRC] = &ce2_clk_src.clkr,
3306 [CE3_CLK_SRC] = &ce3_clk_src.clkr,
3307 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3308 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3309 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3310 [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
3311 [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
3312 [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
3313 [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
3314 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3315 [SATA_ASIC0_CLK_SRC] = &sata_asic0_clk_src.clkr,
3316 [SATA_PMALIVE_CLK_SRC] = &sata_pmalive_clk_src.clkr,
3317 [SATA_RX_CLK_SRC] = &sata_rx_clk_src.clkr,
3318 [SATA_RX_OOB_CLK_SRC] = &sata_rx_oob_clk_src.clkr,
3319 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3320 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3321 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
3322 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
3323 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
3324 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
3325 [USB30_SEC_MOCK_UTMI_CLK_SRC] = &usb30_sec_mock_utmi_clk_src.clkr,
3326 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
3327 [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
3328 [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
3329 [USB_HSIC_MOCK_UTMI_CLK_SRC] = &usb_hsic_mock_utmi_clk_src.clkr,
3330 [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
3331 [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr,
3332 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3333 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3334 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3335 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3336 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3337 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3338 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3339 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3340 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3341 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3342 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3343 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3344 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3345 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3346 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3347 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3348 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3349 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3350 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3351 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3352 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3353 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3354 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3355 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3356 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3357 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3358 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
3359 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
3360 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
3361 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
3362 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
3363 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
3364 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3365 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3366 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
3367 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
3368 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
3369 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
3370 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3371 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
3372 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
3373 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
3374 [GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr,
3375 [GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr,
3376 [GCC_CE2_CLK] = &gcc_ce2_clk.clkr,
3377 [GCC_CE3_AHB_CLK] = &gcc_ce3_ahb_clk.clkr,
3378 [GCC_CE3_AXI_CLK] = &gcc_ce3_axi_clk.clkr,
3379 [GCC_CE3_CLK] = &gcc_ce3_clk.clkr,
3380 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3381 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3382 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3383 [GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr,
3384 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3385 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3386 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3387 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3388 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3389 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3390 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3391 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3392 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3393 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3394 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3395 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3396 [GCC_PERIPH_NOC_USB_HSIC_AHB_CLK] = &gcc_periph_noc_usb_hsic_ahb_clk.clkr,
3397 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3398 [GCC_SATA_ASIC0_CLK] = &gcc_sata_asic0_clk.clkr,
3399 [GCC_SATA_AXI_CLK] = &gcc_sata_axi_clk.clkr,
3400 [GCC_SATA_CFG_AHB_CLK] = &gcc_sata_cfg_ahb_clk.clkr,
3401 [GCC_SATA_PMALIVE_CLK] = &gcc_sata_pmalive_clk.clkr,
3402 [GCC_SATA_RX_CLK] = &gcc_sata_rx_clk.clkr,
3403 [GCC_SATA_RX_OOB_CLK] = &gcc_sata_rx_oob_clk.clkr,
3404 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3405 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3406 [GCC_SDCC1_CDCCAL_FF_CLK] = &gcc_sdcc1_cdccal_ff_clk.clkr,
3407 [GCC_SDCC1_CDCCAL_SLEEP_CLK] = &gcc_sdcc1_cdccal_sleep_clk.clkr,
3408 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3409 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3410 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
3411 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
3412 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3413 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3414 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
3415 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
3416 [GCC_SYS_NOC_USB3_SEC_AXI_CLK] = &gcc_sys_noc_usb3_sec_axi_clk.clkr,
3417 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3418 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3419 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3420 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
3421 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
3422 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
3423 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
3424 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
3425 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
3426 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
3427 [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr,
3428 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
3429 [GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr,
3430 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
3431 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
3432 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
3433 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3434 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3435 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3436 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
3437 [GCC_USB_HS_INACTIVITY_TIMERS_CLK] = &gcc_usb_hs_inactivity_timers_clk.clkr,
3438 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
3439 [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr,
3440 [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr,
3441 [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr,
3442 [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
3443 [GCC_USB_HSIC_MOCK_UTMI_CLK] = &gcc_usb_hsic_mock_utmi_clk.clkr,
3444 [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
3445};
3446
3447static const struct qcom_reset_map gcc_apq8084_resets[] = {
3448 [GCC_SYSTEM_NOC_BCR] = { 0x0100 },
3449 [GCC_CONFIG_NOC_BCR] = { 0x0140 },
3450 [GCC_PERIPH_NOC_BCR] = { 0x0180 },
3451 [GCC_IMEM_BCR] = { 0x0200 },
3452 [GCC_MMSS_BCR] = { 0x0240 },
3453 [GCC_QDSS_BCR] = { 0x0300 },
3454 [GCC_USB_30_BCR] = { 0x03c0 },
3455 [GCC_USB3_PHY_BCR] = { 0x03fc },
3456 [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
3457 [GCC_USB_HS_BCR] = { 0x0480 },
3458 [GCC_USB2A_PHY_BCR] = { 0x04a8 },
3459 [GCC_USB2B_PHY_BCR] = { 0x04b0 },
3460 [GCC_SDCC1_BCR] = { 0x04c0 },
3461 [GCC_SDCC2_BCR] = { 0x0500 },
3462 [GCC_SDCC3_BCR] = { 0x0540 },
3463 [GCC_SDCC4_BCR] = { 0x0580 },
3464 [GCC_BLSP1_BCR] = { 0x05c0 },
3465 [GCC_BLSP1_QUP1_BCR] = { 0x0640 },
3466 [GCC_BLSP1_UART1_BCR] = { 0x0680 },
3467 [GCC_BLSP1_QUP2_BCR] = { 0x06c0 },
3468 [GCC_BLSP1_UART2_BCR] = { 0x0700 },
3469 [GCC_BLSP1_QUP3_BCR] = { 0x0740 },
3470 [GCC_BLSP1_UART3_BCR] = { 0x0780 },
3471 [GCC_BLSP1_QUP4_BCR] = { 0x07c0 },
3472 [GCC_BLSP1_UART4_BCR] = { 0x0800 },
3473 [GCC_BLSP1_QUP5_BCR] = { 0x0840 },
3474 [GCC_BLSP1_UART5_BCR] = { 0x0880 },
3475 [GCC_BLSP1_QUP6_BCR] = { 0x08c0 },
3476 [GCC_BLSP1_UART6_BCR] = { 0x0900 },
3477 [GCC_BLSP2_BCR] = { 0x0940 },
3478 [GCC_BLSP2_QUP1_BCR] = { 0x0980 },
3479 [GCC_BLSP2_UART1_BCR] = { 0x09c0 },
3480 [GCC_BLSP2_QUP2_BCR] = { 0x0a00 },
3481 [GCC_BLSP2_UART2_BCR] = { 0x0a40 },
3482 [GCC_BLSP2_QUP3_BCR] = { 0x0a80 },
3483 [GCC_BLSP2_UART3_BCR] = { 0x0ac0 },
3484 [GCC_BLSP2_QUP4_BCR] = { 0x0b00 },
3485 [GCC_BLSP2_UART4_BCR] = { 0x0b40 },
3486 [GCC_BLSP2_QUP5_BCR] = { 0x0b80 },
3487 [GCC_BLSP2_UART5_BCR] = { 0x0bc0 },
3488 [GCC_BLSP2_QUP6_BCR] = { 0x0c00 },
3489 [GCC_BLSP2_UART6_BCR] = { 0x0c40 },
3490 [GCC_PDM_BCR] = { 0x0cc0 },
3491 [GCC_PRNG_BCR] = { 0x0d00 },
3492 [GCC_BAM_DMA_BCR] = { 0x0d40 },
3493 [GCC_TSIF_BCR] = { 0x0d80 },
3494 [GCC_TCSR_BCR] = { 0x0dc0 },
3495 [GCC_BOOT_ROM_BCR] = { 0x0e00 },
3496 [GCC_MSG_RAM_BCR] = { 0x0e40 },
3497 [GCC_TLMM_BCR] = { 0x0e80 },
3498 [GCC_MPM_BCR] = { 0x0ec0 },
3499 [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 },
3500 [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 },
3501 [GCC_SEC_CTRL_BCR] = { 0x0f40 },
3502 [GCC_SPMI_BCR] = { 0x0fc0 },
3503 [GCC_SPDM_BCR] = { 0x1000 },
3504 [GCC_CE1_BCR] = { 0x1040 },
3505 [GCC_CE2_BCR] = { 0x1080 },
3506 [GCC_BIMC_BCR] = { 0x1100 },
3507 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 },
3508 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 },
3509 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 },
3510 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 },
3511 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 },
3512 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 },
3513 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 },
3514 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 },
3515 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 },
3516 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 },
3517 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 },
3518 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 },
3519 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 },
3520 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 },
3521 [GCC_DEHR_BCR] = { 0x1300 },
3522 [GCC_RBCPR_BCR] = { 0x1380 },
3523 [GCC_MSS_RESTART] = { 0x1680 },
3524 [GCC_LPASS_RESTART] = { 0x16c0 },
3525 [GCC_WCSS_RESTART] = { 0x1700 },
3526 [GCC_VENUS_RESTART] = { 0x1740 },
3527 [GCC_COPSS_SMMU_BCR] = { 0x1a40 },
3528 [GCC_SPSS_BCR] = { 0x1a80 },
3529 [GCC_PCIE_0_BCR] = { 0x1ac0 },
3530 [GCC_PCIE_0_PHY_BCR] = { 0x1b00 },
3531 [GCC_PCIE_1_BCR] = { 0x1b40 },
3532 [GCC_PCIE_1_PHY_BCR] = { 0x1b80 },
3533 [GCC_USB_30_SEC_BCR] = { 0x1bc0 },
3534 [GCC_USB3_SEC_PHY_BCR] = { 0x1bfc },
3535 [GCC_SATA_BCR] = { 0x1c40 },
3536 [GCC_CE3_BCR] = { 0x1d00 },
3537 [GCC_UFS_BCR] = { 0x1d40 },
3538 [GCC_USB30_PHY_COM_BCR] = { 0x1e80 },
3539};
3540
3541static const struct regmap_config gcc_apq8084_regmap_config = {
3542 .reg_bits = 32,
3543 .reg_stride = 4,
3544 .val_bits = 32,
3545 .max_register = 0x1fc0,
3546 .fast_io = true,
3547};
3548
3549static const struct qcom_cc_desc gcc_apq8084_desc = {
3550 .config = &gcc_apq8084_regmap_config,
3551 .clks = gcc_apq8084_clocks,
3552 .num_clks = ARRAY_SIZE(gcc_apq8084_clocks),
3553 .resets = gcc_apq8084_resets,
3554 .num_resets = ARRAY_SIZE(gcc_apq8084_resets),
3555};
3556
3557static const struct of_device_id gcc_apq8084_match_table[] = {
3558 { .compatible = "qcom,gcc-apq8084" },
3559 { }
3560};
3561MODULE_DEVICE_TABLE(of, gcc_apq8084_match_table);
3562
3563static int gcc_apq8084_probe(struct platform_device *pdev)
3564{
3565 struct clk *clk;
3566 struct device *dev = &pdev->dev;
3567
3568 /* Temporary until RPM clocks supported */
3569 clk = clk_register_fixed_rate(dev, "xo", NULL, CLK_IS_ROOT, 19200000);
3570 if (IS_ERR(clk))
3571 return PTR_ERR(clk);
3572
3573 clk = clk_register_fixed_rate(dev, "sleep_clk_src", NULL,
3574 CLK_IS_ROOT, 32768);
3575 if (IS_ERR(clk))
3576 return PTR_ERR(clk);
3577
3578 return qcom_cc_probe(pdev, &gcc_apq8084_desc);
3579}
3580
3581static int gcc_apq8084_remove(struct platform_device *pdev)
3582{
3583 qcom_cc_remove(pdev);
3584 return 0;
3585}
3586
3587static struct platform_driver gcc_apq8084_driver = {
3588 .probe = gcc_apq8084_probe,
3589 .remove = gcc_apq8084_remove,
3590 .driver = {
3591 .name = "gcc-apq8084",
3592 .owner = THIS_MODULE,
3593 .of_match_table = gcc_apq8084_match_table,
3594 },
3595};
3596
3597static int __init gcc_apq8084_init(void)
3598{
3599 return platform_driver_register(&gcc_apq8084_driver);
3600}
3601core_initcall(gcc_apq8084_init);
3602
3603static void __exit gcc_apq8084_exit(void)
3604{
3605 platform_driver_unregister(&gcc_apq8084_driver);
3606}
3607module_exit(gcc_apq8084_exit);
3608
3609MODULE_DESCRIPTION("QCOM GCC APQ8084 Driver");
3610MODULE_LICENSE("GPL v2");
3611MODULE_ALIAS("platform:gcc-apq8084");
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
new file mode 100644
index 000000000000..4032e510d9aa
--- /dev/null
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -0,0 +1,2424 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/bitops.h>
16#include <linux/err.h>
17#include <linux/platform_device.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/clk-provider.h>
22#include <linux/regmap.h>
23#include <linux/reset-controller.h>
24
25#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
26#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
27
28#include "common.h"
29#include "clk-regmap.h"
30#include "clk-pll.h"
31#include "clk-rcg.h"
32#include "clk-branch.h"
33#include "reset.h"
34
35static struct clk_pll pll3 = {
36 .l_reg = 0x3164,
37 .m_reg = 0x3168,
38 .n_reg = 0x316c,
39 .config_reg = 0x3174,
40 .mode_reg = 0x3160,
41 .status_reg = 0x3178,
42 .status_bit = 16,
43 .clkr.hw.init = &(struct clk_init_data){
44 .name = "pll3",
45 .parent_names = (const char *[]){ "pxo" },
46 .num_parents = 1,
47 .ops = &clk_pll_ops,
48 },
49};
50
51static struct clk_pll pll8 = {
52 .l_reg = 0x3144,
53 .m_reg = 0x3148,
54 .n_reg = 0x314c,
55 .config_reg = 0x3154,
56 .mode_reg = 0x3140,
57 .status_reg = 0x3158,
58 .status_bit = 16,
59 .clkr.hw.init = &(struct clk_init_data){
60 .name = "pll8",
61 .parent_names = (const char *[]){ "pxo" },
62 .num_parents = 1,
63 .ops = &clk_pll_ops,
64 },
65};
66
67static struct clk_regmap pll8_vote = {
68 .enable_reg = 0x34c0,
69 .enable_mask = BIT(8),
70 .hw.init = &(struct clk_init_data){
71 .name = "pll8_vote",
72 .parent_names = (const char *[]){ "pll8" },
73 .num_parents = 1,
74 .ops = &clk_pll_vote_ops,
75 },
76};
77
78static struct clk_pll pll14 = {
79 .l_reg = 0x31c4,
80 .m_reg = 0x31c8,
81 .n_reg = 0x31cc,
82 .config_reg = 0x31d4,
83 .mode_reg = 0x31c0,
84 .status_reg = 0x31d8,
85 .status_bit = 16,
86 .clkr.hw.init = &(struct clk_init_data){
87 .name = "pll14",
88 .parent_names = (const char *[]){ "pxo" },
89 .num_parents = 1,
90 .ops = &clk_pll_ops,
91 },
92};
93
94static struct clk_regmap pll14_vote = {
95 .enable_reg = 0x34c0,
96 .enable_mask = BIT(14),
97 .hw.init = &(struct clk_init_data){
98 .name = "pll14_vote",
99 .parent_names = (const char *[]){ "pll14" },
100 .num_parents = 1,
101 .ops = &clk_pll_vote_ops,
102 },
103};
104
105#define P_PXO 0
106#define P_PLL8 1
107#define P_PLL3 1
108#define P_PLL0 2
109#define P_CXO 2
110
111static const u8 gcc_pxo_pll8_map[] = {
112 [P_PXO] = 0,
113 [P_PLL8] = 3,
114};
115
116static const char *gcc_pxo_pll8[] = {
117 "pxo",
118 "pll8_vote",
119};
120
121static const u8 gcc_pxo_pll8_cxo_map[] = {
122 [P_PXO] = 0,
123 [P_PLL8] = 3,
124 [P_CXO] = 5,
125};
126
127static const char *gcc_pxo_pll8_cxo[] = {
128 "pxo",
129 "pll8_vote",
130 "cxo",
131};
132
133static const u8 gcc_pxo_pll3_map[] = {
134 [P_PXO] = 0,
135 [P_PLL3] = 1,
136};
137
138static const u8 gcc_pxo_pll3_sata_map[] = {
139 [P_PXO] = 0,
140 [P_PLL3] = 6,
141};
142
143static const char *gcc_pxo_pll3[] = {
144 "pxo",
145 "pll3",
146};
147
148static const u8 gcc_pxo_pll8_pll0[] = {
149 [P_PXO] = 0,
150 [P_PLL8] = 3,
151 [P_PLL0] = 2,
152};
153
154static const char *gcc_pxo_pll8_pll0_map[] = {
155 "pxo",
156 "pll8_vote",
157 "pll0",
158};
159
160static struct freq_tbl clk_tbl_gsbi_uart[] = {
161 { 1843200, P_PLL8, 2, 6, 625 },
162 { 3686400, P_PLL8, 2, 12, 625 },
163 { 7372800, P_PLL8, 2, 24, 625 },
164 { 14745600, P_PLL8, 2, 48, 625 },
165 { 16000000, P_PLL8, 4, 1, 6 },
166 { 24000000, P_PLL8, 4, 1, 4 },
167 { 32000000, P_PLL8, 4, 1, 3 },
168 { 40000000, P_PLL8, 1, 5, 48 },
169 { 46400000, P_PLL8, 1, 29, 240 },
170 { 48000000, P_PLL8, 4, 1, 2 },
171 { 51200000, P_PLL8, 1, 2, 15 },
172 { 56000000, P_PLL8, 1, 7, 48 },
173 { 58982400, P_PLL8, 1, 96, 625 },
174 { 64000000, P_PLL8, 2, 1, 3 },
175 { }
176};
177
178static struct clk_rcg gsbi1_uart_src = {
179 .ns_reg = 0x29d4,
180 .md_reg = 0x29d0,
181 .mn = {
182 .mnctr_en_bit = 8,
183 .mnctr_reset_bit = 7,
184 .mnctr_mode_shift = 5,
185 .n_val_shift = 16,
186 .m_val_shift = 16,
187 .width = 16,
188 },
189 .p = {
190 .pre_div_shift = 3,
191 .pre_div_width = 2,
192 },
193 .s = {
194 .src_sel_shift = 0,
195 .parent_map = gcc_pxo_pll8_map,
196 },
197 .freq_tbl = clk_tbl_gsbi_uart,
198 .clkr = {
199 .enable_reg = 0x29d4,
200 .enable_mask = BIT(11),
201 .hw.init = &(struct clk_init_data){
202 .name = "gsbi1_uart_src",
203 .parent_names = gcc_pxo_pll8,
204 .num_parents = 2,
205 .ops = &clk_rcg_ops,
206 .flags = CLK_SET_PARENT_GATE,
207 },
208 },
209};
210
211static struct clk_branch gsbi1_uart_clk = {
212 .halt_reg = 0x2fcc,
213 .halt_bit = 12,
214 .clkr = {
215 .enable_reg = 0x29d4,
216 .enable_mask = BIT(9),
217 .hw.init = &(struct clk_init_data){
218 .name = "gsbi1_uart_clk",
219 .parent_names = (const char *[]){
220 "gsbi1_uart_src",
221 },
222 .num_parents = 1,
223 .ops = &clk_branch_ops,
224 .flags = CLK_SET_RATE_PARENT,
225 },
226 },
227};
228
229static struct clk_rcg gsbi2_uart_src = {
230 .ns_reg = 0x29f4,
231 .md_reg = 0x29f0,
232 .mn = {
233 .mnctr_en_bit = 8,
234 .mnctr_reset_bit = 7,
235 .mnctr_mode_shift = 5,
236 .n_val_shift = 16,
237 .m_val_shift = 16,
238 .width = 16,
239 },
240 .p = {
241 .pre_div_shift = 3,
242 .pre_div_width = 2,
243 },
244 .s = {
245 .src_sel_shift = 0,
246 .parent_map = gcc_pxo_pll8_map,
247 },
248 .freq_tbl = clk_tbl_gsbi_uart,
249 .clkr = {
250 .enable_reg = 0x29f4,
251 .enable_mask = BIT(11),
252 .hw.init = &(struct clk_init_data){
253 .name = "gsbi2_uart_src",
254 .parent_names = gcc_pxo_pll8,
255 .num_parents = 2,
256 .ops = &clk_rcg_ops,
257 .flags = CLK_SET_PARENT_GATE,
258 },
259 },
260};
261
262static struct clk_branch gsbi2_uart_clk = {
263 .halt_reg = 0x2fcc,
264 .halt_bit = 8,
265 .clkr = {
266 .enable_reg = 0x29f4,
267 .enable_mask = BIT(9),
268 .hw.init = &(struct clk_init_data){
269 .name = "gsbi2_uart_clk",
270 .parent_names = (const char *[]){
271 "gsbi2_uart_src",
272 },
273 .num_parents = 1,
274 .ops = &clk_branch_ops,
275 .flags = CLK_SET_RATE_PARENT,
276 },
277 },
278};
279
280static struct clk_rcg gsbi4_uart_src = {
281 .ns_reg = 0x2a34,
282 .md_reg = 0x2a30,
283 .mn = {
284 .mnctr_en_bit = 8,
285 .mnctr_reset_bit = 7,
286 .mnctr_mode_shift = 5,
287 .n_val_shift = 16,
288 .m_val_shift = 16,
289 .width = 16,
290 },
291 .p = {
292 .pre_div_shift = 3,
293 .pre_div_width = 2,
294 },
295 .s = {
296 .src_sel_shift = 0,
297 .parent_map = gcc_pxo_pll8_map,
298 },
299 .freq_tbl = clk_tbl_gsbi_uart,
300 .clkr = {
301 .enable_reg = 0x2a34,
302 .enable_mask = BIT(11),
303 .hw.init = &(struct clk_init_data){
304 .name = "gsbi4_uart_src",
305 .parent_names = gcc_pxo_pll8,
306 .num_parents = 2,
307 .ops = &clk_rcg_ops,
308 .flags = CLK_SET_PARENT_GATE,
309 },
310 },
311};
312
313static struct clk_branch gsbi4_uart_clk = {
314 .halt_reg = 0x2fd0,
315 .halt_bit = 26,
316 .clkr = {
317 .enable_reg = 0x2a34,
318 .enable_mask = BIT(9),
319 .hw.init = &(struct clk_init_data){
320 .name = "gsbi4_uart_clk",
321 .parent_names = (const char *[]){
322 "gsbi4_uart_src",
323 },
324 .num_parents = 1,
325 .ops = &clk_branch_ops,
326 .flags = CLK_SET_RATE_PARENT,
327 },
328 },
329};
330
331static struct clk_rcg gsbi5_uart_src = {
332 .ns_reg = 0x2a54,
333 .md_reg = 0x2a50,
334 .mn = {
335 .mnctr_en_bit = 8,
336 .mnctr_reset_bit = 7,
337 .mnctr_mode_shift = 5,
338 .n_val_shift = 16,
339 .m_val_shift = 16,
340 .width = 16,
341 },
342 .p = {
343 .pre_div_shift = 3,
344 .pre_div_width = 2,
345 },
346 .s = {
347 .src_sel_shift = 0,
348 .parent_map = gcc_pxo_pll8_map,
349 },
350 .freq_tbl = clk_tbl_gsbi_uart,
351 .clkr = {
352 .enable_reg = 0x2a54,
353 .enable_mask = BIT(11),
354 .hw.init = &(struct clk_init_data){
355 .name = "gsbi5_uart_src",
356 .parent_names = gcc_pxo_pll8,
357 .num_parents = 2,
358 .ops = &clk_rcg_ops,
359 .flags = CLK_SET_PARENT_GATE,
360 },
361 },
362};
363
364static struct clk_branch gsbi5_uart_clk = {
365 .halt_reg = 0x2fd0,
366 .halt_bit = 22,
367 .clkr = {
368 .enable_reg = 0x2a54,
369 .enable_mask = BIT(9),
370 .hw.init = &(struct clk_init_data){
371 .name = "gsbi5_uart_clk",
372 .parent_names = (const char *[]){
373 "gsbi5_uart_src",
374 },
375 .num_parents = 1,
376 .ops = &clk_branch_ops,
377 .flags = CLK_SET_RATE_PARENT,
378 },
379 },
380};
381
382static struct clk_rcg gsbi6_uart_src = {
383 .ns_reg = 0x2a74,
384 .md_reg = 0x2a70,
385 .mn = {
386 .mnctr_en_bit = 8,
387 .mnctr_reset_bit = 7,
388 .mnctr_mode_shift = 5,
389 .n_val_shift = 16,
390 .m_val_shift = 16,
391 .width = 16,
392 },
393 .p = {
394 .pre_div_shift = 3,
395 .pre_div_width = 2,
396 },
397 .s = {
398 .src_sel_shift = 0,
399 .parent_map = gcc_pxo_pll8_map,
400 },
401 .freq_tbl = clk_tbl_gsbi_uart,
402 .clkr = {
403 .enable_reg = 0x2a74,
404 .enable_mask = BIT(11),
405 .hw.init = &(struct clk_init_data){
406 .name = "gsbi6_uart_src",
407 .parent_names = gcc_pxo_pll8,
408 .num_parents = 2,
409 .ops = &clk_rcg_ops,
410 .flags = CLK_SET_PARENT_GATE,
411 },
412 },
413};
414
415static struct clk_branch gsbi6_uart_clk = {
416 .halt_reg = 0x2fd0,
417 .halt_bit = 18,
418 .clkr = {
419 .enable_reg = 0x2a74,
420 .enable_mask = BIT(9),
421 .hw.init = &(struct clk_init_data){
422 .name = "gsbi6_uart_clk",
423 .parent_names = (const char *[]){
424 "gsbi6_uart_src",
425 },
426 .num_parents = 1,
427 .ops = &clk_branch_ops,
428 .flags = CLK_SET_RATE_PARENT,
429 },
430 },
431};
432
433static struct clk_rcg gsbi7_uart_src = {
434 .ns_reg = 0x2a94,
435 .md_reg = 0x2a90,
436 .mn = {
437 .mnctr_en_bit = 8,
438 .mnctr_reset_bit = 7,
439 .mnctr_mode_shift = 5,
440 .n_val_shift = 16,
441 .m_val_shift = 16,
442 .width = 16,
443 },
444 .p = {
445 .pre_div_shift = 3,
446 .pre_div_width = 2,
447 },
448 .s = {
449 .src_sel_shift = 0,
450 .parent_map = gcc_pxo_pll8_map,
451 },
452 .freq_tbl = clk_tbl_gsbi_uart,
453 .clkr = {
454 .enable_reg = 0x2a94,
455 .enable_mask = BIT(11),
456 .hw.init = &(struct clk_init_data){
457 .name = "gsbi7_uart_src",
458 .parent_names = gcc_pxo_pll8,
459 .num_parents = 2,
460 .ops = &clk_rcg_ops,
461 .flags = CLK_SET_PARENT_GATE,
462 },
463 },
464};
465
466static struct clk_branch gsbi7_uart_clk = {
467 .halt_reg = 0x2fd0,
468 .halt_bit = 14,
469 .clkr = {
470 .enable_reg = 0x2a94,
471 .enable_mask = BIT(9),
472 .hw.init = &(struct clk_init_data){
473 .name = "gsbi7_uart_clk",
474 .parent_names = (const char *[]){
475 "gsbi7_uart_src",
476 },
477 .num_parents = 1,
478 .ops = &clk_branch_ops,
479 .flags = CLK_SET_RATE_PARENT,
480 },
481 },
482};
483
484static struct freq_tbl clk_tbl_gsbi_qup[] = {
485 { 1100000, P_PXO, 1, 2, 49 },
486 { 5400000, P_PXO, 1, 1, 5 },
487 { 10800000, P_PXO, 1, 2, 5 },
488 { 15060000, P_PLL8, 1, 2, 51 },
489 { 24000000, P_PLL8, 4, 1, 4 },
490 { 25600000, P_PLL8, 1, 1, 15 },
491 { 27000000, P_PXO, 1, 0, 0 },
492 { 48000000, P_PLL8, 4, 1, 2 },
493 { 51200000, P_PLL8, 1, 2, 15 },
494 { }
495};
496
497static struct clk_rcg gsbi1_qup_src = {
498 .ns_reg = 0x29cc,
499 .md_reg = 0x29c8,
500 .mn = {
501 .mnctr_en_bit = 8,
502 .mnctr_reset_bit = 7,
503 .mnctr_mode_shift = 5,
504 .n_val_shift = 16,
505 .m_val_shift = 16,
506 .width = 8,
507 },
508 .p = {
509 .pre_div_shift = 3,
510 .pre_div_width = 2,
511 },
512 .s = {
513 .src_sel_shift = 0,
514 .parent_map = gcc_pxo_pll8_map,
515 },
516 .freq_tbl = clk_tbl_gsbi_qup,
517 .clkr = {
518 .enable_reg = 0x29cc,
519 .enable_mask = BIT(11),
520 .hw.init = &(struct clk_init_data){
521 .name = "gsbi1_qup_src",
522 .parent_names = gcc_pxo_pll8,
523 .num_parents = 2,
524 .ops = &clk_rcg_ops,
525 .flags = CLK_SET_PARENT_GATE,
526 },
527 },
528};
529
530static struct clk_branch gsbi1_qup_clk = {
531 .halt_reg = 0x2fcc,
532 .halt_bit = 11,
533 .clkr = {
534 .enable_reg = 0x29cc,
535 .enable_mask = BIT(9),
536 .hw.init = &(struct clk_init_data){
537 .name = "gsbi1_qup_clk",
538 .parent_names = (const char *[]){ "gsbi1_qup_src" },
539 .num_parents = 1,
540 .ops = &clk_branch_ops,
541 .flags = CLK_SET_RATE_PARENT,
542 },
543 },
544};
545
546static struct clk_rcg gsbi2_qup_src = {
547 .ns_reg = 0x29ec,
548 .md_reg = 0x29e8,
549 .mn = {
550 .mnctr_en_bit = 8,
551 .mnctr_reset_bit = 7,
552 .mnctr_mode_shift = 5,
553 .n_val_shift = 16,
554 .m_val_shift = 16,
555 .width = 8,
556 },
557 .p = {
558 .pre_div_shift = 3,
559 .pre_div_width = 2,
560 },
561 .s = {
562 .src_sel_shift = 0,
563 .parent_map = gcc_pxo_pll8_map,
564 },
565 .freq_tbl = clk_tbl_gsbi_qup,
566 .clkr = {
567 .enable_reg = 0x29ec,
568 .enable_mask = BIT(11),
569 .hw.init = &(struct clk_init_data){
570 .name = "gsbi2_qup_src",
571 .parent_names = gcc_pxo_pll8,
572 .num_parents = 2,
573 .ops = &clk_rcg_ops,
574 .flags = CLK_SET_PARENT_GATE,
575 },
576 },
577};
578
579static struct clk_branch gsbi2_qup_clk = {
580 .halt_reg = 0x2fcc,
581 .halt_bit = 6,
582 .clkr = {
583 .enable_reg = 0x29ec,
584 .enable_mask = BIT(9),
585 .hw.init = &(struct clk_init_data){
586 .name = "gsbi2_qup_clk",
587 .parent_names = (const char *[]){ "gsbi2_qup_src" },
588 .num_parents = 1,
589 .ops = &clk_branch_ops,
590 .flags = CLK_SET_RATE_PARENT,
591 },
592 },
593};
594
595static struct clk_rcg gsbi4_qup_src = {
596 .ns_reg = 0x2a2c,
597 .md_reg = 0x2a28,
598 .mn = {
599 .mnctr_en_bit = 8,
600 .mnctr_reset_bit = 7,
601 .mnctr_mode_shift = 5,
602 .n_val_shift = 16,
603 .m_val_shift = 16,
604 .width = 8,
605 },
606 .p = {
607 .pre_div_shift = 3,
608 .pre_div_width = 2,
609 },
610 .s = {
611 .src_sel_shift = 0,
612 .parent_map = gcc_pxo_pll8_map,
613 },
614 .freq_tbl = clk_tbl_gsbi_qup,
615 .clkr = {
616 .enable_reg = 0x2a2c,
617 .enable_mask = BIT(11),
618 .hw.init = &(struct clk_init_data){
619 .name = "gsbi4_qup_src",
620 .parent_names = gcc_pxo_pll8,
621 .num_parents = 2,
622 .ops = &clk_rcg_ops,
623 .flags = CLK_SET_PARENT_GATE,
624 },
625 },
626};
627
628static struct clk_branch gsbi4_qup_clk = {
629 .halt_reg = 0x2fd0,
630 .halt_bit = 24,
631 .clkr = {
632 .enable_reg = 0x2a2c,
633 .enable_mask = BIT(9),
634 .hw.init = &(struct clk_init_data){
635 .name = "gsbi4_qup_clk",
636 .parent_names = (const char *[]){ "gsbi4_qup_src" },
637 .num_parents = 1,
638 .ops = &clk_branch_ops,
639 .flags = CLK_SET_RATE_PARENT,
640 },
641 },
642};
643
644static struct clk_rcg gsbi5_qup_src = {
645 .ns_reg = 0x2a4c,
646 .md_reg = 0x2a48,
647 .mn = {
648 .mnctr_en_bit = 8,
649 .mnctr_reset_bit = 7,
650 .mnctr_mode_shift = 5,
651 .n_val_shift = 16,
652 .m_val_shift = 16,
653 .width = 8,
654 },
655 .p = {
656 .pre_div_shift = 3,
657 .pre_div_width = 2,
658 },
659 .s = {
660 .src_sel_shift = 0,
661 .parent_map = gcc_pxo_pll8_map,
662 },
663 .freq_tbl = clk_tbl_gsbi_qup,
664 .clkr = {
665 .enable_reg = 0x2a4c,
666 .enable_mask = BIT(11),
667 .hw.init = &(struct clk_init_data){
668 .name = "gsbi5_qup_src",
669 .parent_names = gcc_pxo_pll8,
670 .num_parents = 2,
671 .ops = &clk_rcg_ops,
672 .flags = CLK_SET_PARENT_GATE,
673 },
674 },
675};
676
677static struct clk_branch gsbi5_qup_clk = {
678 .halt_reg = 0x2fd0,
679 .halt_bit = 20,
680 .clkr = {
681 .enable_reg = 0x2a4c,
682 .enable_mask = BIT(9),
683 .hw.init = &(struct clk_init_data){
684 .name = "gsbi5_qup_clk",
685 .parent_names = (const char *[]){ "gsbi5_qup_src" },
686 .num_parents = 1,
687 .ops = &clk_branch_ops,
688 .flags = CLK_SET_RATE_PARENT,
689 },
690 },
691};
692
693static struct clk_rcg gsbi6_qup_src = {
694 .ns_reg = 0x2a6c,
695 .md_reg = 0x2a68,
696 .mn = {
697 .mnctr_en_bit = 8,
698 .mnctr_reset_bit = 7,
699 .mnctr_mode_shift = 5,
700 .n_val_shift = 16,
701 .m_val_shift = 16,
702 .width = 8,
703 },
704 .p = {
705 .pre_div_shift = 3,
706 .pre_div_width = 2,
707 },
708 .s = {
709 .src_sel_shift = 0,
710 .parent_map = gcc_pxo_pll8_map,
711 },
712 .freq_tbl = clk_tbl_gsbi_qup,
713 .clkr = {
714 .enable_reg = 0x2a6c,
715 .enable_mask = BIT(11),
716 .hw.init = &(struct clk_init_data){
717 .name = "gsbi6_qup_src",
718 .parent_names = gcc_pxo_pll8,
719 .num_parents = 2,
720 .ops = &clk_rcg_ops,
721 .flags = CLK_SET_PARENT_GATE,
722 },
723 },
724};
725
726static struct clk_branch gsbi6_qup_clk = {
727 .halt_reg = 0x2fd0,
728 .halt_bit = 16,
729 .clkr = {
730 .enable_reg = 0x2a6c,
731 .enable_mask = BIT(9),
732 .hw.init = &(struct clk_init_data){
733 .name = "gsbi6_qup_clk",
734 .parent_names = (const char *[]){ "gsbi6_qup_src" },
735 .num_parents = 1,
736 .ops = &clk_branch_ops,
737 .flags = CLK_SET_RATE_PARENT,
738 },
739 },
740};
741
742static struct clk_rcg gsbi7_qup_src = {
743 .ns_reg = 0x2a8c,
744 .md_reg = 0x2a88,
745 .mn = {
746 .mnctr_en_bit = 8,
747 .mnctr_reset_bit = 7,
748 .mnctr_mode_shift = 5,
749 .n_val_shift = 16,
750 .m_val_shift = 16,
751 .width = 8,
752 },
753 .p = {
754 .pre_div_shift = 3,
755 .pre_div_width = 2,
756 },
757 .s = {
758 .src_sel_shift = 0,
759 .parent_map = gcc_pxo_pll8_map,
760 },
761 .freq_tbl = clk_tbl_gsbi_qup,
762 .clkr = {
763 .enable_reg = 0x2a8c,
764 .enable_mask = BIT(11),
765 .hw.init = &(struct clk_init_data){
766 .name = "gsbi7_qup_src",
767 .parent_names = gcc_pxo_pll8,
768 .num_parents = 2,
769 .ops = &clk_rcg_ops,
770 .flags = CLK_SET_PARENT_GATE,
771 },
772 },
773};
774
775static struct clk_branch gsbi7_qup_clk = {
776 .halt_reg = 0x2fd0,
777 .halt_bit = 12,
778 .clkr = {
779 .enable_reg = 0x2a8c,
780 .enable_mask = BIT(9),
781 .hw.init = &(struct clk_init_data){
782 .name = "gsbi7_qup_clk",
783 .parent_names = (const char *[]){ "gsbi7_qup_src" },
784 .num_parents = 1,
785 .ops = &clk_branch_ops,
786 .flags = CLK_SET_RATE_PARENT,
787 },
788 },
789};
790
791static struct clk_branch gsbi1_h_clk = {
792 .hwcg_reg = 0x29c0,
793 .hwcg_bit = 6,
794 .halt_reg = 0x2fcc,
795 .halt_bit = 13,
796 .clkr = {
797 .enable_reg = 0x29c0,
798 .enable_mask = BIT(4),
799 .hw.init = &(struct clk_init_data){
800 .name = "gsbi1_h_clk",
801 .ops = &clk_branch_ops,
802 .flags = CLK_IS_ROOT,
803 },
804 },
805};
806
807static struct clk_branch gsbi2_h_clk = {
808 .hwcg_reg = 0x29e0,
809 .hwcg_bit = 6,
810 .halt_reg = 0x2fcc,
811 .halt_bit = 9,
812 .clkr = {
813 .enable_reg = 0x29e0,
814 .enable_mask = BIT(4),
815 .hw.init = &(struct clk_init_data){
816 .name = "gsbi2_h_clk",
817 .ops = &clk_branch_ops,
818 .flags = CLK_IS_ROOT,
819 },
820 },
821};
822
823static struct clk_branch gsbi4_h_clk = {
824 .hwcg_reg = 0x2a20,
825 .hwcg_bit = 6,
826 .halt_reg = 0x2fd0,
827 .halt_bit = 27,
828 .clkr = {
829 .enable_reg = 0x2a20,
830 .enable_mask = BIT(4),
831 .hw.init = &(struct clk_init_data){
832 .name = "gsbi4_h_clk",
833 .ops = &clk_branch_ops,
834 .flags = CLK_IS_ROOT,
835 },
836 },
837};
838
839static struct clk_branch gsbi5_h_clk = {
840 .hwcg_reg = 0x2a40,
841 .hwcg_bit = 6,
842 .halt_reg = 0x2fd0,
843 .halt_bit = 23,
844 .clkr = {
845 .enable_reg = 0x2a40,
846 .enable_mask = BIT(4),
847 .hw.init = &(struct clk_init_data){
848 .name = "gsbi5_h_clk",
849 .ops = &clk_branch_ops,
850 .flags = CLK_IS_ROOT,
851 },
852 },
853};
854
855static struct clk_branch gsbi6_h_clk = {
856 .hwcg_reg = 0x2a60,
857 .hwcg_bit = 6,
858 .halt_reg = 0x2fd0,
859 .halt_bit = 19,
860 .clkr = {
861 .enable_reg = 0x2a60,
862 .enable_mask = BIT(4),
863 .hw.init = &(struct clk_init_data){
864 .name = "gsbi6_h_clk",
865 .ops = &clk_branch_ops,
866 .flags = CLK_IS_ROOT,
867 },
868 },
869};
870
871static struct clk_branch gsbi7_h_clk = {
872 .hwcg_reg = 0x2a80,
873 .hwcg_bit = 6,
874 .halt_reg = 0x2fd0,
875 .halt_bit = 15,
876 .clkr = {
877 .enable_reg = 0x2a80,
878 .enable_mask = BIT(4),
879 .hw.init = &(struct clk_init_data){
880 .name = "gsbi7_h_clk",
881 .ops = &clk_branch_ops,
882 .flags = CLK_IS_ROOT,
883 },
884 },
885};
886
887static const struct freq_tbl clk_tbl_gp[] = {
888 { 12500000, P_PXO, 2, 0, 0 },
889 { 25000000, P_PXO, 1, 0, 0 },
890 { 64000000, P_PLL8, 2, 1, 3 },
891 { 76800000, P_PLL8, 1, 1, 5 },
892 { 96000000, P_PLL8, 4, 0, 0 },
893 { 128000000, P_PLL8, 3, 0, 0 },
894 { 192000000, P_PLL8, 2, 0, 0 },
895 { }
896};
897
898static struct clk_rcg gp0_src = {
899 .ns_reg = 0x2d24,
900 .md_reg = 0x2d00,
901 .mn = {
902 .mnctr_en_bit = 8,
903 .mnctr_reset_bit = 7,
904 .mnctr_mode_shift = 5,
905 .n_val_shift = 16,
906 .m_val_shift = 16,
907 .width = 8,
908 },
909 .p = {
910 .pre_div_shift = 3,
911 .pre_div_width = 2,
912 },
913 .s = {
914 .src_sel_shift = 0,
915 .parent_map = gcc_pxo_pll8_cxo_map,
916 },
917 .freq_tbl = clk_tbl_gp,
918 .clkr = {
919 .enable_reg = 0x2d24,
920 .enable_mask = BIT(11),
921 .hw.init = &(struct clk_init_data){
922 .name = "gp0_src",
923 .parent_names = gcc_pxo_pll8_cxo,
924 .num_parents = 3,
925 .ops = &clk_rcg_ops,
926 .flags = CLK_SET_PARENT_GATE,
927 },
928 }
929};
930
931static struct clk_branch gp0_clk = {
932 .halt_reg = 0x2fd8,
933 .halt_bit = 7,
934 .clkr = {
935 .enable_reg = 0x2d24,
936 .enable_mask = BIT(9),
937 .hw.init = &(struct clk_init_data){
938 .name = "gp0_clk",
939 .parent_names = (const char *[]){ "gp0_src" },
940 .num_parents = 1,
941 .ops = &clk_branch_ops,
942 .flags = CLK_SET_RATE_PARENT,
943 },
944 },
945};
946
947static struct clk_rcg gp1_src = {
948 .ns_reg = 0x2d44,
949 .md_reg = 0x2d40,
950 .mn = {
951 .mnctr_en_bit = 8,
952 .mnctr_reset_bit = 7,
953 .mnctr_mode_shift = 5,
954 .n_val_shift = 16,
955 .m_val_shift = 16,
956 .width = 8,
957 },
958 .p = {
959 .pre_div_shift = 3,
960 .pre_div_width = 2,
961 },
962 .s = {
963 .src_sel_shift = 0,
964 .parent_map = gcc_pxo_pll8_cxo_map,
965 },
966 .freq_tbl = clk_tbl_gp,
967 .clkr = {
968 .enable_reg = 0x2d44,
969 .enable_mask = BIT(11),
970 .hw.init = &(struct clk_init_data){
971 .name = "gp1_src",
972 .parent_names = gcc_pxo_pll8_cxo,
973 .num_parents = 3,
974 .ops = &clk_rcg_ops,
975 .flags = CLK_SET_RATE_GATE,
976 },
977 }
978};
979
980static struct clk_branch gp1_clk = {
981 .halt_reg = 0x2fd8,
982 .halt_bit = 6,
983 .clkr = {
984 .enable_reg = 0x2d44,
985 .enable_mask = BIT(9),
986 .hw.init = &(struct clk_init_data){
987 .name = "gp1_clk",
988 .parent_names = (const char *[]){ "gp1_src" },
989 .num_parents = 1,
990 .ops = &clk_branch_ops,
991 .flags = CLK_SET_RATE_PARENT,
992 },
993 },
994};
995
996static struct clk_rcg gp2_src = {
997 .ns_reg = 0x2d64,
998 .md_reg = 0x2d60,
999 .mn = {
1000 .mnctr_en_bit = 8,
1001 .mnctr_reset_bit = 7,
1002 .mnctr_mode_shift = 5,
1003 .n_val_shift = 16,
1004 .m_val_shift = 16,
1005 .width = 8,
1006 },
1007 .p = {
1008 .pre_div_shift = 3,
1009 .pre_div_width = 2,
1010 },
1011 .s = {
1012 .src_sel_shift = 0,
1013 .parent_map = gcc_pxo_pll8_cxo_map,
1014 },
1015 .freq_tbl = clk_tbl_gp,
1016 .clkr = {
1017 .enable_reg = 0x2d64,
1018 .enable_mask = BIT(11),
1019 .hw.init = &(struct clk_init_data){
1020 .name = "gp2_src",
1021 .parent_names = gcc_pxo_pll8_cxo,
1022 .num_parents = 3,
1023 .ops = &clk_rcg_ops,
1024 .flags = CLK_SET_RATE_GATE,
1025 },
1026 }
1027};
1028
1029static struct clk_branch gp2_clk = {
1030 .halt_reg = 0x2fd8,
1031 .halt_bit = 5,
1032 .clkr = {
1033 .enable_reg = 0x2d64,
1034 .enable_mask = BIT(9),
1035 .hw.init = &(struct clk_init_data){
1036 .name = "gp2_clk",
1037 .parent_names = (const char *[]){ "gp2_src" },
1038 .num_parents = 1,
1039 .ops = &clk_branch_ops,
1040 .flags = CLK_SET_RATE_PARENT,
1041 },
1042 },
1043};
1044
1045static struct clk_branch pmem_clk = {
1046 .hwcg_reg = 0x25a0,
1047 .hwcg_bit = 6,
1048 .halt_reg = 0x2fc8,
1049 .halt_bit = 20,
1050 .clkr = {
1051 .enable_reg = 0x25a0,
1052 .enable_mask = BIT(4),
1053 .hw.init = &(struct clk_init_data){
1054 .name = "pmem_clk",
1055 .ops = &clk_branch_ops,
1056 .flags = CLK_IS_ROOT,
1057 },
1058 },
1059};
1060
1061static struct clk_rcg prng_src = {
1062 .ns_reg = 0x2e80,
1063 .p = {
1064 .pre_div_shift = 3,
1065 .pre_div_width = 4,
1066 },
1067 .s = {
1068 .src_sel_shift = 0,
1069 .parent_map = gcc_pxo_pll8_map,
1070 },
1071 .clkr = {
1072 .hw.init = &(struct clk_init_data){
1073 .name = "prng_src",
1074 .parent_names = gcc_pxo_pll8,
1075 .num_parents = 2,
1076 .ops = &clk_rcg_ops,
1077 },
1078 },
1079};
1080
1081static struct clk_branch prng_clk = {
1082 .halt_reg = 0x2fd8,
1083 .halt_check = BRANCH_HALT_VOTED,
1084 .halt_bit = 10,
1085 .clkr = {
1086 .enable_reg = 0x3080,
1087 .enable_mask = BIT(10),
1088 .hw.init = &(struct clk_init_data){
1089 .name = "prng_clk",
1090 .parent_names = (const char *[]){ "prng_src" },
1091 .num_parents = 1,
1092 .ops = &clk_branch_ops,
1093 },
1094 },
1095};
1096
1097static const struct freq_tbl clk_tbl_sdc[] = {
1098 { 144000, P_PXO, 5, 18,625 },
1099 { 400000, P_PLL8, 4, 1, 240 },
1100 { 16000000, P_PLL8, 4, 1, 6 },
1101 { 17070000, P_PLL8, 1, 2, 45 },
1102 { 20210000, P_PLL8, 1, 1, 19 },
1103 { 24000000, P_PLL8, 4, 1, 4 },
1104 { 48000000, P_PLL8, 4, 1, 2 },
1105 { 64000000, P_PLL8, 3, 1, 2 },
1106 { 96000000, P_PLL8, 4, 0, 0 },
1107 { 192000000, P_PLL8, 2, 0, 0 },
1108 { }
1109};
1110
1111static struct clk_rcg sdc1_src = {
1112 .ns_reg = 0x282c,
1113 .md_reg = 0x2828,
1114 .mn = {
1115 .mnctr_en_bit = 8,
1116 .mnctr_reset_bit = 7,
1117 .mnctr_mode_shift = 5,
1118 .n_val_shift = 16,
1119 .m_val_shift = 16,
1120 .width = 8,
1121 },
1122 .p = {
1123 .pre_div_shift = 3,
1124 .pre_div_width = 2,
1125 },
1126 .s = {
1127 .src_sel_shift = 0,
1128 .parent_map = gcc_pxo_pll8_map,
1129 },
1130 .freq_tbl = clk_tbl_sdc,
1131 .clkr = {
1132 .enable_reg = 0x282c,
1133 .enable_mask = BIT(11),
1134 .hw.init = &(struct clk_init_data){
1135 .name = "sdc1_src",
1136 .parent_names = gcc_pxo_pll8,
1137 .num_parents = 2,
1138 .ops = &clk_rcg_ops,
1139 .flags = CLK_SET_RATE_GATE,
1140 },
1141 }
1142};
1143
1144static struct clk_branch sdc1_clk = {
1145 .halt_reg = 0x2fc8,
1146 .halt_bit = 6,
1147 .clkr = {
1148 .enable_reg = 0x282c,
1149 .enable_mask = BIT(9),
1150 .hw.init = &(struct clk_init_data){
1151 .name = "sdc1_clk",
1152 .parent_names = (const char *[]){ "sdc1_src" },
1153 .num_parents = 1,
1154 .ops = &clk_branch_ops,
1155 .flags = CLK_SET_RATE_PARENT,
1156 },
1157 },
1158};
1159
1160static struct clk_rcg sdc3_src = {
1161 .ns_reg = 0x286c,
1162 .md_reg = 0x2868,
1163 .mn = {
1164 .mnctr_en_bit = 8,
1165 .mnctr_reset_bit = 7,
1166 .mnctr_mode_shift = 5,
1167 .n_val_shift = 16,
1168 .m_val_shift = 16,
1169 .width = 8,
1170 },
1171 .p = {
1172 .pre_div_shift = 3,
1173 .pre_div_width = 2,
1174 },
1175 .s = {
1176 .src_sel_shift = 0,
1177 .parent_map = gcc_pxo_pll8_map,
1178 },
1179 .freq_tbl = clk_tbl_sdc,
1180 .clkr = {
1181 .enable_reg = 0x286c,
1182 .enable_mask = BIT(11),
1183 .hw.init = &(struct clk_init_data){
1184 .name = "sdc3_src",
1185 .parent_names = gcc_pxo_pll8,
1186 .num_parents = 2,
1187 .ops = &clk_rcg_ops,
1188 .flags = CLK_SET_RATE_GATE,
1189 },
1190 }
1191};
1192
1193static struct clk_branch sdc3_clk = {
1194 .halt_reg = 0x2fc8,
1195 .halt_bit = 4,
1196 .clkr = {
1197 .enable_reg = 0x286c,
1198 .enable_mask = BIT(9),
1199 .hw.init = &(struct clk_init_data){
1200 .name = "sdc3_clk",
1201 .parent_names = (const char *[]){ "sdc3_src" },
1202 .num_parents = 1,
1203 .ops = &clk_branch_ops,
1204 .flags = CLK_SET_RATE_PARENT,
1205 },
1206 },
1207};
1208
1209static struct clk_branch sdc1_h_clk = {
1210 .hwcg_reg = 0x2820,
1211 .hwcg_bit = 6,
1212 .halt_reg = 0x2fc8,
1213 .halt_bit = 11,
1214 .clkr = {
1215 .enable_reg = 0x2820,
1216 .enable_mask = BIT(4),
1217 .hw.init = &(struct clk_init_data){
1218 .name = "sdc1_h_clk",
1219 .ops = &clk_branch_ops,
1220 .flags = CLK_IS_ROOT,
1221 },
1222 },
1223};
1224
1225static struct clk_branch sdc3_h_clk = {
1226 .hwcg_reg = 0x2860,
1227 .hwcg_bit = 6,
1228 .halt_reg = 0x2fc8,
1229 .halt_bit = 9,
1230 .clkr = {
1231 .enable_reg = 0x2860,
1232 .enable_mask = BIT(4),
1233 .hw.init = &(struct clk_init_data){
1234 .name = "sdc3_h_clk",
1235 .ops = &clk_branch_ops,
1236 .flags = CLK_IS_ROOT,
1237 },
1238 },
1239};
1240
1241static const struct freq_tbl clk_tbl_tsif_ref[] = {
1242 { 105000, P_PXO, 1, 1, 256 },
1243 { }
1244};
1245
1246static struct clk_rcg tsif_ref_src = {
1247 .ns_reg = 0x2710,
1248 .md_reg = 0x270c,
1249 .mn = {
1250 .mnctr_en_bit = 8,
1251 .mnctr_reset_bit = 7,
1252 .mnctr_mode_shift = 5,
1253 .n_val_shift = 16,
1254 .m_val_shift = 16,
1255 .width = 16,
1256 },
1257 .p = {
1258 .pre_div_shift = 3,
1259 .pre_div_width = 2,
1260 },
1261 .s = {
1262 .src_sel_shift = 0,
1263 .parent_map = gcc_pxo_pll8_map,
1264 },
1265 .freq_tbl = clk_tbl_tsif_ref,
1266 .clkr = {
1267 .enable_reg = 0x2710,
1268 .enable_mask = BIT(11),
1269 .hw.init = &(struct clk_init_data){
1270 .name = "tsif_ref_src",
1271 .parent_names = gcc_pxo_pll8,
1272 .num_parents = 2,
1273 .ops = &clk_rcg_ops,
1274 .flags = CLK_SET_RATE_GATE,
1275 },
1276 }
1277};
1278
1279static struct clk_branch tsif_ref_clk = {
1280 .halt_reg = 0x2fd4,
1281 .halt_bit = 5,
1282 .clkr = {
1283 .enable_reg = 0x2710,
1284 .enable_mask = BIT(9),
1285 .hw.init = &(struct clk_init_data){
1286 .name = "tsif_ref_clk",
1287 .parent_names = (const char *[]){ "tsif_ref_src" },
1288 .num_parents = 1,
1289 .ops = &clk_branch_ops,
1290 .flags = CLK_SET_RATE_PARENT,
1291 },
1292 },
1293};
1294
1295static struct clk_branch tsif_h_clk = {
1296 .hwcg_reg = 0x2700,
1297 .hwcg_bit = 6,
1298 .halt_reg = 0x2fd4,
1299 .halt_bit = 7,
1300 .clkr = {
1301 .enable_reg = 0x2700,
1302 .enable_mask = BIT(4),
1303 .hw.init = &(struct clk_init_data){
1304 .name = "tsif_h_clk",
1305 .ops = &clk_branch_ops,
1306 .flags = CLK_IS_ROOT,
1307 },
1308 },
1309};
1310
1311static struct clk_branch dma_bam_h_clk = {
1312 .hwcg_reg = 0x25c0,
1313 .hwcg_bit = 6,
1314 .halt_reg = 0x2fc8,
1315 .halt_bit = 12,
1316 .clkr = {
1317 .enable_reg = 0x25c0,
1318 .enable_mask = BIT(4),
1319 .hw.init = &(struct clk_init_data){
1320 .name = "dma_bam_h_clk",
1321 .ops = &clk_branch_ops,
1322 .flags = CLK_IS_ROOT,
1323 },
1324 },
1325};
1326
1327static struct clk_branch adm0_clk = {
1328 .halt_reg = 0x2fdc,
1329 .halt_check = BRANCH_HALT_VOTED,
1330 .halt_bit = 12,
1331 .clkr = {
1332 .enable_reg = 0x3080,
1333 .enable_mask = BIT(2),
1334 .hw.init = &(struct clk_init_data){
1335 .name = "adm0_clk",
1336 .ops = &clk_branch_ops,
1337 .flags = CLK_IS_ROOT,
1338 },
1339 },
1340};
1341
1342static struct clk_branch adm0_pbus_clk = {
1343 .hwcg_reg = 0x2208,
1344 .hwcg_bit = 6,
1345 .halt_reg = 0x2fdc,
1346 .halt_check = BRANCH_HALT_VOTED,
1347 .halt_bit = 11,
1348 .clkr = {
1349 .enable_reg = 0x3080,
1350 .enable_mask = BIT(3),
1351 .hw.init = &(struct clk_init_data){
1352 .name = "adm0_pbus_clk",
1353 .ops = &clk_branch_ops,
1354 .flags = CLK_IS_ROOT,
1355 },
1356 },
1357};
1358
1359static struct clk_branch pmic_arb0_h_clk = {
1360 .halt_reg = 0x2fd8,
1361 .halt_check = BRANCH_HALT_VOTED,
1362 .halt_bit = 22,
1363 .clkr = {
1364 .enable_reg = 0x3080,
1365 .enable_mask = BIT(8),
1366 .hw.init = &(struct clk_init_data){
1367 .name = "pmic_arb0_h_clk",
1368 .ops = &clk_branch_ops,
1369 .flags = CLK_IS_ROOT,
1370 },
1371 },
1372};
1373
1374static struct clk_branch pmic_arb1_h_clk = {
1375 .halt_reg = 0x2fd8,
1376 .halt_check = BRANCH_HALT_VOTED,
1377 .halt_bit = 21,
1378 .clkr = {
1379 .enable_reg = 0x3080,
1380 .enable_mask = BIT(9),
1381 .hw.init = &(struct clk_init_data){
1382 .name = "pmic_arb1_h_clk",
1383 .ops = &clk_branch_ops,
1384 .flags = CLK_IS_ROOT,
1385 },
1386 },
1387};
1388
1389static struct clk_branch pmic_ssbi2_clk = {
1390 .halt_reg = 0x2fd8,
1391 .halt_check = BRANCH_HALT_VOTED,
1392 .halt_bit = 23,
1393 .clkr = {
1394 .enable_reg = 0x3080,
1395 .enable_mask = BIT(7),
1396 .hw.init = &(struct clk_init_data){
1397 .name = "pmic_ssbi2_clk",
1398 .ops = &clk_branch_ops,
1399 .flags = CLK_IS_ROOT,
1400 },
1401 },
1402};
1403
1404static struct clk_branch rpm_msg_ram_h_clk = {
1405 .hwcg_reg = 0x27e0,
1406 .hwcg_bit = 6,
1407 .halt_reg = 0x2fd8,
1408 .halt_check = BRANCH_HALT_VOTED,
1409 .halt_bit = 12,
1410 .clkr = {
1411 .enable_reg = 0x3080,
1412 .enable_mask = BIT(6),
1413 .hw.init = &(struct clk_init_data){
1414 .name = "rpm_msg_ram_h_clk",
1415 .ops = &clk_branch_ops,
1416 .flags = CLK_IS_ROOT,
1417 },
1418 },
1419};
1420
1421static const struct freq_tbl clk_tbl_pcie_ref[] = {
1422 { 100000000, P_PLL3, 12, 0, 0 },
1423 { }
1424};
1425
1426static struct clk_rcg pcie_ref_src = {
1427 .ns_reg = 0x3860,
1428 .p = {
1429 .pre_div_shift = 3,
1430 .pre_div_width = 4,
1431 },
1432 .s = {
1433 .src_sel_shift = 0,
1434 .parent_map = gcc_pxo_pll3_map,
1435 },
1436 .freq_tbl = clk_tbl_pcie_ref,
1437 .clkr = {
1438 .enable_reg = 0x3860,
1439 .enable_mask = BIT(11),
1440 .hw.init = &(struct clk_init_data){
1441 .name = "pcie_ref_src",
1442 .parent_names = gcc_pxo_pll3,
1443 .num_parents = 2,
1444 .ops = &clk_rcg_ops,
1445 .flags = CLK_SET_RATE_GATE,
1446 },
1447 },
1448};
1449
1450static struct clk_branch pcie_ref_src_clk = {
1451 .halt_reg = 0x2fdc,
1452 .halt_bit = 30,
1453 .clkr = {
1454 .enable_reg = 0x3860,
1455 .enable_mask = BIT(9),
1456 .hw.init = &(struct clk_init_data){
1457 .name = "pcie_ref_src_clk",
1458 .parent_names = (const char *[]){ "pcie_ref_src" },
1459 .num_parents = 1,
1460 .ops = &clk_branch_ops,
1461 .flags = CLK_SET_RATE_PARENT,
1462 },
1463 },
1464};
1465
1466static struct clk_branch pcie_a_clk = {
1467 .halt_reg = 0x2fc0,
1468 .halt_bit = 13,
1469 .clkr = {
1470 .enable_reg = 0x22c0,
1471 .enable_mask = BIT(4),
1472 .hw.init = &(struct clk_init_data){
1473 .name = "pcie_a_clk",
1474 .ops = &clk_branch_ops,
1475 .flags = CLK_IS_ROOT,
1476 },
1477 },
1478};
1479
1480static struct clk_branch pcie_aux_clk = {
1481 .halt_reg = 0x2fdc,
1482 .halt_bit = 31,
1483 .clkr = {
1484 .enable_reg = 0x22c8,
1485 .enable_mask = BIT(4),
1486 .hw.init = &(struct clk_init_data){
1487 .name = "pcie_aux_clk",
1488 .ops = &clk_branch_ops,
1489 .flags = CLK_IS_ROOT,
1490 },
1491 },
1492};
1493
1494static struct clk_branch pcie_h_clk = {
1495 .halt_reg = 0x2fd4,
1496 .halt_bit = 8,
1497 .clkr = {
1498 .enable_reg = 0x22cc,
1499 .enable_mask = BIT(4),
1500 .hw.init = &(struct clk_init_data){
1501 .name = "pcie_h_clk",
1502 .ops = &clk_branch_ops,
1503 .flags = CLK_IS_ROOT,
1504 },
1505 },
1506};
1507
1508static struct clk_branch pcie_phy_clk = {
1509 .halt_reg = 0x2fdc,
1510 .halt_bit = 29,
1511 .clkr = {
1512 .enable_reg = 0x22d0,
1513 .enable_mask = BIT(4),
1514 .hw.init = &(struct clk_init_data){
1515 .name = "pcie_phy_clk",
1516 .ops = &clk_branch_ops,
1517 .flags = CLK_IS_ROOT,
1518 },
1519 },
1520};
1521
1522static struct clk_rcg pcie1_ref_src = {
1523 .ns_reg = 0x3aa0,
1524 .p = {
1525 .pre_div_shift = 3,
1526 .pre_div_width = 4,
1527 },
1528 .s = {
1529 .src_sel_shift = 0,
1530 .parent_map = gcc_pxo_pll3_map,
1531 },
1532 .freq_tbl = clk_tbl_pcie_ref,
1533 .clkr = {
1534 .enable_reg = 0x3aa0,
1535 .enable_mask = BIT(11),
1536 .hw.init = &(struct clk_init_data){
1537 .name = "pcie1_ref_src",
1538 .parent_names = gcc_pxo_pll3,
1539 .num_parents = 2,
1540 .ops = &clk_rcg_ops,
1541 .flags = CLK_SET_RATE_GATE,
1542 },
1543 },
1544};
1545
1546static struct clk_branch pcie1_ref_src_clk = {
1547 .halt_reg = 0x2fdc,
1548 .halt_bit = 27,
1549 .clkr = {
1550 .enable_reg = 0x3aa0,
1551 .enable_mask = BIT(9),
1552 .hw.init = &(struct clk_init_data){
1553 .name = "pcie1_ref_src_clk",
1554 .parent_names = (const char *[]){ "pcie1_ref_src" },
1555 .num_parents = 1,
1556 .ops = &clk_branch_ops,
1557 .flags = CLK_SET_RATE_PARENT,
1558 },
1559 },
1560};
1561
1562static struct clk_branch pcie1_a_clk = {
1563 .halt_reg = 0x2fc0,
1564 .halt_bit = 10,
1565 .clkr = {
1566 .enable_reg = 0x3a80,
1567 .enable_mask = BIT(4),
1568 .hw.init = &(struct clk_init_data){
1569 .name = "pcie1_a_clk",
1570 .ops = &clk_branch_ops,
1571 .flags = CLK_IS_ROOT,
1572 },
1573 },
1574};
1575
1576static struct clk_branch pcie1_aux_clk = {
1577 .halt_reg = 0x2fdc,
1578 .halt_bit = 28,
1579 .clkr = {
1580 .enable_reg = 0x3a88,
1581 .enable_mask = BIT(4),
1582 .hw.init = &(struct clk_init_data){
1583 .name = "pcie1_aux_clk",
1584 .ops = &clk_branch_ops,
1585 .flags = CLK_IS_ROOT,
1586 },
1587 },
1588};
1589
1590static struct clk_branch pcie1_h_clk = {
1591 .halt_reg = 0x2fd4,
1592 .halt_bit = 9,
1593 .clkr = {
1594 .enable_reg = 0x3a8c,
1595 .enable_mask = BIT(4),
1596 .hw.init = &(struct clk_init_data){
1597 .name = "pcie1_h_clk",
1598 .ops = &clk_branch_ops,
1599 .flags = CLK_IS_ROOT,
1600 },
1601 },
1602};
1603
1604static struct clk_branch pcie1_phy_clk = {
1605 .halt_reg = 0x2fdc,
1606 .halt_bit = 26,
1607 .clkr = {
1608 .enable_reg = 0x3a90,
1609 .enable_mask = BIT(4),
1610 .hw.init = &(struct clk_init_data){
1611 .name = "pcie1_phy_clk",
1612 .ops = &clk_branch_ops,
1613 .flags = CLK_IS_ROOT,
1614 },
1615 },
1616};
1617
1618static struct clk_rcg pcie2_ref_src = {
1619 .ns_reg = 0x3ae0,
1620 .p = {
1621 .pre_div_shift = 3,
1622 .pre_div_width = 4,
1623 },
1624 .s = {
1625 .src_sel_shift = 0,
1626 .parent_map = gcc_pxo_pll3_map,
1627 },
1628 .freq_tbl = clk_tbl_pcie_ref,
1629 .clkr = {
1630 .enable_reg = 0x3ae0,
1631 .enable_mask = BIT(11),
1632 .hw.init = &(struct clk_init_data){
1633 .name = "pcie2_ref_src",
1634 .parent_names = gcc_pxo_pll3,
1635 .num_parents = 2,
1636 .ops = &clk_rcg_ops,
1637 .flags = CLK_SET_RATE_GATE,
1638 },
1639 },
1640};
1641
1642static struct clk_branch pcie2_ref_src_clk = {
1643 .halt_reg = 0x2fdc,
1644 .halt_bit = 24,
1645 .clkr = {
1646 .enable_reg = 0x3ae0,
1647 .enable_mask = BIT(9),
1648 .hw.init = &(struct clk_init_data){
1649 .name = "pcie2_ref_src_clk",
1650 .parent_names = (const char *[]){ "pcie2_ref_src" },
1651 .num_parents = 1,
1652 .ops = &clk_branch_ops,
1653 .flags = CLK_SET_RATE_PARENT,
1654 },
1655 },
1656};
1657
1658static struct clk_branch pcie2_a_clk = {
1659 .halt_reg = 0x2fc0,
1660 .halt_bit = 9,
1661 .clkr = {
1662 .enable_reg = 0x3ac0,
1663 .enable_mask = BIT(4),
1664 .hw.init = &(struct clk_init_data){
1665 .name = "pcie2_a_clk",
1666 .ops = &clk_branch_ops,
1667 .flags = CLK_IS_ROOT,
1668 },
1669 },
1670};
1671
1672static struct clk_branch pcie2_aux_clk = {
1673 .halt_reg = 0x2fdc,
1674 .halt_bit = 25,
1675 .clkr = {
1676 .enable_reg = 0x3ac8,
1677 .enable_mask = BIT(4),
1678 .hw.init = &(struct clk_init_data){
1679 .name = "pcie2_aux_clk",
1680 .ops = &clk_branch_ops,
1681 .flags = CLK_IS_ROOT,
1682 },
1683 },
1684};
1685
1686static struct clk_branch pcie2_h_clk = {
1687 .halt_reg = 0x2fd4,
1688 .halt_bit = 10,
1689 .clkr = {
1690 .enable_reg = 0x3acc,
1691 .enable_mask = BIT(4),
1692 .hw.init = &(struct clk_init_data){
1693 .name = "pcie2_h_clk",
1694 .ops = &clk_branch_ops,
1695 .flags = CLK_IS_ROOT,
1696 },
1697 },
1698};
1699
1700static struct clk_branch pcie2_phy_clk = {
1701 .halt_reg = 0x2fdc,
1702 .halt_bit = 23,
1703 .clkr = {
1704 .enable_reg = 0x3ad0,
1705 .enable_mask = BIT(4),
1706 .hw.init = &(struct clk_init_data){
1707 .name = "pcie2_phy_clk",
1708 .ops = &clk_branch_ops,
1709 .flags = CLK_IS_ROOT,
1710 },
1711 },
1712};
1713
1714static const struct freq_tbl clk_tbl_sata_ref[] = {
1715 { 100000000, P_PLL3, 12, 0, 0 },
1716 { }
1717};
1718
1719static struct clk_rcg sata_ref_src = {
1720 .ns_reg = 0x2c08,
1721 .p = {
1722 .pre_div_shift = 3,
1723 .pre_div_width = 4,
1724 },
1725 .s = {
1726 .src_sel_shift = 0,
1727 .parent_map = gcc_pxo_pll3_sata_map,
1728 },
1729 .freq_tbl = clk_tbl_sata_ref,
1730 .clkr = {
1731 .enable_reg = 0x2c08,
1732 .enable_mask = BIT(7),
1733 .hw.init = &(struct clk_init_data){
1734 .name = "sata_ref_src",
1735 .parent_names = gcc_pxo_pll3,
1736 .num_parents = 2,
1737 .ops = &clk_rcg_ops,
1738 .flags = CLK_SET_RATE_GATE,
1739 },
1740 },
1741};
1742
1743static struct clk_branch sata_rxoob_clk = {
1744 .halt_reg = 0x2fdc,
1745 .halt_bit = 20,
1746 .clkr = {
1747 .enable_reg = 0x2c0c,
1748 .enable_mask = BIT(4),
1749 .hw.init = &(struct clk_init_data){
1750 .name = "sata_rxoob_clk",
1751 .parent_names = (const char *[]){ "sata_ref_src" },
1752 .num_parents = 1,
1753 .ops = &clk_branch_ops,
1754 .flags = CLK_SET_RATE_PARENT,
1755 },
1756 },
1757};
1758
1759static struct clk_branch sata_pmalive_clk = {
1760 .halt_reg = 0x2fdc,
1761 .halt_bit = 19,
1762 .clkr = {
1763 .enable_reg = 0x2c10,
1764 .enable_mask = BIT(4),
1765 .hw.init = &(struct clk_init_data){
1766 .name = "sata_pmalive_clk",
1767 .parent_names = (const char *[]){ "sata_ref_src" },
1768 .num_parents = 1,
1769 .ops = &clk_branch_ops,
1770 .flags = CLK_SET_RATE_PARENT,
1771 },
1772 },
1773};
1774
1775static struct clk_branch sata_phy_ref_clk = {
1776 .halt_reg = 0x2fdc,
1777 .halt_bit = 18,
1778 .clkr = {
1779 .enable_reg = 0x2c14,
1780 .enable_mask = BIT(4),
1781 .hw.init = &(struct clk_init_data){
1782 .name = "sata_phy_ref_clk",
1783 .parent_names = (const char *[]){ "pxo" },
1784 .num_parents = 1,
1785 .ops = &clk_branch_ops,
1786 },
1787 },
1788};
1789
1790static struct clk_branch sata_a_clk = {
1791 .halt_reg = 0x2fc0,
1792 .halt_bit = 12,
1793 .clkr = {
1794 .enable_reg = 0x2c20,
1795 .enable_mask = BIT(4),
1796 .hw.init = &(struct clk_init_data){
1797 .name = "sata_a_clk",
1798 .ops = &clk_branch_ops,
1799 .flags = CLK_IS_ROOT,
1800 },
1801 },
1802};
1803
1804static struct clk_branch sata_h_clk = {
1805 .halt_reg = 0x2fdc,
1806 .halt_bit = 21,
1807 .clkr = {
1808 .enable_reg = 0x2c00,
1809 .enable_mask = BIT(4),
1810 .hw.init = &(struct clk_init_data){
1811 .name = "sata_h_clk",
1812 .ops = &clk_branch_ops,
1813 .flags = CLK_IS_ROOT,
1814 },
1815 },
1816};
1817
1818static struct clk_branch sfab_sata_s_h_clk = {
1819 .halt_reg = 0x2fc4,
1820 .halt_bit = 14,
1821 .clkr = {
1822 .enable_reg = 0x2480,
1823 .enable_mask = BIT(4),
1824 .hw.init = &(struct clk_init_data){
1825 .name = "sfab_sata_s_h_clk",
1826 .ops = &clk_branch_ops,
1827 .flags = CLK_IS_ROOT,
1828 },
1829 },
1830};
1831
1832static struct clk_branch sata_phy_cfg_clk = {
1833 .halt_reg = 0x2fcc,
1834 .halt_bit = 14,
1835 .clkr = {
1836 .enable_reg = 0x2c40,
1837 .enable_mask = BIT(4),
1838 .hw.init = &(struct clk_init_data){
1839 .name = "sata_phy_cfg_clk",
1840 .ops = &clk_branch_ops,
1841 .flags = CLK_IS_ROOT,
1842 },
1843 },
1844};
1845
1846static const struct freq_tbl clk_tbl_usb30_master[] = {
1847 { 125000000, P_PLL0, 1, 5, 32 },
1848 { }
1849};
1850
1851static struct clk_rcg usb30_master_clk_src = {
1852 .ns_reg = 0x3b2c,
1853 .md_reg = 0x3b28,
1854 .mn = {
1855 .mnctr_en_bit = 8,
1856 .mnctr_reset_bit = 7,
1857 .mnctr_mode_shift = 5,
1858 .n_val_shift = 16,
1859 .m_val_shift = 16,
1860 .width = 8,
1861 },
1862 .p = {
1863 .pre_div_shift = 3,
1864 .pre_div_width = 2,
1865 },
1866 .s = {
1867 .src_sel_shift = 0,
1868 .parent_map = gcc_pxo_pll8_pll0,
1869 },
1870 .freq_tbl = clk_tbl_usb30_master,
1871 .clkr = {
1872 .enable_reg = 0x3b2c,
1873 .enable_mask = BIT(11),
1874 .hw.init = &(struct clk_init_data){
1875 .name = "usb30_master_ref_src",
1876 .parent_names = gcc_pxo_pll8_pll0_map,
1877 .num_parents = 3,
1878 .ops = &clk_rcg_ops,
1879 .flags = CLK_SET_RATE_GATE,
1880 },
1881 },
1882};
1883
1884static struct clk_branch usb30_0_branch_clk = {
1885 .halt_reg = 0x2fc4,
1886 .halt_bit = 22,
1887 .clkr = {
1888 .enable_reg = 0x3b24,
1889 .enable_mask = BIT(4),
1890 .hw.init = &(struct clk_init_data){
1891 .name = "usb30_0_branch_clk",
1892 .parent_names = (const char *[]){ "usb30_master_ref_src", },
1893 .num_parents = 1,
1894 .ops = &clk_branch_ops,
1895 .flags = CLK_SET_RATE_PARENT,
1896 },
1897 },
1898};
1899
1900static struct clk_branch usb30_1_branch_clk = {
1901 .halt_reg = 0x2fc4,
1902 .halt_bit = 17,
1903 .clkr = {
1904 .enable_reg = 0x3b34,
1905 .enable_mask = BIT(4),
1906 .hw.init = &(struct clk_init_data){
1907 .name = "usb30_1_branch_clk",
1908 .parent_names = (const char *[]){ "usb30_master_ref_src", },
1909 .num_parents = 1,
1910 .ops = &clk_branch_ops,
1911 .flags = CLK_SET_RATE_PARENT,
1912 },
1913 },
1914};
1915
1916static const struct freq_tbl clk_tbl_usb30_utmi[] = {
1917 { 60000000, P_PLL8, 1, 5, 32 },
1918 { }
1919};
1920
1921static struct clk_rcg usb30_utmi_clk = {
1922 .ns_reg = 0x3b44,
1923 .md_reg = 0x3b40,
1924 .mn = {
1925 .mnctr_en_bit = 8,
1926 .mnctr_reset_bit = 7,
1927 .mnctr_mode_shift = 5,
1928 .n_val_shift = 16,
1929 .m_val_shift = 16,
1930 .width = 8,
1931 },
1932 .p = {
1933 .pre_div_shift = 3,
1934 .pre_div_width = 2,
1935 },
1936 .s = {
1937 .src_sel_shift = 0,
1938 .parent_map = gcc_pxo_pll8_pll0,
1939 },
1940 .freq_tbl = clk_tbl_usb30_utmi,
1941 .clkr = {
1942 .enable_reg = 0x3b44,
1943 .enable_mask = BIT(11),
1944 .hw.init = &(struct clk_init_data){
1945 .name = "usb30_utmi_clk",
1946 .parent_names = gcc_pxo_pll8_pll0_map,
1947 .num_parents = 3,
1948 .ops = &clk_rcg_ops,
1949 .flags = CLK_SET_RATE_GATE,
1950 },
1951 },
1952};
1953
1954static struct clk_branch usb30_0_utmi_clk_ctl = {
1955 .halt_reg = 0x2fc4,
1956 .halt_bit = 21,
1957 .clkr = {
1958 .enable_reg = 0x3b48,
1959 .enable_mask = BIT(4),
1960 .hw.init = &(struct clk_init_data){
1961 .name = "usb30_0_utmi_clk_ctl",
1962 .parent_names = (const char *[]){ "usb30_utmi_clk", },
1963 .num_parents = 1,
1964 .ops = &clk_branch_ops,
1965 .flags = CLK_SET_RATE_PARENT,
1966 },
1967 },
1968};
1969
1970static struct clk_branch usb30_1_utmi_clk_ctl = {
1971 .halt_reg = 0x2fc4,
1972 .halt_bit = 15,
1973 .clkr = {
1974 .enable_reg = 0x3b4c,
1975 .enable_mask = BIT(4),
1976 .hw.init = &(struct clk_init_data){
1977 .name = "usb30_1_utmi_clk_ctl",
1978 .parent_names = (const char *[]){ "usb30_utmi_clk", },
1979 .num_parents = 1,
1980 .ops = &clk_branch_ops,
1981 .flags = CLK_SET_RATE_PARENT,
1982 },
1983 },
1984};
1985
1986static const struct freq_tbl clk_tbl_usb[] = {
1987 { 60000000, P_PLL8, 1, 5, 32 },
1988 { }
1989};
1990
1991static struct clk_rcg usb_hs1_xcvr_clk_src = {
1992 .ns_reg = 0x290C,
1993 .md_reg = 0x2908,
1994 .mn = {
1995 .mnctr_en_bit = 8,
1996 .mnctr_reset_bit = 7,
1997 .mnctr_mode_shift = 5,
1998 .n_val_shift = 16,
1999 .m_val_shift = 16,
2000 .width = 8,
2001 },
2002 .p = {
2003 .pre_div_shift = 3,
2004 .pre_div_width = 2,
2005 },
2006 .s = {
2007 .src_sel_shift = 0,
2008 .parent_map = gcc_pxo_pll8_pll0,
2009 },
2010 .freq_tbl = clk_tbl_usb,
2011 .clkr = {
2012 .enable_reg = 0x2968,
2013 .enable_mask = BIT(11),
2014 .hw.init = &(struct clk_init_data){
2015 .name = "usb_hs1_xcvr_src",
2016 .parent_names = gcc_pxo_pll8_pll0_map,
2017 .num_parents = 3,
2018 .ops = &clk_rcg_ops,
2019 .flags = CLK_SET_RATE_GATE,
2020 },
2021 },
2022};
2023
2024static struct clk_branch usb_hs1_xcvr_clk = {
2025 .halt_reg = 0x2fcc,
2026 .halt_bit = 17,
2027 .clkr = {
2028 .enable_reg = 0x290c,
2029 .enable_mask = BIT(9),
2030 .hw.init = &(struct clk_init_data){
2031 .name = "usb_hs1_xcvr_clk",
2032 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
2033 .num_parents = 1,
2034 .ops = &clk_branch_ops,
2035 .flags = CLK_SET_RATE_PARENT,
2036 },
2037 },
2038};
2039
2040static struct clk_branch usb_hs1_h_clk = {
2041 .hwcg_reg = 0x2900,
2042 .hwcg_bit = 6,
2043 .halt_reg = 0x2fc8,
2044 .halt_bit = 1,
2045 .clkr = {
2046 .enable_reg = 0x2900,
2047 .enable_mask = BIT(4),
2048 .hw.init = &(struct clk_init_data){
2049 .name = "usb_hs1_h_clk",
2050 .ops = &clk_branch_ops,
2051 .flags = CLK_IS_ROOT,
2052 },
2053 },
2054};
2055
2056static struct clk_rcg usb_fs1_xcvr_clk_src = {
2057 .ns_reg = 0x2968,
2058 .md_reg = 0x2964,
2059 .mn = {
2060 .mnctr_en_bit = 8,
2061 .mnctr_reset_bit = 7,
2062 .mnctr_mode_shift = 5,
2063 .n_val_shift = 16,
2064 .m_val_shift = 16,
2065 .width = 8,
2066 },
2067 .p = {
2068 .pre_div_shift = 3,
2069 .pre_div_width = 2,
2070 },
2071 .s = {
2072 .src_sel_shift = 0,
2073 .parent_map = gcc_pxo_pll8_pll0,
2074 },
2075 .freq_tbl = clk_tbl_usb,
2076 .clkr = {
2077 .enable_reg = 0x2968,
2078 .enable_mask = BIT(11),
2079 .hw.init = &(struct clk_init_data){
2080 .name = "usb_fs1_xcvr_src",
2081 .parent_names = gcc_pxo_pll8_pll0_map,
2082 .num_parents = 3,
2083 .ops = &clk_rcg_ops,
2084 .flags = CLK_SET_RATE_GATE,
2085 },
2086 },
2087};
2088
2089static struct clk_branch usb_fs1_xcvr_clk = {
2090 .halt_reg = 0x2fcc,
2091 .halt_bit = 17,
2092 .clkr = {
2093 .enable_reg = 0x2968,
2094 .enable_mask = BIT(9),
2095 .hw.init = &(struct clk_init_data){
2096 .name = "usb_fs1_xcvr_clk",
2097 .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2098 .num_parents = 1,
2099 .ops = &clk_branch_ops,
2100 .flags = CLK_SET_RATE_PARENT,
2101 },
2102 },
2103};
2104
2105static struct clk_branch usb_fs1_sys_clk = {
2106 .halt_reg = 0x2fcc,
2107 .halt_bit = 18,
2108 .clkr = {
2109 .enable_reg = 0x296c,
2110 .enable_mask = BIT(4),
2111 .hw.init = &(struct clk_init_data){
2112 .name = "usb_fs1_sys_clk",
2113 .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2114 .num_parents = 1,
2115 .ops = &clk_branch_ops,
2116 .flags = CLK_SET_RATE_PARENT,
2117 },
2118 },
2119};
2120
2121static struct clk_branch usb_fs1_h_clk = {
2122 .halt_reg = 0x2fcc,
2123 .halt_bit = 19,
2124 .clkr = {
2125 .enable_reg = 0x2960,
2126 .enable_mask = BIT(4),
2127 .hw.init = &(struct clk_init_data){
2128 .name = "usb_fs1_h_clk",
2129 .ops = &clk_branch_ops,
2130 .flags = CLK_IS_ROOT,
2131 },
2132 },
2133};
2134
2135static struct clk_regmap *gcc_ipq806x_clks[] = {
2136 [PLL3] = &pll3.clkr,
2137 [PLL8] = &pll8.clkr,
2138 [PLL8_VOTE] = &pll8_vote,
2139 [PLL14] = &pll14.clkr,
2140 [PLL14_VOTE] = &pll14_vote,
2141 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2142 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2143 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
2144 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
2145 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
2146 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
2147 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
2148 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
2149 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
2150 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2151 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2152 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2153 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
2154 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
2155 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
2156 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
2157 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
2158 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
2159 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
2160 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
2161 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
2162 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2163 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2164 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2165 [GP0_SRC] = &gp0_src.clkr,
2166 [GP0_CLK] = &gp0_clk.clkr,
2167 [GP1_SRC] = &gp1_src.clkr,
2168 [GP1_CLK] = &gp1_clk.clkr,
2169 [GP2_SRC] = &gp2_src.clkr,
2170 [GP2_CLK] = &gp2_clk.clkr,
2171 [PMEM_A_CLK] = &pmem_clk.clkr,
2172 [PRNG_SRC] = &prng_src.clkr,
2173 [PRNG_CLK] = &prng_clk.clkr,
2174 [SDC1_SRC] = &sdc1_src.clkr,
2175 [SDC1_CLK] = &sdc1_clk.clkr,
2176 [SDC3_SRC] = &sdc3_src.clkr,
2177 [SDC3_CLK] = &sdc3_clk.clkr,
2178 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
2179 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
2180 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
2181 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
2182 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
2183 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
2184 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
2185 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2186 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2187 [TSIF_H_CLK] = &tsif_h_clk.clkr,
2188 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
2189 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
2190 [ADM0_CLK] = &adm0_clk.clkr,
2191 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
2192 [PCIE_A_CLK] = &pcie_a_clk.clkr,
2193 [PCIE_AUX_CLK] = &pcie_aux_clk.clkr,
2194 [PCIE_H_CLK] = &pcie_h_clk.clkr,
2195 [PCIE_PHY_CLK] = &pcie_phy_clk.clkr,
2196 [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
2197 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
2198 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
2199 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
2200 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
2201 [SATA_H_CLK] = &sata_h_clk.clkr,
2202 [SATA_CLK_SRC] = &sata_ref_src.clkr,
2203 [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
2204 [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
2205 [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
2206 [SATA_A_CLK] = &sata_a_clk.clkr,
2207 [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
2208 [PCIE_ALT_REF_SRC] = &pcie_ref_src.clkr,
2209 [PCIE_ALT_REF_CLK] = &pcie_ref_src_clk.clkr,
2210 [PCIE_1_A_CLK] = &pcie1_a_clk.clkr,
2211 [PCIE_1_AUX_CLK] = &pcie1_aux_clk.clkr,
2212 [PCIE_1_H_CLK] = &pcie1_h_clk.clkr,
2213 [PCIE_1_PHY_CLK] = &pcie1_phy_clk.clkr,
2214 [PCIE_1_ALT_REF_SRC] = &pcie1_ref_src.clkr,
2215 [PCIE_1_ALT_REF_CLK] = &pcie1_ref_src_clk.clkr,
2216 [PCIE_2_A_CLK] = &pcie2_a_clk.clkr,
2217 [PCIE_2_AUX_CLK] = &pcie2_aux_clk.clkr,
2218 [PCIE_2_H_CLK] = &pcie2_h_clk.clkr,
2219 [PCIE_2_PHY_CLK] = &pcie2_phy_clk.clkr,
2220 [PCIE_2_ALT_REF_SRC] = &pcie2_ref_src.clkr,
2221 [PCIE_2_ALT_REF_CLK] = &pcie2_ref_src_clk.clkr,
2222 [USB30_MASTER_SRC] = &usb30_master_clk_src.clkr,
2223 [USB30_0_MASTER_CLK] = &usb30_0_branch_clk.clkr,
2224 [USB30_1_MASTER_CLK] = &usb30_1_branch_clk.clkr,
2225 [USB30_UTMI_SRC] = &usb30_utmi_clk.clkr,
2226 [USB30_0_UTMI_CLK] = &usb30_0_utmi_clk_ctl.clkr,
2227 [USB30_1_UTMI_CLK] = &usb30_1_utmi_clk_ctl.clkr,
2228 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
2229 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_clk_src.clkr,
2230 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
2231 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
2232 [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
2233 [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
2234 [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
2235};
2236
2237static const struct qcom_reset_map gcc_ipq806x_resets[] = {
2238 [QDSS_STM_RESET] = { 0x2060, 6 },
2239 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2240 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2241 [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 },
2242 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
2243 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7 },
2244 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
2245 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
2246 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
2247 [ADM0_C2_RESET] = { 0x220c, 4 },
2248 [ADM0_C1_RESET] = { 0x220c, 3 },
2249 [ADM0_C0_RESET] = { 0x220c, 2 },
2250 [ADM0_PBUS_RESET] = { 0x220c, 1 },
2251 [ADM0_RESET] = { 0x220c, 0 },
2252 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
2253 [QDSS_POR_RESET] = { 0x2260, 4 },
2254 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
2255 [QDSS_HRESET_RESET] = { 0x2260, 2 },
2256 [QDSS_AXI_RESET] = { 0x2260, 1 },
2257 [QDSS_DBG_RESET] = { 0x2260, 0 },
2258 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
2259 [SFAB_PCIE_S_RESET] = { 0x22d8, 0 },
2260 [PCIE_EXT_RESET] = { 0x22dc, 6 },
2261 [PCIE_PHY_RESET] = { 0x22dc, 5 },
2262 [PCIE_PCI_RESET] = { 0x22dc, 4 },
2263 [PCIE_POR_RESET] = { 0x22dc, 3 },
2264 [PCIE_HCLK_RESET] = { 0x22dc, 2 },
2265 [PCIE_ACLK_RESET] = { 0x22dc, 0 },
2266 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
2267 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
2268 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
2269 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
2270 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
2271 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
2272 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
2273 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
2274 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
2275 [DFAB_ARB0_RESET] = { 0x2560, 7 },
2276 [DFAB_ARB1_RESET] = { 0x2564, 7 },
2277 [PPSS_PROC_RESET] = { 0x2594, 1 },
2278 [PPSS_RESET] = { 0x2594, 0 },
2279 [DMA_BAM_RESET] = { 0x25c0, 7 },
2280 [SPS_TIC_H_RESET] = { 0x2600, 7 },
2281 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2282 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
2283 [TSIF_H_RESET] = { 0x2700, 7 },
2284 [CE1_H_RESET] = { 0x2720, 7 },
2285 [CE1_CORE_RESET] = { 0x2724, 7 },
2286 [CE1_SLEEP_RESET] = { 0x2728, 7 },
2287 [CE2_H_RESET] = { 0x2740, 7 },
2288 [CE2_CORE_RESET] = { 0x2744, 7 },
2289 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2290 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2291 [RPM_PROC_RESET] = { 0x27c0, 7 },
2292 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
2293 [SDC1_RESET] = { 0x2830, 0 },
2294 [SDC2_RESET] = { 0x2850, 0 },
2295 [SDC3_RESET] = { 0x2870, 0 },
2296 [SDC4_RESET] = { 0x2890, 0 },
2297 [USB_HS1_RESET] = { 0x2910, 0 },
2298 [USB_HSIC_RESET] = { 0x2934, 0 },
2299 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
2300 [USB_FS1_RESET] = { 0x2974, 0 },
2301 [GSBI1_RESET] = { 0x29dc, 0 },
2302 [GSBI2_RESET] = { 0x29fc, 0 },
2303 [GSBI3_RESET] = { 0x2a1c, 0 },
2304 [GSBI4_RESET] = { 0x2a3c, 0 },
2305 [GSBI5_RESET] = { 0x2a5c, 0 },
2306 [GSBI6_RESET] = { 0x2a7c, 0 },
2307 [GSBI7_RESET] = { 0x2a9c, 0 },
2308 [SPDM_RESET] = { 0x2b6c, 0 },
2309 [SEC_CTRL_RESET] = { 0x2b80, 7 },
2310 [TLMM_H_RESET] = { 0x2ba0, 7 },
2311 [SFAB_SATA_M_RESET] = { 0x2c18, 0 },
2312 [SATA_RESET] = { 0x2c1c, 0 },
2313 [TSSC_RESET] = { 0x2ca0, 7 },
2314 [PDM_RESET] = { 0x2cc0, 12 },
2315 [MPM_H_RESET] = { 0x2da0, 7 },
2316 [MPM_RESET] = { 0x2da4, 0 },
2317 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
2318 [PRNG_RESET] = { 0x2e80, 12 },
2319 [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
2320 [SFAB_CE3_S_RESET] = { 0x36c8, 0 },
2321 [CE3_SLEEP_RESET] = { 0x36d0, 7 },
2322 [PCIE_1_M_RESET] = { 0x3a98, 1 },
2323 [PCIE_1_S_RESET] = { 0x3a98, 0 },
2324 [PCIE_1_EXT_RESET] = { 0x3a9c, 6 },
2325 [PCIE_1_PHY_RESET] = { 0x3a9c, 5 },
2326 [PCIE_1_PCI_RESET] = { 0x3a9c, 4 },
2327 [PCIE_1_POR_RESET] = { 0x3a9c, 3 },
2328 [PCIE_1_HCLK_RESET] = { 0x3a9c, 2 },
2329 [PCIE_1_ACLK_RESET] = { 0x3a9c, 0 },
2330 [PCIE_2_M_RESET] = { 0x3ad8, 1 },
2331 [PCIE_2_S_RESET] = { 0x3ad8, 0 },
2332 [PCIE_2_EXT_RESET] = { 0x3adc, 6 },
2333 [PCIE_2_PHY_RESET] = { 0x3adc, 5 },
2334 [PCIE_2_PCI_RESET] = { 0x3adc, 4 },
2335 [PCIE_2_POR_RESET] = { 0x3adc, 3 },
2336 [PCIE_2_HCLK_RESET] = { 0x3adc, 2 },
2337 [PCIE_2_ACLK_RESET] = { 0x3adc, 0 },
2338 [SFAB_USB30_S_RESET] = { 0x3b54, 1 },
2339 [SFAB_USB30_M_RESET] = { 0x3b54, 0 },
2340 [USB30_0_PORT2_HS_PHY_RESET] = { 0x3b50, 5 },
2341 [USB30_0_MASTER_RESET] = { 0x3b50, 4 },
2342 [USB30_0_SLEEP_RESET] = { 0x3b50, 3 },
2343 [USB30_0_UTMI_PHY_RESET] = { 0x3b50, 2 },
2344 [USB30_0_POWERON_RESET] = { 0x3b50, 1 },
2345 [USB30_0_PHY_RESET] = { 0x3b50, 0 },
2346 [USB30_1_MASTER_RESET] = { 0x3b58, 4 },
2347 [USB30_1_SLEEP_RESET] = { 0x3b58, 3 },
2348 [USB30_1_UTMI_PHY_RESET] = { 0x3b58, 2 },
2349 [USB30_1_POWERON_RESET] = { 0x3b58, 1 },
2350 [USB30_1_PHY_RESET] = { 0x3b58, 0 },
2351 [NSSFB0_RESET] = { 0x3b60, 6 },
2352 [NSSFB1_RESET] = { 0x3b60, 7 },
2353};
2354
2355static const struct regmap_config gcc_ipq806x_regmap_config = {
2356 .reg_bits = 32,
2357 .reg_stride = 4,
2358 .val_bits = 32,
2359 .max_register = 0x3e40,
2360 .fast_io = true,
2361};
2362
2363static const struct qcom_cc_desc gcc_ipq806x_desc = {
2364 .config = &gcc_ipq806x_regmap_config,
2365 .clks = gcc_ipq806x_clks,
2366 .num_clks = ARRAY_SIZE(gcc_ipq806x_clks),
2367 .resets = gcc_ipq806x_resets,
2368 .num_resets = ARRAY_SIZE(gcc_ipq806x_resets),
2369};
2370
2371static const struct of_device_id gcc_ipq806x_match_table[] = {
2372 { .compatible = "qcom,gcc-ipq8064" },
2373 { }
2374};
2375MODULE_DEVICE_TABLE(of, gcc_ipq806x_match_table);
2376
2377static int gcc_ipq806x_probe(struct platform_device *pdev)
2378{
2379 struct clk *clk;
2380 struct device *dev = &pdev->dev;
2381
2382 /* Temporary until RPM clocks supported */
2383 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 25000000);
2384 if (IS_ERR(clk))
2385 return PTR_ERR(clk);
2386
2387 clk = clk_register_fixed_rate(dev, "pxo", NULL, CLK_IS_ROOT, 25000000);
2388 if (IS_ERR(clk))
2389 return PTR_ERR(clk);
2390
2391 return qcom_cc_probe(pdev, &gcc_ipq806x_desc);
2392}
2393
2394static int gcc_ipq806x_remove(struct platform_device *pdev)
2395{
2396 qcom_cc_remove(pdev);
2397 return 0;
2398}
2399
2400static struct platform_driver gcc_ipq806x_driver = {
2401 .probe = gcc_ipq806x_probe,
2402 .remove = gcc_ipq806x_remove,
2403 .driver = {
2404 .name = "gcc-ipq806x",
2405 .owner = THIS_MODULE,
2406 .of_match_table = gcc_ipq806x_match_table,
2407 },
2408};
2409
2410static int __init gcc_ipq806x_init(void)
2411{
2412 return platform_driver_register(&gcc_ipq806x_driver);
2413}
2414core_initcall(gcc_ipq806x_init);
2415
2416static void __exit gcc_ipq806x_exit(void)
2417{
2418 platform_driver_unregister(&gcc_ipq806x_driver);
2419}
2420module_exit(gcc_ipq806x_exit);
2421
2422MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver");
2423MODULE_LICENSE("GPL v2");
2424MODULE_ALIAS("platform:gcc-ipq806x");
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index f4ffd91901f8..007534f7a2d7 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -104,6 +104,7 @@ static struct clk_regmap pll14_vote = {
104 104
105#define P_PXO 0 105#define P_PXO 0
106#define P_PLL8 1 106#define P_PLL8 1
107#define P_PLL3 2
107#define P_CXO 2 108#define P_CXO 2
108 109
109static const u8 gcc_pxo_pll8_map[] = { 110static const u8 gcc_pxo_pll8_map[] = {
@@ -128,6 +129,18 @@ static const char *gcc_pxo_pll8_cxo[] = {
128 "cxo", 129 "cxo",
129}; 130};
130 131
132static const u8 gcc_pxo_pll8_pll3_map[] = {
133 [P_PXO] = 0,
134 [P_PLL8] = 3,
135 [P_PLL3] = 6,
136};
137
138static const char *gcc_pxo_pll8_pll3[] = {
139 "pxo",
140 "pll8_vote",
141 "pll3",
142};
143
131static struct freq_tbl clk_tbl_gsbi_uart[] = { 144static struct freq_tbl clk_tbl_gsbi_uart[] = {
132 { 1843200, P_PLL8, 2, 6, 625 }, 145 { 1843200, P_PLL8, 2, 6, 625 },
133 { 3686400, P_PLL8, 2, 12, 625 }, 146 { 3686400, P_PLL8, 2, 12, 625 },
@@ -1928,6 +1941,104 @@ static struct clk_branch usb_hs1_xcvr_clk = {
1928 }, 1941 },
1929}; 1942};
1930 1943
1944static struct clk_rcg usb_hs3_xcvr_src = {
1945 .ns_reg = 0x370c,
1946 .md_reg = 0x3708,
1947 .mn = {
1948 .mnctr_en_bit = 8,
1949 .mnctr_reset_bit = 7,
1950 .mnctr_mode_shift = 5,
1951 .n_val_shift = 16,
1952 .m_val_shift = 16,
1953 .width = 8,
1954 },
1955 .p = {
1956 .pre_div_shift = 3,
1957 .pre_div_width = 2,
1958 },
1959 .s = {
1960 .src_sel_shift = 0,
1961 .parent_map = gcc_pxo_pll8_map,
1962 },
1963 .freq_tbl = clk_tbl_usb,
1964 .clkr = {
1965 .enable_reg = 0x370c,
1966 .enable_mask = BIT(11),
1967 .hw.init = &(struct clk_init_data){
1968 .name = "usb_hs3_xcvr_src",
1969 .parent_names = gcc_pxo_pll8,
1970 .num_parents = 2,
1971 .ops = &clk_rcg_ops,
1972 .flags = CLK_SET_RATE_GATE,
1973 },
1974 }
1975};
1976
1977static struct clk_branch usb_hs3_xcvr_clk = {
1978 .halt_reg = 0x2fc8,
1979 .halt_bit = 30,
1980 .clkr = {
1981 .enable_reg = 0x370c,
1982 .enable_mask = BIT(9),
1983 .hw.init = &(struct clk_init_data){
1984 .name = "usb_hs3_xcvr_clk",
1985 .parent_names = (const char *[]){ "usb_hs3_xcvr_src" },
1986 .num_parents = 1,
1987 .ops = &clk_branch_ops,
1988 .flags = CLK_SET_RATE_PARENT,
1989 },
1990 },
1991};
1992
1993static struct clk_rcg usb_hs4_xcvr_src = {
1994 .ns_reg = 0x372c,
1995 .md_reg = 0x3728,
1996 .mn = {
1997 .mnctr_en_bit = 8,
1998 .mnctr_reset_bit = 7,
1999 .mnctr_mode_shift = 5,
2000 .n_val_shift = 16,
2001 .m_val_shift = 16,
2002 .width = 8,
2003 },
2004 .p = {
2005 .pre_div_shift = 3,
2006 .pre_div_width = 2,
2007 },
2008 .s = {
2009 .src_sel_shift = 0,
2010 .parent_map = gcc_pxo_pll8_map,
2011 },
2012 .freq_tbl = clk_tbl_usb,
2013 .clkr = {
2014 .enable_reg = 0x372c,
2015 .enable_mask = BIT(11),
2016 .hw.init = &(struct clk_init_data){
2017 .name = "usb_hs4_xcvr_src",
2018 .parent_names = gcc_pxo_pll8,
2019 .num_parents = 2,
2020 .ops = &clk_rcg_ops,
2021 .flags = CLK_SET_RATE_GATE,
2022 },
2023 }
2024};
2025
2026static struct clk_branch usb_hs4_xcvr_clk = {
2027 .halt_reg = 0x2fc8,
2028 .halt_bit = 2,
2029 .clkr = {
2030 .enable_reg = 0x372c,
2031 .enable_mask = BIT(9),
2032 .hw.init = &(struct clk_init_data){
2033 .name = "usb_hs4_xcvr_clk",
2034 .parent_names = (const char *[]){ "usb_hs4_xcvr_src" },
2035 .num_parents = 1,
2036 .ops = &clk_branch_ops,
2037 .flags = CLK_SET_RATE_PARENT,
2038 },
2039 },
2040};
2041
1931static struct clk_rcg usb_hsic_xcvr_fs_src = { 2042static struct clk_rcg usb_hsic_xcvr_fs_src = {
1932 .ns_reg = 0x2928, 2043 .ns_reg = 0x2928,
1933 .md_reg = 0x2924, 2044 .md_reg = 0x2924,
@@ -2456,6 +2567,34 @@ static struct clk_branch usb_hs1_h_clk = {
2456 }, 2567 },
2457}; 2568};
2458 2569
2570static struct clk_branch usb_hs3_h_clk = {
2571 .halt_reg = 0x2fc8,
2572 .halt_bit = 31,
2573 .clkr = {
2574 .enable_reg = 0x3700,
2575 .enable_mask = BIT(4),
2576 .hw.init = &(struct clk_init_data){
2577 .name = "usb_hs3_h_clk",
2578 .ops = &clk_branch_ops,
2579 .flags = CLK_IS_ROOT,
2580 },
2581 },
2582};
2583
2584static struct clk_branch usb_hs4_h_clk = {
2585 .halt_reg = 0x2fc8,
2586 .halt_bit = 7,
2587 .clkr = {
2588 .enable_reg = 0x3720,
2589 .enable_mask = BIT(4),
2590 .hw.init = &(struct clk_init_data){
2591 .name = "usb_hs4_h_clk",
2592 .ops = &clk_branch_ops,
2593 .flags = CLK_IS_ROOT,
2594 },
2595 },
2596};
2597
2459static struct clk_branch usb_hsic_h_clk = { 2598static struct clk_branch usb_hsic_h_clk = {
2460 .halt_reg = 0x2fcc, 2599 .halt_reg = 0x2fcc,
2461 .halt_bit = 28, 2600 .halt_bit = 28,
@@ -2582,6 +2721,244 @@ static struct clk_branch adm0_pbus_clk = {
2582 }, 2721 },
2583}; 2722};
2584 2723
2724static struct freq_tbl clk_tbl_ce3[] = {
2725 { 48000000, P_PLL8, 8 },
2726 { 100000000, P_PLL3, 12 },
2727 { 120000000, P_PLL3, 10 },
2728 { }
2729};
2730
2731static struct clk_rcg ce3_src = {
2732 .ns_reg = 0x36c0,
2733 .p = {
2734 .pre_div_shift = 3,
2735 .pre_div_width = 4,
2736 },
2737 .s = {
2738 .src_sel_shift = 0,
2739 .parent_map = gcc_pxo_pll8_pll3_map,
2740 },
2741 .freq_tbl = clk_tbl_ce3,
2742 .clkr = {
2743 .enable_reg = 0x2c08,
2744 .enable_mask = BIT(7),
2745 .hw.init = &(struct clk_init_data){
2746 .name = "ce3_src",
2747 .parent_names = gcc_pxo_pll8_pll3,
2748 .num_parents = 3,
2749 .ops = &clk_rcg_ops,
2750 .flags = CLK_SET_RATE_GATE,
2751 },
2752 },
2753};
2754
2755static struct clk_branch ce3_core_clk = {
2756 .halt_reg = 0x2fdc,
2757 .halt_bit = 5,
2758 .clkr = {
2759 .enable_reg = 0x36c4,
2760 .enable_mask = BIT(4),
2761 .hw.init = &(struct clk_init_data){
2762 .name = "ce3_core_clk",
2763 .parent_names = (const char *[]){ "ce3_src" },
2764 .num_parents = 1,
2765 .ops = &clk_branch_ops,
2766 .flags = CLK_SET_RATE_PARENT,
2767 },
2768 },
2769};
2770
2771static struct clk_branch ce3_h_clk = {
2772 .halt_reg = 0x2fc4,
2773 .halt_bit = 16,
2774 .clkr = {
2775 .enable_reg = 0x36c4,
2776 .enable_mask = BIT(4),
2777 .hw.init = &(struct clk_init_data){
2778 .name = "ce3_h_clk",
2779 .parent_names = (const char *[]){ "ce3_src" },
2780 .num_parents = 1,
2781 .ops = &clk_branch_ops,
2782 .flags = CLK_SET_RATE_PARENT,
2783 },
2784 },
2785};
2786
2787static const struct freq_tbl clk_tbl_sata_ref[] = {
2788 { 48000000, P_PLL8, 8, 0, 0 },
2789 { 100000000, P_PLL3, 12, 0, 0 },
2790 { }
2791};
2792
2793static struct clk_rcg sata_clk_src = {
2794 .ns_reg = 0x2c08,
2795 .p = {
2796 .pre_div_shift = 3,
2797 .pre_div_width = 4,
2798 },
2799 .s = {
2800 .src_sel_shift = 0,
2801 .parent_map = gcc_pxo_pll8_pll3_map,
2802 },
2803 .freq_tbl = clk_tbl_sata_ref,
2804 .clkr = {
2805 .enable_reg = 0x2c08,
2806 .enable_mask = BIT(7),
2807 .hw.init = &(struct clk_init_data){
2808 .name = "sata_clk_src",
2809 .parent_names = gcc_pxo_pll8_pll3,
2810 .num_parents = 3,
2811 .ops = &clk_rcg_ops,
2812 .flags = CLK_SET_RATE_GATE,
2813 },
2814 },
2815};
2816
2817static struct clk_branch sata_rxoob_clk = {
2818 .halt_reg = 0x2fdc,
2819 .halt_bit = 26,
2820 .clkr = {
2821 .enable_reg = 0x2c0c,
2822 .enable_mask = BIT(4),
2823 .hw.init = &(struct clk_init_data){
2824 .name = "sata_rxoob_clk",
2825 .parent_names = (const char *[]){ "sata_clk_src" },
2826 .num_parents = 1,
2827 .ops = &clk_branch_ops,
2828 .flags = CLK_SET_RATE_PARENT,
2829 },
2830 },
2831};
2832
2833static struct clk_branch sata_pmalive_clk = {
2834 .halt_reg = 0x2fdc,
2835 .halt_bit = 25,
2836 .clkr = {
2837 .enable_reg = 0x2c10,
2838 .enable_mask = BIT(4),
2839 .hw.init = &(struct clk_init_data){
2840 .name = "sata_pmalive_clk",
2841 .parent_names = (const char *[]){ "sata_clk_src" },
2842 .num_parents = 1,
2843 .ops = &clk_branch_ops,
2844 .flags = CLK_SET_RATE_PARENT,
2845 },
2846 },
2847};
2848
2849static struct clk_branch sata_phy_ref_clk = {
2850 .halt_reg = 0x2fdc,
2851 .halt_bit = 24,
2852 .clkr = {
2853 .enable_reg = 0x2c14,
2854 .enable_mask = BIT(4),
2855 .hw.init = &(struct clk_init_data){
2856 .name = "sata_phy_ref_clk",
2857 .parent_names = (const char *[]){ "pxo" },
2858 .num_parents = 1,
2859 .ops = &clk_branch_ops,
2860 },
2861 },
2862};
2863
2864static struct clk_branch sata_a_clk = {
2865 .halt_reg = 0x2fc0,
2866 .halt_bit = 12,
2867 .clkr = {
2868 .enable_reg = 0x2c20,
2869 .enable_mask = BIT(4),
2870 .hw.init = &(struct clk_init_data){
2871 .name = "sata_a_clk",
2872 .ops = &clk_branch_ops,
2873 .flags = CLK_IS_ROOT,
2874 },
2875 },
2876};
2877
2878static struct clk_branch sata_h_clk = {
2879 .halt_reg = 0x2fdc,
2880 .halt_bit = 27,
2881 .clkr = {
2882 .enable_reg = 0x2c00,
2883 .enable_mask = BIT(4),
2884 .hw.init = &(struct clk_init_data){
2885 .name = "sata_h_clk",
2886 .ops = &clk_branch_ops,
2887 .flags = CLK_IS_ROOT,
2888 },
2889 },
2890};
2891
2892static struct clk_branch sfab_sata_s_h_clk = {
2893 .halt_reg = 0x2fc4,
2894 .halt_bit = 14,
2895 .clkr = {
2896 .enable_reg = 0x2480,
2897 .enable_mask = BIT(4),
2898 .hw.init = &(struct clk_init_data){
2899 .name = "sfab_sata_s_h_clk",
2900 .ops = &clk_branch_ops,
2901 .flags = CLK_IS_ROOT,
2902 },
2903 },
2904};
2905
2906static struct clk_branch sata_phy_cfg_clk = {
2907 .halt_reg = 0x2fcc,
2908 .halt_bit = 12,
2909 .clkr = {
2910 .enable_reg = 0x2c40,
2911 .enable_mask = BIT(4),
2912 .hw.init = &(struct clk_init_data){
2913 .name = "sata_phy_cfg_clk",
2914 .ops = &clk_branch_ops,
2915 .flags = CLK_IS_ROOT,
2916 },
2917 },
2918};
2919
2920static struct clk_branch pcie_phy_ref_clk = {
2921 .halt_reg = 0x2fdc,
2922 .halt_bit = 29,
2923 .clkr = {
2924 .enable_reg = 0x22d0,
2925 .enable_mask = BIT(4),
2926 .hw.init = &(struct clk_init_data){
2927 .name = "pcie_phy_ref_clk",
2928 .ops = &clk_branch_ops,
2929 .flags = CLK_IS_ROOT,
2930 },
2931 },
2932};
2933
2934static struct clk_branch pcie_h_clk = {
2935 .halt_reg = 0x2fd4,
2936 .halt_bit = 8,
2937 .clkr = {
2938 .enable_reg = 0x22cc,
2939 .enable_mask = BIT(4),
2940 .hw.init = &(struct clk_init_data){
2941 .name = "pcie_h_clk",
2942 .ops = &clk_branch_ops,
2943 .flags = CLK_IS_ROOT,
2944 },
2945 },
2946};
2947
2948static struct clk_branch pcie_a_clk = {
2949 .halt_reg = 0x2fc0,
2950 .halt_bit = 13,
2951 .clkr = {
2952 .enable_reg = 0x22c0,
2953 .enable_mask = BIT(4),
2954 .hw.init = &(struct clk_init_data){
2955 .name = "pcie_a_clk",
2956 .ops = &clk_branch_ops,
2957 .flags = CLK_IS_ROOT,
2958 },
2959 },
2960};
2961
2585static struct clk_branch pmic_arb0_h_clk = { 2962static struct clk_branch pmic_arb0_h_clk = {
2586 .halt_reg = 0x2fd8, 2963 .halt_reg = 0x2fd8,
2587 .halt_check = BRANCH_HALT_VOTED, 2964 .halt_check = BRANCH_HALT_VOTED,
@@ -2869,13 +3246,205 @@ static const struct qcom_reset_map gcc_msm8960_resets[] = {
2869}; 3246};
2870 3247
2871static struct clk_regmap *gcc_apq8064_clks[] = { 3248static struct clk_regmap *gcc_apq8064_clks[] = {
3249 [PLL3] = &pll3.clkr,
2872 [PLL8] = &pll8.clkr, 3250 [PLL8] = &pll8.clkr,
2873 [PLL8_VOTE] = &pll8_vote, 3251 [PLL8_VOTE] = &pll8_vote,
3252 [PLL14] = &pll14.clkr,
3253 [PLL14_VOTE] = &pll14_vote,
3254 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3255 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3256 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3257 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3258 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3259 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3260 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3261 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3262 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3263 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3264 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3265 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2874 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr, 3266 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2875 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr, 3267 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3268 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3269 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3270 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3271 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3272 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3273 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3274 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3275 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3276 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3277 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3278 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3279 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2876 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr, 3280 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2877 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr, 3281 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3282 [GP0_SRC] = &gp0_src.clkr,
3283 [GP0_CLK] = &gp0_clk.clkr,
3284 [GP1_SRC] = &gp1_src.clkr,
3285 [GP1_CLK] = &gp1_clk.clkr,
3286 [GP2_SRC] = &gp2_src.clkr,
3287 [GP2_CLK] = &gp2_clk.clkr,
3288 [PMEM_A_CLK] = &pmem_clk.clkr,
3289 [PRNG_SRC] = &prng_src.clkr,
3290 [PRNG_CLK] = &prng_clk.clkr,
3291 [SDC1_SRC] = &sdc1_src.clkr,
3292 [SDC1_CLK] = &sdc1_clk.clkr,
3293 [SDC2_SRC] = &sdc2_src.clkr,
3294 [SDC2_CLK] = &sdc2_clk.clkr,
3295 [SDC3_SRC] = &sdc3_src.clkr,
3296 [SDC3_CLK] = &sdc3_clk.clkr,
3297 [SDC4_SRC] = &sdc4_src.clkr,
3298 [SDC4_CLK] = &sdc4_clk.clkr,
3299 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3300 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3301 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3302 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3303 [USB_HS3_XCVR_SRC] = &usb_hs3_xcvr_src.clkr,
3304 [USB_HS3_XCVR_CLK] = &usb_hs3_xcvr_clk.clkr,
3305 [USB_HS4_XCVR_SRC] = &usb_hs4_xcvr_src.clkr,
3306 [USB_HS4_XCVR_CLK] = &usb_hs4_xcvr_clk.clkr,
3307 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3308 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3309 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3310 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3311 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3312 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3313 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3314 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3315 [SATA_H_CLK] = &sata_h_clk.clkr,
3316 [SATA_CLK_SRC] = &sata_clk_src.clkr,
3317 [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
3318 [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
3319 [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
3320 [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
3321 [SATA_A_CLK] = &sata_a_clk.clkr,
3322 [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
3323 [CE3_SRC] = &ce3_src.clkr,
3324 [CE3_CORE_CLK] = &ce3_core_clk.clkr,
3325 [CE3_H_CLK] = &ce3_h_clk.clkr,
3326 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3327 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3328 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3329 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3330 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3331 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3332 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2878 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr, 3333 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3334 [TSIF_H_CLK] = &tsif_h_clk.clkr,
3335 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3336 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3337 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3338 [USB_HS3_H_CLK] = &usb_hs3_h_clk.clkr,
3339 [USB_HS4_H_CLK] = &usb_hs4_h_clk.clkr,
3340 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3341 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3342 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3343 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3344 [ADM0_CLK] = &adm0_clk.clkr,
3345 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3346 [PCIE_A_CLK] = &pcie_a_clk.clkr,
3347 [PCIE_PHY_REF_CLK] = &pcie_phy_ref_clk.clkr,
3348 [PCIE_H_CLK] = &pcie_h_clk.clkr,
3349 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3350 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3351 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3352 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3353};
3354
3355static const struct qcom_reset_map gcc_apq8064_resets[] = {
3356 [QDSS_STM_RESET] = { 0x2060, 6 },
3357 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3358 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3359 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3360 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3361 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3362 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3363 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3364 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3365 [ADM0_C2_RESET] = { 0x220c, 4},
3366 [ADM0_C1_RESET] = { 0x220c, 3},
3367 [ADM0_C0_RESET] = { 0x220c, 2},
3368 [ADM0_PBUS_RESET] = { 0x220c, 1 },
3369 [ADM0_RESET] = { 0x220c },
3370 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3371 [QDSS_POR_RESET] = { 0x2260, 4 },
3372 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3373 [QDSS_HRESET_RESET] = { 0x2260, 2 },
3374 [QDSS_AXI_RESET] = { 0x2260, 1 },
3375 [QDSS_DBG_RESET] = { 0x2260 },
3376 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
3377 [SFAB_PCIE_S_RESET] = { 0x22d8 },
3378 [PCIE_EXT_PCI_RESET] = { 0x22dc, 6 },
3379 [PCIE_PHY_RESET] = { 0x22dc, 5 },
3380 [PCIE_PCI_RESET] = { 0x22dc, 4 },
3381 [PCIE_POR_RESET] = { 0x22dc, 3 },
3382 [PCIE_HCLK_RESET] = { 0x22dc, 2 },
3383 [PCIE_ACLK_RESET] = { 0x22dc },
3384 [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3385 [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3386 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3387 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3388 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3389 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3390 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3391 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3392 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3393 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3394 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3395 [DFAB_ARB0_RESET] = { 0x2560, 7 },
3396 [DFAB_ARB1_RESET] = { 0x2564, 7 },
3397 [PPSS_PROC_RESET] = { 0x2594, 1 },
3398 [PPSS_RESET] = { 0x2594},
3399 [DMA_BAM_RESET] = { 0x25c0, 7 },
3400 [SPS_TIC_H_RESET] = { 0x2600, 7 },
3401 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3402 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3403 [TSIF_H_RESET] = { 0x2700, 7 },
3404 [CE1_H_RESET] = { 0x2720, 7 },
3405 [CE1_CORE_RESET] = { 0x2724, 7 },
3406 [CE1_SLEEP_RESET] = { 0x2728, 7 },
3407 [CE2_H_RESET] = { 0x2740, 7 },
3408 [CE2_CORE_RESET] = { 0x2744, 7 },
3409 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3410 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3411 [RPM_PROC_RESET] = { 0x27c0, 7 },
3412 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3413 [SDC1_RESET] = { 0x2830 },
3414 [SDC2_RESET] = { 0x2850 },
3415 [SDC3_RESET] = { 0x2870 },
3416 [SDC4_RESET] = { 0x2890 },
3417 [USB_HS1_RESET] = { 0x2910 },
3418 [USB_HSIC_RESET] = { 0x2934 },
3419 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3420 [USB_FS1_RESET] = { 0x2974 },
3421 [GSBI1_RESET] = { 0x29dc },
3422 [GSBI2_RESET] = { 0x29fc },
3423 [GSBI3_RESET] = { 0x2a1c },
3424 [GSBI4_RESET] = { 0x2a3c },
3425 [GSBI5_RESET] = { 0x2a5c },
3426 [GSBI6_RESET] = { 0x2a7c },
3427 [GSBI7_RESET] = { 0x2a9c },
3428 [SPDM_RESET] = { 0x2b6c },
3429 [TLMM_H_RESET] = { 0x2ba0, 7 },
3430 [SATA_SFAB_M_RESET] = { 0x2c18 },
3431 [SATA_RESET] = { 0x2c1c },
3432 [GSS_SLP_RESET] = { 0x2c60, 7 },
3433 [GSS_RESET] = { 0x2c64 },
3434 [TSSC_RESET] = { 0x2ca0, 7 },
3435 [PDM_RESET] = { 0x2cc0, 12 },
3436 [MPM_H_RESET] = { 0x2da0, 7 },
3437 [MPM_RESET] = { 0x2da4 },
3438 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3439 [PRNG_RESET] = { 0x2e80, 12 },
3440 [RIVA_RESET] = { 0x35e0 },
3441 [CE3_H_RESET] = { 0x36c4, 7 },
3442 [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
3443 [SFAB_CE3_S_RESET] = { 0x36c8 },
3444 [CE3_RESET] = { 0x36cc, 7 },
3445 [CE3_SLEEP_RESET] = { 0x36d0, 7 },
3446 [USB_HS3_RESET] = { 0x3710 },
3447 [USB_HS4_RESET] = { 0x3730 },
2879}; 3448};
2880 3449
2881static const struct regmap_config gcc_msm8960_regmap_config = { 3450static const struct regmap_config gcc_msm8960_regmap_config = {
@@ -2886,6 +3455,14 @@ static const struct regmap_config gcc_msm8960_regmap_config = {
2886 .fast_io = true, 3455 .fast_io = true,
2887}; 3456};
2888 3457
3458static const struct regmap_config gcc_apq8064_regmap_config = {
3459 .reg_bits = 32,
3460 .reg_stride = 4,
3461 .val_bits = 32,
3462 .max_register = 0x3880,
3463 .fast_io = true,
3464};
3465
2889static const struct qcom_cc_desc gcc_msm8960_desc = { 3466static const struct qcom_cc_desc gcc_msm8960_desc = {
2890 .config = &gcc_msm8960_regmap_config, 3467 .config = &gcc_msm8960_regmap_config,
2891 .clks = gcc_msm8960_clks, 3468 .clks = gcc_msm8960_clks,
@@ -2895,11 +3472,11 @@ static const struct qcom_cc_desc gcc_msm8960_desc = {
2895}; 3472};
2896 3473
2897static const struct qcom_cc_desc gcc_apq8064_desc = { 3474static const struct qcom_cc_desc gcc_apq8064_desc = {
2898 .config = &gcc_msm8960_regmap_config, 3475 .config = &gcc_apq8064_regmap_config,
2899 .clks = gcc_apq8064_clks, 3476 .clks = gcc_apq8064_clks,
2900 .num_clks = ARRAY_SIZE(gcc_apq8064_clks), 3477 .num_clks = ARRAY_SIZE(gcc_apq8064_clks),
2901 .resets = gcc_msm8960_resets, 3478 .resets = gcc_apq8064_resets,
2902 .num_resets = ARRAY_SIZE(gcc_msm8960_resets), 3479 .num_resets = ARRAY_SIZE(gcc_apq8064_resets),
2903}; 3480};
2904 3481
2905static const struct of_device_id gcc_msm8960_match_table[] = { 3482static const struct of_device_id gcc_msm8960_match_table[] = {
diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
new file mode 100644
index 000000000000..751eea376a2b
--- /dev/null
+++ b/drivers/clk/qcom/mmcc-apq8084.c
@@ -0,0 +1,3352 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/module.h>
17#include <linux/regmap.h>
18#include <linux/reset-controller.h>
19
20#include <dt-bindings/clock/qcom,mmcc-apq8084.h>
21#include <dt-bindings/reset/qcom,mmcc-apq8084.h>
22
23#include "common.h"
24#include "clk-regmap.h"
25#include "clk-pll.h"
26#include "clk-rcg.h"
27#include "clk-branch.h"
28#include "reset.h"
29
30#define P_XO 0
31#define P_MMPLL0 1
32#define P_EDPLINK 1
33#define P_MMPLL1 2
34#define P_HDMIPLL 2
35#define P_GPLL0 3
36#define P_EDPVCO 3
37#define P_MMPLL4 4
38#define P_DSI0PLL 4
39#define P_DSI0PLL_BYTE 4
40#define P_MMPLL2 4
41#define P_MMPLL3 4
42#define P_GPLL1 5
43#define P_DSI1PLL 5
44#define P_DSI1PLL_BYTE 5
45#define P_MMSLEEP 6
46
47static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
48 [P_XO] = 0,
49 [P_MMPLL0] = 1,
50 [P_MMPLL1] = 2,
51 [P_GPLL0] = 5,
52};
53
54static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
55 "xo",
56 "mmpll0_vote",
57 "mmpll1_vote",
58 "mmss_gpll0_vote",
59};
60
61static const u8 mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
62 [P_XO] = 0,
63 [P_MMPLL0] = 1,
64 [P_HDMIPLL] = 4,
65 [P_GPLL0] = 5,
66 [P_DSI0PLL] = 2,
67 [P_DSI1PLL] = 3,
68};
69
70static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
71 "xo",
72 "mmpll0_vote",
73 "hdmipll",
74 "mmss_gpll0_vote",
75 "dsi0pll",
76 "dsi1pll",
77};
78
79static const u8 mmcc_xo_mmpll0_1_2_gpll0_map[] = {
80 [P_XO] = 0,
81 [P_MMPLL0] = 1,
82 [P_MMPLL1] = 2,
83 [P_GPLL0] = 5,
84 [P_MMPLL2] = 3,
85};
86
87static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
88 "xo",
89 "mmpll0_vote",
90 "mmpll1_vote",
91 "mmss_gpll0_vote",
92 "mmpll2",
93};
94
95static const u8 mmcc_xo_mmpll0_1_3_gpll0_map[] = {
96 [P_XO] = 0,
97 [P_MMPLL0] = 1,
98 [P_MMPLL1] = 2,
99 [P_GPLL0] = 5,
100 [P_MMPLL3] = 3,
101};
102
103static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
104 "xo",
105 "mmpll0_vote",
106 "mmpll1_vote",
107 "mmss_gpll0_vote",
108 "mmpll3",
109};
110
111static const u8 mmcc_xo_dsi_hdmi_edp_map[] = {
112 [P_XO] = 0,
113 [P_EDPLINK] = 4,
114 [P_HDMIPLL] = 3,
115 [P_EDPVCO] = 5,
116 [P_DSI0PLL] = 1,
117 [P_DSI1PLL] = 2,
118};
119
120static const char *mmcc_xo_dsi_hdmi_edp[] = {
121 "xo",
122 "edp_link_clk",
123 "hdmipll",
124 "edp_vco_div",
125 "dsi0pll",
126 "dsi1pll",
127};
128
129static const u8 mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
130 [P_XO] = 0,
131 [P_EDPLINK] = 4,
132 [P_HDMIPLL] = 3,
133 [P_GPLL0] = 5,
134 [P_DSI0PLL] = 1,
135 [P_DSI1PLL] = 2,
136};
137
138static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
139 "xo",
140 "edp_link_clk",
141 "hdmipll",
142 "gpll0_vote",
143 "dsi0pll",
144 "dsi1pll",
145};
146
147static const u8 mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
148 [P_XO] = 0,
149 [P_EDPLINK] = 4,
150 [P_HDMIPLL] = 3,
151 [P_GPLL0] = 5,
152 [P_DSI0PLL_BYTE] = 1,
153 [P_DSI1PLL_BYTE] = 2,
154};
155
156static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
157 "xo",
158 "edp_link_clk",
159 "hdmipll",
160 "gpll0_vote",
161 "dsi0pllbyte",
162 "dsi1pllbyte",
163};
164
165static const u8 mmcc_xo_mmpll0_1_4_gpll0_map[] = {
166 [P_XO] = 0,
167 [P_MMPLL0] = 1,
168 [P_MMPLL1] = 2,
169 [P_GPLL0] = 5,
170 [P_MMPLL4] = 3,
171};
172
173static const char *mmcc_xo_mmpll0_1_4_gpll0[] = {
174 "xo",
175 "mmpll0",
176 "mmpll1",
177 "mmpll4",
178 "gpll0",
179};
180
181static const u8 mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
182 [P_XO] = 0,
183 [P_MMPLL0] = 1,
184 [P_MMPLL1] = 2,
185 [P_MMPLL4] = 3,
186 [P_GPLL0] = 5,
187 [P_GPLL1] = 4,
188};
189
190static const char *mmcc_xo_mmpll0_1_4_gpll1_0[] = {
191 "xo",
192 "mmpll0",
193 "mmpll1",
194 "mmpll4",
195 "gpll1",
196 "gpll0",
197};
198
199static const u8 mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
200 [P_XO] = 0,
201 [P_MMPLL0] = 1,
202 [P_MMPLL1] = 2,
203 [P_MMPLL4] = 3,
204 [P_GPLL0] = 5,
205 [P_GPLL1] = 4,
206 [P_MMSLEEP] = 6,
207};
208
209static const char *mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
210 "xo",
211 "mmpll0",
212 "mmpll1",
213 "mmpll4",
214 "gpll1",
215 "gpll0",
216 "sleep_clk_src",
217};
218
219#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
220
221static struct clk_pll mmpll0 = {
222 .l_reg = 0x0004,
223 .m_reg = 0x0008,
224 .n_reg = 0x000c,
225 .config_reg = 0x0014,
226 .mode_reg = 0x0000,
227 .status_reg = 0x001c,
228 .status_bit = 17,
229 .clkr.hw.init = &(struct clk_init_data){
230 .name = "mmpll0",
231 .parent_names = (const char *[]){ "xo" },
232 .num_parents = 1,
233 .ops = &clk_pll_ops,
234 },
235};
236
237static struct clk_regmap mmpll0_vote = {
238 .enable_reg = 0x0100,
239 .enable_mask = BIT(0),
240 .hw.init = &(struct clk_init_data){
241 .name = "mmpll0_vote",
242 .parent_names = (const char *[]){ "mmpll0" },
243 .num_parents = 1,
244 .ops = &clk_pll_vote_ops,
245 },
246};
247
248static struct clk_pll mmpll1 = {
249 .l_reg = 0x0044,
250 .m_reg = 0x0048,
251 .n_reg = 0x004c,
252 .config_reg = 0x0050,
253 .mode_reg = 0x0040,
254 .status_reg = 0x005c,
255 .status_bit = 17,
256 .clkr.hw.init = &(struct clk_init_data){
257 .name = "mmpll1",
258 .parent_names = (const char *[]){ "xo" },
259 .num_parents = 1,
260 .ops = &clk_pll_ops,
261 },
262};
263
264static struct clk_regmap mmpll1_vote = {
265 .enable_reg = 0x0100,
266 .enable_mask = BIT(1),
267 .hw.init = &(struct clk_init_data){
268 .name = "mmpll1_vote",
269 .parent_names = (const char *[]){ "mmpll1" },
270 .num_parents = 1,
271 .ops = &clk_pll_vote_ops,
272 },
273};
274
275static struct clk_pll mmpll2 = {
276 .l_reg = 0x4104,
277 .m_reg = 0x4108,
278 .n_reg = 0x410c,
279 .config_reg = 0x4110,
280 .mode_reg = 0x4100,
281 .status_reg = 0x411c,
282 .clkr.hw.init = &(struct clk_init_data){
283 .name = "mmpll2",
284 .parent_names = (const char *[]){ "xo" },
285 .num_parents = 1,
286 .ops = &clk_pll_ops,
287 },
288};
289
290static struct clk_pll mmpll3 = {
291 .l_reg = 0x0084,
292 .m_reg = 0x0088,
293 .n_reg = 0x008c,
294 .config_reg = 0x0090,
295 .mode_reg = 0x0080,
296 .status_reg = 0x009c,
297 .status_bit = 17,
298 .clkr.hw.init = &(struct clk_init_data){
299 .name = "mmpll3",
300 .parent_names = (const char *[]){ "xo" },
301 .num_parents = 1,
302 .ops = &clk_pll_ops,
303 },
304};
305
306static struct clk_pll mmpll4 = {
307 .l_reg = 0x00a4,
308 .m_reg = 0x00a8,
309 .n_reg = 0x00ac,
310 .config_reg = 0x00b0,
311 .mode_reg = 0x0080,
312 .status_reg = 0x00bc,
313 .clkr.hw.init = &(struct clk_init_data){
314 .name = "mmpll4",
315 .parent_names = (const char *[]){ "xo" },
316 .num_parents = 1,
317 .ops = &clk_pll_ops,
318 },
319};
320
321static struct clk_rcg2 mmss_ahb_clk_src = {
322 .cmd_rcgr = 0x5000,
323 .hid_width = 5,
324 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
325 .clkr.hw.init = &(struct clk_init_data){
326 .name = "mmss_ahb_clk_src",
327 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
328 .num_parents = 4,
329 .ops = &clk_rcg2_ops,
330 },
331};
332
333static struct freq_tbl ftbl_mmss_axi_clk[] = {
334 F(19200000, P_XO, 1, 0, 0),
335 F(37500000, P_GPLL0, 16, 0, 0),
336 F(50000000, P_GPLL0, 12, 0, 0),
337 F(75000000, P_GPLL0, 8, 0, 0),
338 F(100000000, P_GPLL0, 6, 0, 0),
339 F(150000000, P_GPLL0, 4, 0, 0),
340 F(333430000, P_MMPLL1, 3.5, 0, 0),
341 F(400000000, P_MMPLL0, 2, 0, 0),
342 F(466800000, P_MMPLL1, 2.5, 0, 0),
343};
344
345static struct clk_rcg2 mmss_axi_clk_src = {
346 .cmd_rcgr = 0x5040,
347 .hid_width = 5,
348 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
349 .freq_tbl = ftbl_mmss_axi_clk,
350 .clkr.hw.init = &(struct clk_init_data){
351 .name = "mmss_axi_clk_src",
352 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
353 .num_parents = 4,
354 .ops = &clk_rcg2_ops,
355 },
356};
357
358static struct freq_tbl ftbl_ocmemnoc_clk[] = {
359 F(19200000, P_XO, 1, 0, 0),
360 F(37500000, P_GPLL0, 16, 0, 0),
361 F(50000000, P_GPLL0, 12, 0, 0),
362 F(75000000, P_GPLL0, 8, 0, 0),
363 F(109090000, P_GPLL0, 5.5, 0, 0),
364 F(150000000, P_GPLL0, 4, 0, 0),
365 F(228570000, P_MMPLL0, 3.5, 0, 0),
366 F(320000000, P_MMPLL0, 2.5, 0, 0),
367};
368
369static struct clk_rcg2 ocmemnoc_clk_src = {
370 .cmd_rcgr = 0x5090,
371 .hid_width = 5,
372 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
373 .freq_tbl = ftbl_ocmemnoc_clk,
374 .clkr.hw.init = &(struct clk_init_data){
375 .name = "ocmemnoc_clk_src",
376 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
377 .num_parents = 4,
378 .ops = &clk_rcg2_ops,
379 },
380};
381
382static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
383 F(100000000, P_GPLL0, 6, 0, 0),
384 F(200000000, P_MMPLL0, 4, 0, 0),
385 { }
386};
387
388static struct clk_rcg2 csi0_clk_src = {
389 .cmd_rcgr = 0x3090,
390 .hid_width = 5,
391 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
392 .freq_tbl = ftbl_camss_csi0_3_clk,
393 .clkr.hw.init = &(struct clk_init_data){
394 .name = "csi0_clk_src",
395 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
396 .num_parents = 5,
397 .ops = &clk_rcg2_ops,
398 },
399};
400
401static struct clk_rcg2 csi1_clk_src = {
402 .cmd_rcgr = 0x3100,
403 .hid_width = 5,
404 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
405 .freq_tbl = ftbl_camss_csi0_3_clk,
406 .clkr.hw.init = &(struct clk_init_data){
407 .name = "csi1_clk_src",
408 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
409 .num_parents = 5,
410 .ops = &clk_rcg2_ops,
411 },
412};
413
414static struct clk_rcg2 csi2_clk_src = {
415 .cmd_rcgr = 0x3160,
416 .hid_width = 5,
417 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
418 .freq_tbl = ftbl_camss_csi0_3_clk,
419 .clkr.hw.init = &(struct clk_init_data){
420 .name = "csi2_clk_src",
421 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
422 .num_parents = 5,
423 .ops = &clk_rcg2_ops,
424 },
425};
426
427static struct clk_rcg2 csi3_clk_src = {
428 .cmd_rcgr = 0x31c0,
429 .hid_width = 5,
430 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
431 .freq_tbl = ftbl_camss_csi0_3_clk,
432 .clkr.hw.init = &(struct clk_init_data){
433 .name = "csi3_clk_src",
434 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
435 .num_parents = 5,
436 .ops = &clk_rcg2_ops,
437 },
438};
439
440static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
441 F(37500000, P_GPLL0, 16, 0, 0),
442 F(50000000, P_GPLL0, 12, 0, 0),
443 F(60000000, P_GPLL0, 10, 0, 0),
444 F(80000000, P_GPLL0, 7.5, 0, 0),
445 F(100000000, P_GPLL0, 6, 0, 0),
446 F(109090000, P_GPLL0, 5.5, 0, 0),
447 F(133330000, P_GPLL0, 4.5, 0, 0),
448 F(200000000, P_GPLL0, 3, 0, 0),
449 F(228570000, P_MMPLL0, 3.5, 0, 0),
450 F(266670000, P_MMPLL0, 3, 0, 0),
451 F(320000000, P_MMPLL0, 2.5, 0, 0),
452 F(465000000, P_MMPLL4, 2, 0, 0),
453 F(600000000, P_GPLL0, 1, 0, 0),
454 { }
455};
456
457static struct clk_rcg2 vfe0_clk_src = {
458 .cmd_rcgr = 0x3600,
459 .hid_width = 5,
460 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
461 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
462 .clkr.hw.init = &(struct clk_init_data){
463 .name = "vfe0_clk_src",
464 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
465 .num_parents = 5,
466 .ops = &clk_rcg2_ops,
467 },
468};
469
470static struct clk_rcg2 vfe1_clk_src = {
471 .cmd_rcgr = 0x3620,
472 .hid_width = 5,
473 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
474 .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
475 .clkr.hw.init = &(struct clk_init_data){
476 .name = "vfe1_clk_src",
477 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
478 .num_parents = 5,
479 .ops = &clk_rcg2_ops,
480 },
481};
482
483static struct freq_tbl ftbl_mdss_mdp_clk[] = {
484 F(37500000, P_GPLL0, 16, 0, 0),
485 F(60000000, P_GPLL0, 10, 0, 0),
486 F(75000000, P_GPLL0, 8, 0, 0),
487 F(85710000, P_GPLL0, 7, 0, 0),
488 F(100000000, P_GPLL0, 6, 0, 0),
489 F(150000000, P_GPLL0, 4, 0, 0),
490 F(160000000, P_MMPLL0, 5, 0, 0),
491 F(200000000, P_MMPLL0, 4, 0, 0),
492 F(228570000, P_MMPLL0, 3.5, 0, 0),
493 F(300000000, P_GPLL0, 2, 0, 0),
494 F(320000000, P_MMPLL0, 2.5, 0, 0),
495 { }
496};
497
498static struct clk_rcg2 mdp_clk_src = {
499 .cmd_rcgr = 0x2040,
500 .hid_width = 5,
501 .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
502 .freq_tbl = ftbl_mdss_mdp_clk,
503 .clkr.hw.init = &(struct clk_init_data){
504 .name = "mdp_clk_src",
505 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
506 .num_parents = 6,
507 .ops = &clk_rcg2_ops,
508 },
509};
510
511static struct clk_rcg2 gfx3d_clk_src = {
512 .cmd_rcgr = 0x4000,
513 .hid_width = 5,
514 .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
515 .clkr.hw.init = &(struct clk_init_data){
516 .name = "gfx3d_clk_src",
517 .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
518 .num_parents = 5,
519 .ops = &clk_rcg2_ops,
520 },
521};
522
523static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
524 F(75000000, P_GPLL0, 8, 0, 0),
525 F(133330000, P_GPLL0, 4.5, 0, 0),
526 F(200000000, P_GPLL0, 3, 0, 0),
527 F(228570000, P_MMPLL0, 3.5, 0, 0),
528 F(266670000, P_MMPLL0, 3, 0, 0),
529 F(320000000, P_MMPLL0, 2.5, 0, 0),
530 { }
531};
532
533static struct clk_rcg2 jpeg0_clk_src = {
534 .cmd_rcgr = 0x3500,
535 .hid_width = 5,
536 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
537 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
538 .clkr.hw.init = &(struct clk_init_data){
539 .name = "jpeg0_clk_src",
540 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
541 .num_parents = 5,
542 .ops = &clk_rcg2_ops,
543 },
544};
545
546static struct clk_rcg2 jpeg1_clk_src = {
547 .cmd_rcgr = 0x3520,
548 .hid_width = 5,
549 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
550 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
551 .clkr.hw.init = &(struct clk_init_data){
552 .name = "jpeg1_clk_src",
553 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
554 .num_parents = 5,
555 .ops = &clk_rcg2_ops,
556 },
557};
558
559static struct clk_rcg2 jpeg2_clk_src = {
560 .cmd_rcgr = 0x3540,
561 .hid_width = 5,
562 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
563 .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
564 .clkr.hw.init = &(struct clk_init_data){
565 .name = "jpeg2_clk_src",
566 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
567 .num_parents = 5,
568 .ops = &clk_rcg2_ops,
569 },
570};
571
572static struct freq_tbl pixel_freq_tbl[] = {
573 { .src = P_DSI0PLL },
574 { }
575};
576
577static struct clk_rcg2 pclk0_clk_src = {
578 .cmd_rcgr = 0x2000,
579 .mnd_width = 8,
580 .hid_width = 5,
581 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
582 .freq_tbl = pixel_freq_tbl,
583 .clkr.hw.init = &(struct clk_init_data){
584 .name = "pclk0_clk_src",
585 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
586 .num_parents = 6,
587 .ops = &clk_pixel_ops,
588 .flags = CLK_SET_RATE_PARENT,
589 },
590};
591
592static struct clk_rcg2 pclk1_clk_src = {
593 .cmd_rcgr = 0x2020,
594 .mnd_width = 8,
595 .hid_width = 5,
596 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
597 .freq_tbl = pixel_freq_tbl,
598 .clkr.hw.init = &(struct clk_init_data){
599 .name = "pclk1_clk_src",
600 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
601 .num_parents = 6,
602 .ops = &clk_pixel_ops,
603 .flags = CLK_SET_RATE_PARENT,
604 },
605};
606
607static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
608 F(50000000, P_GPLL0, 12, 0, 0),
609 F(100000000, P_GPLL0, 6, 0, 0),
610 F(133330000, P_GPLL0, 4.5, 0, 0),
611 F(200000000, P_MMPLL0, 4, 0, 0),
612 F(266670000, P_MMPLL0, 3, 0, 0),
613 F(465000000, P_MMPLL3, 2, 0, 0),
614 { }
615};
616
617static struct clk_rcg2 vcodec0_clk_src = {
618 .cmd_rcgr = 0x1000,
619 .mnd_width = 8,
620 .hid_width = 5,
621 .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
622 .freq_tbl = ftbl_venus0_vcodec0_clk,
623 .clkr.hw.init = &(struct clk_init_data){
624 .name = "vcodec0_clk_src",
625 .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
626 .num_parents = 5,
627 .ops = &clk_rcg2_ops,
628 },
629};
630
631static struct freq_tbl ftbl_avsync_vp_clk[] = {
632 F(150000000, P_GPLL0, 4, 0, 0),
633 F(320000000, P_MMPLL0, 2.5, 0, 0),
634 { }
635};
636
637static struct clk_rcg2 vp_clk_src = {
638 .cmd_rcgr = 0x2430,
639 .hid_width = 5,
640 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
641 .freq_tbl = ftbl_avsync_vp_clk,
642 .clkr.hw.init = &(struct clk_init_data){
643 .name = "vp_clk_src",
644 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
645 .num_parents = 4,
646 .ops = &clk_rcg2_ops,
647 },
648};
649
650static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
651 F(19200000, P_XO, 1, 0, 0),
652 { }
653};
654
655static struct clk_rcg2 cci_clk_src = {
656 .cmd_rcgr = 0x3300,
657 .mnd_width = 8,
658 .hid_width = 5,
659 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
660 .freq_tbl = ftbl_camss_cci_cci_clk,
661 .clkr.hw.init = &(struct clk_init_data){
662 .name = "cci_clk_src",
663 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
664 .num_parents = 6,
665 .ops = &clk_rcg2_ops,
666 },
667};
668
669static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
670 F(10000, P_XO, 16, 1, 120),
671 F(24000, P_XO, 16, 1, 50),
672 F(6000000, P_GPLL0, 10, 1, 10),
673 F(12000000, P_GPLL0, 10, 1, 5),
674 F(13000000, P_GPLL0, 4, 13, 150),
675 F(24000000, P_GPLL0, 5, 1, 5),
676 { }
677};
678
679static struct clk_rcg2 camss_gp0_clk_src = {
680 .cmd_rcgr = 0x3420,
681 .mnd_width = 8,
682 .hid_width = 5,
683 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
684 .freq_tbl = ftbl_camss_gp0_1_clk,
685 .clkr.hw.init = &(struct clk_init_data){
686 .name = "camss_gp0_clk_src",
687 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
688 .num_parents = 7,
689 .ops = &clk_rcg2_ops,
690 },
691};
692
693static struct clk_rcg2 camss_gp1_clk_src = {
694 .cmd_rcgr = 0x3450,
695 .mnd_width = 8,
696 .hid_width = 5,
697 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map,
698 .freq_tbl = ftbl_camss_gp0_1_clk,
699 .clkr.hw.init = &(struct clk_init_data){
700 .name = "camss_gp1_clk_src",
701 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
702 .num_parents = 7,
703 .ops = &clk_rcg2_ops,
704 },
705};
706
707static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
708 F(4800000, P_XO, 4, 0, 0),
709 F(6000000, P_GPLL0, 10, 1, 10),
710 F(8000000, P_GPLL0, 15, 1, 5),
711 F(9600000, P_XO, 2, 0, 0),
712 F(16000000, P_MMPLL0, 10, 1, 5),
713 F(19200000, P_XO, 1, 0, 0),
714 F(24000000, P_GPLL0, 5, 1, 5),
715 F(32000000, P_MMPLL0, 5, 1, 5),
716 F(48000000, P_GPLL0, 12.5, 0, 0),
717 F(64000000, P_MMPLL0, 12.5, 0, 0),
718 { }
719};
720
721static struct clk_rcg2 mclk0_clk_src = {
722 .cmd_rcgr = 0x3360,
723 .mnd_width = 8,
724 .hid_width = 5,
725 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
726 .freq_tbl = ftbl_camss_mclk0_3_clk,
727 .clkr.hw.init = &(struct clk_init_data){
728 .name = "mclk0_clk_src",
729 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
730 .num_parents = 6,
731 .ops = &clk_rcg2_ops,
732 },
733};
734
735static struct clk_rcg2 mclk1_clk_src = {
736 .cmd_rcgr = 0x3390,
737 .mnd_width = 8,
738 .hid_width = 5,
739 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
740 .freq_tbl = ftbl_camss_mclk0_3_clk,
741 .clkr.hw.init = &(struct clk_init_data){
742 .name = "mclk1_clk_src",
743 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
744 .num_parents = 6,
745 .ops = &clk_rcg2_ops,
746 },
747};
748
749static struct clk_rcg2 mclk2_clk_src = {
750 .cmd_rcgr = 0x33c0,
751 .mnd_width = 8,
752 .hid_width = 5,
753 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
754 .freq_tbl = ftbl_camss_mclk0_3_clk,
755 .clkr.hw.init = &(struct clk_init_data){
756 .name = "mclk2_clk_src",
757 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
758 .num_parents = 6,
759 .ops = &clk_rcg2_ops,
760 },
761};
762
763static struct clk_rcg2 mclk3_clk_src = {
764 .cmd_rcgr = 0x33f0,
765 .mnd_width = 8,
766 .hid_width = 5,
767 .parent_map = mmcc_xo_mmpll0_1_4_gpll1_0_map,
768 .freq_tbl = ftbl_camss_mclk0_3_clk,
769 .clkr.hw.init = &(struct clk_init_data){
770 .name = "mclk3_clk_src",
771 .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
772 .num_parents = 6,
773 .ops = &clk_rcg2_ops,
774 },
775};
776
777static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
778 F(100000000, P_GPLL0, 6, 0, 0),
779 F(200000000, P_MMPLL0, 4, 0, 0),
780 { }
781};
782
783static struct clk_rcg2 csi0phytimer_clk_src = {
784 .cmd_rcgr = 0x3000,
785 .hid_width = 5,
786 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
787 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
788 .clkr.hw.init = &(struct clk_init_data){
789 .name = "csi0phytimer_clk_src",
790 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
791 .num_parents = 5,
792 .ops = &clk_rcg2_ops,
793 },
794};
795
796static struct clk_rcg2 csi1phytimer_clk_src = {
797 .cmd_rcgr = 0x3030,
798 .hid_width = 5,
799 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
800 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
801 .clkr.hw.init = &(struct clk_init_data){
802 .name = "csi1phytimer_clk_src",
803 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
804 .num_parents = 5,
805 .ops = &clk_rcg2_ops,
806 },
807};
808
809static struct clk_rcg2 csi2phytimer_clk_src = {
810 .cmd_rcgr = 0x3060,
811 .hid_width = 5,
812 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
813 .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
814 .clkr.hw.init = &(struct clk_init_data){
815 .name = "csi2phytimer_clk_src",
816 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
817 .num_parents = 5,
818 .ops = &clk_rcg2_ops,
819 },
820};
821
822static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
823 F(133330000, P_GPLL0, 4.5, 0, 0),
824 F(266670000, P_MMPLL0, 3, 0, 0),
825 F(320000000, P_MMPLL0, 2.5, 0, 0),
826 F(372000000, P_MMPLL4, 2.5, 0, 0),
827 F(465000000, P_MMPLL4, 2, 0, 0),
828 F(600000000, P_GPLL0, 1, 0, 0),
829 { }
830};
831
832static struct clk_rcg2 cpp_clk_src = {
833 .cmd_rcgr = 0x3640,
834 .hid_width = 5,
835 .parent_map = mmcc_xo_mmpll0_1_4_gpll0_map,
836 .freq_tbl = ftbl_camss_vfe_cpp_clk,
837 .clkr.hw.init = &(struct clk_init_data){
838 .name = "cpp_clk_src",
839 .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
840 .num_parents = 5,
841 .ops = &clk_rcg2_ops,
842 },
843};
844
845static struct freq_tbl byte_freq_tbl[] = {
846 { .src = P_DSI0PLL_BYTE },
847 { }
848};
849
850static struct clk_rcg2 byte0_clk_src = {
851 .cmd_rcgr = 0x2120,
852 .hid_width = 5,
853 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
854 .freq_tbl = byte_freq_tbl,
855 .clkr.hw.init = &(struct clk_init_data){
856 .name = "byte0_clk_src",
857 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
858 .num_parents = 6,
859 .ops = &clk_byte_ops,
860 .flags = CLK_SET_RATE_PARENT,
861 },
862};
863
864static struct clk_rcg2 byte1_clk_src = {
865 .cmd_rcgr = 0x2140,
866 .hid_width = 5,
867 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
868 .freq_tbl = byte_freq_tbl,
869 .clkr.hw.init = &(struct clk_init_data){
870 .name = "byte1_clk_src",
871 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
872 .num_parents = 6,
873 .ops = &clk_byte_ops,
874 .flags = CLK_SET_RATE_PARENT,
875 },
876};
877
878static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
879 F(19200000, P_XO, 1, 0, 0),
880 { }
881};
882
883static struct clk_rcg2 edpaux_clk_src = {
884 .cmd_rcgr = 0x20e0,
885 .hid_width = 5,
886 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
887 .freq_tbl = ftbl_mdss_edpaux_clk,
888 .clkr.hw.init = &(struct clk_init_data){
889 .name = "edpaux_clk_src",
890 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
891 .num_parents = 4,
892 .ops = &clk_rcg2_ops,
893 },
894};
895
896static struct freq_tbl ftbl_mdss_edplink_clk[] = {
897 F(135000000, P_EDPLINK, 2, 0, 0),
898 F(270000000, P_EDPLINK, 11, 0, 0),
899 { }
900};
901
902static struct clk_rcg2 edplink_clk_src = {
903 .cmd_rcgr = 0x20c0,
904 .hid_width = 5,
905 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
906 .freq_tbl = ftbl_mdss_edplink_clk,
907 .clkr.hw.init = &(struct clk_init_data){
908 .name = "edplink_clk_src",
909 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
910 .num_parents = 6,
911 .ops = &clk_rcg2_ops,
912 .flags = CLK_SET_RATE_PARENT,
913 },
914};
915
916static struct freq_tbl edp_pixel_freq_tbl[] = {
917 { .src = P_EDPVCO },
918 { }
919};
920
921static struct clk_rcg2 edppixel_clk_src = {
922 .cmd_rcgr = 0x20a0,
923 .mnd_width = 8,
924 .hid_width = 5,
925 .parent_map = mmcc_xo_dsi_hdmi_edp_map,
926 .freq_tbl = edp_pixel_freq_tbl,
927 .clkr.hw.init = &(struct clk_init_data){
928 .name = "edppixel_clk_src",
929 .parent_names = mmcc_xo_dsi_hdmi_edp,
930 .num_parents = 6,
931 .ops = &clk_edp_pixel_ops,
932 },
933};
934
935static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
936 F(19200000, P_XO, 1, 0, 0),
937 { }
938};
939
940static struct clk_rcg2 esc0_clk_src = {
941 .cmd_rcgr = 0x2160,
942 .hid_width = 5,
943 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
944 .freq_tbl = ftbl_mdss_esc0_1_clk,
945 .clkr.hw.init = &(struct clk_init_data){
946 .name = "esc0_clk_src",
947 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
948 .num_parents = 6,
949 .ops = &clk_rcg2_ops,
950 },
951};
952
953static struct clk_rcg2 esc1_clk_src = {
954 .cmd_rcgr = 0x2180,
955 .hid_width = 5,
956 .parent_map = mmcc_xo_dsibyte_hdmi_edp_gpll0_map,
957 .freq_tbl = ftbl_mdss_esc0_1_clk,
958 .clkr.hw.init = &(struct clk_init_data){
959 .name = "esc1_clk_src",
960 .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
961 .num_parents = 6,
962 .ops = &clk_rcg2_ops,
963 },
964};
965
966static struct freq_tbl extpclk_freq_tbl[] = {
967 { .src = P_HDMIPLL },
968 { }
969};
970
971static struct clk_rcg2 extpclk_clk_src = {
972 .cmd_rcgr = 0x2060,
973 .hid_width = 5,
974 .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
975 .freq_tbl = extpclk_freq_tbl,
976 .clkr.hw.init = &(struct clk_init_data){
977 .name = "extpclk_clk_src",
978 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
979 .num_parents = 6,
980 .ops = &clk_byte_ops,
981 .flags = CLK_SET_RATE_PARENT,
982 },
983};
984
985static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
986 F(19200000, P_XO, 1, 0, 0),
987 { }
988};
989
990static struct clk_rcg2 hdmi_clk_src = {
991 .cmd_rcgr = 0x2100,
992 .hid_width = 5,
993 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
994 .freq_tbl = ftbl_mdss_hdmi_clk,
995 .clkr.hw.init = &(struct clk_init_data){
996 .name = "hdmi_clk_src",
997 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
998 .num_parents = 4,
999 .ops = &clk_rcg2_ops,
1000 },
1001};
1002
1003static struct freq_tbl ftbl_mdss_vsync_clk[] = {
1004 F(19200000, P_XO, 1, 0, 0),
1005 { }
1006};
1007
1008static struct clk_rcg2 vsync_clk_src = {
1009 .cmd_rcgr = 0x2080,
1010 .hid_width = 5,
1011 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1012 .freq_tbl = ftbl_mdss_vsync_clk,
1013 .clkr.hw.init = &(struct clk_init_data){
1014 .name = "vsync_clk_src",
1015 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1016 .num_parents = 4,
1017 .ops = &clk_rcg2_ops,
1018 },
1019};
1020
1021static struct freq_tbl ftbl_mmss_rbcpr_clk[] = {
1022 F(50000000, P_GPLL0, 12, 0, 0),
1023 { }
1024};
1025
1026static struct clk_rcg2 rbcpr_clk_src = {
1027 .cmd_rcgr = 0x4060,
1028 .hid_width = 5,
1029 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1030 .freq_tbl = ftbl_mmss_rbcpr_clk,
1031 .clkr.hw.init = &(struct clk_init_data){
1032 .name = "rbcpr_clk_src",
1033 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1034 .num_parents = 4,
1035 .ops = &clk_rcg2_ops,
1036 },
1037};
1038
1039static struct freq_tbl ftbl_oxili_rbbmtimer_clk[] = {
1040 F(19200000, P_XO, 1, 0, 0),
1041 { }
1042};
1043
1044static struct clk_rcg2 rbbmtimer_clk_src = {
1045 .cmd_rcgr = 0x4090,
1046 .hid_width = 5,
1047 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1048 .freq_tbl = ftbl_oxili_rbbmtimer_clk,
1049 .clkr.hw.init = &(struct clk_init_data){
1050 .name = "rbbmtimer_clk_src",
1051 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1052 .num_parents = 4,
1053 .ops = &clk_rcg2_ops,
1054 },
1055};
1056
1057static struct freq_tbl ftbl_vpu_maple_clk[] = {
1058 F(50000000, P_GPLL0, 12, 0, 0),
1059 F(100000000, P_GPLL0, 6, 0, 0),
1060 F(133330000, P_GPLL0, 4.5, 0, 0),
1061 F(200000000, P_MMPLL0, 4, 0, 0),
1062 F(266670000, P_MMPLL0, 3, 0, 0),
1063 F(465000000, P_MMPLL3, 2, 0, 0),
1064 { }
1065};
1066
1067static struct clk_rcg2 maple_clk_src = {
1068 .cmd_rcgr = 0x1320,
1069 .hid_width = 5,
1070 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1071 .freq_tbl = ftbl_vpu_maple_clk,
1072 .clkr.hw.init = &(struct clk_init_data){
1073 .name = "maple_clk_src",
1074 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1075 .num_parents = 4,
1076 .ops = &clk_rcg2_ops,
1077 },
1078};
1079
1080static struct freq_tbl ftbl_vpu_vdp_clk[] = {
1081 F(50000000, P_GPLL0, 12, 0, 0),
1082 F(100000000, P_GPLL0, 6, 0, 0),
1083 F(200000000, P_MMPLL0, 4, 0, 0),
1084 F(320000000, P_MMPLL0, 2.5, 0, 0),
1085 F(400000000, P_MMPLL0, 2, 0, 0),
1086 { }
1087};
1088
1089static struct clk_rcg2 vdp_clk_src = {
1090 .cmd_rcgr = 0x1300,
1091 .hid_width = 5,
1092 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1093 .freq_tbl = ftbl_vpu_vdp_clk,
1094 .clkr.hw.init = &(struct clk_init_data){
1095 .name = "vdp_clk_src",
1096 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1097 .num_parents = 4,
1098 .ops = &clk_rcg2_ops,
1099 },
1100};
1101
1102static struct freq_tbl ftbl_vpu_bus_clk[] = {
1103 F(40000000, P_GPLL0, 15, 0, 0),
1104 F(80000000, P_MMPLL0, 10, 0, 0),
1105 { }
1106};
1107
1108static struct clk_rcg2 vpu_bus_clk_src = {
1109 .cmd_rcgr = 0x1340,
1110 .hid_width = 5,
1111 .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
1112 .freq_tbl = ftbl_vpu_bus_clk,
1113 .clkr.hw.init = &(struct clk_init_data){
1114 .name = "vpu_bus_clk_src",
1115 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
1116 .num_parents = 4,
1117 .ops = &clk_rcg2_ops,
1118 },
1119};
1120
1121static struct clk_branch mmss_cxo_clk = {
1122 .halt_reg = 0x5104,
1123 .clkr = {
1124 .enable_reg = 0x5104,
1125 .enable_mask = BIT(0),
1126 .hw.init = &(struct clk_init_data){
1127 .name = "mmss_cxo_clk",
1128 .parent_names = (const char *[]){ "xo" },
1129 .num_parents = 1,
1130 .flags = CLK_SET_RATE_PARENT,
1131 .ops = &clk_branch2_ops,
1132 },
1133 },
1134};
1135
1136static struct clk_branch mmss_sleepclk_clk = {
1137 .halt_reg = 0x5100,
1138 .clkr = {
1139 .enable_reg = 0x5100,
1140 .enable_mask = BIT(0),
1141 .hw.init = &(struct clk_init_data){
1142 .name = "mmss_sleepclk_clk",
1143 .parent_names = (const char *[]){
1144 "sleep_clk_src",
1145 },
1146 .num_parents = 1,
1147 .flags = CLK_SET_RATE_PARENT,
1148 .ops = &clk_branch2_ops,
1149 },
1150 },
1151};
1152
1153static struct clk_branch avsync_ahb_clk = {
1154 .halt_reg = 0x2414,
1155 .clkr = {
1156 .enable_reg = 0x2414,
1157 .enable_mask = BIT(0),
1158 .hw.init = &(struct clk_init_data){
1159 .name = "avsync_ahb_clk",
1160 .parent_names = (const char *[]){
1161 "mmss_ahb_clk_src",
1162 },
1163 .num_parents = 1,
1164 .flags = CLK_SET_RATE_PARENT,
1165 .ops = &clk_branch2_ops,
1166 },
1167 },
1168};
1169
1170static struct clk_branch avsync_edppixel_clk = {
1171 .halt_reg = 0x2418,
1172 .clkr = {
1173 .enable_reg = 0x2418,
1174 .enable_mask = BIT(0),
1175 .hw.init = &(struct clk_init_data){
1176 .name = "avsync_edppixel_clk",
1177 .parent_names = (const char *[]){
1178 "edppixel_clk_src",
1179 },
1180 .num_parents = 1,
1181 .flags = CLK_SET_RATE_PARENT,
1182 .ops = &clk_branch2_ops,
1183 },
1184 },
1185};
1186
1187static struct clk_branch avsync_extpclk_clk = {
1188 .halt_reg = 0x2410,
1189 .clkr = {
1190 .enable_reg = 0x2410,
1191 .enable_mask = BIT(0),
1192 .hw.init = &(struct clk_init_data){
1193 .name = "avsync_extpclk_clk",
1194 .parent_names = (const char *[]){
1195 "extpclk_clk_src",
1196 },
1197 .num_parents = 1,
1198 .flags = CLK_SET_RATE_PARENT,
1199 .ops = &clk_branch2_ops,
1200 },
1201 },
1202};
1203
1204static struct clk_branch avsync_pclk0_clk = {
1205 .halt_reg = 0x241c,
1206 .clkr = {
1207 .enable_reg = 0x241c,
1208 .enable_mask = BIT(0),
1209 .hw.init = &(struct clk_init_data){
1210 .name = "avsync_pclk0_clk",
1211 .parent_names = (const char *[]){
1212 "pclk0_clk_src",
1213 },
1214 .num_parents = 1,
1215 .flags = CLK_SET_RATE_PARENT,
1216 .ops = &clk_branch2_ops,
1217 },
1218 },
1219};
1220
1221static struct clk_branch avsync_pclk1_clk = {
1222 .halt_reg = 0x2420,
1223 .clkr = {
1224 .enable_reg = 0x2420,
1225 .enable_mask = BIT(0),
1226 .hw.init = &(struct clk_init_data){
1227 .name = "avsync_pclk1_clk",
1228 .parent_names = (const char *[]){
1229 "pclk1_clk_src",
1230 },
1231 .num_parents = 1,
1232 .flags = CLK_SET_RATE_PARENT,
1233 .ops = &clk_branch2_ops,
1234 },
1235 },
1236};
1237
1238static struct clk_branch avsync_vp_clk = {
1239 .halt_reg = 0x2404,
1240 .clkr = {
1241 .enable_reg = 0x2404,
1242 .enable_mask = BIT(0),
1243 .hw.init = &(struct clk_init_data){
1244 .name = "avsync_vp_clk",
1245 .parent_names = (const char *[]){
1246 "vp_clk_src",
1247 },
1248 .num_parents = 1,
1249 .flags = CLK_SET_RATE_PARENT,
1250 .ops = &clk_branch2_ops,
1251 },
1252 },
1253};
1254
1255static struct clk_branch camss_ahb_clk = {
1256 .halt_reg = 0x348c,
1257 .clkr = {
1258 .enable_reg = 0x348c,
1259 .enable_mask = BIT(0),
1260 .hw.init = &(struct clk_init_data){
1261 .name = "camss_ahb_clk",
1262 .parent_names = (const char *[]){
1263 "mmss_ahb_clk_src",
1264 },
1265 .num_parents = 1,
1266 .flags = CLK_SET_RATE_PARENT,
1267 .ops = &clk_branch2_ops,
1268 },
1269 },
1270};
1271
1272static struct clk_branch camss_cci_cci_ahb_clk = {
1273 .halt_reg = 0x3348,
1274 .clkr = {
1275 .enable_reg = 0x3348,
1276 .enable_mask = BIT(0),
1277 .hw.init = &(struct clk_init_data){
1278 .name = "camss_cci_cci_ahb_clk",
1279 .parent_names = (const char *[]){
1280 "mmss_ahb_clk_src",
1281 },
1282 .num_parents = 1,
1283 .ops = &clk_branch2_ops,
1284 },
1285 },
1286};
1287
1288static struct clk_branch camss_cci_cci_clk = {
1289 .halt_reg = 0x3344,
1290 .clkr = {
1291 .enable_reg = 0x3344,
1292 .enable_mask = BIT(0),
1293 .hw.init = &(struct clk_init_data){
1294 .name = "camss_cci_cci_clk",
1295 .parent_names = (const char *[]){
1296 "cci_clk_src",
1297 },
1298 .num_parents = 1,
1299 .flags = CLK_SET_RATE_PARENT,
1300 .ops = &clk_branch2_ops,
1301 },
1302 },
1303};
1304
1305static struct clk_branch camss_csi0_ahb_clk = {
1306 .halt_reg = 0x30bc,
1307 .clkr = {
1308 .enable_reg = 0x30bc,
1309 .enable_mask = BIT(0),
1310 .hw.init = &(struct clk_init_data){
1311 .name = "camss_csi0_ahb_clk",
1312 .parent_names = (const char *[]){
1313 "mmss_ahb_clk_src",
1314 },
1315 .num_parents = 1,
1316 .ops = &clk_branch2_ops,
1317 },
1318 },
1319};
1320
1321static struct clk_branch camss_csi0_clk = {
1322 .halt_reg = 0x30b4,
1323 .clkr = {
1324 .enable_reg = 0x30b4,
1325 .enable_mask = BIT(0),
1326 .hw.init = &(struct clk_init_data){
1327 .name = "camss_csi0_clk",
1328 .parent_names = (const char *[]){
1329 "csi0_clk_src",
1330 },
1331 .num_parents = 1,
1332 .flags = CLK_SET_RATE_PARENT,
1333 .ops = &clk_branch2_ops,
1334 },
1335 },
1336};
1337
1338static struct clk_branch camss_csi0phy_clk = {
1339 .halt_reg = 0x30c4,
1340 .clkr = {
1341 .enable_reg = 0x30c4,
1342 .enable_mask = BIT(0),
1343 .hw.init = &(struct clk_init_data){
1344 .name = "camss_csi0phy_clk",
1345 .parent_names = (const char *[]){
1346 "csi0_clk_src",
1347 },
1348 .num_parents = 1,
1349 .flags = CLK_SET_RATE_PARENT,
1350 .ops = &clk_branch2_ops,
1351 },
1352 },
1353};
1354
1355static struct clk_branch camss_csi0pix_clk = {
1356 .halt_reg = 0x30e4,
1357 .clkr = {
1358 .enable_reg = 0x30e4,
1359 .enable_mask = BIT(0),
1360 .hw.init = &(struct clk_init_data){
1361 .name = "camss_csi0pix_clk",
1362 .parent_names = (const char *[]){
1363 "csi0_clk_src",
1364 },
1365 .num_parents = 1,
1366 .flags = CLK_SET_RATE_PARENT,
1367 .ops = &clk_branch2_ops,
1368 },
1369 },
1370};
1371
1372static struct clk_branch camss_csi0rdi_clk = {
1373 .halt_reg = 0x30d4,
1374 .clkr = {
1375 .enable_reg = 0x30d4,
1376 .enable_mask = BIT(0),
1377 .hw.init = &(struct clk_init_data){
1378 .name = "camss_csi0rdi_clk",
1379 .parent_names = (const char *[]){
1380 "csi0_clk_src",
1381 },
1382 .num_parents = 1,
1383 .flags = CLK_SET_RATE_PARENT,
1384 .ops = &clk_branch2_ops,
1385 },
1386 },
1387};
1388
1389static struct clk_branch camss_csi1_ahb_clk = {
1390 .halt_reg = 0x3128,
1391 .clkr = {
1392 .enable_reg = 0x3128,
1393 .enable_mask = BIT(0),
1394 .hw.init = &(struct clk_init_data){
1395 .name = "camss_csi1_ahb_clk",
1396 .parent_names = (const char *[]){
1397 "mmss_ahb_clk_src",
1398 },
1399 .num_parents = 1,
1400 .flags = CLK_SET_RATE_PARENT,
1401 .ops = &clk_branch2_ops,
1402 },
1403 },
1404};
1405
1406static struct clk_branch camss_csi1_clk = {
1407 .halt_reg = 0x3124,
1408 .clkr = {
1409 .enable_reg = 0x3124,
1410 .enable_mask = BIT(0),
1411 .hw.init = &(struct clk_init_data){
1412 .name = "camss_csi1_clk",
1413 .parent_names = (const char *[]){
1414 "csi1_clk_src",
1415 },
1416 .num_parents = 1,
1417 .flags = CLK_SET_RATE_PARENT,
1418 .ops = &clk_branch2_ops,
1419 },
1420 },
1421};
1422
1423static struct clk_branch camss_csi1phy_clk = {
1424 .halt_reg = 0x3134,
1425 .clkr = {
1426 .enable_reg = 0x3134,
1427 .enable_mask = BIT(0),
1428 .hw.init = &(struct clk_init_data){
1429 .name = "camss_csi1phy_clk",
1430 .parent_names = (const char *[]){
1431 "csi1_clk_src",
1432 },
1433 .num_parents = 1,
1434 .flags = CLK_SET_RATE_PARENT,
1435 .ops = &clk_branch2_ops,
1436 },
1437 },
1438};
1439
1440static struct clk_branch camss_csi1pix_clk = {
1441 .halt_reg = 0x3154,
1442 .clkr = {
1443 .enable_reg = 0x3154,
1444 .enable_mask = BIT(0),
1445 .hw.init = &(struct clk_init_data){
1446 .name = "camss_csi1pix_clk",
1447 .parent_names = (const char *[]){
1448 "csi1_clk_src",
1449 },
1450 .num_parents = 1,
1451 .flags = CLK_SET_RATE_PARENT,
1452 .ops = &clk_branch2_ops,
1453 },
1454 },
1455};
1456
1457static struct clk_branch camss_csi1rdi_clk = {
1458 .halt_reg = 0x3144,
1459 .clkr = {
1460 .enable_reg = 0x3144,
1461 .enable_mask = BIT(0),
1462 .hw.init = &(struct clk_init_data){
1463 .name = "camss_csi1rdi_clk",
1464 .parent_names = (const char *[]){
1465 "csi1_clk_src",
1466 },
1467 .num_parents = 1,
1468 .flags = CLK_SET_RATE_PARENT,
1469 .ops = &clk_branch2_ops,
1470 },
1471 },
1472};
1473
1474static struct clk_branch camss_csi2_ahb_clk = {
1475 .halt_reg = 0x3188,
1476 .clkr = {
1477 .enable_reg = 0x3188,
1478 .enable_mask = BIT(0),
1479 .hw.init = &(struct clk_init_data){
1480 .name = "camss_csi2_ahb_clk",
1481 .parent_names = (const char *[]){
1482 "mmss_ahb_clk_src",
1483 },
1484 .num_parents = 1,
1485 .ops = &clk_branch2_ops,
1486 },
1487 },
1488};
1489
1490static struct clk_branch camss_csi2_clk = {
1491 .halt_reg = 0x3184,
1492 .clkr = {
1493 .enable_reg = 0x3184,
1494 .enable_mask = BIT(0),
1495 .hw.init = &(struct clk_init_data){
1496 .name = "camss_csi2_clk",
1497 .parent_names = (const char *[]){
1498 "csi2_clk_src",
1499 },
1500 .num_parents = 1,
1501 .flags = CLK_SET_RATE_PARENT,
1502 .ops = &clk_branch2_ops,
1503 },
1504 },
1505};
1506
1507static struct clk_branch camss_csi2phy_clk = {
1508 .halt_reg = 0x3194,
1509 .clkr = {
1510 .enable_reg = 0x3194,
1511 .enable_mask = BIT(0),
1512 .hw.init = &(struct clk_init_data){
1513 .name = "camss_csi2phy_clk",
1514 .parent_names = (const char *[]){
1515 "csi2_clk_src",
1516 },
1517 .num_parents = 1,
1518 .flags = CLK_SET_RATE_PARENT,
1519 .ops = &clk_branch2_ops,
1520 },
1521 },
1522};
1523
1524static struct clk_branch camss_csi2pix_clk = {
1525 .halt_reg = 0x31b4,
1526 .clkr = {
1527 .enable_reg = 0x31b4,
1528 .enable_mask = BIT(0),
1529 .hw.init = &(struct clk_init_data){
1530 .name = "camss_csi2pix_clk",
1531 .parent_names = (const char *[]){
1532 "csi2_clk_src",
1533 },
1534 .num_parents = 1,
1535 .flags = CLK_SET_RATE_PARENT,
1536 .ops = &clk_branch2_ops,
1537 },
1538 },
1539};
1540
1541static struct clk_branch camss_csi2rdi_clk = {
1542 .halt_reg = 0x31a4,
1543 .clkr = {
1544 .enable_reg = 0x31a4,
1545 .enable_mask = BIT(0),
1546 .hw.init = &(struct clk_init_data){
1547 .name = "camss_csi2rdi_clk",
1548 .parent_names = (const char *[]){
1549 "csi2_clk_src",
1550 },
1551 .num_parents = 1,
1552 .flags = CLK_SET_RATE_PARENT,
1553 .ops = &clk_branch2_ops,
1554 },
1555 },
1556};
1557
1558static struct clk_branch camss_csi3_ahb_clk = {
1559 .halt_reg = 0x31e8,
1560 .clkr = {
1561 .enable_reg = 0x31e8,
1562 .enable_mask = BIT(0),
1563 .hw.init = &(struct clk_init_data){
1564 .name = "camss_csi3_ahb_clk",
1565 .parent_names = (const char *[]){
1566 "mmss_ahb_clk_src",
1567 },
1568 .num_parents = 1,
1569 .ops = &clk_branch2_ops,
1570 },
1571 },
1572};
1573
1574static struct clk_branch camss_csi3_clk = {
1575 .halt_reg = 0x31e4,
1576 .clkr = {
1577 .enable_reg = 0x31e4,
1578 .enable_mask = BIT(0),
1579 .hw.init = &(struct clk_init_data){
1580 .name = "camss_csi3_clk",
1581 .parent_names = (const char *[]){
1582 "csi3_clk_src",
1583 },
1584 .num_parents = 1,
1585 .flags = CLK_SET_RATE_PARENT,
1586 .ops = &clk_branch2_ops,
1587 },
1588 },
1589};
1590
1591static struct clk_branch camss_csi3phy_clk = {
1592 .halt_reg = 0x31f4,
1593 .clkr = {
1594 .enable_reg = 0x31f4,
1595 .enable_mask = BIT(0),
1596 .hw.init = &(struct clk_init_data){
1597 .name = "camss_csi3phy_clk",
1598 .parent_names = (const char *[]){
1599 "csi3_clk_src",
1600 },
1601 .num_parents = 1,
1602 .flags = CLK_SET_RATE_PARENT,
1603 .ops = &clk_branch2_ops,
1604 },
1605 },
1606};
1607
1608static struct clk_branch camss_csi3pix_clk = {
1609 .halt_reg = 0x3214,
1610 .clkr = {
1611 .enable_reg = 0x3214,
1612 .enable_mask = BIT(0),
1613 .hw.init = &(struct clk_init_data){
1614 .name = "camss_csi3pix_clk",
1615 .parent_names = (const char *[]){
1616 "csi3_clk_src",
1617 },
1618 .num_parents = 1,
1619 .flags = CLK_SET_RATE_PARENT,
1620 .ops = &clk_branch2_ops,
1621 },
1622 },
1623};
1624
1625static struct clk_branch camss_csi3rdi_clk = {
1626 .halt_reg = 0x3204,
1627 .clkr = {
1628 .enable_reg = 0x3204,
1629 .enable_mask = BIT(0),
1630 .hw.init = &(struct clk_init_data){
1631 .name = "camss_csi3rdi_clk",
1632 .parent_names = (const char *[]){
1633 "csi3_clk_src",
1634 },
1635 .num_parents = 1,
1636 .flags = CLK_SET_RATE_PARENT,
1637 .ops = &clk_branch2_ops,
1638 },
1639 },
1640};
1641
1642static struct clk_branch camss_csi_vfe0_clk = {
1643 .halt_reg = 0x3704,
1644 .clkr = {
1645 .enable_reg = 0x3704,
1646 .enable_mask = BIT(0),
1647 .hw.init = &(struct clk_init_data){
1648 .name = "camss_csi_vfe0_clk",
1649 .parent_names = (const char *[]){
1650 "vfe0_clk_src",
1651 },
1652 .num_parents = 1,
1653 .flags = CLK_SET_RATE_PARENT,
1654 .ops = &clk_branch2_ops,
1655 },
1656 },
1657};
1658
1659static struct clk_branch camss_csi_vfe1_clk = {
1660 .halt_reg = 0x3714,
1661 .clkr = {
1662 .enable_reg = 0x3714,
1663 .enable_mask = BIT(0),
1664 .hw.init = &(struct clk_init_data){
1665 .name = "camss_csi_vfe1_clk",
1666 .parent_names = (const char *[]){
1667 "vfe1_clk_src",
1668 },
1669 .num_parents = 1,
1670 .flags = CLK_SET_RATE_PARENT,
1671 .ops = &clk_branch2_ops,
1672 },
1673 },
1674};
1675
1676static struct clk_branch camss_gp0_clk = {
1677 .halt_reg = 0x3444,
1678 .clkr = {
1679 .enable_reg = 0x3444,
1680 .enable_mask = BIT(0),
1681 .hw.init = &(struct clk_init_data){
1682 .name = "camss_gp0_clk",
1683 .parent_names = (const char *[]){
1684 "camss_gp0_clk_src",
1685 },
1686 .num_parents = 1,
1687 .flags = CLK_SET_RATE_PARENT,
1688 .ops = &clk_branch2_ops,
1689 },
1690 },
1691};
1692
1693static struct clk_branch camss_gp1_clk = {
1694 .halt_reg = 0x3474,
1695 .clkr = {
1696 .enable_reg = 0x3474,
1697 .enable_mask = BIT(0),
1698 .hw.init = &(struct clk_init_data){
1699 .name = "camss_gp1_clk",
1700 .parent_names = (const char *[]){
1701 "camss_gp1_clk_src",
1702 },
1703 .num_parents = 1,
1704 .flags = CLK_SET_RATE_PARENT,
1705 .ops = &clk_branch2_ops,
1706 },
1707 },
1708};
1709
1710static struct clk_branch camss_ispif_ahb_clk = {
1711 .halt_reg = 0x3224,
1712 .clkr = {
1713 .enable_reg = 0x3224,
1714 .enable_mask = BIT(0),
1715 .hw.init = &(struct clk_init_data){
1716 .name = "camss_ispif_ahb_clk",
1717 .parent_names = (const char *[]){
1718 "mmss_ahb_clk_src",
1719 },
1720 .num_parents = 1,
1721 .flags = CLK_SET_RATE_PARENT,
1722 .ops = &clk_branch2_ops,
1723 },
1724 },
1725};
1726
1727static struct clk_branch camss_jpeg_jpeg0_clk = {
1728 .halt_reg = 0x35a8,
1729 .clkr = {
1730 .enable_reg = 0x35a8,
1731 .enable_mask = BIT(0),
1732 .hw.init = &(struct clk_init_data){
1733 .name = "camss_jpeg_jpeg0_clk",
1734 .parent_names = (const char *[]){
1735 "jpeg0_clk_src",
1736 },
1737 .num_parents = 1,
1738 .flags = CLK_SET_RATE_PARENT,
1739 .ops = &clk_branch2_ops,
1740 },
1741 },
1742};
1743
1744static struct clk_branch camss_jpeg_jpeg1_clk = {
1745 .halt_reg = 0x35ac,
1746 .clkr = {
1747 .enable_reg = 0x35ac,
1748 .enable_mask = BIT(0),
1749 .hw.init = &(struct clk_init_data){
1750 .name = "camss_jpeg_jpeg1_clk",
1751 .parent_names = (const char *[]){
1752 "jpeg1_clk_src",
1753 },
1754 .num_parents = 1,
1755 .flags = CLK_SET_RATE_PARENT,
1756 .ops = &clk_branch2_ops,
1757 },
1758 },
1759};
1760
1761static struct clk_branch camss_jpeg_jpeg2_clk = {
1762 .halt_reg = 0x35b0,
1763 .clkr = {
1764 .enable_reg = 0x35b0,
1765 .enable_mask = BIT(0),
1766 .hw.init = &(struct clk_init_data){
1767 .name = "camss_jpeg_jpeg2_clk",
1768 .parent_names = (const char *[]){
1769 "jpeg2_clk_src",
1770 },
1771 .num_parents = 1,
1772 .flags = CLK_SET_RATE_PARENT,
1773 .ops = &clk_branch2_ops,
1774 },
1775 },
1776};
1777
1778static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1779 .halt_reg = 0x35b4,
1780 .clkr = {
1781 .enable_reg = 0x35b4,
1782 .enable_mask = BIT(0),
1783 .hw.init = &(struct clk_init_data){
1784 .name = "camss_jpeg_jpeg_ahb_clk",
1785 .parent_names = (const char *[]){
1786 "mmss_ahb_clk_src",
1787 },
1788 .num_parents = 1,
1789 .ops = &clk_branch2_ops,
1790 },
1791 },
1792};
1793
1794static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1795 .halt_reg = 0x35b8,
1796 .clkr = {
1797 .enable_reg = 0x35b8,
1798 .enable_mask = BIT(0),
1799 .hw.init = &(struct clk_init_data){
1800 .name = "camss_jpeg_jpeg_axi_clk",
1801 .parent_names = (const char *[]){
1802 "mmss_axi_clk_src",
1803 },
1804 .num_parents = 1,
1805 .ops = &clk_branch2_ops,
1806 },
1807 },
1808};
1809
1810static struct clk_branch camss_mclk0_clk = {
1811 .halt_reg = 0x3384,
1812 .clkr = {
1813 .enable_reg = 0x3384,
1814 .enable_mask = BIT(0),
1815 .hw.init = &(struct clk_init_data){
1816 .name = "camss_mclk0_clk",
1817 .parent_names = (const char *[]){
1818 "mclk0_clk_src",
1819 },
1820 .num_parents = 1,
1821 .flags = CLK_SET_RATE_PARENT,
1822 .ops = &clk_branch2_ops,
1823 },
1824 },
1825};
1826
1827static struct clk_branch camss_mclk1_clk = {
1828 .halt_reg = 0x33b4,
1829 .clkr = {
1830 .enable_reg = 0x33b4,
1831 .enable_mask = BIT(0),
1832 .hw.init = &(struct clk_init_data){
1833 .name = "camss_mclk1_clk",
1834 .parent_names = (const char *[]){
1835 "mclk1_clk_src",
1836 },
1837 .num_parents = 1,
1838 .flags = CLK_SET_RATE_PARENT,
1839 .ops = &clk_branch2_ops,
1840 },
1841 },
1842};
1843
1844static struct clk_branch camss_mclk2_clk = {
1845 .halt_reg = 0x33e4,
1846 .clkr = {
1847 .enable_reg = 0x33e4,
1848 .enable_mask = BIT(0),
1849 .hw.init = &(struct clk_init_data){
1850 .name = "camss_mclk2_clk",
1851 .parent_names = (const char *[]){
1852 "mclk2_clk_src",
1853 },
1854 .num_parents = 1,
1855 .flags = CLK_SET_RATE_PARENT,
1856 .ops = &clk_branch2_ops,
1857 },
1858 },
1859};
1860
1861static struct clk_branch camss_mclk3_clk = {
1862 .halt_reg = 0x3414,
1863 .clkr = {
1864 .enable_reg = 0x3414,
1865 .enable_mask = BIT(0),
1866 .hw.init = &(struct clk_init_data){
1867 .name = "camss_mclk3_clk",
1868 .parent_names = (const char *[]){
1869 "mclk3_clk_src",
1870 },
1871 .num_parents = 1,
1872 .flags = CLK_SET_RATE_PARENT,
1873 .ops = &clk_branch2_ops,
1874 },
1875 },
1876};
1877
1878static struct clk_branch camss_micro_ahb_clk = {
1879 .halt_reg = 0x3494,
1880 .clkr = {
1881 .enable_reg = 0x3494,
1882 .enable_mask = BIT(0),
1883 .hw.init = &(struct clk_init_data){
1884 .name = "camss_micro_ahb_clk",
1885 .parent_names = (const char *[]){
1886 "mmss_ahb_clk_src",
1887 },
1888 .num_parents = 1,
1889 .ops = &clk_branch2_ops,
1890 },
1891 },
1892};
1893
1894static struct clk_branch camss_phy0_csi0phytimer_clk = {
1895 .halt_reg = 0x3024,
1896 .clkr = {
1897 .enable_reg = 0x3024,
1898 .enable_mask = BIT(0),
1899 .hw.init = &(struct clk_init_data){
1900 .name = "camss_phy0_csi0phytimer_clk",
1901 .parent_names = (const char *[]){
1902 "csi0phytimer_clk_src",
1903 },
1904 .num_parents = 1,
1905 .flags = CLK_SET_RATE_PARENT,
1906 .ops = &clk_branch2_ops,
1907 },
1908 },
1909};
1910
1911static struct clk_branch camss_phy1_csi1phytimer_clk = {
1912 .halt_reg = 0x3054,
1913 .clkr = {
1914 .enable_reg = 0x3054,
1915 .enable_mask = BIT(0),
1916 .hw.init = &(struct clk_init_data){
1917 .name = "camss_phy1_csi1phytimer_clk",
1918 .parent_names = (const char *[]){
1919 "csi1phytimer_clk_src",
1920 },
1921 .num_parents = 1,
1922 .flags = CLK_SET_RATE_PARENT,
1923 .ops = &clk_branch2_ops,
1924 },
1925 },
1926};
1927
1928static struct clk_branch camss_phy2_csi2phytimer_clk = {
1929 .halt_reg = 0x3084,
1930 .clkr = {
1931 .enable_reg = 0x3084,
1932 .enable_mask = BIT(0),
1933 .hw.init = &(struct clk_init_data){
1934 .name = "camss_phy2_csi2phytimer_clk",
1935 .parent_names = (const char *[]){
1936 "csi2phytimer_clk_src",
1937 },
1938 .num_parents = 1,
1939 .flags = CLK_SET_RATE_PARENT,
1940 .ops = &clk_branch2_ops,
1941 },
1942 },
1943};
1944
1945static struct clk_branch camss_top_ahb_clk = {
1946 .halt_reg = 0x3484,
1947 .clkr = {
1948 .enable_reg = 0x3484,
1949 .enable_mask = BIT(0),
1950 .hw.init = &(struct clk_init_data){
1951 .name = "camss_top_ahb_clk",
1952 .parent_names = (const char *[]){
1953 "mmss_ahb_clk_src",
1954 },
1955 .num_parents = 1,
1956 .flags = CLK_SET_RATE_PARENT,
1957 .ops = &clk_branch2_ops,
1958 },
1959 },
1960};
1961
1962static struct clk_branch camss_vfe_cpp_ahb_clk = {
1963 .halt_reg = 0x36b4,
1964 .clkr = {
1965 .enable_reg = 0x36b4,
1966 .enable_mask = BIT(0),
1967 .hw.init = &(struct clk_init_data){
1968 .name = "camss_vfe_cpp_ahb_clk",
1969 .parent_names = (const char *[]){
1970 "mmss_ahb_clk_src",
1971 },
1972 .num_parents = 1,
1973 .flags = CLK_SET_RATE_PARENT,
1974 .ops = &clk_branch2_ops,
1975 },
1976 },
1977};
1978
1979static struct clk_branch camss_vfe_cpp_clk = {
1980 .halt_reg = 0x36b0,
1981 .clkr = {
1982 .enable_reg = 0x36b0,
1983 .enable_mask = BIT(0),
1984 .hw.init = &(struct clk_init_data){
1985 .name = "camss_vfe_cpp_clk",
1986 .parent_names = (const char *[]){
1987 "cpp_clk_src",
1988 },
1989 .num_parents = 1,
1990 .flags = CLK_SET_RATE_PARENT,
1991 .ops = &clk_branch2_ops,
1992 },
1993 },
1994};
1995
1996static struct clk_branch camss_vfe_vfe0_clk = {
1997 .halt_reg = 0x36a8,
1998 .clkr = {
1999 .enable_reg = 0x36a8,
2000 .enable_mask = BIT(0),
2001 .hw.init = &(struct clk_init_data){
2002 .name = "camss_vfe_vfe0_clk",
2003 .parent_names = (const char *[]){
2004 "vfe0_clk_src",
2005 },
2006 .num_parents = 1,
2007 .flags = CLK_SET_RATE_PARENT,
2008 .ops = &clk_branch2_ops,
2009 },
2010 },
2011};
2012
2013static struct clk_branch camss_vfe_vfe1_clk = {
2014 .halt_reg = 0x36ac,
2015 .clkr = {
2016 .enable_reg = 0x36ac,
2017 .enable_mask = BIT(0),
2018 .hw.init = &(struct clk_init_data){
2019 .name = "camss_vfe_vfe1_clk",
2020 .parent_names = (const char *[]){
2021 "vfe1_clk_src",
2022 },
2023 .num_parents = 1,
2024 .flags = CLK_SET_RATE_PARENT,
2025 .ops = &clk_branch2_ops,
2026 },
2027 },
2028};
2029
2030static struct clk_branch camss_vfe_vfe_ahb_clk = {
2031 .halt_reg = 0x36b8,
2032 .clkr = {
2033 .enable_reg = 0x36b8,
2034 .enable_mask = BIT(0),
2035 .hw.init = &(struct clk_init_data){
2036 .name = "camss_vfe_vfe_ahb_clk",
2037 .parent_names = (const char *[]){
2038 "mmss_ahb_clk_src",
2039 },
2040 .num_parents = 1,
2041 .flags = CLK_SET_RATE_PARENT,
2042 .ops = &clk_branch2_ops,
2043 },
2044 },
2045};
2046
2047static struct clk_branch camss_vfe_vfe_axi_clk = {
2048 .halt_reg = 0x36bc,
2049 .clkr = {
2050 .enable_reg = 0x36bc,
2051 .enable_mask = BIT(0),
2052 .hw.init = &(struct clk_init_data){
2053 .name = "camss_vfe_vfe_axi_clk",
2054 .parent_names = (const char *[]){
2055 "mmss_axi_clk_src",
2056 },
2057 .num_parents = 1,
2058 .flags = CLK_SET_RATE_PARENT,
2059 .ops = &clk_branch2_ops,
2060 },
2061 },
2062};
2063
2064static struct clk_branch mdss_ahb_clk = {
2065 .halt_reg = 0x2308,
2066 .clkr = {
2067 .enable_reg = 0x2308,
2068 .enable_mask = BIT(0),
2069 .hw.init = &(struct clk_init_data){
2070 .name = "mdss_ahb_clk",
2071 .parent_names = (const char *[]){
2072 "mmss_ahb_clk_src",
2073 },
2074 .num_parents = 1,
2075 .flags = CLK_SET_RATE_PARENT,
2076 .ops = &clk_branch2_ops,
2077 },
2078 },
2079};
2080
2081static struct clk_branch mdss_axi_clk = {
2082 .halt_reg = 0x2310,
2083 .clkr = {
2084 .enable_reg = 0x2310,
2085 .enable_mask = BIT(0),
2086 .hw.init = &(struct clk_init_data){
2087 .name = "mdss_axi_clk",
2088 .parent_names = (const char *[]){
2089 "mmss_axi_clk_src",
2090 },
2091 .num_parents = 1,
2092 .flags = CLK_SET_RATE_PARENT,
2093 .ops = &clk_branch2_ops,
2094 },
2095 },
2096};
2097
2098static struct clk_branch mdss_byte0_clk = {
2099 .halt_reg = 0x233c,
2100 .clkr = {
2101 .enable_reg = 0x233c,
2102 .enable_mask = BIT(0),
2103 .hw.init = &(struct clk_init_data){
2104 .name = "mdss_byte0_clk",
2105 .parent_names = (const char *[]){
2106 "byte0_clk_src",
2107 },
2108 .num_parents = 1,
2109 .flags = CLK_SET_RATE_PARENT,
2110 .ops = &clk_branch2_ops,
2111 },
2112 },
2113};
2114
2115static struct clk_branch mdss_byte1_clk = {
2116 .halt_reg = 0x2340,
2117 .clkr = {
2118 .enable_reg = 0x2340,
2119 .enable_mask = BIT(0),
2120 .hw.init = &(struct clk_init_data){
2121 .name = "mdss_byte1_clk",
2122 .parent_names = (const char *[]){
2123 "byte1_clk_src",
2124 },
2125 .num_parents = 1,
2126 .flags = CLK_SET_RATE_PARENT,
2127 .ops = &clk_branch2_ops,
2128 },
2129 },
2130};
2131
2132static struct clk_branch mdss_edpaux_clk = {
2133 .halt_reg = 0x2334,
2134 .clkr = {
2135 .enable_reg = 0x2334,
2136 .enable_mask = BIT(0),
2137 .hw.init = &(struct clk_init_data){
2138 .name = "mdss_edpaux_clk",
2139 .parent_names = (const char *[]){
2140 "edpaux_clk_src",
2141 },
2142 .num_parents = 1,
2143 .flags = CLK_SET_RATE_PARENT,
2144 .ops = &clk_branch2_ops,
2145 },
2146 },
2147};
2148
2149static struct clk_branch mdss_edplink_clk = {
2150 .halt_reg = 0x2330,
2151 .clkr = {
2152 .enable_reg = 0x2330,
2153 .enable_mask = BIT(0),
2154 .hw.init = &(struct clk_init_data){
2155 .name = "mdss_edplink_clk",
2156 .parent_names = (const char *[]){
2157 "edplink_clk_src",
2158 },
2159 .num_parents = 1,
2160 .flags = CLK_SET_RATE_PARENT,
2161 .ops = &clk_branch2_ops,
2162 },
2163 },
2164};
2165
2166static struct clk_branch mdss_edppixel_clk = {
2167 .halt_reg = 0x232c,
2168 .clkr = {
2169 .enable_reg = 0x232c,
2170 .enable_mask = BIT(0),
2171 .hw.init = &(struct clk_init_data){
2172 .name = "mdss_edppixel_clk",
2173 .parent_names = (const char *[]){
2174 "edppixel_clk_src",
2175 },
2176 .num_parents = 1,
2177 .flags = CLK_SET_RATE_PARENT,
2178 .ops = &clk_branch2_ops,
2179 },
2180 },
2181};
2182
2183static struct clk_branch mdss_esc0_clk = {
2184 .halt_reg = 0x2344,
2185 .clkr = {
2186 .enable_reg = 0x2344,
2187 .enable_mask = BIT(0),
2188 .hw.init = &(struct clk_init_data){
2189 .name = "mdss_esc0_clk",
2190 .parent_names = (const char *[]){
2191 "esc0_clk_src",
2192 },
2193 .num_parents = 1,
2194 .flags = CLK_SET_RATE_PARENT,
2195 .ops = &clk_branch2_ops,
2196 },
2197 },
2198};
2199
2200static struct clk_branch mdss_esc1_clk = {
2201 .halt_reg = 0x2348,
2202 .clkr = {
2203 .enable_reg = 0x2348,
2204 .enable_mask = BIT(0),
2205 .hw.init = &(struct clk_init_data){
2206 .name = "mdss_esc1_clk",
2207 .parent_names = (const char *[]){
2208 "esc1_clk_src",
2209 },
2210 .num_parents = 1,
2211 .flags = CLK_SET_RATE_PARENT,
2212 .ops = &clk_branch2_ops,
2213 },
2214 },
2215};
2216
2217static struct clk_branch mdss_extpclk_clk = {
2218 .halt_reg = 0x2324,
2219 .clkr = {
2220 .enable_reg = 0x2324,
2221 .enable_mask = BIT(0),
2222 .hw.init = &(struct clk_init_data){
2223 .name = "mdss_extpclk_clk",
2224 .parent_names = (const char *[]){
2225 "extpclk_clk_src",
2226 },
2227 .num_parents = 1,
2228 .flags = CLK_SET_RATE_PARENT,
2229 .ops = &clk_branch2_ops,
2230 },
2231 },
2232};
2233
2234static struct clk_branch mdss_hdmi_ahb_clk = {
2235 .halt_reg = 0x230c,
2236 .clkr = {
2237 .enable_reg = 0x230c,
2238 .enable_mask = BIT(0),
2239 .hw.init = &(struct clk_init_data){
2240 .name = "mdss_hdmi_ahb_clk",
2241 .parent_names = (const char *[]){
2242 "mmss_ahb_clk_src",
2243 },
2244 .num_parents = 1,
2245 .flags = CLK_SET_RATE_PARENT,
2246 .ops = &clk_branch2_ops,
2247 },
2248 },
2249};
2250
2251static struct clk_branch mdss_hdmi_clk = {
2252 .halt_reg = 0x2338,
2253 .clkr = {
2254 .enable_reg = 0x2338,
2255 .enable_mask = BIT(0),
2256 .hw.init = &(struct clk_init_data){
2257 .name = "mdss_hdmi_clk",
2258 .parent_names = (const char *[]){
2259 "hdmi_clk_src",
2260 },
2261 .num_parents = 1,
2262 .flags = CLK_SET_RATE_PARENT,
2263 .ops = &clk_branch2_ops,
2264 },
2265 },
2266};
2267
2268static struct clk_branch mdss_mdp_clk = {
2269 .halt_reg = 0x231c,
2270 .clkr = {
2271 .enable_reg = 0x231c,
2272 .enable_mask = BIT(0),
2273 .hw.init = &(struct clk_init_data){
2274 .name = "mdss_mdp_clk",
2275 .parent_names = (const char *[]){
2276 "mdp_clk_src",
2277 },
2278 .num_parents = 1,
2279 .flags = CLK_SET_RATE_PARENT,
2280 .ops = &clk_branch2_ops,
2281 },
2282 },
2283};
2284
2285static struct clk_branch mdss_mdp_lut_clk = {
2286 .halt_reg = 0x2320,
2287 .clkr = {
2288 .enable_reg = 0x2320,
2289 .enable_mask = BIT(0),
2290 .hw.init = &(struct clk_init_data){
2291 .name = "mdss_mdp_lut_clk",
2292 .parent_names = (const char *[]){
2293 "mdp_clk_src",
2294 },
2295 .num_parents = 1,
2296 .flags = CLK_SET_RATE_PARENT,
2297 .ops = &clk_branch2_ops,
2298 },
2299 },
2300};
2301
2302static struct clk_branch mdss_pclk0_clk = {
2303 .halt_reg = 0x2314,
2304 .clkr = {
2305 .enable_reg = 0x2314,
2306 .enable_mask = BIT(0),
2307 .hw.init = &(struct clk_init_data){
2308 .name = "mdss_pclk0_clk",
2309 .parent_names = (const char *[]){
2310 "pclk0_clk_src",
2311 },
2312 .num_parents = 1,
2313 .flags = CLK_SET_RATE_PARENT,
2314 .ops = &clk_branch2_ops,
2315 },
2316 },
2317};
2318
2319static struct clk_branch mdss_pclk1_clk = {
2320 .halt_reg = 0x2318,
2321 .clkr = {
2322 .enable_reg = 0x2318,
2323 .enable_mask = BIT(0),
2324 .hw.init = &(struct clk_init_data){
2325 .name = "mdss_pclk1_clk",
2326 .parent_names = (const char *[]){
2327 "pclk1_clk_src",
2328 },
2329 .num_parents = 1,
2330 .flags = CLK_SET_RATE_PARENT,
2331 .ops = &clk_branch2_ops,
2332 },
2333 },
2334};
2335
2336static struct clk_branch mdss_vsync_clk = {
2337 .halt_reg = 0x2328,
2338 .clkr = {
2339 .enable_reg = 0x2328,
2340 .enable_mask = BIT(0),
2341 .hw.init = &(struct clk_init_data){
2342 .name = "mdss_vsync_clk",
2343 .parent_names = (const char *[]){
2344 "vsync_clk_src",
2345 },
2346 .num_parents = 1,
2347 .flags = CLK_SET_RATE_PARENT,
2348 .ops = &clk_branch2_ops,
2349 },
2350 },
2351};
2352
2353static struct clk_branch mmss_rbcpr_ahb_clk = {
2354 .halt_reg = 0x4088,
2355 .clkr = {
2356 .enable_reg = 0x4088,
2357 .enable_mask = BIT(0),
2358 .hw.init = &(struct clk_init_data){
2359 .name = "mmss_rbcpr_ahb_clk",
2360 .parent_names = (const char *[]){
2361 "mmss_ahb_clk_src",
2362 },
2363 .num_parents = 1,
2364 .flags = CLK_SET_RATE_PARENT,
2365 .ops = &clk_branch2_ops,
2366 },
2367 },
2368};
2369
2370static struct clk_branch mmss_rbcpr_clk = {
2371 .halt_reg = 0x4084,
2372 .clkr = {
2373 .enable_reg = 0x4084,
2374 .enable_mask = BIT(0),
2375 .hw.init = &(struct clk_init_data){
2376 .name = "mmss_rbcpr_clk",
2377 .parent_names = (const char *[]){
2378 "rbcpr_clk_src",
2379 },
2380 .num_parents = 1,
2381 .flags = CLK_SET_RATE_PARENT,
2382 .ops = &clk_branch2_ops,
2383 },
2384 },
2385};
2386
2387static struct clk_branch mmss_spdm_ahb_clk = {
2388 .halt_reg = 0x0230,
2389 .clkr = {
2390 .enable_reg = 0x0230,
2391 .enable_mask = BIT(0),
2392 .hw.init = &(struct clk_init_data){
2393 .name = "mmss_spdm_ahb_clk",
2394 .parent_names = (const char *[]){
2395 "mmss_spdm_ahb_div_clk",
2396 },
2397 .num_parents = 1,
2398 .flags = CLK_SET_RATE_PARENT,
2399 .ops = &clk_branch2_ops,
2400 },
2401 },
2402};
2403
2404static struct clk_branch mmss_spdm_axi_clk = {
2405 .halt_reg = 0x0210,
2406 .clkr = {
2407 .enable_reg = 0x0210,
2408 .enable_mask = BIT(0),
2409 .hw.init = &(struct clk_init_data){
2410 .name = "mmss_spdm_axi_clk",
2411 .parent_names = (const char *[]){
2412 "mmss_spdm_axi_div_clk",
2413 },
2414 .num_parents = 1,
2415 .flags = CLK_SET_RATE_PARENT,
2416 .ops = &clk_branch2_ops,
2417 },
2418 },
2419};
2420
2421static struct clk_branch mmss_spdm_csi0_clk = {
2422 .halt_reg = 0x023c,
2423 .clkr = {
2424 .enable_reg = 0x023c,
2425 .enable_mask = BIT(0),
2426 .hw.init = &(struct clk_init_data){
2427 .name = "mmss_spdm_csi0_clk",
2428 .parent_names = (const char *[]){
2429 "mmss_spdm_csi0_div_clk",
2430 },
2431 .num_parents = 1,
2432 .flags = CLK_SET_RATE_PARENT,
2433 .ops = &clk_branch2_ops,
2434 },
2435 },
2436};
2437
2438static struct clk_branch mmss_spdm_gfx3d_clk = {
2439 .halt_reg = 0x022c,
2440 .clkr = {
2441 .enable_reg = 0x022c,
2442 .enable_mask = BIT(0),
2443 .hw.init = &(struct clk_init_data){
2444 .name = "mmss_spdm_gfx3d_clk",
2445 .parent_names = (const char *[]){
2446 "mmss_spdm_gfx3d_div_clk",
2447 },
2448 .num_parents = 1,
2449 .flags = CLK_SET_RATE_PARENT,
2450 .ops = &clk_branch2_ops,
2451 },
2452 },
2453};
2454
2455static struct clk_branch mmss_spdm_jpeg0_clk = {
2456 .halt_reg = 0x0204,
2457 .clkr = {
2458 .enable_reg = 0x0204,
2459 .enable_mask = BIT(0),
2460 .hw.init = &(struct clk_init_data){
2461 .name = "mmss_spdm_jpeg0_clk",
2462 .parent_names = (const char *[]){
2463 "mmss_spdm_jpeg0_div_clk",
2464 },
2465 .num_parents = 1,
2466 .flags = CLK_SET_RATE_PARENT,
2467 .ops = &clk_branch2_ops,
2468 },
2469 },
2470};
2471
2472static struct clk_branch mmss_spdm_jpeg1_clk = {
2473 .halt_reg = 0x0208,
2474 .clkr = {
2475 .enable_reg = 0x0208,
2476 .enable_mask = BIT(0),
2477 .hw.init = &(struct clk_init_data){
2478 .name = "mmss_spdm_jpeg1_clk",
2479 .parent_names = (const char *[]){
2480 "mmss_spdm_jpeg1_div_clk",
2481 },
2482 .num_parents = 1,
2483 .flags = CLK_SET_RATE_PARENT,
2484 .ops = &clk_branch2_ops,
2485 },
2486 },
2487};
2488
2489static struct clk_branch mmss_spdm_jpeg2_clk = {
2490 .halt_reg = 0x0224,
2491 .clkr = {
2492 .enable_reg = 0x0224,
2493 .enable_mask = BIT(0),
2494 .hw.init = &(struct clk_init_data){
2495 .name = "mmss_spdm_jpeg2_clk",
2496 .parent_names = (const char *[]){
2497 "mmss_spdm_jpeg2_div_clk",
2498 },
2499 .num_parents = 1,
2500 .flags = CLK_SET_RATE_PARENT,
2501 .ops = &clk_branch2_ops,
2502 },
2503 },
2504};
2505
2506static struct clk_branch mmss_spdm_mdp_clk = {
2507 .halt_reg = 0x020c,
2508 .clkr = {
2509 .enable_reg = 0x020c,
2510 .enable_mask = BIT(0),
2511 .hw.init = &(struct clk_init_data){
2512 .name = "mmss_spdm_mdp_clk",
2513 .parent_names = (const char *[]){
2514 "mmss_spdm_mdp_div_clk",
2515 },
2516 .num_parents = 1,
2517 .flags = CLK_SET_RATE_PARENT,
2518 .ops = &clk_branch2_ops,
2519 },
2520 },
2521};
2522
2523static struct clk_branch mmss_spdm_pclk0_clk = {
2524 .halt_reg = 0x0234,
2525 .clkr = {
2526 .enable_reg = 0x0234,
2527 .enable_mask = BIT(0),
2528 .hw.init = &(struct clk_init_data){
2529 .name = "mmss_spdm_pclk0_clk",
2530 .parent_names = (const char *[]){
2531 "mmss_spdm_pclk0_div_clk",
2532 },
2533 .num_parents = 1,
2534 .flags = CLK_SET_RATE_PARENT,
2535 .ops = &clk_branch2_ops,
2536 },
2537 },
2538};
2539
2540static struct clk_branch mmss_spdm_pclk1_clk = {
2541 .halt_reg = 0x0228,
2542 .clkr = {
2543 .enable_reg = 0x0228,
2544 .enable_mask = BIT(0),
2545 .hw.init = &(struct clk_init_data){
2546 .name = "mmss_spdm_pclk1_clk",
2547 .parent_names = (const char *[]){
2548 "mmss_spdm_pclk1_div_clk",
2549 },
2550 .num_parents = 1,
2551 .flags = CLK_SET_RATE_PARENT,
2552 .ops = &clk_branch2_ops,
2553 },
2554 },
2555};
2556
2557static struct clk_branch mmss_spdm_vcodec0_clk = {
2558 .halt_reg = 0x0214,
2559 .clkr = {
2560 .enable_reg = 0x0214,
2561 .enable_mask = BIT(0),
2562 .hw.init = &(struct clk_init_data){
2563 .name = "mmss_spdm_vcodec0_clk",
2564 .parent_names = (const char *[]){
2565 "mmss_spdm_vcodec0_div_clk",
2566 },
2567 .num_parents = 1,
2568 .flags = CLK_SET_RATE_PARENT,
2569 .ops = &clk_branch2_ops,
2570 },
2571 },
2572};
2573
2574static struct clk_branch mmss_spdm_vfe0_clk = {
2575 .halt_reg = 0x0218,
2576 .clkr = {
2577 .enable_reg = 0x0218,
2578 .enable_mask = BIT(0),
2579 .hw.init = &(struct clk_init_data){
2580 .name = "mmss_spdm_vfe0_clk",
2581 .parent_names = (const char *[]){
2582 "mmss_spdm_vfe0_div_clk",
2583 },
2584 .num_parents = 1,
2585 .flags = CLK_SET_RATE_PARENT,
2586 .ops = &clk_branch2_ops,
2587 },
2588 },
2589};
2590
2591static struct clk_branch mmss_spdm_vfe1_clk = {
2592 .halt_reg = 0x021c,
2593 .clkr = {
2594 .enable_reg = 0x021c,
2595 .enable_mask = BIT(0),
2596 .hw.init = &(struct clk_init_data){
2597 .name = "mmss_spdm_vfe1_clk",
2598 .parent_names = (const char *[]){
2599 "mmss_spdm_vfe1_div_clk",
2600 },
2601 .num_parents = 1,
2602 .flags = CLK_SET_RATE_PARENT,
2603 .ops = &clk_branch2_ops,
2604 },
2605 },
2606};
2607
2608static struct clk_branch mmss_spdm_rm_axi_clk = {
2609 .halt_reg = 0x0304,
2610 .clkr = {
2611 .enable_reg = 0x0304,
2612 .enable_mask = BIT(0),
2613 .hw.init = &(struct clk_init_data){
2614 .name = "mmss_spdm_rm_axi_clk",
2615 .parent_names = (const char *[]){
2616 "mmss_axi_clk_src",
2617 },
2618 .num_parents = 1,
2619 .flags = CLK_SET_RATE_PARENT,
2620 .ops = &clk_branch2_ops,
2621 },
2622 },
2623};
2624
2625static struct clk_branch mmss_spdm_rm_ocmemnoc_clk = {
2626 .halt_reg = 0x0308,
2627 .clkr = {
2628 .enable_reg = 0x0308,
2629 .enable_mask = BIT(0),
2630 .hw.init = &(struct clk_init_data){
2631 .name = "mmss_spdm_rm_ocmemnoc_clk",
2632 .parent_names = (const char *[]){
2633 "ocmemnoc_clk_src",
2634 },
2635 .num_parents = 1,
2636 .flags = CLK_SET_RATE_PARENT,
2637 .ops = &clk_branch2_ops,
2638 },
2639 },
2640};
2641
2642
2643static struct clk_branch mmss_misc_ahb_clk = {
2644 .halt_reg = 0x502c,
2645 .clkr = {
2646 .enable_reg = 0x502c,
2647 .enable_mask = BIT(0),
2648 .hw.init = &(struct clk_init_data){
2649 .name = "mmss_misc_ahb_clk",
2650 .parent_names = (const char *[]){
2651 "mmss_ahb_clk_src",
2652 },
2653 .num_parents = 1,
2654 .flags = CLK_SET_RATE_PARENT,
2655 .ops = &clk_branch2_ops,
2656 },
2657 },
2658};
2659
2660static struct clk_branch mmss_mmssnoc_ahb_clk = {
2661 .halt_reg = 0x5024,
2662 .clkr = {
2663 .enable_reg = 0x5024,
2664 .enable_mask = BIT(0),
2665 .hw.init = &(struct clk_init_data){
2666 .name = "mmss_mmssnoc_ahb_clk",
2667 .parent_names = (const char *[]){
2668 "mmss_ahb_clk_src",
2669 },
2670 .num_parents = 1,
2671 .ops = &clk_branch2_ops,
2672 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2673 },
2674 },
2675};
2676
2677static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2678 .halt_reg = 0x5028,
2679 .clkr = {
2680 .enable_reg = 0x5028,
2681 .enable_mask = BIT(0),
2682 .hw.init = &(struct clk_init_data){
2683 .name = "mmss_mmssnoc_bto_ahb_clk",
2684 .parent_names = (const char *[]){
2685 "mmss_ahb_clk_src",
2686 },
2687 .num_parents = 1,
2688 .ops = &clk_branch2_ops,
2689 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2690 },
2691 },
2692};
2693
2694static struct clk_branch mmss_mmssnoc_axi_clk = {
2695 .halt_reg = 0x506c,
2696 .clkr = {
2697 .enable_reg = 0x506c,
2698 .enable_mask = BIT(0),
2699 .hw.init = &(struct clk_init_data){
2700 .name = "mmss_mmssnoc_axi_clk",
2701 .parent_names = (const char *[]){
2702 "mmss_axi_clk_src",
2703 },
2704 .num_parents = 1,
2705 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2706 .ops = &clk_branch2_ops,
2707 },
2708 },
2709};
2710
2711static struct clk_branch mmss_s0_axi_clk = {
2712 .halt_reg = 0x5064,
2713 .clkr = {
2714 .enable_reg = 0x5064,
2715 .enable_mask = BIT(0),
2716 .hw.init = &(struct clk_init_data){
2717 .name = "mmss_s0_axi_clk",
2718 .parent_names = (const char *[]){
2719 "mmss_axi_clk_src",
2720 },
2721 .num_parents = 1,
2722 .ops = &clk_branch2_ops,
2723 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2724 },
2725 },
2726};
2727
2728static struct clk_branch ocmemcx_ahb_clk = {
2729 .halt_reg = 0x405c,
2730 .clkr = {
2731 .enable_reg = 0x405c,
2732 .enable_mask = BIT(0),
2733 .hw.init = &(struct clk_init_data){
2734 .name = "ocmemcx_ahb_clk",
2735 .parent_names = (const char *[]){
2736 "mmss_ahb_clk_src",
2737 },
2738 .num_parents = 1,
2739 .flags = CLK_SET_RATE_PARENT,
2740 .ops = &clk_branch2_ops,
2741 },
2742 },
2743};
2744
2745static struct clk_branch ocmemcx_ocmemnoc_clk = {
2746 .halt_reg = 0x4058,
2747 .clkr = {
2748 .enable_reg = 0x4058,
2749 .enable_mask = BIT(0),
2750 .hw.init = &(struct clk_init_data){
2751 .name = "ocmemcx_ocmemnoc_clk",
2752 .parent_names = (const char *[]){
2753 "ocmemnoc_clk_src",
2754 },
2755 .num_parents = 1,
2756 .flags = CLK_SET_RATE_PARENT,
2757 .ops = &clk_branch2_ops,
2758 },
2759 },
2760};
2761
2762static struct clk_branch oxili_ocmemgx_clk = {
2763 .halt_reg = 0x402c,
2764 .clkr = {
2765 .enable_reg = 0x402c,
2766 .enable_mask = BIT(0),
2767 .hw.init = &(struct clk_init_data){
2768 .name = "oxili_ocmemgx_clk",
2769 .parent_names = (const char *[]){
2770 "gfx3d_clk_src",
2771 },
2772 .num_parents = 1,
2773 .flags = CLK_SET_RATE_PARENT,
2774 .ops = &clk_branch2_ops,
2775 },
2776 },
2777};
2778
2779static struct clk_branch oxili_gfx3d_clk = {
2780 .halt_reg = 0x4028,
2781 .clkr = {
2782 .enable_reg = 0x4028,
2783 .enable_mask = BIT(0),
2784 .hw.init = &(struct clk_init_data){
2785 .name = "oxili_gfx3d_clk",
2786 .parent_names = (const char *[]){
2787 "gfx3d_clk_src",
2788 },
2789 .num_parents = 1,
2790 .flags = CLK_SET_RATE_PARENT,
2791 .ops = &clk_branch2_ops,
2792 },
2793 },
2794};
2795
2796static struct clk_branch oxili_rbbmtimer_clk = {
2797 .halt_reg = 0x40b0,
2798 .clkr = {
2799 .enable_reg = 0x40b0,
2800 .enable_mask = BIT(0),
2801 .hw.init = &(struct clk_init_data){
2802 .name = "oxili_rbbmtimer_clk",
2803 .parent_names = (const char *[]){
2804 "rbbmtimer_clk_src",
2805 },
2806 .num_parents = 1,
2807 .flags = CLK_SET_RATE_PARENT,
2808 .ops = &clk_branch2_ops,
2809 },
2810 },
2811};
2812
2813static struct clk_branch oxilicx_ahb_clk = {
2814 .halt_reg = 0x403c,
2815 .clkr = {
2816 .enable_reg = 0x403c,
2817 .enable_mask = BIT(0),
2818 .hw.init = &(struct clk_init_data){
2819 .name = "oxilicx_ahb_clk",
2820 .parent_names = (const char *[]){
2821 "mmss_ahb_clk_src",
2822 },
2823 .num_parents = 1,
2824 .flags = CLK_SET_RATE_PARENT,
2825 .ops = &clk_branch2_ops,
2826 },
2827 },
2828};
2829
2830static struct clk_branch venus0_ahb_clk = {
2831 .halt_reg = 0x1030,
2832 .clkr = {
2833 .enable_reg = 0x1030,
2834 .enable_mask = BIT(0),
2835 .hw.init = &(struct clk_init_data){
2836 .name = "venus0_ahb_clk",
2837 .parent_names = (const char *[]){
2838 "mmss_ahb_clk_src",
2839 },
2840 .num_parents = 1,
2841 .flags = CLK_SET_RATE_PARENT,
2842 .ops = &clk_branch2_ops,
2843 },
2844 },
2845};
2846
2847static struct clk_branch venus0_axi_clk = {
2848 .halt_reg = 0x1034,
2849 .clkr = {
2850 .enable_reg = 0x1034,
2851 .enable_mask = BIT(0),
2852 .hw.init = &(struct clk_init_data){
2853 .name = "venus0_axi_clk",
2854 .parent_names = (const char *[]){
2855 "mmss_axi_clk_src",
2856 },
2857 .num_parents = 1,
2858 .flags = CLK_SET_RATE_PARENT,
2859 .ops = &clk_branch2_ops,
2860 },
2861 },
2862};
2863
2864static struct clk_branch venus0_core0_vcodec_clk = {
2865 .halt_reg = 0x1048,
2866 .clkr = {
2867 .enable_reg = 0x1048,
2868 .enable_mask = BIT(0),
2869 .hw.init = &(struct clk_init_data){
2870 .name = "venus0_core0_vcodec_clk",
2871 .parent_names = (const char *[]){
2872 "vcodec0_clk_src",
2873 },
2874 .num_parents = 1,
2875 .flags = CLK_SET_RATE_PARENT,
2876 .ops = &clk_branch2_ops,
2877 },
2878 },
2879};
2880
2881static struct clk_branch venus0_core1_vcodec_clk = {
2882 .halt_reg = 0x104c,
2883 .clkr = {
2884 .enable_reg = 0x104c,
2885 .enable_mask = BIT(0),
2886 .hw.init = &(struct clk_init_data){
2887 .name = "venus0_core1_vcodec_clk",
2888 .parent_names = (const char *[]){
2889 "vcodec0_clk_src",
2890 },
2891 .num_parents = 1,
2892 .flags = CLK_SET_RATE_PARENT,
2893 .ops = &clk_branch2_ops,
2894 },
2895 },
2896};
2897
2898static struct clk_branch venus0_ocmemnoc_clk = {
2899 .halt_reg = 0x1038,
2900 .clkr = {
2901 .enable_reg = 0x1038,
2902 .enable_mask = BIT(0),
2903 .hw.init = &(struct clk_init_data){
2904 .name = "venus0_ocmemnoc_clk",
2905 .parent_names = (const char *[]){
2906 "ocmemnoc_clk_src",
2907 },
2908 .num_parents = 1,
2909 .flags = CLK_SET_RATE_PARENT,
2910 .ops = &clk_branch2_ops,
2911 },
2912 },
2913};
2914
2915static struct clk_branch venus0_vcodec0_clk = {
2916 .halt_reg = 0x1028,
2917 .clkr = {
2918 .enable_reg = 0x1028,
2919 .enable_mask = BIT(0),
2920 .hw.init = &(struct clk_init_data){
2921 .name = "venus0_vcodec0_clk",
2922 .parent_names = (const char *[]){
2923 "vcodec0_clk_src",
2924 },
2925 .num_parents = 1,
2926 .flags = CLK_SET_RATE_PARENT,
2927 .ops = &clk_branch2_ops,
2928 },
2929 },
2930};
2931
2932static struct clk_branch vpu_ahb_clk = {
2933 .halt_reg = 0x1430,
2934 .clkr = {
2935 .enable_reg = 0x1430,
2936 .enable_mask = BIT(0),
2937 .hw.init = &(struct clk_init_data){
2938 .name = "vpu_ahb_clk",
2939 .parent_names = (const char *[]){
2940 "mmss_ahb_clk_src",
2941 },
2942 .num_parents = 1,
2943 .flags = CLK_SET_RATE_PARENT,
2944 .ops = &clk_branch2_ops,
2945 },
2946 },
2947};
2948
2949static struct clk_branch vpu_axi_clk = {
2950 .halt_reg = 0x143c,
2951 .clkr = {
2952 .enable_reg = 0x143c,
2953 .enable_mask = BIT(0),
2954 .hw.init = &(struct clk_init_data){
2955 .name = "vpu_axi_clk",
2956 .parent_names = (const char *[]){
2957 "mmss_axi_clk_src",
2958 },
2959 .num_parents = 1,
2960 .flags = CLK_SET_RATE_PARENT,
2961 .ops = &clk_branch2_ops,
2962 },
2963 },
2964};
2965
2966static struct clk_branch vpu_bus_clk = {
2967 .halt_reg = 0x1440,
2968 .clkr = {
2969 .enable_reg = 0x1440,
2970 .enable_mask = BIT(0),
2971 .hw.init = &(struct clk_init_data){
2972 .name = "vpu_bus_clk",
2973 .parent_names = (const char *[]){
2974 "vpu_bus_clk_src",
2975 },
2976 .num_parents = 1,
2977 .flags = CLK_SET_RATE_PARENT,
2978 .ops = &clk_branch2_ops,
2979 },
2980 },
2981};
2982
2983static struct clk_branch vpu_cxo_clk = {
2984 .halt_reg = 0x1434,
2985 .clkr = {
2986 .enable_reg = 0x1434,
2987 .enable_mask = BIT(0),
2988 .hw.init = &(struct clk_init_data){
2989 .name = "vpu_cxo_clk",
2990 .parent_names = (const char *[]){ "xo" },
2991 .num_parents = 1,
2992 .flags = CLK_SET_RATE_PARENT,
2993 .ops = &clk_branch2_ops,
2994 },
2995 },
2996};
2997
2998static struct clk_branch vpu_maple_clk = {
2999 .halt_reg = 0x142c,
3000 .clkr = {
3001 .enable_reg = 0x142c,
3002 .enable_mask = BIT(0),
3003 .hw.init = &(struct clk_init_data){
3004 .name = "vpu_maple_clk",
3005 .parent_names = (const char *[]){
3006 "maple_clk_src",
3007 },
3008 .num_parents = 1,
3009 .flags = CLK_SET_RATE_PARENT,
3010 .ops = &clk_branch2_ops,
3011 },
3012 },
3013};
3014
3015static struct clk_branch vpu_sleep_clk = {
3016 .halt_reg = 0x1438,
3017 .clkr = {
3018 .enable_reg = 0x1438,
3019 .enable_mask = BIT(0),
3020 .hw.init = &(struct clk_init_data){
3021 .name = "vpu_sleep_clk",
3022 .parent_names = (const char *[]){
3023 "sleep_clk_src",
3024 },
3025 .num_parents = 1,
3026 .flags = CLK_SET_RATE_PARENT,
3027 .ops = &clk_branch2_ops,
3028 },
3029 },
3030};
3031
3032static struct clk_branch vpu_vdp_clk = {
3033 .halt_reg = 0x1428,
3034 .clkr = {
3035 .enable_reg = 0x1428,
3036 .enable_mask = BIT(0),
3037 .hw.init = &(struct clk_init_data){
3038 .name = "vpu_vdp_clk",
3039 .parent_names = (const char *[]){
3040 "vdp_clk_src",
3041 },
3042 .num_parents = 1,
3043 .flags = CLK_SET_RATE_PARENT,
3044 .ops = &clk_branch2_ops,
3045 },
3046 },
3047};
3048
3049static const struct pll_config mmpll1_config = {
3050 .l = 60,
3051 .m = 25,
3052 .n = 32,
3053 .vco_val = 0x0,
3054 .vco_mask = 0x3 << 20,
3055 .pre_div_val = 0x0,
3056 .pre_div_mask = 0x7 << 12,
3057 .post_div_val = 0x0,
3058 .post_div_mask = 0x3 << 8,
3059 .mn_ena_mask = BIT(24),
3060 .main_output_mask = BIT(0),
3061};
3062
3063static const struct pll_config mmpll3_config = {
3064 .l = 48,
3065 .m = 7,
3066 .n = 16,
3067 .vco_val = 0x0,
3068 .vco_mask = 0x3 << 20,
3069 .pre_div_val = 0x0,
3070 .pre_div_mask = 0x7 << 12,
3071 .post_div_val = 0x0,
3072 .post_div_mask = 0x3 << 8,
3073 .mn_ena_mask = BIT(24),
3074 .main_output_mask = BIT(0),
3075 .aux_output_mask = BIT(1),
3076};
3077
3078static struct clk_regmap *mmcc_apq8084_clocks[] = {
3079 [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
3080 [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
3081 [MMPLL0] = &mmpll0.clkr,
3082 [MMPLL0_VOTE] = &mmpll0_vote,
3083 [MMPLL1] = &mmpll1.clkr,
3084 [MMPLL1_VOTE] = &mmpll1_vote,
3085 [MMPLL2] = &mmpll2.clkr,
3086 [MMPLL3] = &mmpll3.clkr,
3087 [MMPLL4] = &mmpll4.clkr,
3088 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3089 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3090 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3091 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
3092 [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
3093 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3094 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3095 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3096 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3097 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3098 [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
3099 [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
3100 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3101 [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
3102 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
3103 [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
3104 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
3105 [VP_CLK_SRC] = &vp_clk_src.clkr,
3106 [CCI_CLK_SRC] = &cci_clk_src.clkr,
3107 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3108 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3109 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3110 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3111 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
3112 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
3113 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3114 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3115 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
3116 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3117 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3118 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3119 [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
3120 [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
3121 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3122 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3123 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
3124 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3125 [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
3126 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
3127 [MAPLE_CLK_SRC] = &maple_clk_src.clkr,
3128 [VDP_CLK_SRC] = &vdp_clk_src.clkr,
3129 [VPU_BUS_CLK_SRC] = &vpu_bus_clk_src.clkr,
3130 [MMSS_CXO_CLK] = &mmss_cxo_clk.clkr,
3131 [MMSS_SLEEPCLK_CLK] = &mmss_sleepclk_clk.clkr,
3132 [AVSYNC_AHB_CLK] = &avsync_ahb_clk.clkr,
3133 [AVSYNC_EDPPIXEL_CLK] = &avsync_edppixel_clk.clkr,
3134 [AVSYNC_EXTPCLK_CLK] = &avsync_extpclk_clk.clkr,
3135 [AVSYNC_PCLK0_CLK] = &avsync_pclk0_clk.clkr,
3136 [AVSYNC_PCLK1_CLK] = &avsync_pclk1_clk.clkr,
3137 [AVSYNC_VP_CLK] = &avsync_vp_clk.clkr,
3138 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
3139 [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
3140 [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
3141 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
3142 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
3143 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
3144 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
3145 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
3146 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
3147 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
3148 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
3149 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
3150 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
3151 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
3152 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
3153 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
3154 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
3155 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
3156 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
3157 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
3158 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
3159 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
3160 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
3161 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
3162 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
3163 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
3164 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
3165 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
3166 [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
3167 [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
3168 [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
3169 [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
3170 [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
3171 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
3172 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
3173 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
3174 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
3175 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
3176 [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
3177 [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
3178 [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
3179 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
3180 [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
3181 [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
3182 [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
3183 [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
3184 [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
3185 [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
3186 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
3187 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
3188 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
3189 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
3190 [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
3191 [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
3192 [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
3193 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
3194 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
3195 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
3196 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
3197 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
3198 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
3199 [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
3200 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
3201 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
3202 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
3203 [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
3204 [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
3205 [MMSS_SPDM_AHB_CLK] = &mmss_spdm_ahb_clk.clkr,
3206 [MMSS_SPDM_AXI_CLK] = &mmss_spdm_axi_clk.clkr,
3207 [MMSS_SPDM_CSI0_CLK] = &mmss_spdm_csi0_clk.clkr,
3208 [MMSS_SPDM_GFX3D_CLK] = &mmss_spdm_gfx3d_clk.clkr,
3209 [MMSS_SPDM_JPEG0_CLK] = &mmss_spdm_jpeg0_clk.clkr,
3210 [MMSS_SPDM_JPEG1_CLK] = &mmss_spdm_jpeg1_clk.clkr,
3211 [MMSS_SPDM_JPEG2_CLK] = &mmss_spdm_jpeg2_clk.clkr,
3212 [MMSS_SPDM_MDP_CLK] = &mmss_spdm_mdp_clk.clkr,
3213 [MMSS_SPDM_PCLK0_CLK] = &mmss_spdm_pclk0_clk.clkr,
3214 [MMSS_SPDM_PCLK1_CLK] = &mmss_spdm_pclk1_clk.clkr,
3215 [MMSS_SPDM_VCODEC0_CLK] = &mmss_spdm_vcodec0_clk.clkr,
3216 [MMSS_SPDM_VFE0_CLK] = &mmss_spdm_vfe0_clk.clkr,
3217 [MMSS_SPDM_VFE1_CLK] = &mmss_spdm_vfe1_clk.clkr,
3218 [MMSS_SPDM_RM_AXI_CLK] = &mmss_spdm_rm_axi_clk.clkr,
3219 [MMSS_SPDM_RM_OCMEMNOC_CLK] = &mmss_spdm_rm_ocmemnoc_clk.clkr,
3220 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
3221 [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
3222 [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
3223 [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
3224 [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
3225 [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
3226 [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
3227 [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
3228 [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
3229 [OXILI_RBBMTIMER_CLK] = &oxili_rbbmtimer_clk.clkr,
3230 [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
3231 [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
3232 [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
3233 [VENUS0_CORE0_VCODEC_CLK] = &venus0_core0_vcodec_clk.clkr,
3234 [VENUS0_CORE1_VCODEC_CLK] = &venus0_core1_vcodec_clk.clkr,
3235 [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
3236 [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
3237 [VPU_AHB_CLK] = &vpu_ahb_clk.clkr,
3238 [VPU_AXI_CLK] = &vpu_axi_clk.clkr,
3239 [VPU_BUS_CLK] = &vpu_bus_clk.clkr,
3240 [VPU_CXO_CLK] = &vpu_cxo_clk.clkr,
3241 [VPU_MAPLE_CLK] = &vpu_maple_clk.clkr,
3242 [VPU_SLEEP_CLK] = &vpu_sleep_clk.clkr,
3243 [VPU_VDP_CLK] = &vpu_vdp_clk.clkr,
3244};
3245
3246static const struct qcom_reset_map mmcc_apq8084_resets[] = {
3247 [MMSS_SPDM_RESET] = { 0x0200 },
3248 [MMSS_SPDM_RM_RESET] = { 0x0300 },
3249 [VENUS0_RESET] = { 0x1020 },
3250 [VPU_RESET] = { 0x1400 },
3251 [MDSS_RESET] = { 0x2300 },
3252 [AVSYNC_RESET] = { 0x2400 },
3253 [CAMSS_PHY0_RESET] = { 0x3020 },
3254 [CAMSS_PHY1_RESET] = { 0x3050 },
3255 [CAMSS_PHY2_RESET] = { 0x3080 },
3256 [CAMSS_CSI0_RESET] = { 0x30b0 },
3257 [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
3258 [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
3259 [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
3260 [CAMSS_CSI1_RESET] = { 0x3120 },
3261 [CAMSS_CSI1PHY_RESET] = { 0x3130 },
3262 [CAMSS_CSI1RDI_RESET] = { 0x3140 },
3263 [CAMSS_CSI1PIX_RESET] = { 0x3150 },
3264 [CAMSS_CSI2_RESET] = { 0x3180 },
3265 [CAMSS_CSI2PHY_RESET] = { 0x3190 },
3266 [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
3267 [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
3268 [CAMSS_CSI3_RESET] = { 0x31e0 },
3269 [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
3270 [CAMSS_CSI3RDI_RESET] = { 0x3200 },
3271 [CAMSS_CSI3PIX_RESET] = { 0x3210 },
3272 [CAMSS_ISPIF_RESET] = { 0x3220 },
3273 [CAMSS_CCI_RESET] = { 0x3340 },
3274 [CAMSS_MCLK0_RESET] = { 0x3380 },
3275 [CAMSS_MCLK1_RESET] = { 0x33b0 },
3276 [CAMSS_MCLK2_RESET] = { 0x33e0 },
3277 [CAMSS_MCLK3_RESET] = { 0x3410 },
3278 [CAMSS_GP0_RESET] = { 0x3440 },
3279 [CAMSS_GP1_RESET] = { 0x3470 },
3280 [CAMSS_TOP_RESET] = { 0x3480 },
3281 [CAMSS_AHB_RESET] = { 0x3488 },
3282 [CAMSS_MICRO_RESET] = { 0x3490 },
3283 [CAMSS_JPEG_RESET] = { 0x35a0 },
3284 [CAMSS_VFE_RESET] = { 0x36a0 },
3285 [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
3286 [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
3287 [OXILI_RESET] = { 0x4020 },
3288 [OXILICX_RESET] = { 0x4030 },
3289 [OCMEMCX_RESET] = { 0x4050 },
3290 [MMSS_RBCRP_RESET] = { 0x4080 },
3291 [MMSSNOCAHB_RESET] = { 0x5020 },
3292 [MMSSNOCAXI_RESET] = { 0x5060 },
3293};
3294
3295static const struct regmap_config mmcc_apq8084_regmap_config = {
3296 .reg_bits = 32,
3297 .reg_stride = 4,
3298 .val_bits = 32,
3299 .max_register = 0x5104,
3300 .fast_io = true,
3301};
3302
3303static const struct qcom_cc_desc mmcc_apq8084_desc = {
3304 .config = &mmcc_apq8084_regmap_config,
3305 .clks = mmcc_apq8084_clocks,
3306 .num_clks = ARRAY_SIZE(mmcc_apq8084_clocks),
3307 .resets = mmcc_apq8084_resets,
3308 .num_resets = ARRAY_SIZE(mmcc_apq8084_resets),
3309};
3310
3311static const struct of_device_id mmcc_apq8084_match_table[] = {
3312 { .compatible = "qcom,mmcc-apq8084" },
3313 { }
3314};
3315MODULE_DEVICE_TABLE(of, mmcc_apq8084_match_table);
3316
3317static int mmcc_apq8084_probe(struct platform_device *pdev)
3318{
3319 int ret;
3320 struct regmap *regmap;
3321
3322 ret = qcom_cc_probe(pdev, &mmcc_apq8084_desc);
3323 if (ret)
3324 return ret;
3325
3326 regmap = dev_get_regmap(&pdev->dev, NULL);
3327 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
3328 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
3329
3330 return 0;
3331}
3332
3333static int mmcc_apq8084_remove(struct platform_device *pdev)
3334{
3335 qcom_cc_remove(pdev);
3336 return 0;
3337}
3338
3339static struct platform_driver mmcc_apq8084_driver = {
3340 .probe = mmcc_apq8084_probe,
3341 .remove = mmcc_apq8084_remove,
3342 .driver = {
3343 .name = "mmcc-apq8084",
3344 .owner = THIS_MODULE,
3345 .of_match_table = mmcc_apq8084_match_table,
3346 },
3347};
3348module_platform_driver(mmcc_apq8084_driver);
3349
3350MODULE_DESCRIPTION("QCOM MMCC APQ8084 Driver");
3351MODULE_LICENSE("GPL v2");
3352MODULE_ALIAS("platform:mmcc-apq8084");
diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c
index 4c449b3170f6..2e80a219b8ea 100644
--- a/drivers/clk/qcom/mmcc-msm8960.c
+++ b/drivers/clk/qcom/mmcc-msm8960.c
@@ -37,6 +37,9 @@
37#define P_PLL8 1 37#define P_PLL8 1
38#define P_PLL2 2 38#define P_PLL2 2
39#define P_PLL3 3 39#define P_PLL3 3
40#define P_PLL15 3
41
42#define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
40 43
41static u8 mmcc_pxo_pll8_pll2_map[] = { 44static u8 mmcc_pxo_pll8_pll2_map[] = {
42 [P_PXO] = 0, 45 [P_PXO] = 0,
@@ -57,10 +60,24 @@ static u8 mmcc_pxo_pll8_pll2_pll3_map[] = {
57 [P_PLL3] = 3, 60 [P_PLL3] = 3,
58}; 61};
59 62
60static const char *mmcc_pxo_pll8_pll2_pll3[] = { 63static const char *mmcc_pxo_pll8_pll2_pll15[] = {
61 "pxo", 64 "pxo",
65 "pll8_vote",
62 "pll2", 66 "pll2",
67 "pll15",
68};
69
70static u8 mmcc_pxo_pll8_pll2_pll15_map[] = {
71 [P_PXO] = 0,
72 [P_PLL8] = 2,
73 [P_PLL2] = 1,
74 [P_PLL15] = 3,
75};
76
77static const char *mmcc_pxo_pll8_pll2_pll3[] = {
78 "pxo",
63 "pll8_vote", 79 "pll8_vote",
80 "pll2",
64 "pll3", 81 "pll3",
65}; 82};
66 83
@@ -80,6 +97,36 @@ static struct clk_pll pll2 = {
80 }, 97 },
81}; 98};
82 99
100static struct clk_pll pll15 = {
101 .l_reg = 0x33c,
102 .m_reg = 0x340,
103 .n_reg = 0x344,
104 .config_reg = 0x348,
105 .mode_reg = 0x338,
106 .status_reg = 0x350,
107 .status_bit = 16,
108 .clkr.hw.init = &(struct clk_init_data){
109 .name = "pll15",
110 .parent_names = (const char *[]){ "pxo" },
111 .num_parents = 1,
112 .ops = &clk_pll_ops,
113 },
114};
115
116static const struct pll_config pll15_config = {
117 .l = 33,
118 .m = 1,
119 .n = 3,
120 .vco_val = 0x2 << 16,
121 .vco_mask = 0x3 << 16,
122 .pre_div_val = 0x0,
123 .pre_div_mask = BIT(19),
124 .post_div_val = 0x0,
125 .post_div_mask = 0x3 << 20,
126 .mn_ena_mask = BIT(22),
127 .main_output_mask = BIT(23),
128};
129
83static struct freq_tbl clk_tbl_cam[] = { 130static struct freq_tbl clk_tbl_cam[] = {
84 { 6000000, P_PLL8, 4, 1, 16 }, 131 { 6000000, P_PLL8, 4, 1, 16 },
85 { 8000000, P_PLL8, 4, 1, 12 }, 132 { 8000000, P_PLL8, 4, 1, 12 },
@@ -710,18 +757,18 @@ static struct clk_branch csiphy2_timer_clk = {
710}; 757};
711 758
712static struct freq_tbl clk_tbl_gfx2d[] = { 759static struct freq_tbl clk_tbl_gfx2d[] = {
713 { 27000000, P_PXO, 1, 0 }, 760 F_MN( 27000000, P_PXO, 1, 0),
714 { 48000000, P_PLL8, 1, 8 }, 761 F_MN( 48000000, P_PLL8, 1, 8),
715 { 54857000, P_PLL8, 1, 7 }, 762 F_MN( 54857000, P_PLL8, 1, 7),
716 { 64000000, P_PLL8, 1, 6 }, 763 F_MN( 64000000, P_PLL8, 1, 6),
717 { 76800000, P_PLL8, 1, 5 }, 764 F_MN( 76800000, P_PLL8, 1, 5),
718 { 96000000, P_PLL8, 1, 4 }, 765 F_MN( 96000000, P_PLL8, 1, 4),
719 { 128000000, P_PLL8, 1, 3 }, 766 F_MN(128000000, P_PLL8, 1, 3),
720 { 145455000, P_PLL2, 2, 11 }, 767 F_MN(145455000, P_PLL2, 2, 11),
721 { 160000000, P_PLL2, 1, 5 }, 768 F_MN(160000000, P_PLL2, 1, 5),
722 { 177778000, P_PLL2, 2, 9 }, 769 F_MN(177778000, P_PLL2, 2, 9),
723 { 200000000, P_PLL2, 1, 4 }, 770 F_MN(200000000, P_PLL2, 1, 4),
724 { 228571000, P_PLL2, 2, 7 }, 771 F_MN(228571000, P_PLL2, 2, 7),
725 { } 772 { }
726}; 773};
727 774
@@ -842,22 +889,43 @@ static struct clk_branch gfx2d1_clk = {
842}; 889};
843 890
844static struct freq_tbl clk_tbl_gfx3d[] = { 891static struct freq_tbl clk_tbl_gfx3d[] = {
845 { 27000000, P_PXO, 1, 0 }, 892 F_MN( 27000000, P_PXO, 1, 0),
846 { 48000000, P_PLL8, 1, 8 }, 893 F_MN( 48000000, P_PLL8, 1, 8),
847 { 54857000, P_PLL8, 1, 7 }, 894 F_MN( 54857000, P_PLL8, 1, 7),
848 { 64000000, P_PLL8, 1, 6 }, 895 F_MN( 64000000, P_PLL8, 1, 6),
849 { 76800000, P_PLL8, 1, 5 }, 896 F_MN( 76800000, P_PLL8, 1, 5),
850 { 96000000, P_PLL8, 1, 4 }, 897 F_MN( 96000000, P_PLL8, 1, 4),
851 { 128000000, P_PLL8, 1, 3 }, 898 F_MN(128000000, P_PLL8, 1, 3),
852 { 145455000, P_PLL2, 2, 11 }, 899 F_MN(145455000, P_PLL2, 2, 11),
853 { 160000000, P_PLL2, 1, 5 }, 900 F_MN(160000000, P_PLL2, 1, 5),
854 { 177778000, P_PLL2, 2, 9 }, 901 F_MN(177778000, P_PLL2, 2, 9),
855 { 200000000, P_PLL2, 1, 4 }, 902 F_MN(200000000, P_PLL2, 1, 4),
856 { 228571000, P_PLL2, 2, 7 }, 903 F_MN(228571000, P_PLL2, 2, 7),
857 { 266667000, P_PLL2, 1, 3 }, 904 F_MN(266667000, P_PLL2, 1, 3),
858 { 300000000, P_PLL3, 1, 4 }, 905 F_MN(300000000, P_PLL3, 1, 4),
859 { 320000000, P_PLL2, 2, 5 }, 906 F_MN(320000000, P_PLL2, 2, 5),
860 { 400000000, P_PLL2, 1, 2 }, 907 F_MN(400000000, P_PLL2, 1, 2),
908 { }
909};
910
911static struct freq_tbl clk_tbl_gfx3d_8064[] = {
912 F_MN( 27000000, P_PXO, 0, 0),
913 F_MN( 48000000, P_PLL8, 1, 8),
914 F_MN( 54857000, P_PLL8, 1, 7),
915 F_MN( 64000000, P_PLL8, 1, 6),
916 F_MN( 76800000, P_PLL8, 1, 5),
917 F_MN( 96000000, P_PLL8, 1, 4),
918 F_MN(128000000, P_PLL8, 1, 3),
919 F_MN(145455000, P_PLL2, 2, 11),
920 F_MN(160000000, P_PLL2, 1, 5),
921 F_MN(177778000, P_PLL2, 2, 9),
922 F_MN(192000000, P_PLL8, 1, 2),
923 F_MN(200000000, P_PLL2, 1, 4),
924 F_MN(228571000, P_PLL2, 2, 7),
925 F_MN(266667000, P_PLL2, 1, 3),
926 F_MN(320000000, P_PLL2, 2, 5),
927 F_MN(400000000, P_PLL2, 1, 2),
928 F_MN(450000000, P_PLL15, 1, 2),
861 { } 929 { }
862}; 930};
863 931
@@ -897,12 +965,19 @@ static struct clk_dyn_rcg gfx3d_src = {
897 .hw.init = &(struct clk_init_data){ 965 .hw.init = &(struct clk_init_data){
898 .name = "gfx3d_src", 966 .name = "gfx3d_src",
899 .parent_names = mmcc_pxo_pll8_pll2_pll3, 967 .parent_names = mmcc_pxo_pll8_pll2_pll3,
900 .num_parents = 3, 968 .num_parents = 4,
901 .ops = &clk_dyn_rcg_ops, 969 .ops = &clk_dyn_rcg_ops,
902 }, 970 },
903 }, 971 },
904}; 972};
905 973
974static const struct clk_init_data gfx3d_8064_init = {
975 .name = "gfx3d_src",
976 .parent_names = mmcc_pxo_pll8_pll2_pll15,
977 .num_parents = 4,
978 .ops = &clk_dyn_rcg_ops,
979};
980
906static struct clk_branch gfx3d_clk = { 981static struct clk_branch gfx3d_clk = {
907 .halt_reg = 0x01c8, 982 .halt_reg = 0x01c8,
908 .halt_bit = 4, 983 .halt_bit = 4,
@@ -919,6 +994,91 @@ static struct clk_branch gfx3d_clk = {
919 }, 994 },
920}; 995};
921 996
997static struct freq_tbl clk_tbl_vcap[] = {
998 F_MN( 27000000, P_PXO, 0, 0),
999 F_MN( 54860000, P_PLL8, 1, 7),
1000 F_MN( 64000000, P_PLL8, 1, 6),
1001 F_MN( 76800000, P_PLL8, 1, 5),
1002 F_MN(128000000, P_PLL8, 1, 3),
1003 F_MN(160000000, P_PLL2, 1, 5),
1004 F_MN(200000000, P_PLL2, 1, 4),
1005 { }
1006};
1007
1008static struct clk_dyn_rcg vcap_src = {
1009 .ns_reg = 0x021c,
1010 .md_reg[0] = 0x01ec,
1011 .md_reg[1] = 0x0218,
1012 .mn[0] = {
1013 .mnctr_en_bit = 8,
1014 .mnctr_reset_bit = 23,
1015 .mnctr_mode_shift = 9,
1016 .n_val_shift = 18,
1017 .m_val_shift = 4,
1018 .width = 4,
1019 },
1020 .mn[1] = {
1021 .mnctr_en_bit = 5,
1022 .mnctr_reset_bit = 22,
1023 .mnctr_mode_shift = 6,
1024 .n_val_shift = 14,
1025 .m_val_shift = 4,
1026 .width = 4,
1027 },
1028 .s[0] = {
1029 .src_sel_shift = 3,
1030 .parent_map = mmcc_pxo_pll8_pll2_map,
1031 },
1032 .s[1] = {
1033 .src_sel_shift = 0,
1034 .parent_map = mmcc_pxo_pll8_pll2_map,
1035 },
1036 .mux_sel_bit = 11,
1037 .freq_tbl = clk_tbl_vcap,
1038 .clkr = {
1039 .enable_reg = 0x0178,
1040 .enable_mask = BIT(2),
1041 .hw.init = &(struct clk_init_data){
1042 .name = "vcap_src",
1043 .parent_names = mmcc_pxo_pll8_pll2,
1044 .num_parents = 3,
1045 .ops = &clk_dyn_rcg_ops,
1046 },
1047 },
1048};
1049
1050static struct clk_branch vcap_clk = {
1051 .halt_reg = 0x0240,
1052 .halt_bit = 15,
1053 .clkr = {
1054 .enable_reg = 0x0178,
1055 .enable_mask = BIT(0),
1056 .hw.init = &(struct clk_init_data){
1057 .name = "vcap_clk",
1058 .parent_names = (const char *[]){ "vcap_src" },
1059 .num_parents = 1,
1060 .ops = &clk_branch_ops,
1061 .flags = CLK_SET_RATE_PARENT,
1062 },
1063 },
1064};
1065
1066static struct clk_branch vcap_npl_clk = {
1067 .halt_reg = 0x0240,
1068 .halt_bit = 25,
1069 .clkr = {
1070 .enable_reg = 0x0178,
1071 .enable_mask = BIT(13),
1072 .hw.init = &(struct clk_init_data){
1073 .name = "vcap_npl_clk",
1074 .parent_names = (const char *[]){ "vcap_src" },
1075 .num_parents = 1,
1076 .ops = &clk_branch_ops,
1077 .flags = CLK_SET_RATE_PARENT,
1078 },
1079 },
1080};
1081
922static struct freq_tbl clk_tbl_ijpeg[] = { 1082static struct freq_tbl clk_tbl_ijpeg[] = {
923 { 27000000, P_PXO, 1, 0, 0 }, 1083 { 27000000, P_PXO, 1, 0, 0 },
924 { 36570000, P_PLL8, 1, 2, 21 }, 1084 { 36570000, P_PLL8, 1, 2, 21 },
@@ -995,7 +1155,7 @@ static struct clk_rcg jpegd_src = {
995 .ns_reg = 0x00ac, 1155 .ns_reg = 0x00ac,
996 .p = { 1156 .p = {
997 .pre_div_shift = 12, 1157 .pre_div_shift = 12,
998 .pre_div_width = 2, 1158 .pre_div_width = 4,
999 }, 1159 },
1000 .s = { 1160 .s = {
1001 .src_sel_shift = 0, 1161 .src_sel_shift = 0,
@@ -1115,7 +1275,7 @@ static struct clk_branch mdp_lut_clk = {
1115 .enable_reg = 0x016c, 1275 .enable_reg = 0x016c,
1116 .enable_mask = BIT(0), 1276 .enable_mask = BIT(0),
1117 .hw.init = &(struct clk_init_data){ 1277 .hw.init = &(struct clk_init_data){
1118 .parent_names = (const char *[]){ "mdp_clk" }, 1278 .parent_names = (const char *[]){ "mdp_src" },
1119 .num_parents = 1, 1279 .num_parents = 1,
1120 .name = "mdp_lut_clk", 1280 .name = "mdp_lut_clk",
1121 .ops = &clk_branch_ops, 1281 .ops = &clk_branch_ops,
@@ -1218,12 +1378,7 @@ static const char *mmcc_pxo_hdmi[] = {
1218}; 1378};
1219 1379
1220static struct freq_tbl clk_tbl_tv[] = { 1380static struct freq_tbl clk_tbl_tv[] = {
1221 { 25200000, P_HDMI_PLL, 1, 0, 0 }, 1381 { .src = P_HDMI_PLL, .pre_div = 1 },
1222 { 27000000, P_HDMI_PLL, 1, 0, 0 },
1223 { 27030000, P_HDMI_PLL, 1, 0, 0 },
1224 { 74250000, P_HDMI_PLL, 1, 0, 0 },
1225 { 108000000, P_HDMI_PLL, 1, 0, 0 },
1226 { 148500000, P_HDMI_PLL, 1, 0, 0 },
1227 { } 1382 { }
1228}; 1383};
1229 1384
@@ -1254,7 +1409,7 @@ static struct clk_rcg tv_src = {
1254 .name = "tv_src", 1409 .name = "tv_src",
1255 .parent_names = mmcc_pxo_hdmi, 1410 .parent_names = mmcc_pxo_hdmi,
1256 .num_parents = 2, 1411 .num_parents = 2,
1257 .ops = &clk_rcg_ops, 1412 .ops = &clk_rcg_bypass_ops,
1258 .flags = CLK_SET_RATE_PARENT, 1413 .flags = CLK_SET_RATE_PARENT,
1259 }, 1414 },
1260 }, 1415 },
@@ -1326,6 +1481,38 @@ static struct clk_branch hdmi_tv_clk = {
1326 }, 1481 },
1327}; 1482};
1328 1483
1484static struct clk_branch rgb_tv_clk = {
1485 .halt_reg = 0x0240,
1486 .halt_bit = 27,
1487 .clkr = {
1488 .enable_reg = 0x0124,
1489 .enable_mask = BIT(14),
1490 .hw.init = &(struct clk_init_data){
1491 .parent_names = tv_src_name,
1492 .num_parents = 1,
1493 .name = "rgb_tv_clk",
1494 .ops = &clk_branch_ops,
1495 .flags = CLK_SET_RATE_PARENT,
1496 },
1497 },
1498};
1499
1500static struct clk_branch npl_tv_clk = {
1501 .halt_reg = 0x0240,
1502 .halt_bit = 26,
1503 .clkr = {
1504 .enable_reg = 0x0124,
1505 .enable_mask = BIT(16),
1506 .hw.init = &(struct clk_init_data){
1507 .parent_names = tv_src_name,
1508 .num_parents = 1,
1509 .name = "npl_tv_clk",
1510 .ops = &clk_branch_ops,
1511 .flags = CLK_SET_RATE_PARENT,
1512 },
1513 },
1514};
1515
1329static struct clk_branch hdmi_app_clk = { 1516static struct clk_branch hdmi_app_clk = {
1330 .halt_reg = 0x01cc, 1517 .halt_reg = 0x01cc,
1331 .halt_bit = 25, 1518 .halt_bit = 25,
@@ -1342,15 +1529,15 @@ static struct clk_branch hdmi_app_clk = {
1342}; 1529};
1343 1530
1344static struct freq_tbl clk_tbl_vcodec[] = { 1531static struct freq_tbl clk_tbl_vcodec[] = {
1345 { 27000000, P_PXO, 1, 0 }, 1532 F_MN( 27000000, P_PXO, 1, 0),
1346 { 32000000, P_PLL8, 1, 12 }, 1533 F_MN( 32000000, P_PLL8, 1, 12),
1347 { 48000000, P_PLL8, 1, 8 }, 1534 F_MN( 48000000, P_PLL8, 1, 8),
1348 { 54860000, P_PLL8, 1, 7 }, 1535 F_MN( 54860000, P_PLL8, 1, 7),
1349 { 96000000, P_PLL8, 1, 4 }, 1536 F_MN( 96000000, P_PLL8, 1, 4),
1350 { 133330000, P_PLL2, 1, 6 }, 1537 F_MN(133330000, P_PLL2, 1, 6),
1351 { 200000000, P_PLL2, 1, 4 }, 1538 F_MN(200000000, P_PLL2, 1, 4),
1352 { 228570000, P_PLL2, 2, 7 }, 1539 F_MN(228570000, P_PLL2, 2, 7),
1353 { 266670000, P_PLL2, 1, 3 }, 1540 F_MN(266670000, P_PLL2, 1, 3),
1354 { } 1541 { }
1355}; 1542};
1356 1543
@@ -1701,6 +1888,22 @@ static struct clk_branch rot_axi_clk = {
1701 }, 1888 },
1702}; 1889};
1703 1890
1891static struct clk_branch vcap_axi_clk = {
1892 .halt_reg = 0x0240,
1893 .halt_bit = 20,
1894 .hwcg_reg = 0x0244,
1895 .hwcg_bit = 11,
1896 .clkr = {
1897 .enable_reg = 0x0244,
1898 .enable_mask = BIT(12),
1899 .hw.init = &(struct clk_init_data){
1900 .name = "vcap_axi_clk",
1901 .ops = &clk_branch_ops,
1902 .flags = CLK_IS_ROOT,
1903 },
1904 },
1905};
1906
1704static struct clk_branch vpe_axi_clk = { 1907static struct clk_branch vpe_axi_clk = {
1705 .hwcg_reg = 0x0020, 1908 .hwcg_reg = 0x0020,
1706 .hwcg_bit = 27, 1909 .hwcg_bit = 27,
@@ -2003,6 +2206,20 @@ static struct clk_branch tv_enc_ahb_clk = {
2003 }, 2206 },
2004}; 2207};
2005 2208
2209static struct clk_branch vcap_ahb_clk = {
2210 .halt_reg = 0x0240,
2211 .halt_bit = 23,
2212 .clkr = {
2213 .enable_reg = 0x0248,
2214 .enable_mask = BIT(1),
2215 .hw.init = &(struct clk_init_data){
2216 .name = "vcap_ahb_clk",
2217 .ops = &clk_branch_ops,
2218 .flags = CLK_IS_ROOT,
2219 },
2220 },
2221};
2222
2006static struct clk_branch vcodec_ahb_clk = { 2223static struct clk_branch vcodec_ahb_clk = {
2007 .hwcg_reg = 0x0038, 2224 .hwcg_reg = 0x0038,
2008 .hwcg_bit = 26, 2225 .hwcg_bit = 26,
@@ -2215,6 +2432,175 @@ static const struct qcom_reset_map mmcc_msm8960_resets[] = {
2215 [CSI_RDI2_RESET] = { 0x0214 }, 2432 [CSI_RDI2_RESET] = { 0x0214 },
2216}; 2433};
2217 2434
2435static struct clk_regmap *mmcc_apq8064_clks[] = {
2436 [AMP_AHB_CLK] = &amp_ahb_clk.clkr,
2437 [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2438 [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2439 [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2440 [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2441 [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2442 [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2443 [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2444 [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2445 [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2446 [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2447 [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2448 [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2449 [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2450 [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2451 [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2452 [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2453 [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2454 [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2455 [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2456 [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2457 [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2458 [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2459 [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2460 [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2461 [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2462 [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2463 [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2464 [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2465 [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2466 [CSI0_SRC] = &csi0_src.clkr,
2467 [CSI0_CLK] = &csi0_clk.clkr,
2468 [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2469 [CSI1_SRC] = &csi1_src.clkr,
2470 [CSI1_CLK] = &csi1_clk.clkr,
2471 [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2472 [CSI2_SRC] = &csi2_src.clkr,
2473 [CSI2_CLK] = &csi2_clk.clkr,
2474 [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2475 [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2476 [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2477 [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2478 [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2479 [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2480 [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2481 [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2482 [GFX3D_SRC] = &gfx3d_src.clkr,
2483 [GFX3D_CLK] = &gfx3d_clk.clkr,
2484 [IJPEG_SRC] = &ijpeg_src.clkr,
2485 [IJPEG_CLK] = &ijpeg_clk.clkr,
2486 [JPEGD_SRC] = &jpegd_src.clkr,
2487 [JPEGD_CLK] = &jpegd_clk.clkr,
2488 [MDP_SRC] = &mdp_src.clkr,
2489 [MDP_CLK] = &mdp_clk.clkr,
2490 [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2491 [ROT_SRC] = &rot_src.clkr,
2492 [ROT_CLK] = &rot_clk.clkr,
2493 [TV_DAC_CLK] = &tv_dac_clk.clkr,
2494 [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2495 [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2496 [TV_SRC] = &tv_src.clkr,
2497 [VCODEC_SRC] = &vcodec_src.clkr,
2498 [VCODEC_CLK] = &vcodec_clk.clkr,
2499 [VFE_SRC] = &vfe_src.clkr,
2500 [VFE_CLK] = &vfe_clk.clkr,
2501 [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2502 [VPE_SRC] = &vpe_src.clkr,
2503 [VPE_CLK] = &vpe_clk.clkr,
2504 [CAMCLK0_SRC] = &camclk0_src.clkr,
2505 [CAMCLK0_CLK] = &camclk0_clk.clkr,
2506 [CAMCLK1_SRC] = &camclk1_src.clkr,
2507 [CAMCLK1_CLK] = &camclk1_clk.clkr,
2508 [CAMCLK2_SRC] = &camclk2_src.clkr,
2509 [CAMCLK2_CLK] = &camclk2_clk.clkr,
2510 [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2511 [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2512 [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2513 [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2514 [PLL2] = &pll2.clkr,
2515 [RGB_TV_CLK] = &rgb_tv_clk.clkr,
2516 [NPL_TV_CLK] = &npl_tv_clk.clkr,
2517 [VCAP_AHB_CLK] = &vcap_ahb_clk.clkr,
2518 [VCAP_AXI_CLK] = &vcap_axi_clk.clkr,
2519 [VCAP_SRC] = &vcap_src.clkr,
2520 [VCAP_CLK] = &vcap_clk.clkr,
2521 [VCAP_NPL_CLK] = &vcap_npl_clk.clkr,
2522 [PLL15] = &pll15.clkr,
2523};
2524
2525static const struct qcom_reset_map mmcc_apq8064_resets[] = {
2526 [GFX3D_AXI_RESET] = { 0x0208, 17 },
2527 [VCAP_AXI_RESET] = { 0x0208, 16 },
2528 [VPE_AXI_RESET] = { 0x0208, 15 },
2529 [IJPEG_AXI_RESET] = { 0x0208, 14 },
2530 [MPD_AXI_RESET] = { 0x0208, 13 },
2531 [VFE_AXI_RESET] = { 0x0208, 9 },
2532 [SP_AXI_RESET] = { 0x0208, 8 },
2533 [VCODEC_AXI_RESET] = { 0x0208, 7 },
2534 [ROT_AXI_RESET] = { 0x0208, 6 },
2535 [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2536 [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2537 [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2538 [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2539 [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2540 [FAB_S0_AXI_RESET] = { 0x0208 },
2541 [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2542 [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2543 [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2544 [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2545 [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2546 [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2547 [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2548 [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2549 [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2550 [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2551 [APU_AHB_RESET] = { 0x020c, 18 },
2552 [CSI_AHB_RESET] = { 0x020c, 17 },
2553 [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2554 [VPE_AHB_RESET] = { 0x020c, 14 },
2555 [FABRIC_AHB_RESET] = { 0x020c, 13 },
2556 [GFX3D_AHB_RESET] = { 0x020c, 10 },
2557 [HDMI_AHB_RESET] = { 0x020c, 9 },
2558 [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2559 [IJPEG_AHB_RESET] = { 0x020c, 7 },
2560 [DSI_M_AHB_RESET] = { 0x020c, 6 },
2561 [DSI_S_AHB_RESET] = { 0x020c, 5 },
2562 [JPEGD_AHB_RESET] = { 0x020c, 4 },
2563 [MDP_AHB_RESET] = { 0x020c, 3 },
2564 [ROT_AHB_RESET] = { 0x020c, 2 },
2565 [VCODEC_AHB_RESET] = { 0x020c, 1 },
2566 [VFE_AHB_RESET] = { 0x020c, 0 },
2567 [SMMU_VCAP_AHB_RESET] = { 0x0200, 3 },
2568 [VCAP_AHB_RESET] = { 0x0200, 2 },
2569 [DSI2_M_AHB_RESET] = { 0x0200, 1 },
2570 [DSI2_S_AHB_RESET] = { 0x0200, 0 },
2571 [CSIPHY2_RESET] = { 0x0210, 31 },
2572 [CSI_PIX1_RESET] = { 0x0210, 30 },
2573 [CSIPHY0_RESET] = { 0x0210, 29 },
2574 [CSIPHY1_RESET] = { 0x0210, 28 },
2575 [CSI_RDI_RESET] = { 0x0210, 27 },
2576 [CSI_PIX_RESET] = { 0x0210, 26 },
2577 [DSI2_RESET] = { 0x0210, 25 },
2578 [VFE_CSI_RESET] = { 0x0210, 24 },
2579 [MDP_RESET] = { 0x0210, 21 },
2580 [AMP_RESET] = { 0x0210, 20 },
2581 [JPEGD_RESET] = { 0x0210, 19 },
2582 [CSI1_RESET] = { 0x0210, 18 },
2583 [VPE_RESET] = { 0x0210, 17 },
2584 [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2585 [VFE_RESET] = { 0x0210, 15 },
2586 [GFX3D_RESET] = { 0x0210, 12 },
2587 [HDMI_RESET] = { 0x0210, 11 },
2588 [MMSS_IMEM_RESET] = { 0x0210, 10 },
2589 [IJPEG_RESET] = { 0x0210, 9 },
2590 [CSI0_RESET] = { 0x0210, 8 },
2591 [DSI_RESET] = { 0x0210, 7 },
2592 [VCODEC_RESET] = { 0x0210, 6 },
2593 [MDP_TV_RESET] = { 0x0210, 4 },
2594 [MDP_VSYNC_RESET] = { 0x0210, 3 },
2595 [ROT_RESET] = { 0x0210, 2 },
2596 [TV_HDMI_RESET] = { 0x0210, 1 },
2597 [VCAP_NPL_RESET] = { 0x0214, 4 },
2598 [VCAP_RESET] = { 0x0214, 3 },
2599 [CSI2_RESET] = { 0x0214, 2 },
2600 [CSI_RDI1_RESET] = { 0x0214, 1 },
2601 [CSI_RDI2_RESET] = { 0x0214 },
2602};
2603
2218static const struct regmap_config mmcc_msm8960_regmap_config = { 2604static const struct regmap_config mmcc_msm8960_regmap_config = {
2219 .reg_bits = 32, 2605 .reg_bits = 32,
2220 .reg_stride = 4, 2606 .reg_stride = 4,
@@ -2223,6 +2609,14 @@ static const struct regmap_config mmcc_msm8960_regmap_config = {
2223 .fast_io = true, 2609 .fast_io = true,
2224}; 2610};
2225 2611
2612static const struct regmap_config mmcc_apq8064_regmap_config = {
2613 .reg_bits = 32,
2614 .reg_stride = 4,
2615 .val_bits = 32,
2616 .max_register = 0x350,
2617 .fast_io = true,
2618};
2619
2226static const struct qcom_cc_desc mmcc_msm8960_desc = { 2620static const struct qcom_cc_desc mmcc_msm8960_desc = {
2227 .config = &mmcc_msm8960_regmap_config, 2621 .config = &mmcc_msm8960_regmap_config,
2228 .clks = mmcc_msm8960_clks, 2622 .clks = mmcc_msm8960_clks,
@@ -2231,15 +2625,47 @@ static const struct qcom_cc_desc mmcc_msm8960_desc = {
2231 .num_resets = ARRAY_SIZE(mmcc_msm8960_resets), 2625 .num_resets = ARRAY_SIZE(mmcc_msm8960_resets),
2232}; 2626};
2233 2627
2628static const struct qcom_cc_desc mmcc_apq8064_desc = {
2629 .config = &mmcc_apq8064_regmap_config,
2630 .clks = mmcc_apq8064_clks,
2631 .num_clks = ARRAY_SIZE(mmcc_apq8064_clks),
2632 .resets = mmcc_apq8064_resets,
2633 .num_resets = ARRAY_SIZE(mmcc_apq8064_resets),
2634};
2635
2234static const struct of_device_id mmcc_msm8960_match_table[] = { 2636static const struct of_device_id mmcc_msm8960_match_table[] = {
2235 { .compatible = "qcom,mmcc-msm8960" }, 2637 { .compatible = "qcom,mmcc-msm8960", .data = &mmcc_msm8960_desc },
2638 { .compatible = "qcom,mmcc-apq8064", .data = &mmcc_apq8064_desc },
2236 { } 2639 { }
2237}; 2640};
2238MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table); 2641MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table);
2239 2642
2240static int mmcc_msm8960_probe(struct platform_device *pdev) 2643static int mmcc_msm8960_probe(struct platform_device *pdev)
2241{ 2644{
2242 return qcom_cc_probe(pdev, &mmcc_msm8960_desc); 2645 const struct of_device_id *match;
2646 struct regmap *regmap;
2647 bool is_8064;
2648 struct device *dev = &pdev->dev;
2649
2650 match = of_match_device(mmcc_msm8960_match_table, dev);
2651 if (!match)
2652 return -EINVAL;
2653
2654 is_8064 = of_device_is_compatible(dev->of_node, "qcom,mmcc-apq8064");
2655 if (is_8064) {
2656 gfx3d_src.freq_tbl = clk_tbl_gfx3d_8064;
2657 gfx3d_src.clkr.hw.init = &gfx3d_8064_init;
2658 gfx3d_src.s[0].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
2659 gfx3d_src.s[1].parent_map = mmcc_pxo_pll8_pll2_pll15_map;
2660 }
2661
2662 regmap = qcom_cc_map(pdev, match->data);
2663 if (IS_ERR(regmap))
2664 return PTR_ERR(regmap);
2665
2666 clk_pll_configure_sr(&pll15, regmap, &pll15_config, false);
2667
2668 return qcom_cc_really_probe(pdev, match->data, regmap);
2243} 2669}
2244 2670
2245static int mmcc_msm8960_remove(struct platform_device *pdev) 2671static int mmcc_msm8960_remove(struct platform_device *pdev)
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index c65b90515872..bc8f519c47aa 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -2547,18 +2547,16 @@ MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
2547 2547
2548static int mmcc_msm8974_probe(struct platform_device *pdev) 2548static int mmcc_msm8974_probe(struct platform_device *pdev)
2549{ 2549{
2550 int ret;
2551 struct regmap *regmap; 2550 struct regmap *regmap;
2552 2551
2553 ret = qcom_cc_probe(pdev, &mmcc_msm8974_desc); 2552 regmap = qcom_cc_map(pdev, &mmcc_msm8974_desc);
2554 if (ret) 2553 if (IS_ERR(regmap))
2555 return ret; 2554 return PTR_ERR(regmap);
2556 2555
2557 regmap = dev_get_regmap(&pdev->dev, NULL);
2558 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true); 2556 clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
2559 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false); 2557 clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
2560 2558
2561 return 0; 2559 return qcom_cc_really_probe(pdev, &mmcc_msm8974_desc, regmap);
2562} 2560}
2563 2561
2564static int mmcc_msm8974_remove(struct platform_device *pdev) 2562static int mmcc_msm8974_remove(struct platform_device *pdev)
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 8d3aefad2e73..ee6b077381e1 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -3,3 +3,9 @@
3# 3#
4 4
5obj-y += clk-rockchip.o 5obj-y += clk-rockchip.o
6obj-y += clk.o
7obj-y += clk-pll.o
8obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
9
10obj-y += clk-rk3188.o
11obj-y += clk-rk3288.o
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
new file mode 100644
index 000000000000..f2a1c7abf4d9
--- /dev/null
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -0,0 +1,431 @@
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <asm/div64.h>
17#include <linux/slab.h>
18#include <linux/io.h>
19#include <linux/delay.h>
20#include <linux/clk.h>
21#include <linux/clk-provider.h>
22#include <linux/regmap.h>
23#include "clk.h"
24
25#define PLL_MODE_MASK 0x3
26#define PLL_MODE_SLOW 0x0
27#define PLL_MODE_NORM 0x1
28#define PLL_MODE_DEEP 0x2
29
30struct rockchip_clk_pll {
31 struct clk_hw hw;
32
33 struct clk_mux pll_mux;
34 const struct clk_ops *pll_mux_ops;
35
36 struct notifier_block clk_nb;
37 bool rate_change_remuxed;
38
39 void __iomem *reg_base;
40 int lock_offset;
41 unsigned int lock_shift;
42 enum rockchip_pll_type type;
43 const struct rockchip_pll_rate_table *rate_table;
44 unsigned int rate_count;
45 spinlock_t *lock;
46};
47
48#define to_rockchip_clk_pll(_hw) container_of(_hw, struct rockchip_clk_pll, hw)
49#define to_rockchip_clk_pll_nb(nb) \
50 container_of(nb, struct rockchip_clk_pll, clk_nb)
51
52static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
53 struct rockchip_clk_pll *pll, unsigned long rate)
54{
55 const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
56 int i;
57
58 for (i = 0; i < pll->rate_count; i++) {
59 if (rate == rate_table[i].rate)
60 return &rate_table[i];
61 }
62
63 return NULL;
64}
65
66static long rockchip_pll_round_rate(struct clk_hw *hw,
67 unsigned long drate, unsigned long *prate)
68{
69 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
70 const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
71 int i;
72
73 /* Assumming rate_table is in descending order */
74 for (i = 0; i < pll->rate_count; i++) {
75 if (drate >= rate_table[i].rate)
76 return rate_table[i].rate;
77 }
78
79 /* return minimum supported value */
80 return rate_table[i - 1].rate;
81}
82
83/*
84 * Wait for the pll to reach the locked state.
85 * The calling set_rate function is responsible for making sure the
86 * grf regmap is available.
87 */
88static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
89{
90 struct regmap *grf = rockchip_clk_get_grf();
91 unsigned int val;
92 int delay = 24000000, ret;
93
94 while (delay > 0) {
95 ret = regmap_read(grf, pll->lock_offset, &val);
96 if (ret) {
97 pr_err("%s: failed to read pll lock status: %d\n",
98 __func__, ret);
99 return ret;
100 }
101
102 if (val & BIT(pll->lock_shift))
103 return 0;
104 delay--;
105 }
106
107 pr_err("%s: timeout waiting for pll to lock\n", __func__);
108 return -ETIMEDOUT;
109}
110
111/**
112 * Set pll mux when changing the pll rate.
113 * This makes sure to move the pll mux away from the actual pll before
114 * changing its rate and back to the original parent after the change.
115 */
116static int rockchip_pll_notifier_cb(struct notifier_block *nb,
117 unsigned long event, void *data)
118{
119 struct rockchip_clk_pll *pll = to_rockchip_clk_pll_nb(nb);
120 struct clk_mux *pll_mux = &pll->pll_mux;
121 const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
122 int cur_parent;
123
124 switch (event) {
125 case PRE_RATE_CHANGE:
126 cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
127 if (cur_parent == PLL_MODE_NORM) {
128 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
129 pll->rate_change_remuxed = 1;
130 }
131 break;
132 case POST_RATE_CHANGE:
133 if (pll->rate_change_remuxed) {
134 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
135 pll->rate_change_remuxed = 0;
136 }
137 break;
138 }
139
140 return NOTIFY_OK;
141}
142
143/**
144 * PLL used in RK3066, RK3188 and RK3288
145 */
146
147#define RK3066_PLL_RESET_DELAY(nr) ((nr * 500) / 24 + 1)
148
149#define RK3066_PLLCON(i) (i * 0x4)
150#define RK3066_PLLCON0_OD_MASK 0xf
151#define RK3066_PLLCON0_OD_SHIFT 0
152#define RK3066_PLLCON0_NR_MASK 0x3f
153#define RK3066_PLLCON0_NR_SHIFT 8
154#define RK3066_PLLCON1_NF_MASK 0x1fff
155#define RK3066_PLLCON1_NF_SHIFT 0
156#define RK3066_PLLCON2_BWADJ_MASK 0xfff
157#define RK3066_PLLCON2_BWADJ_SHIFT 0
158#define RK3066_PLLCON3_RESET (1 << 5)
159#define RK3066_PLLCON3_PWRDOWN (1 << 1)
160#define RK3066_PLLCON3_BYPASS (1 << 0)
161
162static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw,
163 unsigned long prate)
164{
165 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
166 u64 nf, nr, no, rate64 = prate;
167 u32 pllcon;
168
169 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));
170 if (pllcon & RK3066_PLLCON3_BYPASS) {
171 pr_debug("%s: pll %s is bypassed\n", __func__,
172 __clk_get_name(hw->clk));
173 return prate;
174 }
175
176 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
177 nf = (pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK;
178
179 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
180 nr = (pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK;
181 no = (pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK;
182
183 rate64 *= (nf + 1);
184 do_div(rate64, nr + 1);
185 do_div(rate64, no + 1);
186
187 return (unsigned long)rate64;
188}
189
190static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,
191 unsigned long prate)
192{
193 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
194 const struct rockchip_pll_rate_table *rate;
195 unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate);
196 struct regmap *grf = rockchip_clk_get_grf();
197 int ret;
198
199 if (IS_ERR(grf)) {
200 pr_debug("%s: grf regmap not available, aborting rate change\n",
201 __func__);
202 return PTR_ERR(grf);
203 }
204
205 pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
206 __func__, __clk_get_name(hw->clk), old_rate, drate, prate);
207
208 /* Get required rate settings from table */
209 rate = rockchip_get_pll_settings(pll, drate);
210 if (!rate) {
211 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
212 drate, __clk_get_name(hw->clk));
213 return -EINVAL;
214 }
215
216 pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n",
217 __func__, rate->rate, rate->nr, rate->no, rate->nf);
218
219 /* enter reset mode */
220 writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0),
221 pll->reg_base + RK3066_PLLCON(3));
222
223 /* update pll values */
224 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK,
225 RK3066_PLLCON0_NR_SHIFT) |
226 HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK,
227 RK3066_PLLCON0_OD_SHIFT),
228 pll->reg_base + RK3066_PLLCON(0));
229
230 writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK,
231 RK3066_PLLCON1_NF_SHIFT),
232 pll->reg_base + RK3066_PLLCON(1));
233 writel_relaxed(HIWORD_UPDATE(rate->bwadj, RK3066_PLLCON2_BWADJ_MASK,
234 RK3066_PLLCON2_BWADJ_SHIFT),
235 pll->reg_base + RK3066_PLLCON(2));
236
237 /* leave reset and wait the reset_delay */
238 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0),
239 pll->reg_base + RK3066_PLLCON(3));
240 udelay(RK3066_PLL_RESET_DELAY(rate->nr));
241
242 /* wait for the pll to lock */
243 ret = rockchip_pll_wait_lock(pll);
244 if (ret) {
245 pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
246 __func__, old_rate);
247 rockchip_rk3066_pll_set_rate(hw, old_rate, prate);
248 }
249
250 return ret;
251}
252
253static int rockchip_rk3066_pll_enable(struct clk_hw *hw)
254{
255 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
256
257 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0),
258 pll->reg_base + RK3066_PLLCON(3));
259
260 return 0;
261}
262
263static void rockchip_rk3066_pll_disable(struct clk_hw *hw)
264{
265 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
266
267 writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN,
268 RK3066_PLLCON3_PWRDOWN, 0),
269 pll->reg_base + RK3066_PLLCON(3));
270}
271
272static int rockchip_rk3066_pll_is_enabled(struct clk_hw *hw)
273{
274 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
275 u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3));
276
277 return !(pllcon & RK3066_PLLCON3_PWRDOWN);
278}
279
280static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = {
281 .recalc_rate = rockchip_rk3066_pll_recalc_rate,
282 .enable = rockchip_rk3066_pll_enable,
283 .disable = rockchip_rk3066_pll_disable,
284 .is_enabled = rockchip_rk3066_pll_is_enabled,
285};
286
287static const struct clk_ops rockchip_rk3066_pll_clk_ops = {
288 .recalc_rate = rockchip_rk3066_pll_recalc_rate,
289 .round_rate = rockchip_pll_round_rate,
290 .set_rate = rockchip_rk3066_pll_set_rate,
291 .enable = rockchip_rk3066_pll_enable,
292 .disable = rockchip_rk3066_pll_disable,
293 .is_enabled = rockchip_rk3066_pll_is_enabled,
294};
295
296/*
297 * Common registering of pll clocks
298 */
299
300struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
301 const char *name, const char **parent_names, u8 num_parents,
302 void __iomem *base, int con_offset, int grf_lock_offset,
303 int lock_shift, int mode_offset, int mode_shift,
304 struct rockchip_pll_rate_table *rate_table,
305 spinlock_t *lock)
306{
307 const char *pll_parents[3];
308 struct clk_init_data init;
309 struct rockchip_clk_pll *pll;
310 struct clk_mux *pll_mux;
311 struct clk *pll_clk, *mux_clk;
312 char pll_name[20];
313 int ret;
314
315 if (num_parents != 2) {
316 pr_err("%s: needs two parent clocks\n", __func__);
317 return ERR_PTR(-EINVAL);
318 }
319
320 /* name the actual pll */
321 snprintf(pll_name, sizeof(pll_name), "pll_%s", name);
322
323 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
324 if (!pll)
325 return ERR_PTR(-ENOMEM);
326
327 init.name = pll_name;
328
329 /* keep all plls untouched for now */
330 init.flags = CLK_IGNORE_UNUSED;
331
332 init.parent_names = &parent_names[0];
333 init.num_parents = 1;
334
335 if (rate_table) {
336 int len;
337
338 /* find count of rates in rate_table */
339 for (len = 0; rate_table[len].rate != 0; )
340 len++;
341
342 pll->rate_count = len;
343 pll->rate_table = kmemdup(rate_table,
344 pll->rate_count *
345 sizeof(struct rockchip_pll_rate_table),
346 GFP_KERNEL);
347 WARN(!pll->rate_table,
348 "%s: could not allocate rate table for %s\n",
349 __func__, name);
350 }
351
352 switch (pll_type) {
353 case pll_rk3066:
354 if (!pll->rate_table)
355 init.ops = &rockchip_rk3066_pll_clk_norate_ops;
356 else
357 init.ops = &rockchip_rk3066_pll_clk_ops;
358 break;
359 default:
360 pr_warn("%s: Unknown pll type for pll clk %s\n",
361 __func__, name);
362 }
363
364 pll->hw.init = &init;
365 pll->type = pll_type;
366 pll->reg_base = base + con_offset;
367 pll->lock_offset = grf_lock_offset;
368 pll->lock_shift = lock_shift;
369 pll->lock = lock;
370 pll->clk_nb.notifier_call = rockchip_pll_notifier_cb;
371
372 pll_clk = clk_register(NULL, &pll->hw);
373 if (IS_ERR(pll_clk)) {
374 pr_err("%s: failed to register pll clock %s : %ld\n",
375 __func__, name, PTR_ERR(pll_clk));
376 mux_clk = pll_clk;
377 goto err_pll;
378 }
379
380 ret = clk_notifier_register(pll_clk, &pll->clk_nb);
381 if (ret) {
382 pr_err("%s: failed to register clock notifier for %s : %d\n",
383 __func__, name, ret);
384 mux_clk = ERR_PTR(ret);
385 goto err_pll_notifier;
386 }
387
388 /* create the mux on top of the real pll */
389 pll->pll_mux_ops = &clk_mux_ops;
390 pll_mux = &pll->pll_mux;
391
392 /* the actual muxing is xin24m, pll-output, xin32k */
393 pll_parents[0] = parent_names[0];
394 pll_parents[1] = pll_name;
395 pll_parents[2] = parent_names[1];
396
397 init.name = name;
398 init.flags = CLK_SET_RATE_PARENT;
399 init.ops = pll->pll_mux_ops;
400 init.parent_names = pll_parents;
401 init.num_parents = ARRAY_SIZE(pll_parents);
402
403 pll_mux->reg = base + mode_offset;
404 pll_mux->shift = mode_shift;
405 pll_mux->mask = PLL_MODE_MASK;
406 pll_mux->flags = 0;
407 pll_mux->lock = lock;
408 pll_mux->hw.init = &init;
409
410 if (pll_type == pll_rk3066)
411 pll_mux->flags |= CLK_MUX_HIWORD_MASK;
412
413 mux_clk = clk_register(NULL, &pll_mux->hw);
414 if (IS_ERR(mux_clk))
415 goto err_mux;
416
417 return mux_clk;
418
419err_mux:
420 ret = clk_notifier_unregister(pll_clk, &pll->clk_nb);
421 if (ret) {
422 pr_err("%s: could not unregister clock notifier in error path : %d\n",
423 __func__, ret);
424 return mux_clk;
425 }
426err_pll_notifier:
427 clk_unregister(pll_clk);
428err_pll:
429 kfree(pll);
430 return mux_clk;
431}
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
new file mode 100644
index 000000000000..a83a6d8d0fb6
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -0,0 +1,672 @@
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk-provider.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <dt-bindings/clock/rk3188-cru-common.h>
20#include "clk.h"
21
22#define RK3188_GRF_SOC_STATUS 0xac
23
24enum rk3188_plls {
25 apll, cpll, dpll, gpll,
26};
27
28struct rockchip_pll_rate_table rk3188_pll_rates[] = {
29 RK3066_PLL_RATE(2208000000, 1, 92, 1),
30 RK3066_PLL_RATE(2184000000, 1, 91, 1),
31 RK3066_PLL_RATE(2160000000, 1, 90, 1),
32 RK3066_PLL_RATE(2136000000, 1, 89, 1),
33 RK3066_PLL_RATE(2112000000, 1, 88, 1),
34 RK3066_PLL_RATE(2088000000, 1, 87, 1),
35 RK3066_PLL_RATE(2064000000, 1, 86, 1),
36 RK3066_PLL_RATE(2040000000, 1, 85, 1),
37 RK3066_PLL_RATE(2016000000, 1, 84, 1),
38 RK3066_PLL_RATE(1992000000, 1, 83, 1),
39 RK3066_PLL_RATE(1968000000, 1, 82, 1),
40 RK3066_PLL_RATE(1944000000, 1, 81, 1),
41 RK3066_PLL_RATE(1920000000, 1, 80, 1),
42 RK3066_PLL_RATE(1896000000, 1, 79, 1),
43 RK3066_PLL_RATE(1872000000, 1, 78, 1),
44 RK3066_PLL_RATE(1848000000, 1, 77, 1),
45 RK3066_PLL_RATE(1824000000, 1, 76, 1),
46 RK3066_PLL_RATE(1800000000, 1, 75, 1),
47 RK3066_PLL_RATE(1776000000, 1, 74, 1),
48 RK3066_PLL_RATE(1752000000, 1, 73, 1),
49 RK3066_PLL_RATE(1728000000, 1, 72, 1),
50 RK3066_PLL_RATE(1704000000, 1, 71, 1),
51 RK3066_PLL_RATE(1680000000, 1, 70, 1),
52 RK3066_PLL_RATE(1656000000, 1, 69, 1),
53 RK3066_PLL_RATE(1632000000, 1, 68, 1),
54 RK3066_PLL_RATE(1608000000, 1, 67, 1),
55 RK3066_PLL_RATE(1560000000, 1, 65, 1),
56 RK3066_PLL_RATE(1512000000, 1, 63, 1),
57 RK3066_PLL_RATE(1488000000, 1, 62, 1),
58 RK3066_PLL_RATE(1464000000, 1, 61, 1),
59 RK3066_PLL_RATE(1440000000, 1, 60, 1),
60 RK3066_PLL_RATE(1416000000, 1, 59, 1),
61 RK3066_PLL_RATE(1392000000, 1, 58, 1),
62 RK3066_PLL_RATE(1368000000, 1, 57, 1),
63 RK3066_PLL_RATE(1344000000, 1, 56, 1),
64 RK3066_PLL_RATE(1320000000, 1, 55, 1),
65 RK3066_PLL_RATE(1296000000, 1, 54, 1),
66 RK3066_PLL_RATE(1272000000, 1, 53, 1),
67 RK3066_PLL_RATE(1248000000, 1, 52, 1),
68 RK3066_PLL_RATE(1224000000, 1, 51, 1),
69 RK3066_PLL_RATE(1200000000, 1, 50, 1),
70 RK3066_PLL_RATE(1188000000, 2, 99, 1),
71 RK3066_PLL_RATE(1176000000, 1, 49, 1),
72 RK3066_PLL_RATE(1128000000, 1, 47, 1),
73 RK3066_PLL_RATE(1104000000, 1, 46, 1),
74 RK3066_PLL_RATE(1008000000, 1, 84, 2),
75 RK3066_PLL_RATE( 912000000, 1, 76, 2),
76 RK3066_PLL_RATE( 891000000, 8, 594, 2),
77 RK3066_PLL_RATE( 888000000, 1, 74, 2),
78 RK3066_PLL_RATE( 816000000, 1, 68, 2),
79 RK3066_PLL_RATE( 798000000, 2, 133, 2),
80 RK3066_PLL_RATE( 792000000, 1, 66, 2),
81 RK3066_PLL_RATE( 768000000, 1, 64, 2),
82 RK3066_PLL_RATE( 742500000, 8, 495, 2),
83 RK3066_PLL_RATE( 696000000, 1, 58, 2),
84 RK3066_PLL_RATE( 600000000, 1, 50, 2),
85 RK3066_PLL_RATE( 594000000, 2, 198, 4),
86 RK3066_PLL_RATE( 552000000, 1, 46, 2),
87 RK3066_PLL_RATE( 504000000, 1, 84, 4),
88 RK3066_PLL_RATE( 456000000, 1, 76, 4),
89 RK3066_PLL_RATE( 408000000, 1, 68, 4),
90 RK3066_PLL_RATE( 384000000, 2, 128, 4),
91 RK3066_PLL_RATE( 360000000, 1, 60, 4),
92 RK3066_PLL_RATE( 312000000, 1, 52, 4),
93 RK3066_PLL_RATE( 300000000, 1, 50, 4),
94 RK3066_PLL_RATE( 297000000, 2, 198, 8),
95 RK3066_PLL_RATE( 252000000, 1, 84, 8),
96 RK3066_PLL_RATE( 216000000, 1, 72, 8),
97 RK3066_PLL_RATE( 148500000, 2, 99, 8),
98 RK3066_PLL_RATE( 126000000, 1, 84, 16),
99 RK3066_PLL_RATE( 48000000, 1, 64, 32),
100 { /* sentinel */ },
101};
102
103PNAME(mux_pll_p) = { "xin24m", "xin32k" };
104PNAME(mux_armclk_p) = { "apll", "gpll_armclk" };
105PNAME(mux_ddrphy_p) = { "dpll", "gpll_ddr" };
106PNAME(mux_pll_src_gpll_cpll_p) = { "gpll", "cpll" };
107PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
108PNAME(mux_aclk_cpu_p) = { "apll", "gpll" };
109PNAME(mux_sclk_cif0_p) = { "cif0_pre", "xin24m" };
110PNAME(mux_sclk_i2s0_p) = { "i2s0_pre", "i2s0_frac", "xin12m" };
111PNAME(mux_sclk_spdif_p) = { "spdif_src", "spdif_frac", "xin12m" };
112PNAME(mux_sclk_uart0_p) = { "uart0_pre", "uart0_frac", "xin24m" };
113PNAME(mux_sclk_uart1_p) = { "uart1_pre", "uart1_frac", "xin24m" };
114PNAME(mux_sclk_uart2_p) = { "uart2_pre", "uart2_frac", "xin24m" };
115PNAME(mux_sclk_uart3_p) = { "uart3_pre", "uart3_frac", "xin24m" };
116PNAME(mux_sclk_hsadc_p) = { "hsadc_src", "hsadc_frac", "ext_hsadc" };
117PNAME(mux_mac_p) = { "gpll", "dpll" };
118PNAME(mux_sclk_macref_p) = { "mac_src", "ext_rmii" };
119
120static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = {
121 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
122 RK2928_MODE_CON, 0, 6, rk3188_pll_rates),
123 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
124 RK2928_MODE_CON, 4, 5, NULL),
125 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
126 RK2928_MODE_CON, 8, 7, rk3188_pll_rates),
127 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
128 RK2928_MODE_CON, 12, 8, rk3188_pll_rates),
129};
130
131#define MFLAGS CLK_MUX_HIWORD_MASK
132#define DFLAGS CLK_DIVIDER_HIWORD_MASK
133#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
134
135/* 2 ^ (val + 1) */
136static struct clk_div_table div_core_peri_t[] = {
137 { .val = 0, .div = 2 },
138 { .val = 1, .div = 4 },
139 { .val = 2, .div = 8 },
140 { .val = 3, .div = 16 },
141 { /* sentinel */ },
142};
143
144static struct rockchip_clk_branch common_clk_branches[] __initdata = {
145 /*
146 * Clock-Architecture Diagram 2
147 */
148
149 GATE(0, "gpll_armclk", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
150
151 /* these two are set by the cpuclk and should not be changed */
152 COMPOSITE_NOMUX_DIVTBL(CORE_PERI, "core_peri", "armclk", 0,
153 RK2928_CLKSEL_CON(0), 6, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
154 div_core_peri_t, RK2928_CLKGATE_CON(0), 0, GFLAGS),
155
156 COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0,
157 RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS,
158 RK2928_CLKGATE_CON(3), 9, GFLAGS),
159 GATE(0, "hclk_vepu", "aclk_vepu", 0,
160 RK2928_CLKGATE_CON(3), 10, GFLAGS),
161 COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0,
162 RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
163 RK2928_CLKGATE_CON(3), 11, GFLAGS),
164 GATE(0, "hclk_vdpu", "aclk_vdpu", 0,
165 RK2928_CLKGATE_CON(3), 12, GFLAGS),
166
167 GATE(0, "gpll_ddr", "gpll", 0,
168 RK2928_CLKGATE_CON(1), 7, GFLAGS),
169 COMPOSITE(0, "ddrphy", mux_ddrphy_p, 0,
170 RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
171 RK2928_CLKGATE_CON(0), 2, GFLAGS),
172
173 GATE(0, "aclk_cpu", "aclk_cpu_pre", 0,
174 RK2928_CLKGATE_CON(0), 3, GFLAGS),
175
176 DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0,
177 RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
178 GATE(0, "atclk_cpu", "pclk_cpu_pre", 0,
179 RK2928_CLKGATE_CON(0), 6, GFLAGS),
180 GATE(0, "pclk_cpu", "pclk_cpu_pre", 0,
181 RK2928_CLKGATE_CON(0), 5, GFLAGS),
182 DIV(0, "hclk_cpu_pre", "aclk_cpu_pre", 0,
183 RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
184 COMPOSITE_NOMUX(0, "hclk_ahb2apb", "hclk_cpu_pre", 0,
185 RK2928_CLKSEL_CON(1), 14, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
186 RK2928_CLKGATE_CON(4), 9, GFLAGS),
187 GATE(0, "hclk_cpu", "hclk_cpu_pre", 0,
188 RK2928_CLKGATE_CON(0), 4, GFLAGS),
189
190 COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, 0,
191 RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS,
192 RK2928_CLKGATE_CON(3), 0, GFLAGS),
193 COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0,
194 RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS,
195 RK2928_CLKGATE_CON(1), 4, GFLAGS),
196
197 GATE(0, "aclk_peri", "aclk_peri_pre", 0,
198 RK2928_CLKGATE_CON(2), 1, GFLAGS),
199 COMPOSITE_NOMUX(0, "hclk_peri", "aclk_peri_pre", 0,
200 RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
201 RK2928_CLKGATE_CON(2), 2, GFLAGS),
202 COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_pre", 0,
203 RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
204 RK2928_CLKGATE_CON(2), 3, GFLAGS),
205
206 MUX(0, "cif_src", mux_pll_src_cpll_gpll_p, 0,
207 RK2928_CLKSEL_CON(29), 0, 1, MFLAGS),
208 COMPOSITE_NOMUX(0, "cif0_pre", "cif_src", 0,
209 RK2928_CLKSEL_CON(29), 1, 5, DFLAGS,
210 RK2928_CLKGATE_CON(3), 7, GFLAGS),
211 MUX(SCLK_CIF0, "sclk_cif0", mux_sclk_cif0_p, 0,
212 RK2928_CLKSEL_CON(29), 7, 1, MFLAGS),
213
214 GATE(0, "pclkin_cif0", "ext_cif0", 0,
215 RK2928_CLKGATE_CON(3), 3, GFLAGS),
216
217 /*
218 * the 480m are generated inside the usb block from these clocks,
219 * but they are also a source for the hsicphy clock.
220 */
221 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", 0,
222 RK2928_CLKGATE_CON(1), 5, GFLAGS),
223 GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", 0,
224 RK2928_CLKGATE_CON(1), 6, GFLAGS),
225
226 COMPOSITE(0, "mac_src", mux_mac_p, 0,
227 RK2928_CLKSEL_CON(21), 0, 1, MFLAGS, 8, 5, DFLAGS,
228 RK2928_CLKGATE_CON(2), 5, GFLAGS),
229 MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT,
230 RK2928_CLKSEL_CON(21), 4, 1, MFLAGS),
231 GATE(0, "sclk_mac_lbtest", "sclk_macref",
232 RK2928_CLKGATE_CON(2), 12, 0, GFLAGS),
233
234 COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,
235 RK2928_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
236 RK2928_CLKGATE_CON(2), 6, GFLAGS),
237 COMPOSITE_FRAC(0, "hsadc_frac", "hsadc_src",
238 RK2928_CLKSEL_CON(23), 0,
239 RK2928_CLKGATE_CON(2), 7, 0, GFLAGS),
240 MUX(SCLK_HSADC, "sclk_hsadc", mux_sclk_hsadc_p, 0,
241 RK2928_CLKSEL_CON(22), 4, 2, MFLAGS),
242
243 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
244 RK2928_CLKSEL_CON(24), 8, 8, DFLAGS,
245 RK2928_CLKGATE_CON(2), 8, GFLAGS),
246
247 /*
248 * Clock-Architecture Diagram 4
249 */
250
251 GATE(SCLK_SMC, "sclk_smc", "hclk_peri",
252 RK2928_CLKGATE_CON(2), 4, 0, GFLAGS),
253
254 COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0,
255 RK2928_CLKSEL_CON(25), 0, 7, DFLAGS,
256 RK2928_CLKGATE_CON(2), 9, GFLAGS),
257 COMPOSITE_NOMUX(SCLK_SPI1, "sclk_spi1", "pclk_peri", 0,
258 RK2928_CLKSEL_CON(25), 8, 7, DFLAGS,
259 RK2928_CLKGATE_CON(2), 10, GFLAGS),
260
261 COMPOSITE_NOMUX(SCLK_SDMMC, "sclk_sdmmc", "hclk_peri", 0,
262 RK2928_CLKSEL_CON(11), 0, 6, DFLAGS,
263 RK2928_CLKGATE_CON(2), 11, GFLAGS),
264 COMPOSITE_NOMUX(SCLK_SDIO, "sclk_sdio", "hclk_peri", 0,
265 RK2928_CLKSEL_CON(12), 0, 6, DFLAGS,
266 RK2928_CLKGATE_CON(2), 13, GFLAGS),
267 COMPOSITE_NOMUX(SCLK_EMMC, "sclk_emmc", "hclk_peri", 0,
268 RK2928_CLKSEL_CON(12), 8, 6, DFLAGS,
269 RK2928_CLKGATE_CON(2), 14, GFLAGS),
270
271 MUX(0, "uart_src", mux_pll_src_gpll_cpll_p, 0,
272 RK2928_CLKSEL_CON(12), 15, 1, MFLAGS),
273 COMPOSITE_NOMUX(0, "uart0_pre", "uart_src", 0,
274 RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
275 RK2928_CLKGATE_CON(1), 8, GFLAGS),
276 COMPOSITE_FRAC(0, "uart0_frac", "uart0_pre", 0,
277 RK2928_CLKSEL_CON(17), 0,
278 RK2928_CLKGATE_CON(1), 9, GFLAGS),
279 MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0,
280 RK2928_CLKSEL_CON(13), 8, 2, MFLAGS),
281 COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0,
282 RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
283 RK2928_CLKGATE_CON(1), 10, GFLAGS),
284 COMPOSITE_FRAC(0, "uart1_frac", "uart1_pre", 0,
285 RK2928_CLKSEL_CON(18), 0,
286 RK2928_CLKGATE_CON(1), 11, GFLAGS),
287 MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0,
288 RK2928_CLKSEL_CON(14), 8, 2, MFLAGS),
289 COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0,
290 RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
291 RK2928_CLKGATE_CON(1), 12, GFLAGS),
292 COMPOSITE_FRAC(0, "uart2_frac", "uart2_pre", 0,
293 RK2928_CLKSEL_CON(19), 0,
294 RK2928_CLKGATE_CON(1), 13, GFLAGS),
295 MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0,
296 RK2928_CLKSEL_CON(15), 8, 2, MFLAGS),
297 COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0,
298 RK2928_CLKSEL_CON(16), 0, 7, DFLAGS,
299 RK2928_CLKGATE_CON(1), 14, GFLAGS),
300 COMPOSITE_FRAC(0, "uart3_frac", "uart3_pre", 0,
301 RK2928_CLKSEL_CON(20), 0,
302 RK2928_CLKGATE_CON(1), 15, GFLAGS),
303 MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0,
304 RK2928_CLKSEL_CON(16), 8, 2, MFLAGS),
305
306 GATE(SCLK_JTAG, "jtag", "ext_jtag", 0, RK2928_CLKGATE_CON(1), 3, GFLAGS),
307
308 GATE(SCLK_TIMER0, "timer0", "xin24m", 0, RK2928_CLKGATE_CON(1), 0, GFLAGS),
309 GATE(SCLK_TIMER1, "timer1", "xin24m", 0, RK2928_CLKGATE_CON(1), 1, GFLAGS),
310
311 /* clk_core_pre gates */
312 GATE(0, "core_dbg", "armclk", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),
313
314 /* aclk_cpu gates */
315 GATE(ACLK_DMA1, "aclk_dma1", "aclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS),
316 GATE(0, "aclk_intmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 12, GFLAGS),
317 GATE(0, "aclk_strc_sys", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 10, GFLAGS),
318
319 /* hclk_cpu gates */
320 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS),
321 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
322 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS),
323 GATE(0, "hclk_cpubus", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 8, GFLAGS),
324 /* hclk_ahb2apb is part of a clk branch */
325 GATE(0, "hclk_vio_bus", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS),
326 GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS),
327 GATE(HCLK_LCDC1, "hclk_lcdc1", "aclk_cpu", 0, RK2928_CLKGATE_CON(6), 2, GFLAGS),
328 GATE(HCLK_CIF0, "hclk_cif0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS),
329 GATE(HCLK_IPP, "hclk_ipp", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 9, GFLAGS),
330 GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, GFLAGS),
331
332 /* hclk_peri gates */
333 GATE(0, "hclk_peri_axi_matrix", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 0, GFLAGS),
334 GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 6, GFLAGS),
335 GATE(0, "hclk_emem_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 7, GFLAGS),
336 GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
337 GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
338 GATE(0, "hclk_usb_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 5, GFLAGS),
339 GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 13, GFLAGS),
340 GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 5, GFLAGS),
341 GATE(HCLK_PIDF, "hclk_pidfilter", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 6, GFLAGS),
342 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
343 GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 11, GFLAGS),
344 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 12, GFLAGS),
345
346 /* aclk_lcdc0_pre gates */
347 GATE(0, "aclk_vio0", "aclk_lcdc0_pre", 0, RK2928_CLKGATE_CON(6), 13, GFLAGS),
348 GATE(ACLK_LCDC0, "aclk_lcdc0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 0, GFLAGS),
349 GATE(ACLK_CIF0, "aclk_cif0", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 5, GFLAGS),
350 GATE(ACLK_IPP, "aclk_ipp", "aclk_vio0", 0, RK2928_CLKGATE_CON(6), 8, GFLAGS),
351
352 /* aclk_lcdc1_pre gates */
353 GATE(0, "aclk_vio1", "aclk_lcdc1_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),
354 GATE(ACLK_LCDC1, "aclk_lcdc1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 3, GFLAGS),
355 GATE(ACLK_RGA, "aclk_rga", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 11, GFLAGS),
356
357 /* atclk_cpu gates */
358 GATE(0, "atclk", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 3, GFLAGS),
359 GATE(0, "trace", "atclk_cpu", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),
360
361 /* pclk_cpu gates */
362 GATE(PCLK_PWM01, "pclk_pwm01", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
363 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS),
364 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
365 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 5, GFLAGS),
366 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
367 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
368 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
369 GATE(PCLK_EFUSE, "pclk_efuse", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 2, GFLAGS),
370 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 3, GFLAGS),
371 GATE(0, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),
372 GATE(0, "pclk_ddrpubl", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 6, GFLAGS),
373 GATE(0, "pclk_dbg", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
374 GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 4, GFLAGS),
375 GATE(PCLK_PMU, "pclk_pmu", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 5, GFLAGS),
376
377 /* aclk_peri */
378 GATE(ACLK_DMA2, "aclk_dma2", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 1, GFLAGS),
379 GATE(ACLK_SMC, "aclk_smc", "aclk_peri", 0, RK2928_CLKGATE_CON(5), 8, GFLAGS),
380 GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 4, GFLAGS),
381 GATE(0, "aclk_cpu_peri", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 2, GFLAGS),
382 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", 0, RK2928_CLKGATE_CON(4), 3, GFLAGS),
383
384 /* pclk_peri gates */
385 GATE(0, "pclk_peri_axi_matrix", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 1, GFLAGS),
386 GATE(PCLK_PWM23, "pclk_pwm23", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 11, GFLAGS),
387 GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
388 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),
389 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 13, GFLAGS),
390 GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 2, GFLAGS),
391 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
392 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
393 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
394 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
395 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
396 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 14, GFLAGS),
397};
398
399PNAME(mux_rk3066_lcdc0_p) = { "dclk_lcdc0_src", "xin27m" };
400PNAME(mux_rk3066_lcdc1_p) = { "dclk_lcdc1_src", "xin27m" };
401PNAME(mux_sclk_cif1_p) = { "cif1_pre", "xin24m" };
402PNAME(mux_sclk_i2s1_p) = { "i2s1_pre", "i2s1_frac", "xin12m" };
403PNAME(mux_sclk_i2s2_p) = { "i2s2_pre", "i2s2_frac", "xin12m" };
404
405static struct clk_div_table div_aclk_cpu_t[] = {
406 { .val = 0, .div = 1 },
407 { .val = 1, .div = 2 },
408 { .val = 2, .div = 3 },
409 { .val = 3, .div = 4 },
410 { .val = 4, .div = 8 },
411 { /* sentinel */ },
412};
413
414static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
415 COMPOSITE_NOGATE(0, "armclk", mux_armclk_p, 0,
416 RK2928_CLKSEL_CON(0), 8, 1, MFLAGS, 0, 5, DFLAGS),
417 DIVTBL(0, "aclk_cpu_pre", "armclk", 0,
418 RK2928_CLKSEL_CON(1), 0, 3, DFLAGS, div_aclk_cpu_t),
419
420 GATE(CORE_L2C, "core_l2c", "aclk_cpu", 0,
421 RK2928_CLKGATE_CON(9), 4, GFLAGS),
422
423 COMPOSITE(0, "aclk_peri_pre", mux_pll_src_gpll_cpll_p, 0,
424 RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
425 RK2928_CLKGATE_CON(2), 0, GFLAGS),
426
427 COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0,
428 RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
429 RK2928_CLKGATE_CON(3), 1, GFLAGS),
430 MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, 0,
431 RK2928_CLKSEL_CON(27), 4, 1, MFLAGS),
432 COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0,
433 RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
434 RK2928_CLKGATE_CON(3), 2, GFLAGS),
435 MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, 0,
436 RK2928_CLKSEL_CON(28), 4, 1, MFLAGS),
437
438 COMPOSITE_NOMUX(0, "cif1_pre", "cif_src", 0,
439 RK2928_CLKSEL_CON(29), 8, 5, DFLAGS,
440 RK2928_CLKGATE_CON(3), 8, GFLAGS),
441 MUX(SCLK_CIF1, "sclk_cif1", mux_sclk_cif1_p, 0,
442 RK2928_CLKSEL_CON(29), 15, 1, MFLAGS),
443
444 GATE(0, "pclkin_cif1", "ext_cif1", 0,
445 RK2928_CLKGATE_CON(3), 4, GFLAGS),
446
447 COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
448 RK2928_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 5, DFLAGS,
449 RK2928_CLKGATE_CON(3), 13, GFLAGS),
450 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0,
451 RK2928_CLKGATE_CON(5), 15, GFLAGS),
452
453 GATE(SCLK_TIMER2, "timer2", "xin24m", 0,
454 RK2928_CLKGATE_CON(3), 2, GFLAGS),
455
456 COMPOSITE_NOMUX(0, "sclk_tsadc", "xin24m", 0,
457 RK2928_CLKSEL_CON(34), 0, 16, DFLAGS,
458 RK2928_CLKGATE_CON(2), 15, GFLAGS),
459
460 MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
461 RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
462 COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
463 RK2928_CLKSEL_CON(2), 0, 7, DFLAGS,
464 RK2928_CLKGATE_CON(0), 7, GFLAGS),
465 COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_pre", 0,
466 RK2928_CLKSEL_CON(6), 0,
467 RK2928_CLKGATE_CON(0), 8, GFLAGS),
468 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
469 RK2928_CLKSEL_CON(2), 8, 2, MFLAGS),
470 COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0,
471 RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
472 RK2928_CLKGATE_CON(0), 9, GFLAGS),
473 COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_pre", 0,
474 RK2928_CLKSEL_CON(7), 0,
475 RK2928_CLKGATE_CON(0), 10, GFLAGS),
476 MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, 0,
477 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
478 COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0,
479 RK2928_CLKSEL_CON(4), 0, 7, DFLAGS,
480 RK2928_CLKGATE_CON(0), 11, GFLAGS),
481 COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_pre", 0,
482 RK2928_CLKSEL_CON(8), 0,
483 RK2928_CLKGATE_CON(0), 12, GFLAGS),
484 MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0,
485 RK2928_CLKSEL_CON(4), 8, 2, MFLAGS),
486 COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
487 RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
488 RK2928_CLKGATE_CON(0), 13, GFLAGS),
489 COMPOSITE_FRAC(0, "spdif_frac", "spdif_pll", 0,
490 RK2928_CLKSEL_CON(9), 0,
491 RK2928_CLKGATE_CON(0), 14, GFLAGS),
492 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
493 RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),
494
495 GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
496 GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
497 GATE(0, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS),
498 GATE(0, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
499
500 GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
501
502 GATE(0, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS),
503
504 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 8, GFLAGS),
505 GATE(PCLK_TIMER2, "pclk_timer2", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
506 GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
507 GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
508 GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
509
510 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
511 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK2928_CLKGATE_CON(4), 13, GFLAGS),
512};
513
514static struct clk_div_table div_rk3188_aclk_core_t[] = {
515 { .val = 0, .div = 1 },
516 { .val = 1, .div = 2 },
517 { .val = 2, .div = 3 },
518 { .val = 3, .div = 4 },
519 { .val = 4, .div = 8 },
520 { /* sentinel */ },
521};
522
523PNAME(mux_hsicphy_p) = { "sclk_otgphy0", "sclk_otgphy1",
524 "gpll", "cpll" };
525
526static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
527 COMPOSITE_NOGATE(0, "armclk", mux_armclk_p, 0,
528 RK2928_CLKSEL_CON(0), 8, 1, MFLAGS, 9, 5, DFLAGS),
529 COMPOSITE_NOMUX_DIVTBL(0, "aclk_core", "armclk", 0,
530 RK2928_CLKSEL_CON(1), 3, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
531 div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS),
532
533 /* do not source aclk_cpu_pre from the apll, to keep complexity down */
534 COMPOSITE_NOGATE(0, "aclk_cpu_pre", mux_aclk_cpu_p, CLK_SET_RATE_NO_REPARENT,
535 RK2928_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS),
536
537 GATE(CORE_L2C, "core_l2c", "armclk", 0,
538 RK2928_CLKGATE_CON(9), 4, GFLAGS),
539
540 COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, 0,
541 RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
542 RK2928_CLKGATE_CON(2), 0, GFLAGS),
543
544 COMPOSITE(DCLK_LCDC0, "dclk_lcdc0", mux_pll_src_cpll_gpll_p, 0,
545 RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
546 RK2928_CLKGATE_CON(3), 1, GFLAGS),
547 COMPOSITE(DCLK_LCDC1, "dclk_lcdc1", mux_pll_src_cpll_gpll_p, 0,
548 RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
549 RK2928_CLKGATE_CON(3), 2, GFLAGS),
550
551 COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
552 RK2928_CLKSEL_CON(34), 7, 1, MFLAGS, 0, 5, DFLAGS,
553 RK2928_CLKGATE_CON(3), 15, GFLAGS),
554 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_src", 0,
555 RK2928_CLKGATE_CON(9), 7, GFLAGS),
556
557 GATE(SCLK_TIMER2, "timer2", "xin24m", 0, RK2928_CLKGATE_CON(3), 4, GFLAGS),
558 GATE(SCLK_TIMER3, "timer3", "xin24m", 0, RK2928_CLKGATE_CON(1), 2, GFLAGS),
559 GATE(SCLK_TIMER4, "timer4", "xin24m", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS),
560 GATE(SCLK_TIMER5, "timer5", "xin24m", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
561 GATE(SCLK_TIMER6, "timer6", "xin24m", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS),
562
563 COMPOSITE_NODIV(0, "sclk_hsicphy_480m", mux_hsicphy_p, 0,
564 RK2928_CLKSEL_CON(30), 0, 2, DFLAGS,
565 RK2928_CLKGATE_CON(3), 6, GFLAGS),
566 DIV(0, "sclk_hsicphy_12m", "sclk_hsicphy_480m", 0,
567 RK2928_CLKGATE_CON(11), 8, 6, DFLAGS),
568
569 MUX(0, "i2s_src", mux_pll_src_gpll_cpll_p, 0,
570 RK2928_CLKSEL_CON(2), 15, 1, MFLAGS),
571 COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
572 RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
573 RK2928_CLKGATE_CON(0), 9, GFLAGS),
574 COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_pre", 0,
575 RK2928_CLKSEL_CON(7), 0,
576 RK2928_CLKGATE_CON(0), 10, GFLAGS),
577 MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
578 RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
579 COMPOSITE_NOMUX(0, "spdif_pre", "i2s_src", 0,
580 RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
581 RK2928_CLKGATE_CON(13), 13, GFLAGS),
582 COMPOSITE_FRAC(0, "spdif_frac", "spdif_pll", 0,
583 RK2928_CLKSEL_CON(9), 0,
584 RK2928_CLKGATE_CON(0), 14, GFLAGS),
585 MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
586 RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),
587
588 GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
589 GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS),
590
591 GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
592 GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
593
594 GATE(PCLK_TIMER3, "pclk_timer3", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
595
596 GATE(PCLK_UART0, "pclk_uart0", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
597 GATE(PCLK_UART1, "pclk_uart1", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
598
599 GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
600};
601
602static void __init rk3188_common_clk_init(struct device_node *np)
603{
604 void __iomem *reg_base;
605 struct clk *clk;
606
607 reg_base = of_iomap(np, 0);
608 if (!reg_base) {
609 pr_err("%s: could not map cru region\n", __func__);
610 return;
611 }
612
613 rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
614
615 /* xin12m is created by an cru-internal divider */
616 clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
617 if (IS_ERR(clk))
618 pr_warn("%s: could not register clock xin12m: %ld\n",
619 __func__, PTR_ERR(clk));
620
621 clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
622 if (IS_ERR(clk))
623 pr_warn("%s: could not register clock usb480m: %ld\n",
624 __func__, PTR_ERR(clk));
625
626 rockchip_clk_register_plls(rk3188_pll_clks,
627 ARRAY_SIZE(rk3188_pll_clks),
628 RK3188_GRF_SOC_STATUS);
629 rockchip_clk_register_branches(common_clk_branches,
630 ARRAY_SIZE(common_clk_branches));
631
632 rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
633 ROCKCHIP_SOFTRST_HIWORD_MASK);
634}
635
636static void __init rk3066a_clk_init(struct device_node *np)
637{
638 rk3188_common_clk_init(np);
639 rockchip_clk_register_branches(rk3066a_clk_branches,
640 ARRAY_SIZE(rk3066a_clk_branches));
641}
642CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init);
643
644static void __init rk3188a_clk_init(struct device_node *np)
645{
646 rk3188_common_clk_init(np);
647 rockchip_clk_register_branches(rk3188_clk_branches,
648 ARRAY_SIZE(rk3188_clk_branches));
649}
650CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init);
651
652static void __init rk3188_clk_init(struct device_node *np)
653{
654 int i;
655
656 for (i = 0; i < ARRAY_SIZE(rk3188_pll_clks); i++) {
657 struct rockchip_pll_clock *pll = &rk3188_pll_clks[i];
658 struct rockchip_pll_rate_table *rate;
659
660 if (!pll->rate_table)
661 continue;
662
663 rate = pll->rate_table;
664 while (rate->rate > 0) {
665 rate->bwadj = 0;
666 rate++;
667 }
668 }
669
670 rk3188a_clk_init(np);
671}
672CLK_OF_DECLARE(rk3188_cru, "rockchip,rk3188-cru", rk3188_clk_init);
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
new file mode 100644
index 000000000000..0d8c6c59a75e
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -0,0 +1,717 @@
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk-provider.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <dt-bindings/clock/rk3288-cru.h>
20#include "clk.h"
21
22#define RK3288_GRF_SOC_CON(x) (0x244 + x * 4)
23#define RK3288_GRF_SOC_STATUS 0x280
24
25enum rk3288_plls {
26 apll, dpll, cpll, gpll, npll,
27};
28
29struct rockchip_pll_rate_table rk3288_pll_rates[] = {
30 RK3066_PLL_RATE(2208000000, 1, 92, 1),
31 RK3066_PLL_RATE(2184000000, 1, 91, 1),
32 RK3066_PLL_RATE(2160000000, 1, 90, 1),
33 RK3066_PLL_RATE(2136000000, 1, 89, 1),
34 RK3066_PLL_RATE(2112000000, 1, 88, 1),
35 RK3066_PLL_RATE(2088000000, 1, 87, 1),
36 RK3066_PLL_RATE(2064000000, 1, 86, 1),
37 RK3066_PLL_RATE(2040000000, 1, 85, 1),
38 RK3066_PLL_RATE(2016000000, 1, 84, 1),
39 RK3066_PLL_RATE(1992000000, 1, 83, 1),
40 RK3066_PLL_RATE(1968000000, 1, 82, 1),
41 RK3066_PLL_RATE(1944000000, 1, 81, 1),
42 RK3066_PLL_RATE(1920000000, 1, 80, 1),
43 RK3066_PLL_RATE(1896000000, 1, 79, 1),
44 RK3066_PLL_RATE(1872000000, 1, 78, 1),
45 RK3066_PLL_RATE(1848000000, 1, 77, 1),
46 RK3066_PLL_RATE(1824000000, 1, 76, 1),
47 RK3066_PLL_RATE(1800000000, 1, 75, 1),
48 RK3066_PLL_RATE(1776000000, 1, 74, 1),
49 RK3066_PLL_RATE(1752000000, 1, 73, 1),
50 RK3066_PLL_RATE(1728000000, 1, 72, 1),
51 RK3066_PLL_RATE(1704000000, 1, 71, 1),
52 RK3066_PLL_RATE(1680000000, 1, 70, 1),
53 RK3066_PLL_RATE(1656000000, 1, 69, 1),
54 RK3066_PLL_RATE(1632000000, 1, 68, 1),
55 RK3066_PLL_RATE(1608000000, 1, 67, 1),
56 RK3066_PLL_RATE(1560000000, 1, 65, 1),
57 RK3066_PLL_RATE(1512000000, 1, 63, 1),
58 RK3066_PLL_RATE(1488000000, 1, 62, 1),
59 RK3066_PLL_RATE(1464000000, 1, 61, 1),
60 RK3066_PLL_RATE(1440000000, 1, 60, 1),
61 RK3066_PLL_RATE(1416000000, 1, 59, 1),
62 RK3066_PLL_RATE(1392000000, 1, 58, 1),
63 RK3066_PLL_RATE(1368000000, 1, 57, 1),
64 RK3066_PLL_RATE(1344000000, 1, 56, 1),
65 RK3066_PLL_RATE(1320000000, 1, 55, 1),
66 RK3066_PLL_RATE(1296000000, 1, 54, 1),
67 RK3066_PLL_RATE(1272000000, 1, 53, 1),
68 RK3066_PLL_RATE(1248000000, 1, 52, 1),
69 RK3066_PLL_RATE(1224000000, 1, 51, 1),
70 RK3066_PLL_RATE(1200000000, 1, 50, 1),
71 RK3066_PLL_RATE(1188000000, 2, 99, 1),
72 RK3066_PLL_RATE(1176000000, 1, 49, 1),
73 RK3066_PLL_RATE(1128000000, 1, 47, 1),
74 RK3066_PLL_RATE(1104000000, 1, 46, 1),
75 RK3066_PLL_RATE(1008000000, 1, 84, 2),
76 RK3066_PLL_RATE( 912000000, 1, 76, 2),
77 RK3066_PLL_RATE( 891000000, 8, 594, 2),
78 RK3066_PLL_RATE( 888000000, 1, 74, 2),
79 RK3066_PLL_RATE( 816000000, 1, 68, 2),
80 RK3066_PLL_RATE( 798000000, 2, 133, 2),
81 RK3066_PLL_RATE( 792000000, 1, 66, 2),
82 RK3066_PLL_RATE( 768000000, 1, 64, 2),
83 RK3066_PLL_RATE( 742500000, 8, 495, 2),
84 RK3066_PLL_RATE( 696000000, 1, 58, 2),
85 RK3066_PLL_RATE( 600000000, 1, 50, 2),
86 RK3066_PLL_RATE( 594000000, 2, 198, 4),
87 RK3066_PLL_RATE( 552000000, 1, 46, 2),
88 RK3066_PLL_RATE( 504000000, 1, 84, 4),
89 RK3066_PLL_RATE( 456000000, 1, 76, 4),
90 RK3066_PLL_RATE( 408000000, 1, 68, 4),
91 RK3066_PLL_RATE( 384000000, 2, 128, 4),
92 RK3066_PLL_RATE( 360000000, 1, 60, 4),
93 RK3066_PLL_RATE( 312000000, 1, 52, 4),
94 RK3066_PLL_RATE( 300000000, 1, 50, 4),
95 RK3066_PLL_RATE( 297000000, 2, 198, 8),
96 RK3066_PLL_RATE( 252000000, 1, 84, 8),
97 RK3066_PLL_RATE( 216000000, 1, 72, 8),
98 RK3066_PLL_RATE( 148500000, 2, 99, 8),
99 RK3066_PLL_RATE( 126000000, 1, 84, 16),
100 RK3066_PLL_RATE( 48000000, 1, 64, 32),
101 { /* sentinel */ },
102};
103
104PNAME(mux_pll_p) = { "xin24m", "xin32k" };
105PNAME(mux_armclk_p) = { "apll_core", "gpll_core" };
106PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
107PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" };
108
109PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
110PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
111PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
112PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" };
113
114PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "xin24m" };
115PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
116PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
117PNAME(mux_spdif_p) = { "spdif_pre", "spdif_frac", "xin12m" };
118PNAME(mux_spdif_8ch_p) = { "spdif_8ch_pre", "spdif_8ch_frac", "xin12m" };
119PNAME(mux_uart0_pll_p) = { "cpll", "gpll", "usbphy_480m_src", "npll" };
120PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
121PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
122PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
123PNAME(mux_uart3_p) = { "uart3_src", "uart3_frac", "xin24m" };
124PNAME(mux_uart4_p) = { "uart4_src", "uart4_frac", "xin24m" };
125PNAME(mux_cif_out_p) = { "cif_src", "xin24m" };
126PNAME(mux_macref_p) = { "mac_src", "ext_gmac" };
127PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" };
128PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" };
129PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" };
130
131PNAME(mux_usbphy480m_p) = { "sclk_otgphy0", "sclk_otgphy1",
132 "sclk_otgphy2" };
133PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" };
134PNAME(mux_hsicphy12m_p) = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" };
135
136static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
137 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK3288_PLL_CON(0),
138 RK3288_MODE_CON, 0, 6, rk3288_pll_rates),
139 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),
140 RK3288_MODE_CON, 4, 5, NULL),
141 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
142 RK3288_MODE_CON, 8, 7, rk3288_pll_rates),
143 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
144 RK3288_MODE_CON, 12, 8, rk3288_pll_rates),
145 [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
146 RK3288_MODE_CON, 14, 9, NULL),
147};
148
149static struct clk_div_table div_hclk_cpu_t[] = {
150 { .val = 0, .div = 1 },
151 { .val = 1, .div = 2 },
152 { .val = 3, .div = 4 },
153 { /* sentinel */},
154};
155
156#define MFLAGS CLK_MUX_HIWORD_MASK
157#define DFLAGS CLK_DIVIDER_HIWORD_MASK
158#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
159
160static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
161 /*
162 * Clock-Architecture Diagram 1
163 */
164
165 GATE(0, "apll_core", "apll", 0,
166 RK3288_CLKGATE_CON(0), 1, GFLAGS),
167 GATE(0, "gpll_core", "gpll", 0,
168 RK3288_CLKGATE_CON(0), 2, GFLAGS),
169 COMPOSITE_NOGATE(0, "armclk", mux_armclk_p, 0,
170 RK3288_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
171
172 COMPOSITE_NOMUX(0, "armcore0", "armclk", 0,
173 RK3288_CLKSEL_CON(36), 0, 3, DFLAGS,
174 RK3288_CLKGATE_CON(12), 0, GFLAGS),
175 COMPOSITE_NOMUX(0, "armcore1", "armclk", 0,
176 RK3288_CLKSEL_CON(36), 4, 3, DFLAGS,
177 RK3288_CLKGATE_CON(12), 1, GFLAGS),
178 COMPOSITE_NOMUX(0, "armcore2", "armclk", 0,
179 RK3288_CLKSEL_CON(36), 8, 3, DFLAGS,
180 RK3288_CLKGATE_CON(12), 2, GFLAGS),
181 COMPOSITE_NOMUX(0, "armcore3", "armclk", 0,
182 RK3288_CLKSEL_CON(36), 12, 3, DFLAGS,
183 RK3288_CLKGATE_CON(12), 3, GFLAGS),
184 COMPOSITE_NOMUX(0, "l2ram", "armclk", 0,
185 RK3288_CLKSEL_CON(37), 0, 3, DFLAGS,
186 RK3288_CLKGATE_CON(12), 4, GFLAGS),
187 COMPOSITE_NOMUX(0, "aclk_core_m0", "armclk", 0,
188 RK3288_CLKSEL_CON(0), 0, 4, DFLAGS,
189 RK3288_CLKGATE_CON(12), 5, GFLAGS),
190 COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", 0,
191 RK3288_CLKSEL_CON(0), 4, 4, DFLAGS,
192 RK3288_CLKGATE_CON(12), 6, GFLAGS),
193 COMPOSITE_NOMUX(0, "atclk", "armclk", 0,
194 RK3288_CLKSEL_CON(37), 4, 5, DFLAGS,
195 RK3288_CLKGATE_CON(12), 7, GFLAGS),
196 COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", 0,
197 RK3288_CLKSEL_CON(37), 9, 5, DFLAGS,
198 RK3288_CLKGATE_CON(12), 8, GFLAGS),
199 GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
200 RK3288_CLKGATE_CON(12), 9, GFLAGS),
201 GATE(0, "cs_dbg", "pclk_dbg_pre", 0,
202 RK3288_CLKGATE_CON(12), 10, GFLAGS),
203 GATE(0, "pclk_core_niu", "pclk_dbg_pre", 0,
204 RK3288_CLKGATE_CON(12), 11, GFLAGS),
205
206 GATE(0, "dpll_ddr", "dpll", 0,
207 RK3288_CLKGATE_CON(0), 8, GFLAGS),
208 GATE(0, "gpll_ddr", "gpll", 0,
209 RK3288_CLKGATE_CON(0), 9, GFLAGS),
210 COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, 0,
211 RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2,
212 DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
213
214 GATE(0, "gpll_aclk_cpu", "gpll", 0,
215 RK3288_CLKGATE_CON(0), 10, GFLAGS),
216 GATE(0, "cpll_aclk_cpu", "cpll", 0,
217 RK3288_CLKGATE_CON(0), 11, GFLAGS),
218 COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
219 RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),
220 DIV(0, "aclk_cpu_pre", "aclk_cpu_src", 0,
221 RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
222 GATE(0, "aclk_cpu", "aclk_cpu_pre", 0,
223 RK3288_CLKGATE_CON(0), 3, GFLAGS),
224 COMPOSITE_NOMUX(0, "pclk_cpu", "aclk_cpu_pre", 0,
225 RK3288_CLKSEL_CON(1), 12, 3, DFLAGS,
226 RK3288_CLKGATE_CON(0), 5, GFLAGS),
227 COMPOSITE_NOMUX_DIVTBL(0, "hclk_cpu", "aclk_cpu_pre", 0,
228 RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t,
229 RK3288_CLKGATE_CON(0), 4, GFLAGS),
230 GATE(0, "c2c_host", "aclk_cpu_src", 0,
231 RK3288_CLKGATE_CON(13), 8, GFLAGS),
232 COMPOSITE_NOMUX(0, "crypto", "aclk_cpu_pre", 0,
233 RK3288_CLKSEL_CON(26), 6, 2, DFLAGS,
234 RK3288_CLKGATE_CON(5), 4, GFLAGS),
235 GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", 0,
236 RK3288_CLKGATE_CON(0), 7, GFLAGS),
237
238 COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
239 RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
240 RK3288_CLKGATE_CON(4), 1, GFLAGS),
241 COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", 0,
242 RK3288_CLKSEL_CON(8), 0,
243 RK3288_CLKGATE_CON(4), 2, GFLAGS),
244 MUX(0, "i2s_pre", mux_i2s_pre_p, 0,
245 RK3288_CLKSEL_CON(4), 8, 2, MFLAGS),
246 COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, 0,
247 RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
248 RK3288_CLKGATE_CON(4), 0, GFLAGS),
249 GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", 0,
250 RK3288_CLKGATE_CON(4), 3, GFLAGS),
251
252 MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
253 RK3288_CLKSEL_CON(5), 15, 1, MFLAGS),
254 COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", 0,
255 RK3288_CLKSEL_CON(5), 0, 7, DFLAGS,
256 RK3288_CLKGATE_CON(4), 4, GFLAGS),
257 COMPOSITE_FRAC(0, "spdif_frac", "spdif_src", 0,
258 RK3288_CLKSEL_CON(9), 0,
259 RK3288_CLKGATE_CON(4), 5, GFLAGS),
260 COMPOSITE_NODIV(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0,
261 RK3288_CLKSEL_CON(5), 8, 2, MFLAGS,
262 RK3288_CLKGATE_CON(4), 6, GFLAGS),
263 COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", 0,
264 RK3288_CLKSEL_CON(40), 0, 7, DFLAGS,
265 RK3288_CLKGATE_CON(4), 7, GFLAGS),
266 COMPOSITE_FRAC(0, "spdif_8ch_frac", "spdif_8ch_src", 0,
267 RK3288_CLKSEL_CON(41), 0,
268 RK3288_CLKGATE_CON(4), 8, GFLAGS),
269 COMPOSITE_NODIV(SCLK_SPDIF8CH, "sclk_spdif_8ch", mux_spdif_8ch_p, 0,
270 RK3288_CLKSEL_CON(40), 8, 2, MFLAGS,
271 RK3288_CLKGATE_CON(4), 9, GFLAGS),
272
273 GATE(0, "sclk_acc_efuse", "xin24m", 0,
274 RK3288_CLKGATE_CON(0), 12, GFLAGS),
275
276 GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
277 RK3288_CLKGATE_CON(1), 0, GFLAGS),
278 GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
279 RK3288_CLKGATE_CON(1), 1, GFLAGS),
280 GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
281 RK3288_CLKGATE_CON(1), 2, GFLAGS),
282 GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
283 RK3288_CLKGATE_CON(1), 3, GFLAGS),
284 GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
285 RK3288_CLKGATE_CON(1), 4, GFLAGS),
286 GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
287 RK3288_CLKGATE_CON(1), 5, GFLAGS),
288
289 /*
290 * Clock-Architecture Diagram 2
291 */
292
293 COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_usb480m_p, 0,
294 RK3288_CLKSEL_CON(32), 6, 2, MFLAGS, 0, 5, DFLAGS,
295 RK3288_CLKGATE_CON(3), 9, GFLAGS),
296 COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
297 RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
298 RK3288_CLKGATE_CON(3), 11, GFLAGS),
299
300 COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, 0,
301 RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
302 RK3288_CLKGATE_CON(3), 0, GFLAGS),
303 DIV(0, "hclk_vio", "aclk_vio0", 0,
304 RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
305 COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, 0,
306 RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
307 RK3288_CLKGATE_CON(3), 2, GFLAGS),
308
309 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb480m_p, 0,
310 RK3288_CLKSEL_CON(30), 6, 2, MFLAGS, 0, 5, DFLAGS,
311 RK3288_CLKGATE_CON(3), 5, GFLAGS),
312 COMPOSITE(0, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0,
313 RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
314 RK3288_CLKGATE_CON(3), 4, GFLAGS),
315
316 COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
317 RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
318 RK3288_CLKGATE_CON(3), 1, GFLAGS),
319 COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
320 RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,
321 RK3288_CLKGATE_CON(3), 3, GFLAGS),
322
323 COMPOSITE_NODIV(0, "sclk_edp_24m", mux_edp_24m_p, 0,
324 RK3288_CLKSEL_CON(28), 15, 1, MFLAGS,
325 RK3288_CLKGATE_CON(3), 12, GFLAGS),
326 COMPOSITE(0, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
327 RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS,
328 RK3288_CLKGATE_CON(3), 13, GFLAGS),
329
330 COMPOSITE(0, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
331 RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
332 RK3288_CLKGATE_CON(3), 14, GFLAGS),
333 COMPOSITE(0, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
334 RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
335 RK3288_CLKGATE_CON(3), 15, GFLAGS),
336
337 GATE(0, "sclk_hdmi_hdcp", "xin24m", 0,
338 RK3288_CLKGATE_CON(5), 12, GFLAGS),
339 GATE(0, "sclk_hdmi_cec", "xin32k", 0,
340 RK3288_CLKGATE_CON(5), 11, GFLAGS),
341
342 COMPOSITE(0, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
343 RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS,
344 RK3288_CLKGATE_CON(13), 13, GFLAGS),
345 DIV(0, "hclk_hevc", "aclk_hevc", 0,
346 RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),
347
348 COMPOSITE(0, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0,
349 RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
350 RK3288_CLKGATE_CON(13), 14, GFLAGS),
351 COMPOSITE(0, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0,
352 RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
353 RK3288_CLKGATE_CON(13), 15, GFLAGS),
354
355 COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
356 RK3288_CLKSEL_CON(26), 8, 1, MFLAGS,
357 RK3288_CLKGATE_CON(3), 7, GFLAGS),
358 COMPOSITE_NOGATE(0, "sclk_vip_out", mux_cif_out_p, 0,
359 RK3288_CLKSEL_CON(26), 15, 1, MFLAGS, 9, 5, DFLAGS),
360
361 DIV(0, "pclk_pd_alive", "gpll", 0,
362 RK3288_CLKSEL_CON(33), 8, 5, DFLAGS),
363 COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", 0,
364 RK3288_CLKSEL_CON(33), 0, 5, DFLAGS,
365 RK3288_CLKGATE_CON(5), 8, GFLAGS),
366
367 COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
368 RK3288_CLKSEL_CON(34), 6, 2, MFLAGS, 0, 5, DFLAGS,
369 RK3288_CLKGATE_CON(5), 7, GFLAGS),
370
371 COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, 0,
372 RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
373 RK3288_CLKGATE_CON(2), 0, GFLAGS),
374 COMPOSITE_NOMUX(0, "pclk_peri", "aclk_peri_src", 0,
375 RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
376 RK3288_CLKGATE_CON(2), 3, GFLAGS),
377 COMPOSITE_NOMUX(0, "hclk_peri", "aclk_peri_src", 0,
378 RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
379 RK3288_CLKGATE_CON(2), 2, GFLAGS),
380 GATE(0, "aclk_peri", "aclk_peri_src", 0,
381 RK3288_CLKGATE_CON(2), 1, GFLAGS),
382
383 /*
384 * Clock-Architecture Diagram 3
385 */
386
387 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
388 RK3288_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
389 RK3288_CLKGATE_CON(2), 9, GFLAGS),
390 COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0,
391 RK3288_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
392 RK3288_CLKGATE_CON(2), 10, GFLAGS),
393 COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
394 RK3288_CLKSEL_CON(39), 7, 1, MFLAGS, 0, 7, DFLAGS,
395 RK3288_CLKGATE_CON(2), 11, GFLAGS),
396
397 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
398 RK3288_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
399 RK3288_CLKGATE_CON(13), 0, GFLAGS),
400 COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0,
401 RK3288_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 6, DFLAGS,
402 RK3288_CLKGATE_CON(13), 1, GFLAGS),
403 COMPOSITE(SCLK_SDIO1, "sclk_sdio1", mux_mmc_src_p, 0,
404 RK3288_CLKSEL_CON(34), 14, 2, MFLAGS, 8, 6, DFLAGS,
405 RK3288_CLKGATE_CON(13), 2, GFLAGS),
406 COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
407 RK3288_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS,
408 RK3288_CLKGATE_CON(13), 3, GFLAGS),
409
410 COMPOSITE(0, "sclk_tspout", mux_tspout_p, 0,
411 RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
412 RK3288_CLKGATE_CON(4), 11, GFLAGS),
413 COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
414 RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
415 RK3288_CLKGATE_CON(4), 10, GFLAGS),
416
417 GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", 0,
418 RK3288_CLKGATE_CON(13), 4, GFLAGS),
419 GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", 0,
420 RK3288_CLKGATE_CON(13), 5, GFLAGS),
421 GATE(SCLK_OTGPHY2, "sclk_otgphy2", "usb480m", 0,
422 RK3288_CLKGATE_CON(13), 6, GFLAGS),
423 GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", 0,
424 RK3288_CLKGATE_CON(13), 7, GFLAGS),
425
426 COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin32k", 0,
427 RK3288_CLKSEL_CON(2), 0, 6, DFLAGS,
428 RK3288_CLKGATE_CON(2), 7, GFLAGS),
429
430 COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
431 RK3288_CLKSEL_CON(24), 8, 8, DFLAGS,
432 RK3288_CLKGATE_CON(2), 8, GFLAGS),
433
434 GATE(SCLK_PS2C, "sclk_ps2c", "xin24m", 0,
435 RK3288_CLKGATE_CON(5), 13, GFLAGS),
436
437 COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0,
438 RK3288_CLKSEL_CON(38), 7, 1, MFLAGS, 0, 5, DFLAGS,
439 RK3288_CLKGATE_CON(5), 5, GFLAGS),
440 COMPOSITE(SCLK_NANDC1, "sclk_nandc1", mux_pll_src_cpll_gpll_p, 0,
441 RK3288_CLKSEL_CON(38), 15, 1, MFLAGS, 8, 5, DFLAGS,
442 RK3288_CLKGATE_CON(5), 6, GFLAGS),
443
444 COMPOSITE(0, "uart0_src", mux_uart0_pll_p, 0,
445 RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS,
446 RK3288_CLKGATE_CON(1), 8, GFLAGS),
447 COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", 0,
448 RK3288_CLKSEL_CON(17), 0,
449 RK3288_CLKGATE_CON(1), 9, GFLAGS),
450 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, 0,
451 RK3288_CLKSEL_CON(13), 8, 2, MFLAGS),
452 MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
453 RK3288_CLKSEL_CON(13), 15, 1, MFLAGS),
454 COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
455 RK3288_CLKSEL_CON(14), 0, 7, DFLAGS,
456 RK3288_CLKGATE_CON(1), 10, GFLAGS),
457 COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", 0,
458 RK3288_CLKSEL_CON(18), 0,
459 RK3288_CLKGATE_CON(1), 11, GFLAGS),
460 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, 0,
461 RK3288_CLKSEL_CON(14), 8, 2, MFLAGS),
462 COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
463 RK3288_CLKSEL_CON(15), 0, 7, DFLAGS,
464 RK3288_CLKGATE_CON(1), 12, GFLAGS),
465 COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", 0,
466 RK3288_CLKSEL_CON(19), 0,
467 RK3288_CLKGATE_CON(1), 13, GFLAGS),
468 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, 0,
469 RK3288_CLKSEL_CON(15), 8, 2, MFLAGS),
470 COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
471 RK3288_CLKSEL_CON(16), 0, 7, DFLAGS,
472 RK3288_CLKGATE_CON(1), 14, GFLAGS),
473 COMPOSITE_FRAC(0, "uart3_frac", "uart3_src", 0,
474 RK3288_CLKSEL_CON(20), 0,
475 RK3288_CLKGATE_CON(1), 15, GFLAGS),
476 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, 0,
477 RK3288_CLKSEL_CON(16), 8, 2, MFLAGS),
478 COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
479 RK3288_CLKSEL_CON(3), 0, 7, DFLAGS,
480 RK3288_CLKGATE_CON(2), 12, GFLAGS),
481 COMPOSITE_FRAC(0, "uart4_frac", "uart4_src", 0,
482 RK3288_CLKSEL_CON(7), 0,
483 RK3288_CLKGATE_CON(2), 13, GFLAGS),
484 MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, 0,
485 RK3288_CLKSEL_CON(3), 8, 2, MFLAGS),
486
487 COMPOSITE(0, "mac_src", mux_pll_src_npll_cpll_gpll_p, 0,
488 RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS,
489 RK3288_CLKGATE_CON(2), 5, GFLAGS),
490 MUX(0, "macref", mux_macref_p, 0,
491 RK3288_CLKSEL_CON(21), 4, 1, MFLAGS),
492 GATE(0, "sclk_macref_out", "macref", 0,
493 RK3288_CLKGATE_CON(5), 3, GFLAGS),
494 GATE(SCLK_MACREF, "sclk_macref", "macref", 0,
495 RK3288_CLKGATE_CON(5), 2, GFLAGS),
496 GATE(SCLK_MAC_RX, "sclk_mac_rx", "macref", 0,
497 RK3288_CLKGATE_CON(5), 0, GFLAGS),
498 GATE(SCLK_MAC_TX, "sclk_mac_tx", "macref", 0,
499 RK3288_CLKGATE_CON(5), 1, GFLAGS),
500
501 COMPOSITE(0, "hsadc_src", mux_pll_src_cpll_gpll_p, 0,
502 RK3288_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
503 RK3288_CLKGATE_CON(2), 6, GFLAGS),
504 MUX(SCLK_HSADC, "sclk_hsadc_out", mux_hsadcout_p, 0,
505 RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
506
507 GATE(0, "jtag", "ext_jtag", 0,
508 RK3288_CLKGATE_CON(4), 14, GFLAGS),
509
510 COMPOSITE_NODIV(0, "usbphy480m_src", mux_usbphy480m_p, 0,
511 RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
512 RK3288_CLKGATE_CON(5), 15, GFLAGS),
513 COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
514 RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
515 RK3288_CLKGATE_CON(3), 6, GFLAGS),
516 GATE(0, "hsicphy12m_xin12m", "xin12m", 0,
517 RK3288_CLKGATE_CON(13), 9, GFLAGS),
518 DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0,
519 RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),
520 MUX(SCLK_HSICPHY12M, "sclk_hsicphy12m", mux_hsicphy12m_p, 0,
521 RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
522
523 /*
524 * Clock-Architecture Diagram 4
525 */
526
527 /* aclk_cpu gates */
528 GATE(0, "sclk_intmem0", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 5, GFLAGS),
529 GATE(0, "sclk_intmem1", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 6, GFLAGS),
530 GATE(0, "sclk_intmem2", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 7, GFLAGS),
531 GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 12, GFLAGS),
532 GATE(0, "aclk_strc_sys", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 13, GFLAGS),
533 GATE(0, "aclk_intmem", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 4, GFLAGS),
534 GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 6, GFLAGS),
535 GATE(0, "aclk_ccp", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 8, GFLAGS),
536
537 /* hclk_cpu gates */
538 GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK3288_CLKGATE_CON(11), 7, GFLAGS),
539 GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 8, GFLAGS),
540 GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 9, GFLAGS),
541 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 10, GFLAGS),
542 GATE(HCLK_SPDIF8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 11, GFLAGS),
543
544 /* pclk_cpu gates */
545 GATE(PCLK_PWM, "pclk_pwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 0, GFLAGS),
546 GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 1, GFLAGS),
547 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 2, GFLAGS),
548 GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 3, GFLAGS),
549 GATE(0, "pclk_ddrupctl0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 14, GFLAGS),
550 GATE(0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS),
551 GATE(0, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS),
552 GATE(0, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS),
553 GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS),
554 GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS),
555 GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),
556 GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
557 GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 11, GFLAGS),
558
559 /* ddrctrl [DDR Controller PHY clock] gates */
560 GATE(0, "nclk_ddrupctl0", "ddrphy", 0, RK3288_CLKGATE_CON(11), 4, GFLAGS),
561 GATE(0, "nclk_ddrupctl1", "ddrphy", 0, RK3288_CLKGATE_CON(11), 5, GFLAGS),
562
563 /* ddrphy gates */
564 GATE(0, "sclk_ddrphy0", "ddrphy", 0, RK3288_CLKGATE_CON(4), 12, GFLAGS),
565 GATE(0, "sclk_ddrphy1", "ddrphy", 0, RK3288_CLKGATE_CON(4), 13, GFLAGS),
566
567 /* aclk_peri gates */
568 GATE(0, "aclk_peri_axi_matrix", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 2, GFLAGS),
569 GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 3, GFLAGS),
570 GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK3288_CLKGATE_CON(7), 11, GFLAGS),
571 GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 12, GFLAGS),
572 GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 0, GFLAGS),
573 GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 2, GFLAGS),
574
575 /* hclk_peri gates */
576 GATE(0, "hclk_peri_matrix", "hclk_peri", 0, RK3288_CLKGATE_CON(6), 0, GFLAGS),
577 GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 4, GFLAGS),
578 GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 6, GFLAGS),
579 GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 7, GFLAGS),
580 GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 8, GFLAGS),
581 GATE(0, "hclk_usb_peri", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 9, GFLAGS),
582 GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 10, GFLAGS),
583 GATE(0, "hclk_emem", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 12, GFLAGS),
584 GATE(0, "hclk_mem", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 13, GFLAGS),
585 GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 14, GFLAGS),
586 GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 15, GFLAGS),
587 GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 8, GFLAGS),
588 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 3, GFLAGS),
589 GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 4, GFLAGS),
590 GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 5, GFLAGS),
591 GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 6, GFLAGS),
592 GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 7, GFLAGS),
593 GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 5, GFLAGS),
594
595 /* pclk_peri gates */
596 GATE(0, "pclk_peri_matrix", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 1, GFLAGS),
597 GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 4, GFLAGS),
598 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 5, GFLAGS),
599 GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 6, GFLAGS),
600 GATE(PCLK_PS2C, "pclk_ps2c", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 7, GFLAGS),
601 GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 8, GFLAGS),
602 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 9, GFLAGS),
603 GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 15, GFLAGS),
604 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 11, GFLAGS),
605 GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 12, GFLAGS),
606 GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 13, GFLAGS),
607 GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 14, GFLAGS),
608 GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 1, GFLAGS),
609 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 2, GFLAGS),
610 GATE(PCLK_SIM, "pclk_sim", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 3, GFLAGS),
611 GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 0, GFLAGS),
612 GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK3288_CLKGATE_CON(8), 1, GFLAGS),
613
614 GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m", 0, RK3288_CLKGATE_CON(13), 10, GFLAGS),
615 GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS),
616 GATE(0, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS),
617 GATE(0, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS),
618 GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),
619
620 /* sclk_gpu gates */
621 GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0, GFLAGS),
622
623 /* pclk_pd_alive gates */
624 GATE(PCLK_GPIO8, "pclk_gpio8", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 8, GFLAGS),
625 GATE(PCLK_GPIO7, "pclk_gpio7", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 7, GFLAGS),
626 GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 1, GFLAGS),
627 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 2, GFLAGS),
628 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 3, GFLAGS),
629 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 4, GFLAGS),
630 GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 5, GFLAGS),
631 GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 6, GFLAGS),
632 GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 11, GFLAGS),
633 GATE(0, "pclk_alive_niu", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 12, GFLAGS),
634
635 /* pclk_pd_pmu gates */
636 GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 0, GFLAGS),
637 GATE(0, "pclk_intmem1", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 1, GFLAGS),
638 GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 2, GFLAGS),
639 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 3, GFLAGS),
640 GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 4, GFLAGS),
641
642 /* hclk_vio gates */
643 GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS),
644 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS),
645 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS),
646 GATE(0, "hclk_vio_ahb_arbi", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 9, GFLAGS),
647 GATE(0, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS),
648 GATE(0, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),
649 GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS),
650 GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS),
651 GATE(0, "hclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 10, GFLAGS),
652 GATE(0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS),
653 GATE(0, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),
654 GATE(0, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS),
655 GATE(0, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS),
656 GATE(0, "pclk_edp_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 8, GFLAGS),
657 GATE(0, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS),
658 GATE(0, "pclk_vio2_h2p", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 11, GFLAGS),
659
660 /* aclk_vio0 gates */
661 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS),
662 GATE(0, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS),
663 GATE(0, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS),
664 GATE(0, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),
665
666 /* aclk_vio1 gates */
667 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS),
668 GATE(0, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS),
669 GATE(0, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS),
670
671 /* aclk_rga_pre gates */
672 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS),
673 GATE(0, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS),
674
675 /*
676 * Other ungrouped clocks.
677 */
678
679 GATE(0, "pclk_vip_in", "ext_vip", 0, RK3288_CLKGATE_CON(16), 0, GFLAGS),
680 GATE(0, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),
681};
682
683static void __init rk3288_clk_init(struct device_node *np)
684{
685 void __iomem *reg_base;
686 struct clk *clk;
687
688 reg_base = of_iomap(np, 0);
689 if (!reg_base) {
690 pr_err("%s: could not map cru region\n", __func__);
691 return;
692 }
693
694 rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
695
696 /* xin12m is created by an cru-internal divider */
697 clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
698 if (IS_ERR(clk))
699 pr_warn("%s: could not register clock xin12m: %ld\n",
700 __func__, PTR_ERR(clk));
701
702
703 clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
704 if (IS_ERR(clk))
705 pr_warn("%s: could not register clock usb480m: %ld\n",
706 __func__, PTR_ERR(clk));
707
708 rockchip_clk_register_plls(rk3288_pll_clks,
709 ARRAY_SIZE(rk3288_pll_clks),
710 RK3288_GRF_SOC_STATUS);
711 rockchip_clk_register_branches(rk3288_clk_branches,
712 ARRAY_SIZE(rk3288_clk_branches));
713
714 rockchip_register_softrst(np, 9, reg_base + RK3288_SOFTRST_CON(0),
715 ROCKCHIP_SOFTRST_HIWORD_MASK);
716}
717CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
new file mode 100644
index 000000000000..278cf9dd1e23
--- /dev/null
+++ b/drivers/clk/rockchip/clk.c
@@ -0,0 +1,244 @@
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * based on
6 *
7 * samsung/clk.c
8 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
9 * Copyright (c) 2013 Linaro Ltd.
10 * Author: Thomas Abraham <thomas.ab@samsung.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 */
22
23#include <linux/slab.h>
24#include <linux/clk.h>
25#include <linux/clk-provider.h>
26#include <linux/mfd/syscon.h>
27#include <linux/regmap.h>
28#include "clk.h"
29
30/**
31 * Register a clock branch.
32 * Most clock branches have a form like
33 *
34 * src1 --|--\
35 * |M |--[GATE]-[DIV]-
36 * src2 --|--/
37 *
38 * sometimes without one of those components.
39 */
40struct clk *rockchip_clk_register_branch(const char *name,
41 const char **parent_names, u8 num_parents, void __iomem *base,
42 int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
43 u8 div_shift, u8 div_width, u8 div_flags,
44 struct clk_div_table *div_table, int gate_offset,
45 u8 gate_shift, u8 gate_flags, unsigned long flags,
46 spinlock_t *lock)
47{
48 struct clk *clk;
49 struct clk_mux *mux = NULL;
50 struct clk_gate *gate = NULL;
51 struct clk_divider *div = NULL;
52 const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
53 *gate_ops = NULL;
54
55 if (num_parents > 1) {
56 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
57 if (!mux)
58 return ERR_PTR(-ENOMEM);
59
60 mux->reg = base + muxdiv_offset;
61 mux->shift = mux_shift;
62 mux->mask = BIT(mux_width) - 1;
63 mux->flags = mux_flags;
64 mux->lock = lock;
65 mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
66 : &clk_mux_ops;
67 }
68
69 if (gate_offset >= 0) {
70 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
71 if (!gate)
72 return ERR_PTR(-ENOMEM);
73
74 gate->flags = gate_flags;
75 gate->reg = base + gate_offset;
76 gate->bit_idx = gate_shift;
77 gate->lock = lock;
78 gate_ops = &clk_gate_ops;
79 }
80
81 if (div_width > 0) {
82 div = kzalloc(sizeof(*div), GFP_KERNEL);
83 if (!div)
84 return ERR_PTR(-ENOMEM);
85
86 div->flags = div_flags;
87 div->reg = base + muxdiv_offset;
88 div->shift = div_shift;
89 div->width = div_width;
90 div->lock = lock;
91 div->table = div_table;
92 div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
93 ? &clk_divider_ro_ops
94 : &clk_divider_ops;
95 }
96
97 clk = clk_register_composite(NULL, name, parent_names, num_parents,
98 mux ? &mux->hw : NULL, mux_ops,
99 div ? &div->hw : NULL, div_ops,
100 gate ? &gate->hw : NULL, gate_ops,
101 flags);
102
103 return clk;
104}
105
106static DEFINE_SPINLOCK(clk_lock);
107static struct clk **clk_table;
108static void __iomem *reg_base;
109static struct clk_onecell_data clk_data;
110static struct device_node *cru_node;
111static struct regmap *grf;
112
113void __init rockchip_clk_init(struct device_node *np, void __iomem *base,
114 unsigned long nr_clks)
115{
116 reg_base = base;
117 cru_node = np;
118 grf = ERR_PTR(-EPROBE_DEFER);
119
120 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
121 if (!clk_table)
122 pr_err("%s: could not allocate clock lookup table\n", __func__);
123
124 clk_data.clks = clk_table;
125 clk_data.clk_num = nr_clks;
126 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
127}
128
129struct regmap *rockchip_clk_get_grf(void)
130{
131 if (IS_ERR(grf))
132 grf = syscon_regmap_lookup_by_phandle(cru_node, "rockchip,grf");
133 return grf;
134}
135
136void rockchip_clk_add_lookup(struct clk *clk, unsigned int id)
137{
138 if (clk_table && id)
139 clk_table[id] = clk;
140}
141
142void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list,
143 unsigned int nr_pll, int grf_lock_offset)
144{
145 struct clk *clk;
146 int idx;
147
148 for (idx = 0; idx < nr_pll; idx++, list++) {
149 clk = rockchip_clk_register_pll(list->type, list->name,
150 list->parent_names, list->num_parents,
151 reg_base, list->con_offset, grf_lock_offset,
152 list->lock_shift, list->mode_offset,
153 list->mode_shift, list->rate_table, &clk_lock);
154 if (IS_ERR(clk)) {
155 pr_err("%s: failed to register clock %s\n", __func__,
156 list->name);
157 continue;
158 }
159
160 rockchip_clk_add_lookup(clk, list->id);
161 }
162}
163
164void __init rockchip_clk_register_branches(
165 struct rockchip_clk_branch *list,
166 unsigned int nr_clk)
167{
168 struct clk *clk = NULL;
169 unsigned int idx;
170 unsigned long flags;
171
172 for (idx = 0; idx < nr_clk; idx++, list++) {
173 flags = list->flags;
174
175 /* catch simple muxes */
176 switch (list->branch_type) {
177 case branch_mux:
178 clk = clk_register_mux(NULL, list->name,
179 list->parent_names, list->num_parents,
180 flags, reg_base + list->muxdiv_offset,
181 list->mux_shift, list->mux_width,
182 list->mux_flags, &clk_lock);
183 break;
184 case branch_divider:
185 if (list->div_table)
186 clk = clk_register_divider_table(NULL,
187 list->name, list->parent_names[0],
188 flags, reg_base + list->muxdiv_offset,
189 list->div_shift, list->div_width,
190 list->div_flags, list->div_table,
191 &clk_lock);
192 else
193 clk = clk_register_divider(NULL, list->name,
194 list->parent_names[0], flags,
195 reg_base + list->muxdiv_offset,
196 list->div_shift, list->div_width,
197 list->div_flags, &clk_lock);
198 break;
199 case branch_fraction_divider:
200 /* unimplemented */
201 continue;
202 break;
203 case branch_gate:
204 flags |= CLK_SET_RATE_PARENT;
205
206 /* keep all gates untouched for now */
207 flags |= CLK_IGNORE_UNUSED;
208
209 clk = clk_register_gate(NULL, list->name,
210 list->parent_names[0], flags,
211 reg_base + list->gate_offset,
212 list->gate_shift, list->gate_flags, &clk_lock);
213 break;
214 case branch_composite:
215 /* keep all gates untouched for now */
216 flags |= CLK_IGNORE_UNUSED;
217
218 clk = rockchip_clk_register_branch(list->name,
219 list->parent_names, list->num_parents,
220 reg_base, list->muxdiv_offset, list->mux_shift,
221 list->mux_width, list->mux_flags,
222 list->div_shift, list->div_width,
223 list->div_flags, list->div_table,
224 list->gate_offset, list->gate_shift,
225 list->gate_flags, flags, &clk_lock);
226 break;
227 }
228
229 /* none of the cases above matched */
230 if (!clk) {
231 pr_err("%s: unknown clock type %d\n",
232 __func__, list->branch_type);
233 continue;
234 }
235
236 if (IS_ERR(clk)) {
237 pr_err("%s: failed to register clock %s: %ld\n",
238 __func__, list->name, PTR_ERR(clk));
239 continue;
240 }
241
242 rockchip_clk_add_lookup(clk, list->id);
243 }
244}
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
new file mode 100644
index 000000000000..887cbdeca2aa
--- /dev/null
+++ b/drivers/clk/rockchip/clk.h
@@ -0,0 +1,347 @@
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * based on
6 *
7 * samsung/clk.h
8 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
9 * Copyright (c) 2013 Linaro Ltd.
10 * Author: Thomas Abraham <thomas.ab@samsung.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 */
22
23#ifndef CLK_ROCKCHIP_CLK_H
24#define CLK_ROCKCHIP_CLK_H
25
26#include <linux/io.h>
27#include <linux/clk.h>
28#include <linux/clk-provider.h>
29
30#define HIWORD_UPDATE(val, mask, shift) \
31 ((val) << (shift) | (mask) << ((shift) + 16))
32
33/* register positions shared by RK2928, RK3066 and RK3188 */
34#define RK2928_PLL_CON(x) (x * 0x4)
35#define RK2928_MODE_CON 0x40
36#define RK2928_CLKSEL_CON(x) (x * 0x4 + 0x44)
37#define RK2928_CLKGATE_CON(x) (x * 0x4 + 0xd0)
38#define RK2928_GLB_SRST_FST 0x100
39#define RK2928_GLB_SRST_SND 0x104
40#define RK2928_SOFTRST_CON(x) (x * 0x4 + 0x110)
41#define RK2928_MISC_CON 0x134
42
43#define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
44#define RK3288_MODE_CON 0x50
45#define RK3288_CLKSEL_CON(x) (x * 0x4 + 0x60)
46#define RK3288_CLKGATE_CON(x) (x * 0x4 + 0x160)
47#define RK3288_GLB_SRST_FST 0x1b0
48#define RK3288_GLB_SRST_SND 0x1b4
49#define RK3288_SOFTRST_CON(x) (x * 0x4 + 0x1b8)
50#define RK3288_MISC_CON 0x1e8
51
52enum rockchip_pll_type {
53 pll_rk3066,
54};
55
56#define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
57{ \
58 .rate = _rate##U, \
59 .nr = _nr, \
60 .nf = _nf, \
61 .no = _no, \
62 .bwadj = (_nf >> 1), \
63}
64
65struct rockchip_pll_rate_table {
66 unsigned long rate;
67 unsigned int nr;
68 unsigned int nf;
69 unsigned int no;
70 unsigned int bwadj;
71};
72
73/**
74 * struct rockchip_pll_clock: information about pll clock
75 * @id: platform specific id of the clock.
76 * @name: name of this pll clock.
77 * @parent_name: name of the parent clock.
78 * @flags: optional flags for basic clock.
79 * @con_offset: offset of the register for configuring the PLL.
80 * @mode_offset: offset of the register for configuring the PLL-mode.
81 * @mode_shift: offset inside the mode-register for the mode of this pll.
82 * @lock_shift: offset inside the lock register for the lock status.
83 * @type: Type of PLL to be registered.
84 * @rate_table: Table of usable pll rates
85 */
86struct rockchip_pll_clock {
87 unsigned int id;
88 const char *name;
89 const char **parent_names;
90 u8 num_parents;
91 unsigned long flags;
92 int con_offset;
93 int mode_offset;
94 int mode_shift;
95 int lock_shift;
96 enum rockchip_pll_type type;
97 struct rockchip_pll_rate_table *rate_table;
98};
99
100#define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
101 _lshift, _rtable) \
102 { \
103 .id = _id, \
104 .type = _type, \
105 .name = _name, \
106 .parent_names = _pnames, \
107 .num_parents = ARRAY_SIZE(_pnames), \
108 .flags = CLK_GET_RATE_NOCACHE | _flags, \
109 .con_offset = _con, \
110 .mode_offset = _mode, \
111 .mode_shift = _mshift, \
112 .lock_shift = _lshift, \
113 .rate_table = _rtable, \
114 }
115
116struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
117 const char *name, const char **parent_names, u8 num_parents,
118 void __iomem *base, int con_offset, int grf_lock_offset,
119 int lock_shift, int reg_mode, int mode_shift,
120 struct rockchip_pll_rate_table *rate_table,
121 spinlock_t *lock);
122
123#define PNAME(x) static const char *x[] __initconst
124
125enum rockchip_clk_branch_type {
126 branch_composite,
127 branch_mux,
128 branch_divider,
129 branch_fraction_divider,
130 branch_gate,
131};
132
133struct rockchip_clk_branch {
134 unsigned int id;
135 enum rockchip_clk_branch_type branch_type;
136 const char *name;
137 const char **parent_names;
138 u8 num_parents;
139 unsigned long flags;
140 int muxdiv_offset;
141 u8 mux_shift;
142 u8 mux_width;
143 u8 mux_flags;
144 u8 div_shift;
145 u8 div_width;
146 u8 div_flags;
147 struct clk_div_table *div_table;
148 int gate_offset;
149 u8 gate_shift;
150 u8 gate_flags;
151};
152
153#define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
154 df, go, gs, gf) \
155 { \
156 .id = _id, \
157 .branch_type = branch_composite, \
158 .name = cname, \
159 .parent_names = pnames, \
160 .num_parents = ARRAY_SIZE(pnames), \
161 .flags = f, \
162 .muxdiv_offset = mo, \
163 .mux_shift = ms, \
164 .mux_width = mw, \
165 .mux_flags = mf, \
166 .div_shift = ds, \
167 .div_width = dw, \
168 .div_flags = df, \
169 .gate_offset = go, \
170 .gate_shift = gs, \
171 .gate_flags = gf, \
172 }
173
174#define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
175 go, gs, gf) \
176 { \
177 .id = _id, \
178 .branch_type = branch_composite, \
179 .name = cname, \
180 .parent_names = (const char *[]){ pname }, \
181 .num_parents = 1, \
182 .flags = f, \
183 .muxdiv_offset = mo, \
184 .div_shift = ds, \
185 .div_width = dw, \
186 .div_flags = df, \
187 .gate_offset = go, \
188 .gate_shift = gs, \
189 .gate_flags = gf, \
190 }
191
192#define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
193 df, dt, go, gs, gf) \
194 { \
195 .id = _id, \
196 .branch_type = branch_composite, \
197 .name = cname, \
198 .parent_names = (const char *[]){ pname }, \
199 .num_parents = 1, \
200 .flags = f, \
201 .muxdiv_offset = mo, \
202 .div_shift = ds, \
203 .div_width = dw, \
204 .div_flags = df, \
205 .div_table = dt, \
206 .gate_offset = go, \
207 .gate_shift = gs, \
208 .gate_flags = gf, \
209 }
210
211#define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \
212 go, gs, gf) \
213 { \
214 .id = _id, \
215 .branch_type = branch_composite, \
216 .name = cname, \
217 .parent_names = pnames, \
218 .num_parents = ARRAY_SIZE(pnames), \
219 .flags = f, \
220 .muxdiv_offset = mo, \
221 .mux_shift = ms, \
222 .mux_width = mw, \
223 .mux_flags = mf, \
224 .gate_offset = go, \
225 .gate_shift = gs, \
226 .gate_flags = gf, \
227 }
228
229#define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
230 ds, dw, df) \
231 { \
232 .id = _id, \
233 .branch_type = branch_composite, \
234 .name = cname, \
235 .parent_names = pnames, \
236 .num_parents = ARRAY_SIZE(pnames), \
237 .flags = f, \
238 .muxdiv_offset = mo, \
239 .mux_shift = ms, \
240 .mux_width = mw, \
241 .mux_flags = mf, \
242 .div_shift = ds, \
243 .div_width = dw, \
244 .div_flags = df, \
245 .gate_offset = -1, \
246 }
247
248#define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
249 { \
250 .id = _id, \
251 .branch_type = branch_fraction_divider, \
252 .name = cname, \
253 .parent_names = (const char *[]){ pname }, \
254 .num_parents = 1, \
255 .flags = f, \
256 .muxdiv_offset = mo, \
257 .div_shift = 16, \
258 .div_width = 16, \
259 .div_flags = df, \
260 .gate_offset = go, \
261 .gate_shift = gs, \
262 .gate_flags = gf, \
263 }
264
265#define MUX(_id, cname, pnames, f, o, s, w, mf) \
266 { \
267 .id = _id, \
268 .branch_type = branch_mux, \
269 .name = cname, \
270 .parent_names = pnames, \
271 .num_parents = ARRAY_SIZE(pnames), \
272 .flags = f, \
273 .muxdiv_offset = o, \
274 .mux_shift = s, \
275 .mux_width = w, \
276 .mux_flags = mf, \
277 .gate_offset = -1, \
278 }
279
280#define DIV(_id, cname, pname, f, o, s, w, df) \
281 { \
282 .id = _id, \
283 .branch_type = branch_divider, \
284 .name = cname, \
285 .parent_names = (const char *[]){ pname }, \
286 .num_parents = 1, \
287 .flags = f, \
288 .muxdiv_offset = o, \
289 .div_shift = s, \
290 .div_width = w, \
291 .div_flags = df, \
292 .gate_offset = -1, \
293 }
294
295#define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \
296 { \
297 .id = _id, \
298 .branch_type = branch_divider, \
299 .name = cname, \
300 .parent_names = (const char *[]){ pname }, \
301 .num_parents = 1, \
302 .flags = f, \
303 .muxdiv_offset = o, \
304 .div_shift = s, \
305 .div_width = w, \
306 .div_flags = df, \
307 .div_table = dt, \
308 }
309
310#define GATE(_id, cname, pname, f, o, b, gf) \
311 { \
312 .id = _id, \
313 .branch_type = branch_gate, \
314 .name = cname, \
315 .parent_names = (const char *[]){ pname }, \
316 .num_parents = 1, \
317 .flags = f, \
318 .gate_offset = o, \
319 .gate_shift = b, \
320 .gate_flags = gf, \
321 }
322
323
324void rockchip_clk_init(struct device_node *np, void __iomem *base,
325 unsigned long nr_clks);
326struct regmap *rockchip_clk_get_grf(void);
327void rockchip_clk_add_lookup(struct clk *clk, unsigned int id);
328void rockchip_clk_register_branches(struct rockchip_clk_branch *clk_list,
329 unsigned int nr_clk);
330void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list,
331 unsigned int nr_pll, int grf_lock_offset);
332
333#define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
334
335#ifdef CONFIG_RESET_CONTROLLER
336void rockchip_register_softrst(struct device_node *np,
337 unsigned int num_regs,
338 void __iomem *base, u8 flags);
339#else
340static inline void rockchip_register_softrst(struct device_node *np,
341 unsigned int num_regs,
342 void __iomem *base, u8 flags)
343{
344}
345#endif
346
347#endif
diff --git a/drivers/clk/rockchip/softrst.c b/drivers/clk/rockchip/softrst.c
new file mode 100644
index 000000000000..552f7bb15bc5
--- /dev/null
+++ b/drivers/clk/rockchip/softrst.c
@@ -0,0 +1,118 @@
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/slab.h>
17#include <linux/io.h>
18#include <linux/reset-controller.h>
19#include <linux/spinlock.h>
20#include "clk.h"
21
22struct rockchip_softrst {
23 struct reset_controller_dev rcdev;
24 void __iomem *reg_base;
25 int num_regs;
26 int num_per_reg;
27 u8 flags;
28 spinlock_t lock;
29};
30
31static int rockchip_softrst_assert(struct reset_controller_dev *rcdev,
32 unsigned long id)
33{
34 struct rockchip_softrst *softrst = container_of(rcdev,
35 struct rockchip_softrst,
36 rcdev);
37 int bank = id / softrst->num_per_reg;
38 int offset = id % softrst->num_per_reg;
39
40 if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) {
41 writel(BIT(offset) | (BIT(offset) << 16),
42 softrst->reg_base + (bank * 4));
43 } else {
44 unsigned long flags;
45 u32 reg;
46
47 spin_lock_irqsave(&softrst->lock, flags);
48
49 reg = readl(softrst->reg_base + (bank * 4));
50 writel(reg | BIT(offset), softrst->reg_base + (bank * 4));
51
52 spin_unlock_irqrestore(&softrst->lock, flags);
53 }
54
55 return 0;
56}
57
58static int rockchip_softrst_deassert(struct reset_controller_dev *rcdev,
59 unsigned long id)
60{
61 struct rockchip_softrst *softrst = container_of(rcdev,
62 struct rockchip_softrst,
63 rcdev);
64 int bank = id / softrst->num_per_reg;
65 int offset = id % softrst->num_per_reg;
66
67 if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) {
68 writel((BIT(offset) << 16), softrst->reg_base + (bank * 4));
69 } else {
70 unsigned long flags;
71 u32 reg;
72
73 spin_lock_irqsave(&softrst->lock, flags);
74
75 reg = readl(softrst->reg_base + (bank * 4));
76 writel(reg & ~BIT(offset), softrst->reg_base + (bank * 4));
77
78 spin_unlock_irqrestore(&softrst->lock, flags);
79 }
80
81 return 0;
82}
83
84static struct reset_control_ops rockchip_softrst_ops = {
85 .assert = rockchip_softrst_assert,
86 .deassert = rockchip_softrst_deassert,
87};
88
89void __init rockchip_register_softrst(struct device_node *np,
90 unsigned int num_regs,
91 void __iomem *base, u8 flags)
92{
93 struct rockchip_softrst *softrst;
94 int ret;
95
96 softrst = kzalloc(sizeof(*softrst), GFP_KERNEL);
97 if (!softrst)
98 return;
99
100 spin_lock_init(&softrst->lock);
101
102 softrst->reg_base = base;
103 softrst->flags = flags;
104 softrst->num_regs = num_regs;
105 softrst->num_per_reg = (flags & ROCKCHIP_SOFTRST_HIWORD_MASK) ? 16
106 : 32;
107
108 softrst->rcdev.owner = THIS_MODULE;
109 softrst->rcdev.nr_resets = num_regs * softrst->num_per_reg;
110 softrst->rcdev.ops = &rockchip_softrst_ops;
111 softrst->rcdev.of_node = np;
112 ret = reset_controller_register(&softrst->rcdev);
113 if (ret) {
114 pr_err("%s: could not register reset controller, %d\n",
115 __func__, ret);
116 kfree(softrst);
117 }
118};
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 69e81773164e..2949a556af8f 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
11obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o 11obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
12obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o 12obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
13obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o 13obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
14obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o
14obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o 15obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
15obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o 16obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
16obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o 17obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
diff --git a/drivers/clk/samsung/clk-exynos-clkout.c b/drivers/clk/samsung/clk-exynos-clkout.c
new file mode 100644
index 000000000000..3a7cb2506731
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos-clkout.c
@@ -0,0 +1,153 @@
1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Tomasz Figa <t.figa@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Clock driver for Exynos clock output
10 */
11
12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/clk-provider.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/syscore_ops.h>
18
19#define EXYNOS_CLKOUT_NR_CLKS 1
20#define EXYNOS_CLKOUT_PARENTS 32
21
22#define EXYNOS_PMU_DEBUG_REG 0xa00
23#define EXYNOS_CLKOUT_DISABLE_SHIFT 0
24#define EXYNOS_CLKOUT_MUX_SHIFT 8
25#define EXYNOS4_CLKOUT_MUX_MASK 0xf
26#define EXYNOS5_CLKOUT_MUX_MASK 0x1f
27
28struct exynos_clkout {
29 struct clk_gate gate;
30 struct clk_mux mux;
31 spinlock_t slock;
32 struct clk_onecell_data data;
33 struct clk *clk_table[EXYNOS_CLKOUT_NR_CLKS];
34 void __iomem *reg;
35 u32 pmu_debug_save;
36};
37
38static struct exynos_clkout *clkout;
39
40static int exynos_clkout_suspend(void)
41{
42 clkout->pmu_debug_save = readl(clkout->reg + EXYNOS_PMU_DEBUG_REG);
43
44 return 0;
45}
46
47static void exynos_clkout_resume(void)
48{
49 writel(clkout->pmu_debug_save, clkout->reg + EXYNOS_PMU_DEBUG_REG);
50}
51
52static struct syscore_ops exynos_clkout_syscore_ops = {
53 .suspend = exynos_clkout_suspend,
54 .resume = exynos_clkout_resume,
55};
56
57static void __init exynos_clkout_init(struct device_node *node, u32 mux_mask)
58{
59 const char *parent_names[EXYNOS_CLKOUT_PARENTS];
60 struct clk *parents[EXYNOS_CLKOUT_PARENTS];
61 int parent_count;
62 int ret;
63 int i;
64
65 clkout = kzalloc(sizeof(*clkout), GFP_KERNEL);
66 if (!clkout)
67 return;
68
69 spin_lock_init(&clkout->slock);
70
71 parent_count = 0;
72 for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i) {
73 char name[] = "clkoutXX";
74
75 snprintf(name, sizeof(name), "clkout%d", i);
76 parents[i] = of_clk_get_by_name(node, name);
77 if (IS_ERR(parents[i])) {
78 parent_names[i] = "none";
79 continue;
80 }
81
82 parent_names[i] = __clk_get_name(parents[i]);
83 parent_count = i + 1;
84 }
85
86 if (!parent_count)
87 goto free_clkout;
88
89 clkout->reg = of_iomap(node, 0);
90 if (!clkout->reg)
91 goto clks_put;
92
93 clkout->gate.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
94 clkout->gate.bit_idx = EXYNOS_CLKOUT_DISABLE_SHIFT;
95 clkout->gate.flags = CLK_GATE_SET_TO_DISABLE;
96 clkout->gate.lock = &clkout->slock;
97
98 clkout->mux.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG;
99 clkout->mux.mask = mux_mask;
100 clkout->mux.shift = EXYNOS_CLKOUT_MUX_SHIFT;
101 clkout->mux.lock = &clkout->slock;
102
103 clkout->clk_table[0] = clk_register_composite(NULL, "clkout",
104 parent_names, parent_count, &clkout->mux.hw,
105 &clk_mux_ops, NULL, NULL, &clkout->gate.hw,
106 &clk_gate_ops, CLK_SET_RATE_PARENT
107 | CLK_SET_RATE_NO_REPARENT);
108 if (IS_ERR(clkout->clk_table[0]))
109 goto err_unmap;
110
111 clkout->data.clks = clkout->clk_table;
112 clkout->data.clk_num = EXYNOS_CLKOUT_NR_CLKS;
113 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &clkout->data);
114 if (ret)
115 goto err_clk_unreg;
116
117 register_syscore_ops(&exynos_clkout_syscore_ops);
118
119 return;
120
121err_clk_unreg:
122 clk_unregister(clkout->clk_table[0]);
123err_unmap:
124 iounmap(clkout->reg);
125clks_put:
126 for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i)
127 if (!IS_ERR(parents[i]))
128 clk_put(parents[i]);
129free_clkout:
130 kfree(clkout);
131
132 pr_err("%s: failed to register clkout clock\n", __func__);
133}
134
135static void __init exynos4_clkout_init(struct device_node *node)
136{
137 exynos_clkout_init(node, EXYNOS4_CLKOUT_MUX_MASK);
138}
139CLK_OF_DECLARE(exynos4210_clkout, "samsung,exynos4210-pmu",
140 exynos4_clkout_init);
141CLK_OF_DECLARE(exynos4212_clkout, "samsung,exynos4212-pmu",
142 exynos4_clkout_init);
143CLK_OF_DECLARE(exynos4412_clkout, "samsung,exynos4412-pmu",
144 exynos4_clkout_init);
145
146static void __init exynos5_clkout_init(struct device_node *node)
147{
148 exynos_clkout_init(node, EXYNOS5_CLKOUT_MUX_MASK);
149}
150CLK_OF_DECLARE(exynos5250_clkout, "samsung,exynos5250-pmu",
151 exynos5_clkout_init);
152CLK_OF_DECLARE(exynos5420_clkout, "samsung,exynos5420-pmu",
153 exynos5_clkout_init);
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index 7a17bd40d1dd..dc85f8e7a2d7 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -87,6 +87,22 @@
87#define SRC_CPU 0x14200 87#define SRC_CPU 0x14200
88#define DIV_CPU0 0x14500 88#define DIV_CPU0 0x14500
89#define DIV_CPU1 0x14504 89#define DIV_CPU1 0x14504
90#define PWR_CTRL1 0x15020
91#define PWR_CTRL2 0x15024
92
93/* Below definitions are used for PWR_CTRL settings */
94#define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
95#define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
96#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
97#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
98#define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
99#define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
100#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
101#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
102#define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
103#define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
104#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
105#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
90 106
91/* list of PLLs to be registered */ 107/* list of PLLs to be registered */
92enum exynos3250_plls { 108enum exynos3250_plls {
@@ -168,6 +184,8 @@ static unsigned long exynos3250_cmu_clk_regs[] __initdata = {
168 SRC_CPU, 184 SRC_CPU,
169 DIV_CPU0, 185 DIV_CPU0,
170 DIV_CPU1, 186 DIV_CPU1,
187 PWR_CTRL1,
188 PWR_CTRL2,
171}; 189};
172 190
173static int exynos3250_clk_suspend(void) 191static int exynos3250_clk_suspend(void)
@@ -748,6 +766,27 @@ static struct samsung_pll_clock exynos3250_plls[nr_plls] __initdata = {
748 UPLL_LOCK, UPLL_CON0, NULL), 766 UPLL_LOCK, UPLL_CON0, NULL),
749}; 767};
750 768
769static void __init exynos3_core_down_clock(void)
770{
771 unsigned int tmp;
772
773 /*
774 * Enable arm clock down (in idle) and set arm divider
775 * ratios in WFI/WFE state.
776 */
777 tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
778 PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
779 PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
780 PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
781 __raw_writel(tmp, reg_base + PWR_CTRL1);
782
783 /*
784 * Disable the clock up feature on Exynos4x12, in case it was
785 * enabled by bootloader.
786 */
787 __raw_writel(0x0, reg_base + PWR_CTRL2);
788}
789
751static void __init exynos3250_cmu_init(struct device_node *np) 790static void __init exynos3250_cmu_init(struct device_node *np)
752{ 791{
753 struct samsung_clk_provider *ctx; 792 struct samsung_clk_provider *ctx;
@@ -775,6 +814,10 @@ static void __init exynos3250_cmu_init(struct device_node *np)
775 samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks)); 814 samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks));
776 samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks)); 815 samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks));
777 816
817 exynos3_core_down_clock();
818
778 exynos3250_clk_sleep_init(); 819 exynos3250_clk_sleep_init();
820
821 samsung_clk_of_add_provider(np, ctx);
779} 822}
780CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init); 823CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init);
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 7f4a473a7ad7..ac163d7f5bc3 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -25,10 +25,12 @@
25#define DIV_LEFTBUS 0x4500 25#define DIV_LEFTBUS 0x4500
26#define GATE_IP_LEFTBUS 0x4800 26#define GATE_IP_LEFTBUS 0x4800
27#define E4X12_GATE_IP_IMAGE 0x4930 27#define E4X12_GATE_IP_IMAGE 0x4930
28#define CLKOUT_CMU_LEFTBUS 0x4a00
28#define SRC_RIGHTBUS 0x8200 29#define SRC_RIGHTBUS 0x8200
29#define DIV_RIGHTBUS 0x8500 30#define DIV_RIGHTBUS 0x8500
30#define GATE_IP_RIGHTBUS 0x8800 31#define GATE_IP_RIGHTBUS 0x8800
31#define E4X12_GATE_IP_PERIR 0x8960 32#define E4X12_GATE_IP_PERIR 0x8960
33#define CLKOUT_CMU_RIGHTBUS 0x8a00
32#define EPLL_LOCK 0xc010 34#define EPLL_LOCK 0xc010
33#define VPLL_LOCK 0xc020 35#define VPLL_LOCK 0xc020
34#define EPLL_CON0 0xc110 36#define EPLL_CON0 0xc110
@@ -98,6 +100,7 @@
98#define GATE_IP_PERIL 0xc950 100#define GATE_IP_PERIL 0xc950
99#define E4210_GATE_IP_PERIR 0xc960 101#define E4210_GATE_IP_PERIR 0xc960
100#define GATE_BLOCK 0xc970 102#define GATE_BLOCK 0xc970
103#define CLKOUT_CMU_TOP 0xca00
101#define E4X12_MPLL_LOCK 0x10008 104#define E4X12_MPLL_LOCK 0x10008
102#define E4X12_MPLL_CON0 0x10108 105#define E4X12_MPLL_CON0 0x10108
103#define SRC_DMC 0x10200 106#define SRC_DMC 0x10200
@@ -105,6 +108,7 @@
105#define DIV_DMC0 0x10500 108#define DIV_DMC0 0x10500
106#define DIV_DMC1 0x10504 109#define DIV_DMC1 0x10504
107#define GATE_IP_DMC 0x10900 110#define GATE_IP_DMC 0x10900
111#define CLKOUT_CMU_DMC 0x10a00
108#define APLL_LOCK 0x14000 112#define APLL_LOCK 0x14000
109#define E4210_MPLL_LOCK 0x14008 113#define E4210_MPLL_LOCK 0x14008
110#define APLL_CON0 0x14100 114#define APLL_CON0 0x14100
@@ -114,11 +118,28 @@
114#define DIV_CPU1 0x14504 118#define DIV_CPU1 0x14504
115#define GATE_SCLK_CPU 0x14800 119#define GATE_SCLK_CPU 0x14800
116#define GATE_IP_CPU 0x14900 120#define GATE_IP_CPU 0x14900
121#define CLKOUT_CMU_CPU 0x14a00
122#define PWR_CTRL1 0x15020
123#define E4X12_PWR_CTRL2 0x15024
117#define E4X12_DIV_ISP0 0x18300 124#define E4X12_DIV_ISP0 0x18300
118#define E4X12_DIV_ISP1 0x18304 125#define E4X12_DIV_ISP1 0x18304
119#define E4X12_GATE_ISP0 0x18800 126#define E4X12_GATE_ISP0 0x18800
120#define E4X12_GATE_ISP1 0x18804 127#define E4X12_GATE_ISP1 0x18804
121 128
129/* Below definitions are used for PWR_CTRL settings */
130#define PWR_CTRL1_CORE2_DOWN_RATIO(x) (((x) & 0x7) << 28)
131#define PWR_CTRL1_CORE1_DOWN_RATIO(x) (((x) & 0x7) << 16)
132#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
133#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
134#define PWR_CTRL1_USE_CORE3_WFE (1 << 7)
135#define PWR_CTRL1_USE_CORE2_WFE (1 << 6)
136#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
137#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
138#define PWR_CTRL1_USE_CORE3_WFI (1 << 3)
139#define PWR_CTRL1_USE_CORE2_WFI (1 << 2)
140#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
141#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
142
122/* the exynos4 soc type */ 143/* the exynos4 soc type */
123enum exynos4_soc { 144enum exynos4_soc {
124 EXYNOS4210, 145 EXYNOS4210,
@@ -155,6 +176,7 @@ static unsigned long exynos4210_clk_save[] __initdata = {
155 E4210_GATE_IP_LCD1, 176 E4210_GATE_IP_LCD1,
156 E4210_GATE_IP_PERIR, 177 E4210_GATE_IP_PERIR,
157 E4210_MPLL_CON0, 178 E4210_MPLL_CON0,
179 PWR_CTRL1,
158}; 180};
159 181
160static unsigned long exynos4x12_clk_save[] __initdata = { 182static unsigned long exynos4x12_clk_save[] __initdata = {
@@ -164,6 +186,8 @@ static unsigned long exynos4x12_clk_save[] __initdata = {
164 E4X12_DIV_ISP, 186 E4X12_DIV_ISP,
165 E4X12_DIV_CAM1, 187 E4X12_DIV_CAM1,
166 E4X12_MPLL_CON0, 188 E4X12_MPLL_CON0,
189 PWR_CTRL1,
190 E4X12_PWR_CTRL2,
167}; 191};
168 192
169static unsigned long exynos4_clk_pll_regs[] __initdata = { 193static unsigned long exynos4_clk_pll_regs[] __initdata = {
@@ -242,6 +266,11 @@ static unsigned long exynos4_clk_regs[] __initdata = {
242 DIV_CPU1, 266 DIV_CPU1,
243 GATE_SCLK_CPU, 267 GATE_SCLK_CPU,
244 GATE_IP_CPU, 268 GATE_IP_CPU,
269 CLKOUT_CMU_LEFTBUS,
270 CLKOUT_CMU_RIGHTBUS,
271 CLKOUT_CMU_TOP,
272 CLKOUT_CMU_DMC,
273 CLKOUT_CMU_CPU,
245}; 274};
246 275
247static const struct samsung_clk_reg_dump src_mask_suspend[] = { 276static const struct samsung_clk_reg_dump src_mask_suspend[] = {
@@ -397,10 +426,32 @@ PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m",
397 "sclk_epll", "sclk_vpll", }; 426 "sclk_epll", "sclk_vpll", };
398PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", }; 427PNAME(mout_mixer_p4210) = { "sclk_dac", "sclk_hdmi", };
399PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", }; 428PNAME(mout_dac_p4210) = { "sclk_vpll", "sclk_hdmiphy", };
429PNAME(mout_pwi_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
430 "sclk_usbphy1", "sclk_hdmiphy", "none",
431 "sclk_epll", "sclk_vpll" };
432PNAME(clkout_left_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
433 "div_gdl", "div_gpl" };
434PNAME(clkout_right_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
435 "div_gdr", "div_gpr" };
436PNAME(clkout_top_p4210) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
437 "sclk_usbphy0", "sclk_usbphy1", "sclk_hdmiphy",
438 "cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
439 "aclk160", "aclk133", "aclk200", "aclk100",
440 "sclk_mfc", "sclk_g3d", "sclk_g2d",
441 "cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
442 "s_rxbyteclkhs0_4l" };
443PNAME(clkout_dmc_p4210) = { "div_dmcd", "div_dmcp", "div_acp_pclk", "div_dmc",
444 "div_dphy", "none", "div_pwi" };
445PNAME(clkout_cpu_p4210) = { "fout_apll_div_2", "none", "fout_mpll_div_2",
446 "none", "arm_clk_div_2", "div_corem0",
447 "div_corem1", "div_corem0", "div_atb",
448 "div_periph", "div_pclk_dbg", "div_hpm" };
400 449
401/* Exynos 4x12-specific parent groups */ 450/* Exynos 4x12-specific parent groups */
402PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", }; 451PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
403PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", }; 452PNAME(mout_core_p4x12) = { "mout_apll", "mout_mpll_user_c", };
453PNAME(mout_gdl_p4x12) = { "mout_mpll_user_l", "sclk_apll", };
454PNAME(mout_gdr_p4x12) = { "mout_mpll_user_r", "sclk_apll", };
404PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", }; 455PNAME(sclk_ampll_p4x12) = { "mout_mpll_user_t", "sclk_apll", };
405PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0", 456PNAME(group1_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
406 "none", "sclk_hdmiphy", "mout_mpll_user_t", 457 "none", "sclk_hdmiphy", "mout_mpll_user_t",
@@ -418,6 +469,32 @@ PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", };
418PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", }; 469PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
419PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", }; 470PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
420PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", }; 471PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
472PNAME(mout_pwi_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
473 "none", "sclk_hdmiphy", "sclk_mpll",
474 "sclk_epll", "sclk_vpll" };
475PNAME(clkout_left_p4x12) = { "sclk_mpll_user_l_div_2", "sclk_apll_div_2",
476 "div_gdl", "div_gpl" };
477PNAME(clkout_right_p4x12) = { "sclk_mpll_user_r_div_2", "sclk_apll_div_2",
478 "div_gdr", "div_gpr" };
479PNAME(clkout_top_p4x12) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
480 "sclk_usbphy0", "none", "sclk_hdmiphy",
481 "cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
482 "aclk160", "aclk133", "aclk200", "aclk100",
483 "sclk_mfc", "sclk_g3d", "aclk400_mcuisp",
484 "cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
485 "s_rxbyteclkhs0_4l", "rx_half_byte_clk_csis0",
486 "rx_half_byte_clk_csis1", "div_jpeg",
487 "sclk_pwm_isp", "sclk_spi0_isp",
488 "sclk_spi1_isp", "sclk_uart_isp",
489 "sclk_mipihsi", "sclk_hdmi", "sclk_fimd0",
490 "sclk_pcm0" };
491PNAME(clkout_dmc_p4x12) = { "div_dmcd", "div_dmcp", "aclk_acp", "div_acp_pclk",
492 "div_dmc", "div_dphy", "fout_mpll_div_2",
493 "div_pwi", "none", "div_c2c", "div_c2c_aclk" };
494PNAME(clkout_cpu_p4x12) = { "fout_apll_div_2", "none", "none", "none",
495 "arm_clk_div_2", "div_corem0", "div_corem1",
496 "div_cores", "div_atb", "div_periph",
497 "div_pclk_dbg", "div_hpm" };
421 498
422/* fixed rate clocks generated outside the soc */ 499/* fixed rate clocks generated outside the soc */
423static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = { 500static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
@@ -436,6 +513,24 @@ static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata =
436 FRATE(0, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000), 513 FRATE(0, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000),
437}; 514};
438 515
516static struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initdata = {
517 FFACTOR(0, "sclk_apll_div_2", "sclk_apll", 1, 2, 0),
518 FFACTOR(0, "fout_mpll_div_2", "fout_mpll", 1, 2, 0),
519 FFACTOR(0, "fout_apll_div_2", "fout_apll", 1, 2, 0),
520 FFACTOR(0, "arm_clk_div_2", "arm_clk", 1, 2, 0),
521};
522
523static struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initdata = {
524 FFACTOR(0, "sclk_mpll_div_2", "sclk_mpll", 1, 2, 0),
525};
526
527static struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initdata = {
528 FFACTOR(0, "sclk_mpll_user_l_div_2", "mout_mpll_user_l", 1, 2, 0),
529 FFACTOR(0, "sclk_mpll_user_r_div_2", "mout_mpll_user_r", 1, 2, 0),
530 FFACTOR(0, "sclk_mpll_user_t_div_2", "mout_mpll_user_t", 1, 2, 0),
531 FFACTOR(0, "sclk_mpll_user_c_div_2", "mout_mpll_user_c", 1, 2, 0),
532};
533
439/* list of mux clocks supported in all exynos4 soc's */ 534/* list of mux clocks supported in all exynos4 soc's */
440static struct samsung_mux_clock exynos4_mux_clks[] __initdata = { 535static struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
441 MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 536 MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
@@ -451,6 +546,9 @@ static struct samsung_mux_clock exynos4_mux_clks[] __initdata = {
451 MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1), 546 MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
452 MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1), 547 MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1),
453 MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1), 548 MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
549
550 MUX(0, "mout_dmc_bus", sclk_ampll_p4210, SRC_DMC, 4, 1),
551 MUX(0, "mout_dphy", sclk_ampll_p4210, SRC_DMC, 8, 1),
454}; 552};
455 553
456/* list of mux clocks supported in exynos4210 soc */ 554/* list of mux clocks supported in exynos4210 soc */
@@ -459,6 +557,14 @@ static struct samsung_mux_clock exynos4210_mux_early[] __initdata = {
459}; 557};
460 558
461static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { 559static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
560 MUX(0, "mout_gdl", sclk_ampll_p4210, SRC_LEFTBUS, 0, 1),
561 MUX(0, "mout_clkout_leftbus", clkout_left_p4210,
562 CLKOUT_CMU_LEFTBUS, 0, 5),
563
564 MUX(0, "mout_gdr", sclk_ampll_p4210, SRC_RIGHTBUS, 0, 1),
565 MUX(0, "mout_clkout_rightbus", clkout_right_p4210,
566 CLKOUT_CMU_RIGHTBUS, 0, 5),
567
462 MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1), 568 MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
463 MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1), 569 MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
464 MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1), 570 MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
@@ -472,6 +578,7 @@ static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
472 MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), 578 MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
473 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1), 579 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
474 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1), 580 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
581 MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1),
475 MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1), 582 MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),
476 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), 583 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
477 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4), 584 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
@@ -503,12 +610,30 @@ static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
503 MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4), 610 MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
504 MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4), 611 MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
505 MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4), 612 MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
613 MUX(0, "mout_clkout_top", clkout_top_p4210, CLKOUT_CMU_TOP, 0, 5),
614
615 MUX(0, "mout_pwi", mout_pwi_p4210, SRC_DMC, 16, 4),
616 MUX(0, "mout_clkout_dmc", clkout_dmc_p4210, CLKOUT_CMU_DMC, 0, 5),
617
618 MUX(0, "mout_clkout_cpu", clkout_cpu_p4210, CLKOUT_CMU_CPU, 0, 5),
506}; 619};
507 620
508/* list of mux clocks supported in exynos4x12 soc */ 621/* list of mux clocks supported in exynos4x12 soc */
509static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { 622static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
623 MUX(0, "mout_mpll_user_l", mout_mpll_p, SRC_LEFTBUS, 4, 1),
624 MUX(0, "mout_gdl", mout_gdl_p4x12, SRC_LEFTBUS, 0, 1),
625 MUX(0, "mout_clkout_leftbus", clkout_left_p4x12,
626 CLKOUT_CMU_LEFTBUS, 0, 5),
627
628 MUX(0, "mout_mpll_user_r", mout_mpll_p, SRC_RIGHTBUS, 4, 1),
629 MUX(0, "mout_gdr", mout_gdr_p4x12, SRC_RIGHTBUS, 0, 1),
630 MUX(0, "mout_clkout_rightbus", clkout_right_p4x12,
631 CLKOUT_CMU_RIGHTBUS, 0, 5),
632
510 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12, 633 MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12,
511 SRC_CPU, 24, 1), 634 SRC_CPU, 24, 1),
635 MUX(0, "mout_clkout_cpu", clkout_cpu_p4x12, CLKOUT_CMU_CPU, 0, 5),
636
512 MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1), 637 MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
513 MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1), 638 MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
514 MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12, 639 MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12,
@@ -531,6 +656,7 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
531 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1), 656 MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1),
532 MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1), 657 MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
533 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1), 658 MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
659 MUX(0, "mout_hpm", mout_core_p4x12, SRC_CPU, 20, 1),
534 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), 660 MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
535 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), 661 MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
536 MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), 662 MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
@@ -565,15 +691,39 @@ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
565 MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4), 691 MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
566 MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4), 692 MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
567 MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4), 693 MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
694 MUX(0, "mout_clkout_top", clkout_top_p4x12, CLKOUT_CMU_TOP, 0, 5),
695
696 MUX(0, "mout_c2c", sclk_ampll_p4210, SRC_DMC, 0, 1),
697 MUX(0, "mout_pwi", mout_pwi_p4x12, SRC_DMC, 16, 4),
568 MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1), 698 MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
569 MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1), 699 MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
570 MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1), 700 MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
701 MUX(0, "mout_clkout_dmc", clkout_dmc_p4x12, CLKOUT_CMU_DMC, 0, 5),
571}; 702};
572 703
573/* list of divider clocks supported in all exynos4 soc's */ 704/* list of divider clocks supported in all exynos4 soc's */
574static struct samsung_div_clock exynos4_div_clks[] __initdata = { 705static struct samsung_div_clock exynos4_div_clks[] __initdata = {
706 DIV(0, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
707 DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
708 DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
709 CLKOUT_CMU_LEFTBUS, 8, 6),
710
711 DIV(0, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
712 DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
713 DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
714 CLKOUT_CMU_RIGHTBUS, 8, 6),
715
575 DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3), 716 DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
717 DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
718 DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
719 DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
720 DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
721 DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
576 DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3), 722 DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
723 DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
724 DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
725 DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
726
577 DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4), 727 DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
578 DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4), 728 DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
579 DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4), 729 DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
@@ -631,6 +781,16 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
631 CLK_SET_RATE_PARENT, 0), 781 CLK_SET_RATE_PARENT, 0),
632 DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8, 782 DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
633 CLK_SET_RATE_PARENT, 0), 783 CLK_SET_RATE_PARENT, 0),
784 DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6),
785
786 DIV(0, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
787 DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3),
788 DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3),
789 DIV(0, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
790 DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3),
791 DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3),
792 DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4),
793 DIV(0, "div_clkout_dmc", "mout_clkout_dmc", CLKOUT_CMU_DMC, 8, 6),
634}; 794};
635 795
636/* list of divider clocks supported in exynos4210 soc */ 796/* list of divider clocks supported in exynos4210 soc */
@@ -671,6 +831,8 @@ static struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
671 DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 831 DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
672 8, 3, CLK_GET_RATE_NOCACHE, 0), 832 8, 3, CLK_GET_RATE_NOCACHE, 0),
673 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), 833 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
834 DIV(0, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
835 DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
674}; 836};
675 837
676/* list of gate clocks supported in all exynos4 soc's */ 838/* list of gate clocks supported in all exynos4 soc's */
@@ -680,6 +842,8 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
680 * the device name and clock alias names specified below for some 842 * the device name and clock alias names specified below for some
681 * of the clocks can be removed. 843 * of the clocks can be removed.
682 */ 844 */
845 GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
846 GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),
683 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0), 847 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
684 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0, 848 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0,
685 0), 849 0),
@@ -695,11 +859,13 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
695 GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0), 859 GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
696 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0, 860 GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0,
697 CLK_SET_RATE_PARENT, 0), 861 CLK_SET_RATE_PARENT, 0),
862 GATE(CLK_PPMUG3D, "ppmug3d", "aclk200", GATE_IP_G3D, 1, 0, 0),
698 GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0), 863 GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
699 GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0), 864 GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
700 GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0), 865 GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
701 GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0), 866 GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
702 GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0), 867 GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
868 GATE(CLK_PPMUGPS, "ppmugps", "aclk200", GATE_IP_GPS, 2, 0, 0),
703 GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0), 869 GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
704 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4, 870 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
705 CLK_SET_RATE_PARENT, 0), 871 CLK_SET_RATE_PARENT, 0),
@@ -781,19 +947,24 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
781 0, 0), 947 0, 0),
782 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11, 948 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11,
783 0, 0), 949 0, 0),
950 GATE(CLK_PPMUCAMIF, "ppmucamif", "aclk160", GATE_IP_CAM, 16, 0, 0),
784 GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0), 951 GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
785 GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0), 952 GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
786 GATE(CLK_SMMU_TV, "smmu_tv", "aclk160", GATE_IP_TV, 4, 953 GATE(CLK_SMMU_TV, "smmu_tv", "aclk160", GATE_IP_TV, 4,
787 0, 0), 954 0, 0),
955 GATE(CLK_PPMUTV, "ppmutv", "aclk160", GATE_IP_TV, 5, 0, 0),
788 GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0), 956 GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0),
789 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1, 957 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1,
790 0, 0), 958 0, 0),
791 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2, 959 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2,
792 0, 0), 960 0, 0),
961 GATE(CLK_PPMUMFC_L, "ppmumfc_l", "aclk100", GATE_IP_MFC, 3, 0, 0),
962 GATE(CLK_PPMUMFC_R, "ppmumfc_r", "aclk100", GATE_IP_MFC, 4, 0, 0),
793 GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0, 963 GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0,
794 0, 0), 964 0, 0),
795 GATE(CLK_SMMU_FIMD0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4, 965 GATE(CLK_SMMU_FIMD0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4,
796 0, 0), 966 0, 0),
967 GATE(CLK_PPMULCD0, "ppmulcd0", "aclk160", GATE_IP_LCD0, 5, 0, 0),
797 GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0, 968 GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0,
798 0, 0), 969 0, 0),
799 GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1, 970 GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1,
@@ -806,6 +977,7 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
806 0, 0), 977 0, 0),
807 GATE(CLK_SDMMC3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8, 978 GATE(CLK_SDMMC3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8,
808 0, 0), 979 0, 0),
980 GATE(CLK_PPMUFILE, "ppmufile", "aclk133", GATE_IP_FSYS, 17, 0, 0),
809 GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0, 981 GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0,
810 0, 0), 982 0, 0),
811 GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1, 983 GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1,
@@ -852,6 +1024,21 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = {
852 0, 0), 1024 0, 0),
853 GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27, 1025 GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27,
854 0, 0), 1026 0, 0),
1027 GATE(CLK_PPMUDMC0, "ppmudmc0", "aclk133", GATE_IP_DMC, 8, 0, 0),
1028 GATE(CLK_PPMUDMC1, "ppmudmc1", "aclk133", GATE_IP_DMC, 9, 0, 0),
1029 GATE(CLK_PPMUCPU, "ppmucpu", "aclk133", GATE_IP_DMC, 10, 0, 0),
1030 GATE(CLK_PPMUACP, "ppmuacp", "aclk133", GATE_IP_DMC, 16, 0, 0),
1031
1032 GATE(CLK_OUT_LEFTBUS, "clkout_leftbus", "div_clkout_leftbus",
1033 CLKOUT_CMU_LEFTBUS, 16, CLK_SET_RATE_PARENT, 0),
1034 GATE(CLK_OUT_RIGHTBUS, "clkout_rightbus", "div_clkout_rightbus",
1035 CLKOUT_CMU_RIGHTBUS, 16, CLK_SET_RATE_PARENT, 0),
1036 GATE(CLK_OUT_TOP, "clkout_top", "div_clkout_top",
1037 CLKOUT_CMU_TOP, 16, CLK_SET_RATE_PARENT, 0),
1038 GATE(CLK_OUT_DMC, "clkout_dmc", "div_clkout_dmc",
1039 CLKOUT_CMU_DMC, 16, CLK_SET_RATE_PARENT, 0),
1040 GATE(CLK_OUT_CPU, "clkout_cpu", "div_clkout_cpu",
1041 CLKOUT_CMU_CPU, 16, CLK_SET_RATE_PARENT, 0),
855}; 1042};
856 1043
857/* list of gate clocks supported in exynos4210 soc */ 1044/* list of gate clocks supported in exynos4210 soc */
@@ -863,6 +1050,9 @@ static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
863 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0), 1050 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
864 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, 1051 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0,
865 0), 1052 0),
1053 GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4210_GATE_IP_IMAGE, 9, 0,
1054 0),
1055 GATE(CLK_PPMULCD1, "ppmulcd1", "aclk160", E4210_GATE_IP_LCD1, 5, 0, 0),
866 GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0), 1056 GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
867 GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0), 1057 GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
868 GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0), 1058 GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
@@ -906,6 +1096,8 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
906 GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0), 1096 GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
907 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 1097 GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
908 0), 1098 0),
1099 GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0,
1100 0),
909 GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), 1101 GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
910 GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0), 1102 GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
911 GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 1103 GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
@@ -1062,7 +1254,7 @@ static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx)
1062 1254
1063} 1255}
1064 1256
1065static struct of_device_id ext_clk_match[] __initdata = { 1257static const struct of_device_id ext_clk_match[] __initconst = {
1066 { .compatible = "samsung,clock-xxti", .data = (void *)0, }, 1258 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
1067 { .compatible = "samsung,clock-xusbxti", .data = (void *)1, }, 1259 { .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
1068 {}, 1260 {},
@@ -1164,6 +1356,32 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
1164 VPLL_LOCK, VPLL_CON0, NULL), 1356 VPLL_LOCK, VPLL_CON0, NULL),
1165}; 1357};
1166 1358
1359static void __init exynos4_core_down_clock(enum exynos4_soc soc)
1360{
1361 unsigned int tmp;
1362
1363 /*
1364 * Enable arm clock down (in idle) and set arm divider
1365 * ratios in WFI/WFE state.
1366 */
1367 tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
1368 PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
1369 PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
1370 PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
1371 /* On Exynos4412 enable it also on core 2 and 3 */
1372 if (num_possible_cpus() == 4)
1373 tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE |
1374 PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI;
1375 __raw_writel(tmp, reg_base + PWR_CTRL1);
1376
1377 /*
1378 * Disable the clock up feature on Exynos4x12, in case it was
1379 * enabled by bootloader.
1380 */
1381 if (exynos4_soc == EXYNOS4X12)
1382 __raw_writel(0x0, reg_base + E4X12_PWR_CTRL2);
1383}
1384
1167/* register exynos4 clocks */ 1385/* register exynos4 clocks */
1168static void __init exynos4_clk_init(struct device_node *np, 1386static void __init exynos4_clk_init(struct device_node *np,
1169 enum exynos4_soc soc) 1387 enum exynos4_soc soc)
@@ -1224,6 +1442,8 @@ static void __init exynos4_clk_init(struct device_node *np,
1224 ARRAY_SIZE(exynos4_div_clks)); 1442 ARRAY_SIZE(exynos4_div_clks));
1225 samsung_clk_register_gate(ctx, exynos4_gate_clks, 1443 samsung_clk_register_gate(ctx, exynos4_gate_clks,
1226 ARRAY_SIZE(exynos4_gate_clks)); 1444 ARRAY_SIZE(exynos4_gate_clks));
1445 samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks,
1446 ARRAY_SIZE(exynos4_fixed_factor_clks));
1227 1447
1228 if (exynos4_soc == EXYNOS4210) { 1448 if (exynos4_soc == EXYNOS4210) {
1229 samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks, 1449 samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
@@ -1236,6 +1456,9 @@ static void __init exynos4_clk_init(struct device_node *np,
1236 ARRAY_SIZE(exynos4210_gate_clks)); 1456 ARRAY_SIZE(exynos4210_gate_clks));
1237 samsung_clk_register_alias(ctx, exynos4210_aliases, 1457 samsung_clk_register_alias(ctx, exynos4210_aliases,
1238 ARRAY_SIZE(exynos4210_aliases)); 1458 ARRAY_SIZE(exynos4210_aliases));
1459 samsung_clk_register_fixed_factor(ctx,
1460 exynos4210_fixed_factor_clks,
1461 ARRAY_SIZE(exynos4210_fixed_factor_clks));
1239 } else { 1462 } else {
1240 samsung_clk_register_mux(ctx, exynos4x12_mux_clks, 1463 samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
1241 ARRAY_SIZE(exynos4x12_mux_clks)); 1464 ARRAY_SIZE(exynos4x12_mux_clks));
@@ -1245,13 +1468,19 @@ static void __init exynos4_clk_init(struct device_node *np,
1245 ARRAY_SIZE(exynos4x12_gate_clks)); 1468 ARRAY_SIZE(exynos4x12_gate_clks));
1246 samsung_clk_register_alias(ctx, exynos4x12_aliases, 1469 samsung_clk_register_alias(ctx, exynos4x12_aliases,
1247 ARRAY_SIZE(exynos4x12_aliases)); 1470 ARRAY_SIZE(exynos4x12_aliases));
1471 samsung_clk_register_fixed_factor(ctx,
1472 exynos4x12_fixed_factor_clks,
1473 ARRAY_SIZE(exynos4x12_fixed_factor_clks));
1248 } 1474 }
1249 1475
1250 samsung_clk_register_alias(ctx, exynos4_aliases, 1476 samsung_clk_register_alias(ctx, exynos4_aliases,
1251 ARRAY_SIZE(exynos4_aliases)); 1477 ARRAY_SIZE(exynos4_aliases));
1252 1478
1479 exynos4_core_down_clock(soc);
1253 exynos4_clk_sleep_init(); 1480 exynos4_clk_sleep_init();
1254 1481
1482 samsung_clk_of_add_provider(np, ctx);
1483
1255 pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n" 1484 pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
1256 "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n", 1485 "\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
1257 exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12", 1486 exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 184f64293b26..70ec3d2608a1 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -748,7 +748,7 @@ static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
748 VPLL_LOCK, VPLL_CON0, NULL), 748 VPLL_LOCK, VPLL_CON0, NULL),
749}; 749};
750 750
751static struct of_device_id ext_clk_match[] __initdata = { 751static const struct of_device_id ext_clk_match[] __initconst = {
752 { .compatible = "samsung,clock-xxti", .data = (void *)0, }, 752 { .compatible = "samsung,clock-xxti", .data = (void *)0, },
753 { }, 753 { },
754}; 754};
@@ -820,6 +820,8 @@ static void __init exynos5250_clk_init(struct device_node *np)
820 820
821 exynos5250_clk_sleep_init(); 821 exynos5250_clk_sleep_init();
822 822
823 samsung_clk_of_add_provider(np, ctx);
824
823 pr_info("Exynos5250: clock setup completed, armclk=%ld\n", 825 pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
824 _get_rate("div_arm2")); 826 _get_rate("div_arm2"));
825} 827}
diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c
index 64596ba58df1..ce3de97e5f11 100644
--- a/drivers/clk/samsung/clk-exynos5260.c
+++ b/drivers/clk/samsung/clk-exynos5260.c
@@ -206,6 +206,8 @@ void __init exynos5260_cmu_register_one(struct device_node *np,
206 if (cmu->clk_regs) 206 if (cmu->clk_regs)
207 exynos5260_clk_sleep_init(reg_base, cmu->clk_regs, 207 exynos5260_clk_sleep_init(reg_base, cmu->clk_regs,
208 cmu->nr_clk_regs); 208 cmu->nr_clk_regs);
209
210 samsung_clk_of_add_provider(np, ctx);
209} 211}
210 212
211 213
diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
index c9505ab9ee70..231475bc2b99 100644
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -204,6 +204,8 @@ static void __init exynos5410_clk_init(struct device_node *np)
204 samsung_clk_register_gate(ctx, exynos5410_gate_clks, 204 samsung_clk_register_gate(ctx, exynos5410_gate_clks,
205 ARRAY_SIZE(exynos5410_gate_clks)); 205 ARRAY_SIZE(exynos5410_gate_clks));
206 206
207 samsung_clk_of_add_provider(np, ctx);
208
207 pr_debug("Exynos5410: clock setup completed.\n"); 209 pr_debug("Exynos5410: clock setup completed.\n");
208} 210}
209CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init); 211CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index a4e6cc782e5c..848d602efc06 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -28,6 +28,7 @@
28#define GATE_BUS_CPU 0x700 28#define GATE_BUS_CPU 0x700
29#define GATE_SCLK_CPU 0x800 29#define GATE_SCLK_CPU 0x800
30#define CLKOUT_CMU_CPU 0xa00 30#define CLKOUT_CMU_CPU 0xa00
31#define SRC_MASK_CPERI 0x4300
31#define GATE_IP_G2D 0x8800 32#define GATE_IP_G2D 0x8800
32#define CPLL_LOCK 0x10020 33#define CPLL_LOCK 0x10020
33#define DPLL_LOCK 0x10030 34#define DPLL_LOCK 0x10030
@@ -70,6 +71,8 @@
70#define SRC_TOP11 0x10284 71#define SRC_TOP11 0x10284
71#define SRC_TOP12 0x10288 72#define SRC_TOP12 0x10288
72#define SRC_TOP13 0x1028c /* 5800 specific */ 73#define SRC_TOP13 0x1028c /* 5800 specific */
74#define SRC_MASK_TOP0 0x10300
75#define SRC_MASK_TOP1 0x10304
73#define SRC_MASK_TOP2 0x10308 76#define SRC_MASK_TOP2 0x10308
74#define SRC_MASK_TOP7 0x1031c 77#define SRC_MASK_TOP7 0x1031c
75#define SRC_MASK_DISP10 0x1032c 78#define SRC_MASK_DISP10 0x1032c
@@ -77,6 +80,7 @@
77#define SRC_MASK_FSYS 0x10340 80#define SRC_MASK_FSYS 0x10340
78#define SRC_MASK_PERIC0 0x10350 81#define SRC_MASK_PERIC0 0x10350
79#define SRC_MASK_PERIC1 0x10354 82#define SRC_MASK_PERIC1 0x10354
83#define SRC_MASK_ISP 0x10370
80#define DIV_TOP0 0x10500 84#define DIV_TOP0 0x10500
81#define DIV_TOP1 0x10504 85#define DIV_TOP1 0x10504
82#define DIV_TOP2 0x10508 86#define DIV_TOP2 0x10508
@@ -98,6 +102,7 @@
98#define DIV2_RATIO0 0x10590 102#define DIV2_RATIO0 0x10590
99#define DIV4_RATIO 0x105a0 103#define DIV4_RATIO 0x105a0
100#define GATE_BUS_TOP 0x10700 104#define GATE_BUS_TOP 0x10700
105#define GATE_BUS_DISP1 0x10728
101#define GATE_BUS_GEN 0x1073c 106#define GATE_BUS_GEN 0x1073c
102#define GATE_BUS_FSYS0 0x10740 107#define GATE_BUS_FSYS0 0x10740
103#define GATE_BUS_FSYS2 0x10748 108#define GATE_BUS_FSYS2 0x10748
@@ -190,6 +195,10 @@ static unsigned long exynos5x_clk_regs[] __initdata = {
190 SRC_MASK_FSYS, 195 SRC_MASK_FSYS,
191 SRC_MASK_PERIC0, 196 SRC_MASK_PERIC0,
192 SRC_MASK_PERIC1, 197 SRC_MASK_PERIC1,
198 SRC_MASK_TOP0,
199 SRC_MASK_TOP1,
200 SRC_MASK_MAU,
201 SRC_MASK_ISP,
193 SRC_ISP, 202 SRC_ISP,
194 DIV_TOP0, 203 DIV_TOP0,
195 DIV_TOP1, 204 DIV_TOP1,
@@ -208,6 +217,7 @@ static unsigned long exynos5x_clk_regs[] __initdata = {
208 SCLK_DIV_ISP1, 217 SCLK_DIV_ISP1,
209 DIV2_RATIO0, 218 DIV2_RATIO0,
210 DIV4_RATIO, 219 DIV4_RATIO,
220 GATE_BUS_DISP1,
211 GATE_BUS_TOP, 221 GATE_BUS_TOP,
212 GATE_BUS_GEN, 222 GATE_BUS_GEN,
213 GATE_BUS_FSYS0, 223 GATE_BUS_FSYS0,
@@ -249,6 +259,22 @@ static unsigned long exynos5800_clk_regs[] __initdata = {
249 GATE_IP_CAM, 259 GATE_IP_CAM,
250}; 260};
251 261
262static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
263 { .offset = SRC_MASK_CPERI, .value = 0xffffffff, },
264 { .offset = SRC_MASK_TOP0, .value = 0x11111111, },
265 { .offset = SRC_MASK_TOP1, .value = 0x11101111, },
266 { .offset = SRC_MASK_TOP2, .value = 0x11111110, },
267 { .offset = SRC_MASK_TOP7, .value = 0x00111100, },
268 { .offset = SRC_MASK_DISP10, .value = 0x11111110, },
269 { .offset = SRC_MASK_MAU, .value = 0x10000000, },
270 { .offset = SRC_MASK_FSYS, .value = 0x11111110, },
271 { .offset = SRC_MASK_PERIC0, .value = 0x11111110, },
272 { .offset = SRC_MASK_PERIC1, .value = 0x11111100, },
273 { .offset = SRC_MASK_ISP, .value = 0x11111000, },
274 { .offset = GATE_BUS_DISP1, .value = 0xffffffff, },
275 { .offset = GATE_IP_PERIC, .value = 0xffffffff, },
276};
277
252static int exynos5420_clk_suspend(void) 278static int exynos5420_clk_suspend(void)
253{ 279{
254 samsung_clk_save(reg_base, exynos5x_save, 280 samsung_clk_save(reg_base, exynos5x_save,
@@ -258,6 +284,9 @@ static int exynos5420_clk_suspend(void)
258 samsung_clk_save(reg_base, exynos5800_save, 284 samsung_clk_save(reg_base, exynos5800_save,
259 ARRAY_SIZE(exynos5800_clk_regs)); 285 ARRAY_SIZE(exynos5800_clk_regs));
260 286
287 samsung_clk_restore(reg_base, exynos5420_set_clksrc,
288 ARRAY_SIZE(exynos5420_set_clksrc));
289
261 return 0; 290 return 0;
262} 291}
263 292
@@ -1169,6 +1198,28 @@ static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = {
1169 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), 1198 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
1170}; 1199};
1171 1200
1201static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] = {
1202 PLL_35XX_RATE(2000000000, 250, 3, 0),
1203 PLL_35XX_RATE(1900000000, 475, 6, 0),
1204 PLL_35XX_RATE(1800000000, 225, 3, 0),
1205 PLL_35XX_RATE(1700000000, 425, 6, 0),
1206 PLL_35XX_RATE(1600000000, 200, 3, 0),
1207 PLL_35XX_RATE(1500000000, 250, 4, 0),
1208 PLL_35XX_RATE(1400000000, 175, 3, 0),
1209 PLL_35XX_RATE(1300000000, 325, 6, 0),
1210 PLL_35XX_RATE(1200000000, 200, 2, 1),
1211 PLL_35XX_RATE(1100000000, 275, 3, 1),
1212 PLL_35XX_RATE(1000000000, 250, 3, 1),
1213 PLL_35XX_RATE(900000000, 150, 2, 1),
1214 PLL_35XX_RATE(800000000, 200, 3, 1),
1215 PLL_35XX_RATE(700000000, 175, 3, 1),
1216 PLL_35XX_RATE(600000000, 200, 2, 2),
1217 PLL_35XX_RATE(500000000, 250, 3, 2),
1218 PLL_35XX_RATE(400000000, 200, 3, 2),
1219 PLL_35XX_RATE(300000000, 200, 2, 3),
1220 PLL_35XX_RATE(200000000, 200, 3, 3),
1221};
1222
1172static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { 1223static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
1173 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 1224 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
1174 APLL_CON0, NULL), 1225 APLL_CON0, NULL),
@@ -1194,7 +1245,7 @@ static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
1194 KPLL_CON0, NULL), 1245 KPLL_CON0, NULL),
1195}; 1246};
1196 1247
1197static struct of_device_id ext_clk_match[] __initdata = { 1248static const struct of_device_id ext_clk_match[] __initconst = {
1198 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, 1249 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
1199 { }, 1250 { },
1200}; 1251};
@@ -1222,6 +1273,12 @@ static void __init exynos5x_clk_init(struct device_node *np,
1222 samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks, 1273 samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
1223 ARRAY_SIZE(exynos5x_fixed_rate_ext_clks), 1274 ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
1224 ext_clk_match); 1275 ext_clk_match);
1276
1277 if (_get_rate("fin_pll") == 24 * MHZ) {
1278 exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1279 exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1280 }
1281
1225 samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), 1282 samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
1226 reg_base); 1283 reg_base);
1227 samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks, 1284 samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
@@ -1253,6 +1310,8 @@ static void __init exynos5x_clk_init(struct device_node *np,
1253 } 1310 }
1254 1311
1255 exynos5420_clk_sleep_init(); 1312 exynos5420_clk_sleep_init();
1313
1314 samsung_clk_of_add_provider(np, ctx);
1256} 1315}
1257 1316
1258static void __init exynos5420_clk_init(struct device_node *np) 1317static void __init exynos5420_clk_init(struct device_node *np)
diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c
index 647f1440aa6a..00d1d00a41de 100644
--- a/drivers/clk/samsung/clk-exynos5440.c
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -84,7 +84,7 @@ static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = {
84 GATE(CLK_CS250_O, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0), 84 GATE(CLK_CS250_O, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0),
85}; 85};
86 86
87static struct of_device_id ext_clk_match[] __initdata = { 87static const struct of_device_id ext_clk_match[] __initconst = {
88 { .compatible = "samsung,clock-xtal", .data = (void *)0, }, 88 { .compatible = "samsung,clock-xtal", .data = (void *)0, },
89 {}, 89 {},
90}; 90};
@@ -123,6 +123,8 @@ static void __init exynos5440_clk_init(struct device_node *np)
123 samsung_clk_register_gate(ctx, exynos5440_gate_clks, 123 samsung_clk_register_gate(ctx, exynos5440_gate_clks,
124 ARRAY_SIZE(exynos5440_gate_clks)); 124 ARRAY_SIZE(exynos5440_gate_clks));
125 125
126 samsung_clk_of_add_provider(np, ctx);
127
126 pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk")); 128 pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk"));
127 pr_info("exynos5440 clock initialization complete\n"); 129 pr_info("exynos5440 clock initialization complete\n");
128} 130}
diff --git a/drivers/clk/samsung/clk-s3c2410.c b/drivers/clk/samsung/clk-s3c2410.c
index 140f4733c02e..5d2f03461bc5 100644
--- a/drivers/clk/samsung/clk-s3c2410.c
+++ b/drivers/clk/samsung/clk-s3c2410.c
@@ -466,6 +466,8 @@ void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
466 } 466 }
467 467
468 s3c2410_clk_sleep_init(); 468 s3c2410_clk_sleep_init();
469
470 samsung_clk_of_add_provider(np, ctx);
469} 471}
470 472
471static void __init s3c2410_clk_init(struct device_node *np) 473static void __init s3c2410_clk_init(struct device_node *np)
diff --git a/drivers/clk/samsung/clk-s3c2412.c b/drivers/clk/samsung/clk-s3c2412.c
index 23e4313f625e..34af09f6a155 100644
--- a/drivers/clk/samsung/clk-s3c2412.c
+++ b/drivers/clk/samsung/clk-s3c2412.c
@@ -265,6 +265,8 @@ void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
265 ARRAY_SIZE(s3c2412_aliases)); 265 ARRAY_SIZE(s3c2412_aliases));
266 266
267 s3c2412_clk_sleep_init(); 267 s3c2412_clk_sleep_init();
268
269 samsung_clk_of_add_provider(np, ctx);
268} 270}
269 271
270static void __init s3c2412_clk_init(struct device_node *np) 272static void __init s3c2412_clk_init(struct device_node *np)
diff --git a/drivers/clk/samsung/clk-s3c2443.c b/drivers/clk/samsung/clk-s3c2443.c
index c4bbdabebaa4..c92f853fca9f 100644
--- a/drivers/clk/samsung/clk-s3c2443.c
+++ b/drivers/clk/samsung/clk-s3c2443.c
@@ -445,6 +445,8 @@ void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
445 } 445 }
446 446
447 s3c2443_clk_sleep_init(); 447 s3c2443_clk_sleep_init();
448
449 samsung_clk_of_add_provider(np, ctx);
448} 450}
449 451
450static void __init s3c2416_clk_init(struct device_node *np) 452static void __init s3c2416_clk_init(struct device_node *np)
diff --git a/drivers/clk/samsung/clk-s3c64xx.c b/drivers/clk/samsung/clk-s3c64xx.c
index 8889ff1c10fc..0f590e5550cb 100644
--- a/drivers/clk/samsung/clk-s3c64xx.c
+++ b/drivers/clk/samsung/clk-s3c64xx.c
@@ -518,6 +518,8 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
518 ARRAY_SIZE(s3c64xx_clock_aliases)); 518 ARRAY_SIZE(s3c64xx_clock_aliases));
519 s3c64xx_clk_sleep_init(); 519 s3c64xx_clk_sleep_init();
520 520
521 samsung_clk_of_add_provider(np, ctx);
522
521 pr_info("%s clocks: apll = %lu, mpll = %lu\n" 523 pr_info("%s clocks: apll = %lu, mpll = %lu\n"
522 "\tepll = %lu, arm_clk = %lu\n", 524 "\tepll = %lu, arm_clk = %lu\n",
523 is_s3c6400 ? "S3C6400" : "S3C6410", 525 is_s3c6400 ? "S3C6400" : "S3C6410",
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index 49629c71c9e7..deab84d9f37d 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -53,7 +53,6 @@ struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
53{ 53{
54 struct samsung_clk_provider *ctx; 54 struct samsung_clk_provider *ctx;
55 struct clk **clk_table; 55 struct clk **clk_table;
56 int ret;
57 int i; 56 int i;
58 57
59 ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL); 58 ctx = kzalloc(sizeof(struct samsung_clk_provider), GFP_KERNEL);
@@ -72,17 +71,19 @@ struct samsung_clk_provider *__init samsung_clk_init(struct device_node *np,
72 ctx->clk_data.clk_num = nr_clks; 71 ctx->clk_data.clk_num = nr_clks;
73 spin_lock_init(&ctx->lock); 72 spin_lock_init(&ctx->lock);
74 73
75 if (!np)
76 return ctx;
77
78 ret = of_clk_add_provider(np, of_clk_src_onecell_get,
79 &ctx->clk_data);
80 if (ret)
81 panic("could not register clock provide\n");
82
83 return ctx; 74 return ctx;
84} 75}
85 76
77void __init samsung_clk_of_add_provider(struct device_node *np,
78 struct samsung_clk_provider *ctx)
79{
80 if (np) {
81 if (of_clk_add_provider(np, of_clk_src_onecell_get,
82 &ctx->clk_data))
83 panic("could not register clk provider\n");
84 }
85}
86
86/* add a clock instance to the clock lookup table used for dt based lookup */ 87/* add a clock instance to the clock lookup table used for dt based lookup */
87void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk, 88void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk,
88 unsigned int id) 89 unsigned int id)
@@ -284,7 +285,7 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
284void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx, 285void __init samsung_clk_of_register_fixed_ext(struct samsung_clk_provider *ctx,
285 struct samsung_fixed_rate_clock *fixed_rate_clk, 286 struct samsung_fixed_rate_clock *fixed_rate_clk,
286 unsigned int nr_fixed_rate_clk, 287 unsigned int nr_fixed_rate_clk,
287 struct of_device_id *clk_matches) 288 const struct of_device_id *clk_matches)
288{ 289{
289 const struct of_device_id *match; 290 const struct of_device_id *match;
290 struct device_node *clk_np; 291 struct device_node *clk_np;
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index 9693b80d924f..66ab36b5cef1 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -327,11 +327,13 @@ struct samsung_pll_clock {
327extern struct samsung_clk_provider *__init samsung_clk_init( 327extern struct samsung_clk_provider *__init samsung_clk_init(
328 struct device_node *np, void __iomem *base, 328 struct device_node *np, void __iomem *base,
329 unsigned long nr_clks); 329 unsigned long nr_clks);
330extern void __init samsung_clk_of_add_provider(struct device_node *np,
331 struct samsung_clk_provider *ctx);
330extern void __init samsung_clk_of_register_fixed_ext( 332extern void __init samsung_clk_of_register_fixed_ext(
331 struct samsung_clk_provider *ctx, 333 struct samsung_clk_provider *ctx,
332 struct samsung_fixed_rate_clock *fixed_rate_clk, 334 struct samsung_fixed_rate_clock *fixed_rate_clk,
333 unsigned int nr_fixed_rate_clk, 335 unsigned int nr_fixed_rate_clk,
334 struct of_device_id *clk_matches); 336 const struct of_device_id *clk_matches);
335 337
336extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, 338extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
337 struct clk *clk, unsigned int id); 339 struct clk *clk, unsigned int id);
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index 65894f7687ed..4daa5977793a 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -742,19 +742,19 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
742 clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0, 742 clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
743 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB, 743 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
744 0, &_lock); 744 0, &_lock);
745 clk_register_clkdev(clk, NULL, "dw_pcie.0"); 745 clk_register_clkdev(clk, NULL, "b1000000.pcie");
746 clk_register_clkdev(clk, NULL, "b1000000.ahci"); 746 clk_register_clkdev(clk, NULL, "b1000000.ahci");
747 747
748 clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0, 748 clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
749 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB, 749 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
750 0, &_lock); 750 0, &_lock);
751 clk_register_clkdev(clk, NULL, "dw_pcie.1"); 751 clk_register_clkdev(clk, NULL, "b1800000.pcie");
752 clk_register_clkdev(clk, NULL, "b1800000.ahci"); 752 clk_register_clkdev(clk, NULL, "b1800000.ahci");
753 753
754 clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0, 754 clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
755 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB, 755 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
756 0, &_lock); 756 0, &_lock);
757 clk_register_clkdev(clk, NULL, "dw_pcie.2"); 757 clk_register_clkdev(clk, NULL, "b4000000.pcie");
758 clk_register_clkdev(clk, NULL, "b4000000.ahci"); 758 clk_register_clkdev(clk, NULL, "b4000000.ahci");
759 759
760 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0, 760 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index fe835c1845fe..5a5c6648308d 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -839,7 +839,7 @@ void __init spear1340_clk_init(void __iomem *misc_base)
839 clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0, 839 clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
840 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB, 840 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
841 0, &_lock); 841 0, &_lock);
842 clk_register_clkdev(clk, NULL, "dw_pcie"); 842 clk_register_clkdev(clk, NULL, "b1000000.pcie");
843 clk_register_clkdev(clk, NULL, "b1000000.ahci"); 843 clk_register_clkdev(clk, NULL, "b1000000.ahci");
844 844
845 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0, 845 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
diff --git a/drivers/clk/st/Makefile b/drivers/clk/st/Makefile
index c7455ffdbdf7..ede7b2f13092 100644
--- a/drivers/clk/st/Makefile
+++ b/drivers/clk/st/Makefile
@@ -1 +1 @@
obj-y += clkgen-mux.o clkgen-pll.o clkgen-fsyn.o obj-y += clkgen-mux.o clkgen-pll.o clkgen-fsyn.o clk-flexgen.o
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
new file mode 100644
index 000000000000..2282cef9f2ff
--- /dev/null
+++ b/drivers/clk/st/clk-flexgen.c
@@ -0,0 +1,331 @@
1/*
2 * clk-flexgen.c
3 *
4 * Copyright (C) ST-Microelectronics SA 2013
5 * Author: Maxime Coquelin <maxime.coquelin@st.com> for ST-Microelectronics.
6 * License terms: GNU General Public License (GPL), version 2 */
7
8#include <linux/clk-provider.h>
9#include <linux/module.h>
10#include <linux/slab.h>
11#include <linux/io.h>
12#include <linux/err.h>
13#include <linux/string.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16
17struct flexgen {
18 struct clk_hw hw;
19
20 /* Crossbar */
21 struct clk_mux mux;
22 /* Pre-divisor's gate */
23 struct clk_gate pgate;
24 /* Pre-divisor */
25 struct clk_divider pdiv;
26 /* Final divisor's gate */
27 struct clk_gate fgate;
28 /* Final divisor */
29 struct clk_divider fdiv;
30};
31
32#define to_flexgen(_hw) container_of(_hw, struct flexgen, hw)
33
34static int flexgen_enable(struct clk_hw *hw)
35{
36 struct flexgen *flexgen = to_flexgen(hw);
37 struct clk_hw *pgate_hw = &flexgen->pgate.hw;
38 struct clk_hw *fgate_hw = &flexgen->fgate.hw;
39
40 pgate_hw->clk = hw->clk;
41 fgate_hw->clk = hw->clk;
42
43 clk_gate_ops.enable(pgate_hw);
44
45 clk_gate_ops.enable(fgate_hw);
46
47 pr_debug("%s: flexgen output enabled\n", __clk_get_name(hw->clk));
48 return 0;
49}
50
51static void flexgen_disable(struct clk_hw *hw)
52{
53 struct flexgen *flexgen = to_flexgen(hw);
54 struct clk_hw *fgate_hw = &flexgen->fgate.hw;
55
56 /* disable only the final gate */
57 fgate_hw->clk = hw->clk;
58
59 clk_gate_ops.disable(fgate_hw);
60
61 pr_debug("%s: flexgen output disabled\n", __clk_get_name(hw->clk));
62}
63
64static int flexgen_is_enabled(struct clk_hw *hw)
65{
66 struct flexgen *flexgen = to_flexgen(hw);
67 struct clk_hw *fgate_hw = &flexgen->fgate.hw;
68
69 fgate_hw->clk = hw->clk;
70
71 if (!clk_gate_ops.is_enabled(fgate_hw))
72 return 0;
73
74 return 1;
75}
76
77static u8 flexgen_get_parent(struct clk_hw *hw)
78{
79 struct flexgen *flexgen = to_flexgen(hw);
80 struct clk_hw *mux_hw = &flexgen->mux.hw;
81
82 mux_hw->clk = hw->clk;
83
84 return clk_mux_ops.get_parent(mux_hw);
85}
86
87static int flexgen_set_parent(struct clk_hw *hw, u8 index)
88{
89 struct flexgen *flexgen = to_flexgen(hw);
90 struct clk_hw *mux_hw = &flexgen->mux.hw;
91
92 mux_hw->clk = hw->clk;
93
94 return clk_mux_ops.set_parent(mux_hw, index);
95}
96
97static inline unsigned long
98clk_best_div(unsigned long parent_rate, unsigned long rate)
99{
100 return parent_rate / rate + ((rate > (2*(parent_rate % rate))) ? 0 : 1);
101}
102
103static long flexgen_round_rate(struct clk_hw *hw, unsigned long rate,
104 unsigned long *prate)
105{
106 unsigned long div;
107
108 /* Round div according to exact prate and wished rate */
109 div = clk_best_div(*prate, rate);
110
111 if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
112 *prate = rate * div;
113 return rate;
114 }
115
116 return *prate / div;
117}
118
119unsigned long flexgen_recalc_rate(struct clk_hw *hw,
120 unsigned long parent_rate)
121{
122 struct flexgen *flexgen = to_flexgen(hw);
123 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
124 struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;
125 unsigned long mid_rate;
126
127 pdiv_hw->clk = hw->clk;
128 fdiv_hw->clk = hw->clk;
129
130 mid_rate = clk_divider_ops.recalc_rate(pdiv_hw, parent_rate);
131
132 return clk_divider_ops.recalc_rate(fdiv_hw, mid_rate);
133}
134
135static int flexgen_set_rate(struct clk_hw *hw, unsigned long rate,
136 unsigned long parent_rate)
137{
138 struct flexgen *flexgen = to_flexgen(hw);
139 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw;
140 struct clk_hw *fdiv_hw = &flexgen->fdiv.hw;
141 unsigned long primary_div = 0;
142 int ret = 0;
143
144 pdiv_hw->clk = hw->clk;
145 fdiv_hw->clk = hw->clk;
146
147 primary_div = clk_best_div(parent_rate, rate);
148
149 clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate);
150 ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * primary_div);
151
152 return ret;
153}
154
155static const struct clk_ops flexgen_ops = {
156 .enable = flexgen_enable,
157 .disable = flexgen_disable,
158 .is_enabled = flexgen_is_enabled,
159 .get_parent = flexgen_get_parent,
160 .set_parent = flexgen_set_parent,
161 .round_rate = flexgen_round_rate,
162 .recalc_rate = flexgen_recalc_rate,
163 .set_rate = flexgen_set_rate,
164};
165
166struct clk *clk_register_flexgen(const char *name,
167 const char **parent_names, u8 num_parents,
168 void __iomem *reg, spinlock_t *lock, u32 idx,
169 unsigned long flexgen_flags) {
170 struct flexgen *fgxbar;
171 struct clk *clk;
172 struct clk_init_data init;
173 u32 xbar_shift;
174 void __iomem *xbar_reg, *fdiv_reg;
175
176 fgxbar = kzalloc(sizeof(struct flexgen), GFP_KERNEL);
177 if (!fgxbar)
178 return ERR_PTR(-ENOMEM);
179
180 init.name = name;
181 init.ops = &flexgen_ops;
182 init.flags = CLK_IS_BASIC | flexgen_flags;
183 init.parent_names = parent_names;
184 init.num_parents = num_parents;
185
186 xbar_reg = reg + 0x18 + (idx & ~0x3);
187 xbar_shift = (idx % 4) * 0x8;
188 fdiv_reg = reg + 0x164 + idx * 4;
189
190 /* Crossbar element config */
191 fgxbar->mux.lock = lock;
192 fgxbar->mux.mask = BIT(6) - 1;
193 fgxbar->mux.reg = xbar_reg;
194 fgxbar->mux.shift = xbar_shift;
195 fgxbar->mux.table = NULL;
196
197
198 /* Pre-divider's gate config (in xbar register)*/
199 fgxbar->pgate.lock = lock;
200 fgxbar->pgate.reg = xbar_reg;
201 fgxbar->pgate.bit_idx = xbar_shift + 6;
202
203 /* Pre-divider config */
204 fgxbar->pdiv.lock = lock;
205 fgxbar->pdiv.reg = reg + 0x58 + idx * 4;
206 fgxbar->pdiv.width = 10;
207
208 /* Final divider's gate config */
209 fgxbar->fgate.lock = lock;
210 fgxbar->fgate.reg = fdiv_reg;
211 fgxbar->fgate.bit_idx = 6;
212
213 /* Final divider config */
214 fgxbar->fdiv.lock = lock;
215 fgxbar->fdiv.reg = fdiv_reg;
216 fgxbar->fdiv.width = 6;
217
218 fgxbar->hw.init = &init;
219
220 clk = clk_register(NULL, &fgxbar->hw);
221 if (IS_ERR(clk))
222 kfree(fgxbar);
223 else
224 pr_debug("%s: parent %s rate %u\n",
225 __clk_get_name(clk),
226 __clk_get_name(clk_get_parent(clk)),
227 (unsigned int)clk_get_rate(clk));
228 return clk;
229}
230
231static const char ** __init flexgen_get_parents(struct device_node *np,
232 int *num_parents)
233{
234 const char **parents;
235 int nparents, i;
236
237 nparents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
238 if (WARN_ON(nparents <= 0))
239 return NULL;
240
241 parents = kcalloc(nparents, sizeof(const char *), GFP_KERNEL);
242 if (!parents)
243 return NULL;
244
245 for (i = 0; i < nparents; i++)
246 parents[i] = of_clk_get_parent_name(np, i);
247
248 *num_parents = nparents;
249 return parents;
250}
251
252void __init st_of_flexgen_setup(struct device_node *np)
253{
254 struct device_node *pnode;
255 void __iomem *reg;
256 struct clk_onecell_data *clk_data;
257 const char **parents;
258 int num_parents, i;
259 spinlock_t *rlock = NULL;
260 unsigned long flex_flags = 0;
261
262 pnode = of_get_parent(np);
263 if (!pnode)
264 return;
265
266 reg = of_iomap(pnode, 0);
267 if (!reg)
268 return;
269
270 parents = flexgen_get_parents(np, &num_parents);
271 if (!parents)
272 return;
273
274 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
275 if (!clk_data)
276 goto err;
277
278 clk_data->clk_num = of_property_count_strings(np ,
279 "clock-output-names");
280 if (clk_data->clk_num <= 0) {
281 pr_err("%s: Failed to get number of output clocks (%d)",
282 __func__, clk_data->clk_num);
283 goto err;
284 }
285
286 clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
287 GFP_KERNEL);
288 if (!clk_data->clks)
289 goto err;
290
291 rlock = kzalloc(sizeof(spinlock_t), GFP_KERNEL);
292 if (!rlock)
293 goto err;
294
295 for (i = 0; i < clk_data->clk_num; i++) {
296 struct clk *clk;
297 const char *clk_name;
298
299 if (of_property_read_string_index(np, "clock-output-names",
300 i, &clk_name)) {
301 break;
302 }
303
304 /*
305 * If we read an empty clock name then the output is unused
306 */
307 if (*clk_name == '\0')
308 continue;
309
310 clk = clk_register_flexgen(clk_name, parents, num_parents,
311 reg, rlock, i, flex_flags);
312
313 if (IS_ERR(clk))
314 goto err;
315
316 clk_data->clks[i] = clk;
317 }
318
319 kfree(parents);
320 of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
321
322 return;
323
324err:
325 if (clk_data)
326 kfree(clk_data->clks);
327 kfree(clk_data);
328 kfree(parents);
329 kfree(rlock);
330}
331CLK_OF_DECLARE(flexgen, "st,flexgen", st_of_flexgen_setup);
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index 4f53ee0778d9..af94ed82cfcb 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -41,7 +41,7 @@ struct stm_fs {
41 unsigned long nsdiv; 41 unsigned long nsdiv;
42}; 42};
43 43
44static struct stm_fs fs216c65_rtbl[] = { 44static const struct stm_fs fs216c65_rtbl[] = {
45 { .mdiv = 0x1f, .pe = 0x0, .sdiv = 0x7, .nsdiv = 0 }, /* 312.5 Khz */ 45 { .mdiv = 0x1f, .pe = 0x0, .sdiv = 0x7, .nsdiv = 0 }, /* 312.5 Khz */
46 { .mdiv = 0x17, .pe = 0x25ed, .sdiv = 0x1, .nsdiv = 0 }, /* 27 MHz */ 46 { .mdiv = 0x17, .pe = 0x25ed, .sdiv = 0x1, .nsdiv = 0 }, /* 27 MHz */
47 { .mdiv = 0x1a, .pe = 0x7b36, .sdiv = 0x2, .nsdiv = 1 }, /* 36.87 MHz */ 47 { .mdiv = 0x1a, .pe = 0x7b36, .sdiv = 0x2, .nsdiv = 1 }, /* 36.87 MHz */
@@ -49,31 +49,86 @@ static struct stm_fs fs216c65_rtbl[] = {
49 { .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x1, .nsdiv = 1 }, /* 108 MHz */ 49 { .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x1, .nsdiv = 1 }, /* 108 MHz */
50}; 50};
51 51
52static struct stm_fs fs432c65_rtbl[] = { 52static const struct stm_fs fs432c65_rtbl[] = {
53 { .mdiv = 0x1f, .pe = 0x0, .sdiv = 0x7, .nsdiv = 0 }, /* 625 Khz */ 53 { .mdiv = 0x1f, .pe = 0x0, .sdiv = 0x7, .nsdiv = 0 }, /* 625 Khz */
54 { .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x2, .nsdiv = 1 }, /* 108 MHz */ 54 { .mdiv = 0x13, .pe = 0x777c, .sdiv = 0x4, .nsdiv = 1 }, /* 25.175 MHz */
55 { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x0, .nsdiv = 1 }, /* 297 MHz */ 55 { .mdiv = 0x19, .pe = 0x4d35, .sdiv = 0x2, .nsdiv = 0 }, /* 25.200 MHz */
56 { .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x4, .nsdiv = 1 }, /* 27.000 MHz */
57 { .mdiv = 0x17, .pe = 0x28f5, .sdiv = 0x2, .nsdiv = 0 }, /* 27.027 MHz */
58 { .mdiv = 0x16, .pe = 0x3359, .sdiv = 0x2, .nsdiv = 0 }, /* 28.320 MHz */
59 { .mdiv = 0x1f, .pe = 0x2083, .sdiv = 0x3, .nsdiv = 1 }, /* 30.240 MHz */
60 { .mdiv = 0x1e, .pe = 0x430d, .sdiv = 0x3, .nsdiv = 1 }, /* 31.500 MHz */
61 { .mdiv = 0x17, .pe = 0x0, .sdiv = 0x3, .nsdiv = 1 }, /* 40.000 MHz */
62 { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x1, .nsdiv = 0 }, /* 49.500 MHz */
63 { .mdiv = 0x13, .pe = 0x6667, .sdiv = 0x3, .nsdiv = 1 }, /* 50.000 MHz */
64 { .mdiv = 0x10, .pe = 0x1ee6, .sdiv = 0x3, .nsdiv = 1 }, /* 57.284 MHz */
65 { .mdiv = 0x1d, .pe = 0x3b14, .sdiv = 0x2, .nsdiv = 1 }, /* 65.000 MHz */
66 { .mdiv = 0x12, .pe = 0x7c65, .sdiv = 0x1, .nsdiv = 0 }, /* 71.000 MHz */
67 { .mdiv = 0x19, .pe = 0xecd, .sdiv = 0x2, .nsdiv = 1 }, /* 74.176 MHz */
68 { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x2, .nsdiv = 1 }, /* 74.250 MHz */
69 { .mdiv = 0x19, .pe = 0x3334, .sdiv = 0x2, .nsdiv = 1 }, /* 75.000 MHz */
70 { .mdiv = 0x18, .pe = 0x5138, .sdiv = 0x2, .nsdiv = 1 }, /* 78.800 MHz */
71 { .mdiv = 0x1d, .pe = 0x77d, .sdiv = 0x0, .nsdiv = 0 }, /* 85.500 MHz */
72 { .mdiv = 0x1c, .pe = 0x13d5, .sdiv = 0x0, .nsdiv = 0 }, /* 88.750 MHz */
73 { .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x2, .nsdiv = 1 }, /* 108.000 MHz */
74 { .mdiv = 0x17, .pe = 0x28f5, .sdiv = 0x0, .nsdiv = 0 }, /* 108.108 MHz */
75 { .mdiv = 0x10, .pe = 0x6e26, .sdiv = 0x2, .nsdiv = 1 }, /* 118.963 MHz */
76 { .mdiv = 0x15, .pe = 0x3e63, .sdiv = 0x0, .nsdiv = 0 }, /* 119.000 MHz */
77 { .mdiv = 0x1c, .pe = 0x471d, .sdiv = 0x1, .nsdiv = 1 }, /* 135.000 MHz */
78 { .mdiv = 0x19, .pe = 0xecd, .sdiv = 0x1, .nsdiv = 1 }, /* 148.352 MHz */
79 { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x1, .nsdiv = 1 }, /* 148.500 MHz */
80 { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x0, .nsdiv = 1 }, /* 297 MHz */
56}; 81};
57 82
58static struct stm_fs fs660c32_rtbl[] = { 83static const struct stm_fs fs660c32_rtbl[] = {
59 { .mdiv = 0x01, .pe = 0x2aaa, .sdiv = 0x8, .nsdiv = 0 }, /* 600 KHz */ 84 { .mdiv = 0x14, .pe = 0x376b, .sdiv = 0x4, .nsdiv = 1 }, /* 25.175 MHz */
60 { .mdiv = 0x02, .pe = 0x3d33, .sdiv = 0x0, .nsdiv = 0 }, /* 148.5 Mhz */ 85 { .mdiv = 0x14, .pe = 0x30c3, .sdiv = 0x4, .nsdiv = 1 }, /* 25.200 MHz */
61 { .mdiv = 0x13, .pe = 0x5bcc, .sdiv = 0x0, .nsdiv = 1 }, /* 297 Mhz */ 86 { .mdiv = 0x10, .pe = 0x71c7, .sdiv = 0x4, .nsdiv = 1 }, /* 27.000 MHz */
62 { .mdiv = 0x0e, .pe = 0x1025, .sdiv = 0x0, .nsdiv = 1 }, /* 333 Mhz */ 87 { .mdiv = 0x00, .pe = 0x47af, .sdiv = 0x3, .nsdiv = 0 }, /* 27.027 MHz */
63 { .mdiv = 0x0b, .pe = 0x715f, .sdiv = 0x0, .nsdiv = 1 }, /* 350 Mhz */ 88 { .mdiv = 0x0e, .pe = 0x4e1a, .sdiv = 0x4, .nsdiv = 1 }, /* 28.320 MHz */
89 { .mdiv = 0x0b, .pe = 0x534d, .sdiv = 0x4, .nsdiv = 1 }, /* 30.240 MHz */
90 { .mdiv = 0x17, .pe = 0x6fbf, .sdiv = 0x2, .nsdiv = 0 }, /* 31.500 MHz */
91 { .mdiv = 0x01, .pe = 0x0, .sdiv = 0x4, .nsdiv = 1 }, /* 40.000 MHz */
92 { .mdiv = 0x15, .pe = 0x2aab, .sdiv = 0x3, .nsdiv = 1 }, /* 49.500 MHz */
93 { .mdiv = 0x14, .pe = 0x6666, .sdiv = 0x3, .nsdiv = 1 }, /* 50.000 MHz */
94 { .mdiv = 0x1d, .pe = 0x395f, .sdiv = 0x1, .nsdiv = 0 }, /* 57.284 MHz */
95 { .mdiv = 0x08, .pe = 0x4ec5, .sdiv = 0x3, .nsdiv = 1 }, /* 65.000 MHz */
96 { .mdiv = 0x05, .pe = 0x1770, .sdiv = 0x3, .nsdiv = 1 }, /* 71.000 MHz */
97 { .mdiv = 0x03, .pe = 0x4ba7, .sdiv = 0x3, .nsdiv = 1 }, /* 74.176 MHz */
98 { .mdiv = 0x0f, .pe = 0x3426, .sdiv = 0x1, .nsdiv = 0 }, /* 74.250 MHz */
99 { .mdiv = 0x0e, .pe = 0x7777, .sdiv = 0x1, .nsdiv = 0 }, /* 75.000 MHz */
100 { .mdiv = 0x01, .pe = 0x4053, .sdiv = 0x3, .nsdiv = 1 }, /* 78.800 MHz */
101 { .mdiv = 0x09, .pe = 0x15b5, .sdiv = 0x1, .nsdiv = 0 }, /* 85.500 MHz */
102 { .mdiv = 0x1b, .pe = 0x3f19, .sdiv = 0x2, .nsdiv = 1 }, /* 88.750 MHz */
103 { .mdiv = 0x10, .pe = 0x71c7, .sdiv = 0x2, .nsdiv = 1 }, /* 108.000 MHz */
104 { .mdiv = 0x00, .pe = 0x47af, .sdiv = 0x1, .nsdiv = 0 }, /* 108.108 MHz */
105 { .mdiv = 0x0c, .pe = 0x3118, .sdiv = 0x2, .nsdiv = 1 }, /* 118.963 MHz */
106 { .mdiv = 0x0c, .pe = 0x2f54, .sdiv = 0x2, .nsdiv = 1 }, /* 119.000 MHz */
107 { .mdiv = 0x07, .pe = 0xe39, .sdiv = 0x2, .nsdiv = 1 }, /* 135.000 MHz */
108 { .mdiv = 0x03, .pe = 0x4ba7, .sdiv = 0x2, .nsdiv = 1 }, /* 148.352 MHz */
109 { .mdiv = 0x0f, .pe = 0x3426, .sdiv = 0x0, .nsdiv = 0 }, /* 148.500 MHz */
110 { .mdiv = 0x03, .pe = 0x4ba7, .sdiv = 0x1, .nsdiv = 1 }, /* 296.704 MHz */
111 { .mdiv = 0x03, .pe = 0x471c, .sdiv = 0x1, .nsdiv = 1 }, /* 297.000 MHz */
112 { .mdiv = 0x00, .pe = 0x295f, .sdiv = 0x1, .nsdiv = 1 }, /* 326.700 MHz */
113 { .mdiv = 0x1f, .pe = 0x3633, .sdiv = 0x0, .nsdiv = 1 }, /* 333.000 MHz */
114 { .mdiv = 0x1c, .pe = 0x0, .sdiv = 0x0, .nsdiv = 1 }, /* 352.000 Mhz */
64}; 115};
65 116
66struct clkgen_quadfs_data { 117struct clkgen_quadfs_data {
67 bool reset_present; 118 bool reset_present;
68 bool bwfilter_present; 119 bool bwfilter_present;
69 bool lockstatus_present; 120 bool lockstatus_present;
121 bool powerup_polarity;
122 bool standby_polarity;
70 bool nsdiv_present; 123 bool nsdiv_present;
124 bool nrst_present;
71 struct clkgen_field ndiv; 125 struct clkgen_field ndiv;
72 struct clkgen_field ref_bw; 126 struct clkgen_field ref_bw;
73 struct clkgen_field nreset; 127 struct clkgen_field nreset;
74 struct clkgen_field npda; 128 struct clkgen_field npda;
75 struct clkgen_field lock_status; 129 struct clkgen_field lock_status;
76 130
131 struct clkgen_field nrst[QUADFS_MAX_CHAN];
77 struct clkgen_field nsb[QUADFS_MAX_CHAN]; 132 struct clkgen_field nsb[QUADFS_MAX_CHAN];
78 struct clkgen_field en[QUADFS_MAX_CHAN]; 133 struct clkgen_field en[QUADFS_MAX_CHAN];
79 struct clkgen_field mdiv[QUADFS_MAX_CHAN]; 134 struct clkgen_field mdiv[QUADFS_MAX_CHAN];
@@ -82,9 +137,9 @@ struct clkgen_quadfs_data {
82 struct clkgen_field nsdiv[QUADFS_MAX_CHAN]; 137 struct clkgen_field nsdiv[QUADFS_MAX_CHAN];
83 138
84 const struct clk_ops *pll_ops; 139 const struct clk_ops *pll_ops;
85 struct stm_fs *rtbl; 140 const struct stm_fs *rtbl;
86 u8 rtbl_cnt; 141 u8 rtbl_cnt;
87 int (*get_rate)(unsigned long , struct stm_fs *, 142 int (*get_rate)(unsigned long , const struct stm_fs *,
88 unsigned long *); 143 unsigned long *);
89}; 144};
90 145
@@ -94,11 +149,11 @@ static const struct clk_ops st_quadfs_fs216c65_ops;
94static const struct clk_ops st_quadfs_fs432c65_ops; 149static const struct clk_ops st_quadfs_fs432c65_ops;
95static const struct clk_ops st_quadfs_fs660c32_ops; 150static const struct clk_ops st_quadfs_fs660c32_ops;
96 151
97static int clk_fs216c65_get_rate(unsigned long, struct stm_fs *, 152static int clk_fs216c65_get_rate(unsigned long, const struct stm_fs *,
98 unsigned long *); 153 unsigned long *);
99static int clk_fs432c65_get_rate(unsigned long, struct stm_fs *, 154static int clk_fs432c65_get_rate(unsigned long, const struct stm_fs *,
100 unsigned long *); 155 unsigned long *);
101static int clk_fs660c32_dig_get_rate(unsigned long, struct stm_fs *, 156static int clk_fs660c32_dig_get_rate(unsigned long, const struct stm_fs *,
102 unsigned long *); 157 unsigned long *);
103/* 158/*
104 * Values for all of the standalone instances of this clock 159 * Values for all of the standalone instances of this clock
@@ -106,7 +161,7 @@ static int clk_fs660c32_dig_get_rate(unsigned long, struct stm_fs *,
106 * that the individual channel standby control bits (nsb) are in the 161 * that the individual channel standby control bits (nsb) are in the
107 * first register along with the PLL control bits. 162 * first register along with the PLL control bits.
108 */ 163 */
109static struct clkgen_quadfs_data st_fs216c65_416 = { 164static const struct clkgen_quadfs_data st_fs216c65_416 = {
110 /* 416 specific */ 165 /* 416 specific */
111 .npda = CLKGEN_FIELD(0x0, 0x1, 14), 166 .npda = CLKGEN_FIELD(0x0, 0x1, 14),
112 .nsb = { CLKGEN_FIELD(0x0, 0x1, 10), 167 .nsb = { CLKGEN_FIELD(0x0, 0x1, 10),
@@ -143,7 +198,7 @@ static struct clkgen_quadfs_data st_fs216c65_416 = {
143 .get_rate = clk_fs216c65_get_rate, 198 .get_rate = clk_fs216c65_get_rate,
144}; 199};
145 200
146static struct clkgen_quadfs_data st_fs432c65_416 = { 201static const struct clkgen_quadfs_data st_fs432c65_416 = {
147 .npda = CLKGEN_FIELD(0x0, 0x1, 14), 202 .npda = CLKGEN_FIELD(0x0, 0x1, 14),
148 .nsb = { CLKGEN_FIELD(0x0, 0x1, 10), 203 .nsb = { CLKGEN_FIELD(0x0, 0x1, 10),
149 CLKGEN_FIELD(0x0, 0x1, 11), 204 CLKGEN_FIELD(0x0, 0x1, 11),
@@ -179,7 +234,7 @@ static struct clkgen_quadfs_data st_fs432c65_416 = {
179 .get_rate = clk_fs432c65_get_rate, 234 .get_rate = clk_fs432c65_get_rate,
180}; 235};
181 236
182static struct clkgen_quadfs_data st_fs660c32_E_416 = { 237static const struct clkgen_quadfs_data st_fs660c32_E_416 = {
183 .npda = CLKGEN_FIELD(0x0, 0x1, 14), 238 .npda = CLKGEN_FIELD(0x0, 0x1, 14),
184 .nsb = { CLKGEN_FIELD(0x0, 0x1, 10), 239 .nsb = { CLKGEN_FIELD(0x0, 0x1, 10),
185 CLKGEN_FIELD(0x0, 0x1, 11), 240 CLKGEN_FIELD(0x0, 0x1, 11),
@@ -215,7 +270,7 @@ static struct clkgen_quadfs_data st_fs660c32_E_416 = {
215 .get_rate = clk_fs660c32_dig_get_rate, 270 .get_rate = clk_fs660c32_dig_get_rate,
216}; 271};
217 272
218static struct clkgen_quadfs_data st_fs660c32_F_416 = { 273static const struct clkgen_quadfs_data st_fs660c32_F_416 = {
219 .npda = CLKGEN_FIELD(0x0, 0x1, 14), 274 .npda = CLKGEN_FIELD(0x0, 0x1, 14),
220 .nsb = { CLKGEN_FIELD(0x0, 0x1, 10), 275 .nsb = { CLKGEN_FIELD(0x0, 0x1, 10),
221 CLKGEN_FIELD(0x0, 0x1, 11), 276 CLKGEN_FIELD(0x0, 0x1, 11),
@@ -251,6 +306,91 @@ static struct clkgen_quadfs_data st_fs660c32_F_416 = {
251 .get_rate = clk_fs660c32_dig_get_rate, 306 .get_rate = clk_fs660c32_dig_get_rate,
252}; 307};
253 308
309static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
310 .nrst_present = true,
311 .nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0),
312 CLKGEN_FIELD(0x2f0, 0x1, 1),
313 CLKGEN_FIELD(0x2f0, 0x1, 2),
314 CLKGEN_FIELD(0x2f0, 0x1, 3) },
315 .npda = CLKGEN_FIELD(0x2f0, 0x1, 12),
316 .nsb = { CLKGEN_FIELD(0x2f0, 0x1, 8),
317 CLKGEN_FIELD(0x2f0, 0x1, 9),
318 CLKGEN_FIELD(0x2f0, 0x1, 10),
319 CLKGEN_FIELD(0x2f0, 0x1, 11) },
320 .nsdiv_present = true,
321 .nsdiv = { CLKGEN_FIELD(0x304, 0x1, 24),
322 CLKGEN_FIELD(0x308, 0x1, 24),
323 CLKGEN_FIELD(0x30c, 0x1, 24),
324 CLKGEN_FIELD(0x310, 0x1, 24) },
325 .mdiv = { CLKGEN_FIELD(0x304, 0x1f, 15),
326 CLKGEN_FIELD(0x308, 0x1f, 15),
327 CLKGEN_FIELD(0x30c, 0x1f, 15),
328 CLKGEN_FIELD(0x310, 0x1f, 15) },
329 .en = { CLKGEN_FIELD(0x2fc, 0x1, 0),
330 CLKGEN_FIELD(0x2fc, 0x1, 1),
331 CLKGEN_FIELD(0x2fc, 0x1, 2),
332 CLKGEN_FIELD(0x2fc, 0x1, 3) },
333 .ndiv = CLKGEN_FIELD(0x2f4, 0x7, 16),
334 .pe = { CLKGEN_FIELD(0x304, 0x7fff, 0),
335 CLKGEN_FIELD(0x308, 0x7fff, 0),
336 CLKGEN_FIELD(0x30c, 0x7fff, 0),
337 CLKGEN_FIELD(0x310, 0x7fff, 0) },
338 .sdiv = { CLKGEN_FIELD(0x304, 0xf, 20),
339 CLKGEN_FIELD(0x308, 0xf, 20),
340 CLKGEN_FIELD(0x30c, 0xf, 20),
341 CLKGEN_FIELD(0x310, 0xf, 20) },
342 .lockstatus_present = true,
343 .lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
344 .powerup_polarity = 1,
345 .standby_polarity = 1,
346 .pll_ops = &st_quadfs_pll_c32_ops,
347 .rtbl = fs660c32_rtbl,
348 .rtbl_cnt = ARRAY_SIZE(fs660c32_rtbl),
349 .get_rate = clk_fs660c32_dig_get_rate,
350};
351
352static const struct clkgen_quadfs_data st_fs660c32_D_407 = {
353 .nrst_present = true,
354 .nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0),
355 CLKGEN_FIELD(0x2a0, 0x1, 1),
356 CLKGEN_FIELD(0x2a0, 0x1, 2),
357 CLKGEN_FIELD(0x2a0, 0x1, 3) },
358 .ndiv = CLKGEN_FIELD(0x2a4, 0x7, 16),
359 .pe = { CLKGEN_FIELD(0x2b4, 0x7fff, 0),
360 CLKGEN_FIELD(0x2b8, 0x7fff, 0),
361 CLKGEN_FIELD(0x2bc, 0x7fff, 0),
362 CLKGEN_FIELD(0x2c0, 0x7fff, 0) },
363 .sdiv = { CLKGEN_FIELD(0x2b4, 0xf, 20),
364 CLKGEN_FIELD(0x2b8, 0xf, 20),
365 CLKGEN_FIELD(0x2bc, 0xf, 20),
366 CLKGEN_FIELD(0x2c0, 0xf, 20) },
367 .npda = CLKGEN_FIELD(0x2a0, 0x1, 12),
368 .nsb = { CLKGEN_FIELD(0x2a0, 0x1, 8),
369 CLKGEN_FIELD(0x2a0, 0x1, 9),
370 CLKGEN_FIELD(0x2a0, 0x1, 10),
371 CLKGEN_FIELD(0x2a0, 0x1, 11) },
372 .nsdiv_present = true,
373 .nsdiv = { CLKGEN_FIELD(0x2b4, 0x1, 24),
374 CLKGEN_FIELD(0x2b8, 0x1, 24),
375 CLKGEN_FIELD(0x2bc, 0x1, 24),
376 CLKGEN_FIELD(0x2c0, 0x1, 24) },
377 .mdiv = { CLKGEN_FIELD(0x2b4, 0x1f, 15),
378 CLKGEN_FIELD(0x2b8, 0x1f, 15),
379 CLKGEN_FIELD(0x2bc, 0x1f, 15),
380 CLKGEN_FIELD(0x2c0, 0x1f, 15) },
381 .en = { CLKGEN_FIELD(0x2ac, 0x1, 0),
382 CLKGEN_FIELD(0x2ac, 0x1, 1),
383 CLKGEN_FIELD(0x2ac, 0x1, 2),
384 CLKGEN_FIELD(0x2ac, 0x1, 3) },
385 .lockstatus_present = true,
386 .lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
387 .powerup_polarity = 1,
388 .standby_polarity = 1,
389 .pll_ops = &st_quadfs_pll_c32_ops,
390 .rtbl = fs660c32_rtbl,
391 .rtbl_cnt = ARRAY_SIZE(fs660c32_rtbl),
392 .get_rate = clk_fs660c32_dig_get_rate,};
393
254/** 394/**
255 * DOC: A Frequency Synthesizer that multiples its input clock by a fixed factor 395 * DOC: A Frequency Synthesizer that multiples its input clock by a fixed factor
256 * 396 *
@@ -308,7 +448,7 @@ static int quadfs_pll_enable(struct clk_hw *hw)
308 /* 448 /*
309 * Power up the PLL 449 * Power up the PLL
310 */ 450 */
311 CLKGEN_WRITE(pll, npda, 1); 451 CLKGEN_WRITE(pll, npda, !pll->data->powerup_polarity);
312 452
313 if (pll->lock) 453 if (pll->lock)
314 spin_unlock_irqrestore(pll->lock, flags); 454 spin_unlock_irqrestore(pll->lock, flags);
@@ -335,7 +475,7 @@ static void quadfs_pll_disable(struct clk_hw *hw)
335 * Powerdown the PLL and then put block into soft reset if we have 475 * Powerdown the PLL and then put block into soft reset if we have
336 * reset control. 476 * reset control.
337 */ 477 */
338 CLKGEN_WRITE(pll, npda, 0); 478 CLKGEN_WRITE(pll, npda, pll->data->powerup_polarity);
339 479
340 if (pll->data->reset_present) 480 if (pll->data->reset_present)
341 CLKGEN_WRITE(pll, nreset, 0); 481 CLKGEN_WRITE(pll, nreset, 0);
@@ -611,7 +751,10 @@ static int quadfs_fsynth_enable(struct clk_hw *hw)
611 if (fs->lock) 751 if (fs->lock)
612 spin_lock_irqsave(fs->lock, flags); 752 spin_lock_irqsave(fs->lock, flags);
613 753
614 CLKGEN_WRITE(fs, nsb[fs->chan], 1); 754 CLKGEN_WRITE(fs, nsb[fs->chan], !fs->data->standby_polarity);
755
756 if (fs->data->nrst_present)
757 CLKGEN_WRITE(fs, nrst[fs->chan], 0);
615 758
616 if (fs->lock) 759 if (fs->lock)
617 spin_unlock_irqrestore(fs->lock, flags); 760 spin_unlock_irqrestore(fs->lock, flags);
@@ -631,7 +774,7 @@ static void quadfs_fsynth_disable(struct clk_hw *hw)
631 if (fs->lock) 774 if (fs->lock)
632 spin_lock_irqsave(fs->lock, flags); 775 spin_lock_irqsave(fs->lock, flags);
633 776
634 CLKGEN_WRITE(fs, nsb[fs->chan], 0); 777 CLKGEN_WRITE(fs, nsb[fs->chan], !fs->data->standby_polarity);
635 778
636 if (fs->lock) 779 if (fs->lock)
637 spin_unlock_irqrestore(fs->lock, flags); 780 spin_unlock_irqrestore(fs->lock, flags);
@@ -645,12 +788,12 @@ static int quadfs_fsynth_is_enabled(struct clk_hw *hw)
645 pr_debug("%s: %s enable bit = 0x%x\n", 788 pr_debug("%s: %s enable bit = 0x%x\n",
646 __func__, __clk_get_name(hw->clk), nsb); 789 __func__, __clk_get_name(hw->clk), nsb);
647 790
648 return !!nsb; 791 return fs->data->standby_polarity ? !nsb : !!nsb;
649} 792}
650 793
651#define P15 (uint64_t)(1 << 15) 794#define P15 (uint64_t)(1 << 15)
652 795
653static int clk_fs216c65_get_rate(unsigned long input, struct stm_fs *fs, 796static int clk_fs216c65_get_rate(unsigned long input, const struct stm_fs *fs,
654 unsigned long *rate) 797 unsigned long *rate)
655{ 798{
656 uint64_t res; 799 uint64_t res;
@@ -670,7 +813,7 @@ static int clk_fs216c65_get_rate(unsigned long input, struct stm_fs *fs,
670 return 0; 813 return 0;
671} 814}
672 815
673static int clk_fs432c65_get_rate(unsigned long input, struct stm_fs *fs, 816static int clk_fs432c65_get_rate(unsigned long input, const struct stm_fs *fs,
674 unsigned long *rate) 817 unsigned long *rate)
675{ 818{
676 uint64_t res; 819 uint64_t res;
@@ -693,7 +836,7 @@ static int clk_fs432c65_get_rate(unsigned long input, struct stm_fs *fs,
693#define P20 (uint64_t)(1 << 20) 836#define P20 (uint64_t)(1 << 20)
694 837
695static int clk_fs660c32_dig_get_rate(unsigned long input, 838static int clk_fs660c32_dig_get_rate(unsigned long input,
696 struct stm_fs *fs, unsigned long *rate) 839 const struct stm_fs *fs, unsigned long *rate)
697{ 840{
698 unsigned long s = (1 << fs->sdiv); 841 unsigned long s = (1 << fs->sdiv);
699 unsigned long ns; 842 unsigned long ns;
@@ -749,7 +892,7 @@ static long quadfs_find_best_rate(struct clk_hw *hw, unsigned long drate,
749{ 892{
750 struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw); 893 struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw);
751 int (*clk_fs_get_rate)(unsigned long , 894 int (*clk_fs_get_rate)(unsigned long ,
752 struct stm_fs *, unsigned long *); 895 const struct stm_fs *, unsigned long *);
753 struct stm_fs prev_params; 896 struct stm_fs prev_params;
754 unsigned long prev_rate, rate = 0; 897 unsigned long prev_rate, rate = 0;
755 unsigned long diff_rate, prev_diff_rate = ~0; 898 unsigned long diff_rate, prev_diff_rate = ~0;
@@ -793,7 +936,7 @@ static unsigned long quadfs_recalc_rate(struct clk_hw *hw,
793 unsigned long rate = 0; 936 unsigned long rate = 0;
794 struct stm_fs params; 937 struct stm_fs params;
795 int (*clk_fs_get_rate)(unsigned long , 938 int (*clk_fs_get_rate)(unsigned long ,
796 struct stm_fs *, unsigned long *); 939 const struct stm_fs *, unsigned long *);
797 940
798 clk_fs_get_rate = fs->data->get_rate; 941 clk_fs_get_rate = fs->data->get_rate;
799 942
@@ -917,19 +1060,31 @@ static struct clk * __init st_clk_register_quadfs_fsynth(
917static struct of_device_id quadfs_of_match[] = { 1060static struct of_device_id quadfs_of_match[] = {
918 { 1061 {
919 .compatible = "st,stih416-quadfs216", 1062 .compatible = "st,stih416-quadfs216",
920 .data = (void *)&st_fs216c65_416 1063 .data = &st_fs216c65_416
921 }, 1064 },
922 { 1065 {
923 .compatible = "st,stih416-quadfs432", 1066 .compatible = "st,stih416-quadfs432",
924 .data = (void *)&st_fs432c65_416 1067 .data = &st_fs432c65_416
925 }, 1068 },
926 { 1069 {
927 .compatible = "st,stih416-quadfs660-E", 1070 .compatible = "st,stih416-quadfs660-E",
928 .data = (void *)&st_fs660c32_E_416 1071 .data = &st_fs660c32_E_416
929 }, 1072 },
930 { 1073 {
931 .compatible = "st,stih416-quadfs660-F", 1074 .compatible = "st,stih416-quadfs660-F",
932 .data = (void *)&st_fs660c32_F_416 1075 .data = &st_fs660c32_F_416
1076 },
1077 {
1078 .compatible = "st,stih407-quadfs660-C",
1079 .data = &st_fs660c32_C_407
1080 },
1081 {
1082 .compatible = "st,stih407-quadfs660-D",
1083 .data = &st_fs660c32_D_407
1084 },
1085 {
1086 .compatible = "st,stih407-quadfs660-D",
1087 .data = (void *)&st_fs660c32_D_407
933 }, 1088 },
934 {} 1089 {}
935}; 1090};
diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
index a329906d1e81..79dc40b5cc68 100644
--- a/drivers/clk/st/clkgen-mux.c
+++ b/drivers/clk/st/clkgen-mux.c
@@ -580,6 +580,11 @@ static struct clkgen_mux_data stih416_a9_mux_data = {
580 .shift = 0, 580 .shift = 0,
581 .width = 2, 581 .width = 2,
582}; 582};
583static struct clkgen_mux_data stih407_a9_mux_data = {
584 .offset = 0x1a4,
585 .shift = 1,
586 .width = 2,
587};
583 588
584static struct of_device_id mux_of_match[] = { 589static struct of_device_id mux_of_match[] = {
585 { 590 {
@@ -610,6 +615,10 @@ static struct of_device_id mux_of_match[] = {
610 .compatible = "st,stih416-clkgen-a9-mux", 615 .compatible = "st,stih416-clkgen-a9-mux",
611 .data = &stih416_a9_mux_data, 616 .data = &stih416_a9_mux_data,
612 }, 617 },
618 {
619 .compatible = "st,stih407-clkgen-a9-mux",
620 .data = &stih407_a9_mux_data,
621 },
613 {} 622 {}
614}; 623};
615 624
@@ -765,7 +774,8 @@ void __init st_of_clkgen_vcc_setup(struct device_node *np)
765 div->reg = reg + VCC_DIV_OFFSET; 774 div->reg = reg + VCC_DIV_OFFSET;
766 div->shift = 2 * i; 775 div->shift = 2 * i;
767 div->width = 2; 776 div->width = 2;
768 div->flags = CLK_DIVIDER_POWER_OF_TWO; 777 div->flags = CLK_DIVIDER_POWER_OF_TWO |
778 CLK_DIVIDER_ROUND_CLOSEST;
769 779
770 mux->reg = reg + VCC_MUX_OFFSET; 780 mux->reg = reg + VCC_MUX_OFFSET;
771 mux->shift = 2 * i; 781 mux->shift = 2 * i;
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index d8b9b1a2aeda..29769d79e306 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -59,7 +59,7 @@ static const struct clk_ops st_pll800c65_ops;
59static const struct clk_ops stm_pll3200c32_ops; 59static const struct clk_ops stm_pll3200c32_ops;
60static const struct clk_ops st_pll1200c32_ops; 60static const struct clk_ops st_pll1200c32_ops;
61 61
62static struct clkgen_pll_data st_pll1600c65_ax = { 62static const struct clkgen_pll_data st_pll1600c65_ax = {
63 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 19), 63 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 19),
64 .locked_status = CLKGEN_FIELD(0x0, 0x1, 31), 64 .locked_status = CLKGEN_FIELD(0x0, 0x1, 31),
65 .mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL1600_MASK, 0), 65 .mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL1600_MASK, 0),
@@ -67,7 +67,7 @@ static struct clkgen_pll_data st_pll1600c65_ax = {
67 .ops = &st_pll1600c65_ops 67 .ops = &st_pll1600c65_ops
68}; 68};
69 69
70static struct clkgen_pll_data st_pll800c65_ax = { 70static const struct clkgen_pll_data st_pll800c65_ax = {
71 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 19), 71 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 19),
72 .locked_status = CLKGEN_FIELD(0x0, 0x1, 31), 72 .locked_status = CLKGEN_FIELD(0x0, 0x1, 31),
73 .mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL800_MASK, 0), 73 .mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL800_MASK, 0),
@@ -76,7 +76,7 @@ static struct clkgen_pll_data st_pll800c65_ax = {
76 .ops = &st_pll800c65_ops 76 .ops = &st_pll800c65_ops
77}; 77};
78 78
79static struct clkgen_pll_data st_pll3200c32_a1x_0 = { 79static const struct clkgen_pll_data st_pll3200c32_a1x_0 = {
80 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 31), 80 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 31),
81 .locked_status = CLKGEN_FIELD(0x4, 0x1, 31), 81 .locked_status = CLKGEN_FIELD(0x4, 0x1, 31),
82 .ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 0x0), 82 .ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 0x0),
@@ -93,7 +93,7 @@ static struct clkgen_pll_data st_pll3200c32_a1x_0 = {
93 .ops = &stm_pll3200c32_ops, 93 .ops = &stm_pll3200c32_ops,
94}; 94};
95 95
96static struct clkgen_pll_data st_pll3200c32_a1x_1 = { 96static const struct clkgen_pll_data st_pll3200c32_a1x_1 = {
97 .pdn_status = CLKGEN_FIELD(0xC, 0x1, 31), 97 .pdn_status = CLKGEN_FIELD(0xC, 0x1, 31),
98 .locked_status = CLKGEN_FIELD(0x10, 0x1, 31), 98 .locked_status = CLKGEN_FIELD(0x10, 0x1, 31),
99 .ndiv = CLKGEN_FIELD(0xC, C32_NDIV_MASK, 0x0), 99 .ndiv = CLKGEN_FIELD(0xC, C32_NDIV_MASK, 0x0),
@@ -111,7 +111,7 @@ static struct clkgen_pll_data st_pll3200c32_a1x_1 = {
111}; 111};
112 112
113/* 415 specific */ 113/* 415 specific */
114static struct clkgen_pll_data st_pll3200c32_a9_415 = { 114static const struct clkgen_pll_data st_pll3200c32_a9_415 = {
115 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0), 115 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
116 .locked_status = CLKGEN_FIELD(0x6C, 0x1, 0), 116 .locked_status = CLKGEN_FIELD(0x6C, 0x1, 0),
117 .ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 9), 117 .ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 9),
@@ -122,7 +122,7 @@ static struct clkgen_pll_data st_pll3200c32_a9_415 = {
122 .ops = &stm_pll3200c32_ops, 122 .ops = &stm_pll3200c32_ops,
123}; 123};
124 124
125static struct clkgen_pll_data st_pll3200c32_ddr_415 = { 125static const struct clkgen_pll_data st_pll3200c32_ddr_415 = {
126 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0), 126 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
127 .locked_status = CLKGEN_FIELD(0x100, 0x1, 0), 127 .locked_status = CLKGEN_FIELD(0x100, 0x1, 0),
128 .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0), 128 .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
@@ -135,7 +135,7 @@ static struct clkgen_pll_data st_pll3200c32_ddr_415 = {
135 .ops = &stm_pll3200c32_ops, 135 .ops = &stm_pll3200c32_ops,
136}; 136};
137 137
138static struct clkgen_pll_data st_pll1200c32_gpu_415 = { 138static const struct clkgen_pll_data st_pll1200c32_gpu_415 = {
139 .pdn_status = CLKGEN_FIELD(0x144, 0x1, 3), 139 .pdn_status = CLKGEN_FIELD(0x144, 0x1, 3),
140 .locked_status = CLKGEN_FIELD(0x168, 0x1, 0), 140 .locked_status = CLKGEN_FIELD(0x168, 0x1, 0),
141 .ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3), 141 .ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3),
@@ -146,7 +146,7 @@ static struct clkgen_pll_data st_pll1200c32_gpu_415 = {
146}; 146};
147 147
148/* 416 specific */ 148/* 416 specific */
149static struct clkgen_pll_data st_pll3200c32_a9_416 = { 149static const struct clkgen_pll_data st_pll3200c32_a9_416 = {
150 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0), 150 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
151 .locked_status = CLKGEN_FIELD(0x6C, 0x1, 0), 151 .locked_status = CLKGEN_FIELD(0x6C, 0x1, 0),
152 .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0), 152 .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
@@ -157,7 +157,7 @@ static struct clkgen_pll_data st_pll3200c32_a9_416 = {
157 .ops = &stm_pll3200c32_ops, 157 .ops = &stm_pll3200c32_ops,
158}; 158};
159 159
160static struct clkgen_pll_data st_pll3200c32_ddr_416 = { 160static const struct clkgen_pll_data st_pll3200c32_ddr_416 = {
161 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0), 161 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0),
162 .locked_status = CLKGEN_FIELD(0x10C, 0x1, 0), 162 .locked_status = CLKGEN_FIELD(0x10C, 0x1, 0),
163 .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0), 163 .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0),
@@ -170,7 +170,7 @@ static struct clkgen_pll_data st_pll3200c32_ddr_416 = {
170 .ops = &stm_pll3200c32_ops, 170 .ops = &stm_pll3200c32_ops,
171}; 171};
172 172
173static struct clkgen_pll_data st_pll1200c32_gpu_416 = { 173static const struct clkgen_pll_data st_pll1200c32_gpu_416 = {
174 .pdn_status = CLKGEN_FIELD(0x8E4, 0x1, 3), 174 .pdn_status = CLKGEN_FIELD(0x8E4, 0x1, 3),
175 .locked_status = CLKGEN_FIELD(0x90C, 0x1, 0), 175 .locked_status = CLKGEN_FIELD(0x90C, 0x1, 0),
176 .ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3), 176 .ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3),
@@ -180,6 +180,54 @@ static struct clkgen_pll_data st_pll1200c32_gpu_416 = {
180 .ops = &st_pll1200c32_ops, 180 .ops = &st_pll1200c32_ops,
181}; 181};
182 182
183static const struct clkgen_pll_data st_pll3200c32_407_a0 = {
184 /* 407 A0 */
185 .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
186 .locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
187 .ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16),
188 .idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0),
189 .num_odfs = 1,
190 .odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) },
191 .odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) },
192 .ops = &stm_pll3200c32_ops,
193};
194
195static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = {
196 /* 407 C0 PLL0 */
197 .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
198 .locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
199 .ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16),
200 .idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0),
201 .num_odfs = 1,
202 .odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) },
203 .odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) },
204 .ops = &stm_pll3200c32_ops,
205};
206
207static const struct clkgen_pll_data st_pll3200c32_407_c0_1 = {
208 /* 407 C0 PLL1 */
209 .pdn_status = CLKGEN_FIELD(0x2c8, 0x1, 8),
210 .locked_status = CLKGEN_FIELD(0x2c8, 0x1, 24),
211 .ndiv = CLKGEN_FIELD(0x2cc, C32_NDIV_MASK, 16),
212 .idf = CLKGEN_FIELD(0x2cc, C32_IDF_MASK, 0x0),
213 .num_odfs = 1,
214 .odf = { CLKGEN_FIELD(0x2dc, C32_ODF_MASK, 0) },
215 .odf_gate = { CLKGEN_FIELD(0x2dc, 0x1, 6) },
216 .ops = &stm_pll3200c32_ops,
217};
218
219static const struct clkgen_pll_data st_pll3200c32_407_a9 = {
220 /* 407 A9 */
221 .pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0),
222 .locked_status = CLKGEN_FIELD(0x87c, 0x1, 0),
223 .ndiv = CLKGEN_FIELD(0x1b0, C32_NDIV_MASK, 0),
224 .idf = CLKGEN_FIELD(0x1a8, C32_IDF_MASK, 25),
225 .num_odfs = 1,
226 .odf = { CLKGEN_FIELD(0x1b0, C32_ODF_MASK, 8) },
227 .odf_gate = { CLKGEN_FIELD(0x1ac, 0x1, 28) },
228 .ops = &stm_pll3200c32_ops,
229};
230
183/** 231/**
184 * DOC: Clock Generated by PLL, rate set and enabled by bootloader 232 * DOC: Clock Generated by PLL, rate set and enabled by bootloader
185 * 233 *
@@ -450,9 +498,8 @@ static void __init clkgena_c65_pll_setup(struct device_node *np)
450 * PLL0 HS (high speed) output 498 * PLL0 HS (high speed) output
451 */ 499 */
452 clk_data->clks[0] = clkgen_pll_register(parent_name, 500 clk_data->clks[0] = clkgen_pll_register(parent_name,
453 &st_pll1600c65_ax, 501 (struct clkgen_pll_data *) &st_pll1600c65_ax,
454 reg + CLKGENAx_PLL0_OFFSET, 502 reg + CLKGENAx_PLL0_OFFSET, clk_name);
455 clk_name);
456 503
457 if (IS_ERR(clk_data->clks[0])) 504 if (IS_ERR(clk_data->clks[0]))
458 goto err; 505 goto err;
@@ -480,9 +527,8 @@ static void __init clkgena_c65_pll_setup(struct device_node *np)
480 * PLL1 output 527 * PLL1 output
481 */ 528 */
482 clk_data->clks[2] = clkgen_pll_register(parent_name, 529 clk_data->clks[2] = clkgen_pll_register(parent_name,
483 &st_pll800c65_ax, 530 (struct clkgen_pll_data *) &st_pll800c65_ax,
484 reg + CLKGENAx_PLL1_OFFSET, 531 reg + CLKGENAx_PLL1_OFFSET, clk_name);
485 clk_name);
486 532
487 if (IS_ERR(clk_data->clks[2])) 533 if (IS_ERR(clk_data->clks[2]))
488 goto err; 534 goto err;
@@ -572,6 +618,22 @@ static struct of_device_id c32_pll_of_match[] = {
572 .compatible = "st,stih416-plls-c32-ddr", 618 .compatible = "st,stih416-plls-c32-ddr",
573 .data = &st_pll3200c32_ddr_416, 619 .data = &st_pll3200c32_ddr_416,
574 }, 620 },
621 {
622 .compatible = "st,stih407-plls-c32-a0",
623 .data = &st_pll3200c32_407_a0,
624 },
625 {
626 .compatible = "st,stih407-plls-c32-c0_0",
627 .data = &st_pll3200c32_407_c0_0,
628 },
629 {
630 .compatible = "st,stih407-plls-c32-c0_1",
631 .data = &st_pll3200c32_407_c0_1,
632 },
633 {
634 .compatible = "st,stih407-plls-c32-a9",
635 .data = &st_pll3200c32_407_a9,
636 },
575 {} 637 {}
576}; 638};
577 639
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 762fd64dbd1f..6850cba35871 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -6,4 +6,6 @@ obj-y += clk-sunxi.o clk-factors.o
6obj-y += clk-a10-hosc.o 6obj-y += clk-a10-hosc.o
7obj-y += clk-a20-gmac.o 7obj-y += clk-a20-gmac.o
8 8
9obj-$(CONFIG_MFD_SUN6I_PRCM) += clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o 9obj-$(CONFIG_MFD_SUN6I_PRCM) += \
10 clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
11 clk-sun8i-apb0.o
diff --git a/drivers/clk/sunxi/clk-a20-gmac.c b/drivers/clk/sunxi/clk-a20-gmac.c
index 633ddc4389ef..5296fd6dd7b3 100644
--- a/drivers/clk/sunxi/clk-a20-gmac.c
+++ b/drivers/clk/sunxi/clk-a20-gmac.c
@@ -60,7 +60,7 @@ static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)
60 struct clk_gate *gate; 60 struct clk_gate *gate;
61 const char *clk_name = node->name; 61 const char *clk_name = node->name;
62 const char *parents[SUN7I_A20_GMAC_PARENTS]; 62 const char *parents[SUN7I_A20_GMAC_PARENTS];
63 void *reg; 63 void __iomem *reg;
64 64
65 if (of_property_read_string(node, "clock-output-names", &clk_name)) 65 if (of_property_read_string(node, "clock-output-names", &clk_name))
66 return; 66 return;
diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index 3806d97e529b..2057c8ac648f 100644
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -62,7 +62,7 @@ static unsigned long clk_factors_recalc_rate(struct clk_hw *hw,
62 p = FACTOR_GET(config->pshift, config->pwidth, reg); 62 p = FACTOR_GET(config->pshift, config->pwidth, reg);
63 63
64 /* Calculate the rate */ 64 /* Calculate the rate */
65 rate = (parent_rate * n * (k + 1) >> p) / (m + 1); 65 rate = (parent_rate * (n + config->n_start) * (k + 1) >> p) / (m + 1);
66 66
67 return rate; 67 return rate;
68} 68}
diff --git a/drivers/clk/sunxi/clk-factors.h b/drivers/clk/sunxi/clk-factors.h
index 02e1a43ebac7..d2d0efa39379 100644
--- a/drivers/clk/sunxi/clk-factors.h
+++ b/drivers/clk/sunxi/clk-factors.h
@@ -15,6 +15,7 @@ struct clk_factors_config {
15 u8 mwidth; 15 u8 mwidth;
16 u8 pshift; 16 u8 pshift;
17 u8 pwidth; 17 u8 pwidth;
18 u8 n_start;
18}; 19};
19 20
20struct clk_factors { 21struct clk_factors {
diff --git a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
index 670f90d629d7..e10d0521ec76 100644
--- a/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
+++ b/drivers/clk/sunxi/clk-sun6i-apb0-gates.c
@@ -9,23 +9,53 @@
9 */ 9 */
10 10
11#include <linux/clk-provider.h> 11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
12#include <linux/module.h> 13#include <linux/module.h>
13#include <linux/of.h> 14#include <linux/of.h>
15#include <linux/of_device.h>
14#include <linux/platform_device.h> 16#include <linux/platform_device.h>
15 17
16#define SUN6I_APB0_GATES_MAX_SIZE 32 18#define SUN6I_APB0_GATES_MAX_SIZE 32
17 19
20struct gates_data {
21 DECLARE_BITMAP(mask, SUN6I_APB0_GATES_MAX_SIZE);
22};
23
24static const struct gates_data sun6i_a31_apb0_gates __initconst = {
25 .mask = {0x7F},
26};
27
28static const struct gates_data sun8i_a23_apb0_gates __initconst = {
29 .mask = {0x5D},
30};
31
32static const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = {
33 { .compatible = "allwinner,sun6i-a31-apb0-gates-clk", .data = &sun6i_a31_apb0_gates },
34 { .compatible = "allwinner,sun8i-a23-apb0-gates-clk", .data = &sun8i_a23_apb0_gates },
35 { /* sentinel */ }
36};
37
18static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev) 38static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev)
19{ 39{
20 struct device_node *np = pdev->dev.of_node; 40 struct device_node *np = pdev->dev.of_node;
21 struct clk_onecell_data *clk_data; 41 struct clk_onecell_data *clk_data;
42 const struct of_device_id *device;
43 const struct gates_data *data;
22 const char *clk_parent; 44 const char *clk_parent;
23 const char *clk_name; 45 const char *clk_name;
24 struct resource *r; 46 struct resource *r;
25 void __iomem *reg; 47 void __iomem *reg;
26 int gate_id;
27 int ngates; 48 int ngates;
28 int i; 49 int i;
50 int j = 0;
51
52 if (!np)
53 return -ENODEV;
54
55 device = of_match_device(sun6i_a31_apb0_gates_clk_dt_ids, &pdev->dev);
56 if (!device)
57 return -ENODEV;
58 data = device->data;
29 59
30 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 60 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
31 reg = devm_ioremap_resource(&pdev->dev, r); 61 reg = devm_ioremap_resource(&pdev->dev, r);
@@ -36,54 +66,36 @@ static int sun6i_a31_apb0_gates_clk_probe(struct platform_device *pdev)
36 if (!clk_parent) 66 if (!clk_parent)
37 return -EINVAL; 67 return -EINVAL;
38 68
39 ngates = of_property_count_strings(np, "clock-output-names");
40 if (ngates < 0)
41 return ngates;
42
43 if (!ngates || ngates > SUN6I_APB0_GATES_MAX_SIZE)
44 return -EINVAL;
45
46 clk_data = devm_kzalloc(&pdev->dev, sizeof(struct clk_onecell_data), 69 clk_data = devm_kzalloc(&pdev->dev, sizeof(struct clk_onecell_data),
47 GFP_KERNEL); 70 GFP_KERNEL);
48 if (!clk_data) 71 if (!clk_data)
49 return -ENOMEM; 72 return -ENOMEM;
50 73
51 clk_data->clks = devm_kzalloc(&pdev->dev, 74 /* Worst-case size approximation and memory allocation */
52 SUN6I_APB0_GATES_MAX_SIZE * 75 ngates = find_last_bit(data->mask, SUN6I_APB0_GATES_MAX_SIZE);
53 sizeof(struct clk *), 76 clk_data->clks = devm_kcalloc(&pdev->dev, (ngates + 1),
54 GFP_KERNEL); 77 sizeof(struct clk *), GFP_KERNEL);
55 if (!clk_data->clks) 78 if (!clk_data->clks)
56 return -ENOMEM; 79 return -ENOMEM;
57 80
58 for (i = 0; i < ngates; i++) { 81 for_each_set_bit(i, data->mask, SUN6I_APB0_GATES_MAX_SIZE) {
59 of_property_read_string_index(np, "clock-output-names", 82 of_property_read_string_index(np, "clock-output-names",
60 i, &clk_name); 83 j, &clk_name);
61 84
62 gate_id = i; 85 clk_data->clks[i] = clk_register_gate(&pdev->dev, clk_name,
63 of_property_read_u32_index(np, "clock-indices", i, &gate_id); 86 clk_parent, 0, reg, i,
87 0, NULL);
88 WARN_ON(IS_ERR(clk_data->clks[i]));
89 clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
64 90
65 WARN_ON(gate_id >= SUN6I_APB0_GATES_MAX_SIZE); 91 j++;
66 if (gate_id >= SUN6I_APB0_GATES_MAX_SIZE)
67 continue;
68
69 clk_data->clks[gate_id] = clk_register_gate(&pdev->dev,
70 clk_name,
71 clk_parent, 0,
72 reg, gate_id,
73 0, NULL);
74 WARN_ON(IS_ERR(clk_data->clks[gate_id]));
75 } 92 }
76 93
77 clk_data->clk_num = ngates; 94 clk_data->clk_num = ngates + 1;
78 95
79 return of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); 96 return of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
80} 97}
81 98
82const struct of_device_id sun6i_a31_apb0_gates_clk_dt_ids[] = {
83 { .compatible = "allwinner,sun6i-a31-apb0-gates-clk" },
84 { /* sentinel */ }
85};
86
87static struct platform_driver sun6i_a31_apb0_gates_clk_driver = { 99static struct platform_driver sun6i_a31_apb0_gates_clk_driver = {
88 .driver = { 100 .driver = {
89 .name = "sun6i-a31-apb0-gates-clk", 101 .name = "sun6i-a31-apb0-gates-clk",
diff --git a/drivers/clk/sunxi/clk-sun6i-apb0.c b/drivers/clk/sunxi/clk-sun6i-apb0.c
index 11f17c34c2ae..1fa23371c8c6 100644
--- a/drivers/clk/sunxi/clk-sun6i-apb0.c
+++ b/drivers/clk/sunxi/clk-sun6i-apb0.c
@@ -57,7 +57,7 @@ static int sun6i_a31_apb0_clk_probe(struct platform_device *pdev)
57 return of_clk_add_provider(np, of_clk_src_simple_get, clk); 57 return of_clk_add_provider(np, of_clk_src_simple_get, clk);
58} 58}
59 59
60const struct of_device_id sun6i_a31_apb0_clk_dt_ids[] = { 60static const struct of_device_id sun6i_a31_apb0_clk_dt_ids[] = {
61 { .compatible = "allwinner,sun6i-a31-apb0-clk" }, 61 { .compatible = "allwinner,sun6i-a31-apb0-clk" },
62 { /* sentinel */ } 62 { /* sentinel */ }
63}; 63};
diff --git a/drivers/clk/sunxi/clk-sun6i-ar100.c b/drivers/clk/sunxi/clk-sun6i-ar100.c
index f73cc051f0dd..eca8ca025b6a 100644
--- a/drivers/clk/sunxi/clk-sun6i-ar100.c
+++ b/drivers/clk/sunxi/clk-sun6i-ar100.c
@@ -160,7 +160,7 @@ static int ar100_set_rate(struct clk_hw *hw, unsigned long rate,
160 return 0; 160 return 0;
161} 161}
162 162
163struct clk_ops ar100_ops = { 163static struct clk_ops ar100_ops = {
164 .recalc_rate = ar100_recalc_rate, 164 .recalc_rate = ar100_recalc_rate,
165 .determine_rate = ar100_determine_rate, 165 .determine_rate = ar100_determine_rate,
166 .set_parent = ar100_set_parent, 166 .set_parent = ar100_set_parent,
@@ -213,7 +213,7 @@ static int sun6i_a31_ar100_clk_probe(struct platform_device *pdev)
213 return of_clk_add_provider(np, of_clk_src_simple_get, clk); 213 return of_clk_add_provider(np, of_clk_src_simple_get, clk);
214} 214}
215 215
216const struct of_device_id sun6i_a31_ar100_clk_dt_ids[] = { 216static const struct of_device_id sun6i_a31_ar100_clk_dt_ids[] = {
217 { .compatible = "allwinner,sun6i-a31-ar100-clk" }, 217 { .compatible = "allwinner,sun6i-a31-ar100-clk" },
218 { /* sentinel */ } 218 { /* sentinel */ }
219}; 219};
diff --git a/drivers/clk/sunxi/clk-sun8i-apb0.c b/drivers/clk/sunxi/clk-sun8i-apb0.c
new file mode 100644
index 000000000000..1f5ba9b4b8cd
--- /dev/null
+++ b/drivers/clk/sunxi/clk-sun8i-apb0.c
@@ -0,0 +1,68 @@
1/*
2 * Copyright (C) 2014 Chen-Yu Tsai
3 * Author: Chen-Yu Tsai <wens@csie.org>
4 *
5 * Allwinner A23 APB0 clock driver
6 *
7 * License Terms: GNU General Public License v2
8 *
9 * Based on clk-sun6i-apb0.c
10 * Allwinner A31 APB0 clock driver
11 *
12 * Copyright (C) 2014 Free Electrons
13 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
14 *
15 */
16
17#include <linux/clk-provider.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21
22static int sun8i_a23_apb0_clk_probe(struct platform_device *pdev)
23{
24 struct device_node *np = pdev->dev.of_node;
25 const char *clk_name = np->name;
26 const char *clk_parent;
27 struct resource *r;
28 void __iomem *reg;
29 struct clk *clk;
30
31 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
32 reg = devm_ioremap_resource(&pdev->dev, r);
33 if (IS_ERR(reg))
34 return PTR_ERR(reg);
35
36 clk_parent = of_clk_get_parent_name(np, 0);
37 if (!clk_parent)
38 return -EINVAL;
39
40 of_property_read_string(np, "clock-output-names", &clk_name);
41
42 /* The A23 APB0 clock is a standard 2 bit wide divider clock */
43 clk = clk_register_divider(&pdev->dev, clk_name, clk_parent, 0, reg,
44 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
45 if (IS_ERR(clk))
46 return PTR_ERR(clk);
47
48 return of_clk_add_provider(np, of_clk_src_simple_get, clk);
49}
50
51static const struct of_device_id sun8i_a23_apb0_clk_dt_ids[] = {
52 { .compatible = "allwinner,sun8i-a23-apb0-clk" },
53 { /* sentinel */ }
54};
55
56static struct platform_driver sun8i_a23_apb0_clk_driver = {
57 .driver = {
58 .name = "sun8i-a23-apb0-clk",
59 .owner = THIS_MODULE,
60 .of_match_table = sun8i_a23_apb0_clk_dt_ids,
61 },
62 .probe = sun8i_a23_apb0_clk_probe,
63};
64module_platform_driver(sun8i_a23_apb0_clk_driver);
65
66MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
67MODULE_DESCRIPTION("Allwinner A23 APB0 clock Driver");
68MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index fb2ce8440f0e..b654b7b1d137 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -164,6 +164,54 @@ static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
164} 164}
165 165
166/** 166/**
167 * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
168 * PLL1 rate is calculated as follows
169 * rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
170 * parent_rate is always 24Mhz
171 */
172
173static void sun8i_a23_get_pll1_factors(u32 *freq, u32 parent_rate,
174 u8 *n, u8 *k, u8 *m, u8 *p)
175{
176 u8 div;
177
178 /* Normalize value to a 6M multiple */
179 div = *freq / 6000000;
180 *freq = 6000000 * div;
181
182 /* we were called to round the frequency, we can now return */
183 if (n == NULL)
184 return;
185
186 /* m is always zero for pll1 */
187 *m = 0;
188
189 /* k is 1 only on these cases */
190 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
191 *k = 1;
192 else
193 *k = 0;
194
195 /* p will be 2 for divs under 20 and odd divs under 32 */
196 if (div < 20 || (div < 32 && (div & 1)))
197 *p = 2;
198
199 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
200 * of divs between 40-62 */
201 else if (div < 40 || (div < 64 && (div & 2)))
202 *p = 1;
203
204 /* any other entries have p = 0 */
205 else
206 *p = 0;
207
208 /* calculate a suitable n based on k and p */
209 div <<= *p;
210 div /= (*k + 1);
211 *n = div / 4 - 1;
212}
213
214/**
167 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5 215 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
168 * PLL5 rate is calculated as follows 216 * PLL5 rate is calculated as follows
169 * rate = parent_rate * n * (k + 1) 217 * rate = parent_rate * n * (k + 1)
@@ -422,6 +470,18 @@ static struct clk_factors_config sun6i_a31_pll1_config = {
422 .mwidth = 2, 470 .mwidth = 2,
423}; 471};
424 472
473static struct clk_factors_config sun8i_a23_pll1_config = {
474 .nshift = 8,
475 .nwidth = 5,
476 .kshift = 4,
477 .kwidth = 2,
478 .mshift = 0,
479 .mwidth = 2,
480 .pshift = 16,
481 .pwidth = 2,
482 .n_start = 1,
483};
484
425static struct clk_factors_config sun4i_pll5_config = { 485static struct clk_factors_config sun4i_pll5_config = {
426 .nshift = 8, 486 .nshift = 8,
427 .nwidth = 5, 487 .nwidth = 5,
@@ -471,6 +531,12 @@ static const struct factors_data sun6i_a31_pll1_data __initconst = {
471 .getter = sun6i_a31_get_pll1_factors, 531 .getter = sun6i_a31_get_pll1_factors,
472}; 532};
473 533
534static const struct factors_data sun8i_a23_pll1_data __initconst = {
535 .enable = 31,
536 .table = &sun8i_a23_pll1_config,
537 .getter = sun8i_a23_get_pll1_factors,
538};
539
474static const struct factors_data sun7i_a20_pll4_data __initconst = { 540static const struct factors_data sun7i_a20_pll4_data __initconst = {
475 .enable = 31, 541 .enable = 31,
476 .table = &sun4i_pll5_config, 542 .table = &sun4i_pll5_config,
@@ -527,7 +593,7 @@ static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
527 struct clk_hw *mux_hw = NULL; 593 struct clk_hw *mux_hw = NULL;
528 const char *clk_name = node->name; 594 const char *clk_name = node->name;
529 const char *parents[SUNXI_MAX_PARENTS]; 595 const char *parents[SUNXI_MAX_PARENTS];
530 void *reg; 596 void __iomem *reg;
531 int i = 0; 597 int i = 0;
532 598
533 reg = of_iomap(node, 0); 599 reg = of_iomap(node, 0);
@@ -632,7 +698,7 @@ static void __init sunxi_mux_clk_setup(struct device_node *node,
632 struct clk *clk; 698 struct clk *clk;
633 const char *clk_name = node->name; 699 const char *clk_name = node->name;
634 const char *parents[SUNXI_MAX_PARENTS]; 700 const char *parents[SUNXI_MAX_PARENTS];
635 void *reg; 701 void __iomem *reg;
636 int i = 0; 702 int i = 0;
637 703
638 reg = of_iomap(node, 0); 704 reg = of_iomap(node, 0);
@@ -664,6 +730,7 @@ struct div_data {
664 u8 shift; 730 u8 shift;
665 u8 pow; 731 u8 pow;
666 u8 width; 732 u8 width;
733 const struct clk_div_table *table;
667}; 734};
668 735
669static const struct div_data sun4i_axi_data __initconst = { 736static const struct div_data sun4i_axi_data __initconst = {
@@ -672,6 +739,23 @@ static const struct div_data sun4i_axi_data __initconst = {
672 .width = 2, 739 .width = 2,
673}; 740};
674 741
742static const struct clk_div_table sun8i_a23_axi_table[] __initconst = {
743 { .val = 0, .div = 1 },
744 { .val = 1, .div = 2 },
745 { .val = 2, .div = 3 },
746 { .val = 3, .div = 4 },
747 { .val = 4, .div = 4 },
748 { .val = 5, .div = 4 },
749 { .val = 6, .div = 4 },
750 { .val = 7, .div = 4 },
751 { } /* sentinel */
752};
753
754static const struct div_data sun8i_a23_axi_data __initconst = {
755 .width = 3,
756 .table = sun8i_a23_axi_table,
757};
758
675static const struct div_data sun4i_ahb_data __initconst = { 759static const struct div_data sun4i_ahb_data __initconst = {
676 .shift = 4, 760 .shift = 4,
677 .pow = 1, 761 .pow = 1,
@@ -696,7 +780,7 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
696 struct clk *clk; 780 struct clk *clk;
697 const char *clk_name = node->name; 781 const char *clk_name = node->name;
698 const char *clk_parent; 782 const char *clk_parent;
699 void *reg; 783 void __iomem *reg;
700 784
701 reg = of_iomap(node, 0); 785 reg = of_iomap(node, 0);
702 786
@@ -704,10 +788,10 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
704 788
705 of_property_read_string(node, "clock-output-names", &clk_name); 789 of_property_read_string(node, "clock-output-names", &clk_name);
706 790
707 clk = clk_register_divider(NULL, clk_name, clk_parent, 0, 791 clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0,
708 reg, data->shift, data->width, 792 reg, data->shift, data->width,
709 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0, 793 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
710 &clk_lock); 794 data->table, &clk_lock);
711 if (clk) { 795 if (clk) {
712 of_clk_add_provider(node, of_clk_src_simple_get, clk); 796 of_clk_add_provider(node, of_clk_src_simple_get, clk);
713 clk_register_clkdev(clk, clk_name, NULL); 797 clk_register_clkdev(clk, clk_name, NULL);
@@ -804,6 +888,10 @@ static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
804 .mask = { 0x12f77fff, 0x16ff3f }, 888 .mask = { 0x12f77fff, 0x16ff3f },
805}; 889};
806 890
891static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
892 .mask = {0x25386742, 0x2505111},
893};
894
807static const struct gates_data sun4i_apb0_gates_data __initconst = { 895static const struct gates_data sun4i_apb0_gates_data __initconst = {
808 .mask = {0x4EF}, 896 .mask = {0x4EF},
809}; 897};
@@ -836,6 +924,10 @@ static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
836 .mask = {0x3031}, 924 .mask = {0x3031},
837}; 925};
838 926
927static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
928 .mask = {0x3021},
929};
930
839static const struct gates_data sun6i_a31_apb2_gates_data __initconst = { 931static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
840 .mask = {0x3F000F}, 932 .mask = {0x3F000F},
841}; 933};
@@ -844,6 +936,10 @@ static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
844 .mask = { 0xff80ff }, 936 .mask = { 0xff80ff },
845}; 937};
846 938
939static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
940 .mask = {0x1F0007},
941};
942
847static const struct gates_data sun4i_a10_usb_gates_data __initconst = { 943static const struct gates_data sun4i_a10_usb_gates_data __initconst = {
848 .mask = {0x1C0}, 944 .mask = {0x1C0},
849 .reset_mask = 0x07, 945 .reset_mask = 0x07,
@@ -866,11 +962,10 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
866 struct gates_reset_data *reset_data; 962 struct gates_reset_data *reset_data;
867 const char *clk_parent; 963 const char *clk_parent;
868 const char *clk_name; 964 const char *clk_name;
869 void *reg; 965 void __iomem *reg;
870 int qty; 966 int qty;
871 int i = 0; 967 int i = 0;
872 int j = 0; 968 int j = 0;
873 int ignore;
874 969
875 reg = of_iomap(node, 0); 970 reg = of_iomap(node, 0);
876 971
@@ -891,14 +986,12 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
891 of_property_read_string_index(node, "clock-output-names", 986 of_property_read_string_index(node, "clock-output-names",
892 j, &clk_name); 987 j, &clk_name);
893 988
894 /* No driver claims this clock, but it should remain gated */
895 ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0;
896
897 clk_data->clks[i] = clk_register_gate(NULL, clk_name, 989 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
898 clk_parent, ignore, 990 clk_parent, 0,
899 reg + 4 * (i/32), i % 32, 991 reg + 4 * (i/32), i % 32,
900 0, &clk_lock); 992 0, &clk_lock);
901 WARN_ON(IS_ERR(clk_data->clks[i])); 993 WARN_ON(IS_ERR(clk_data->clks[i]));
994 clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
902 995
903 j++; 996 j++;
904 } 997 }
@@ -991,7 +1084,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
991 struct clk_gate *gate = NULL; 1084 struct clk_gate *gate = NULL;
992 struct clk_fixed_factor *fix_factor; 1085 struct clk_fixed_factor *fix_factor;
993 struct clk_divider *divider; 1086 struct clk_divider *divider;
994 void *reg; 1087 void __iomem *reg;
995 int i = 0; 1088 int i = 0;
996 int flags, clkflags; 1089 int flags, clkflags;
997 1090
@@ -1102,6 +1195,7 @@ free_clkdata:
1102static const struct of_device_id clk_factors_match[] __initconst = { 1195static const struct of_device_id clk_factors_match[] __initconst = {
1103 {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,}, 1196 {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
1104 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,}, 1197 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
1198 {.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,},
1105 {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,}, 1199 {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
1106 {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,}, 1200 {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
1107 {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,}, 1201 {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
@@ -1113,6 +1207,7 @@ static const struct of_device_id clk_factors_match[] __initconst = {
1113/* Matches for divider clocks */ 1207/* Matches for divider clocks */
1114static const struct of_device_id clk_div_match[] __initconst = { 1208static const struct of_device_id clk_div_match[] __initconst = {
1115 {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,}, 1209 {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,},
1210 {.compatible = "allwinner,sun8i-a23-axi-clk", .data = &sun8i_a23_axi_data,},
1116 {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,}, 1211 {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
1117 {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,}, 1212 {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
1118 {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,}, 1213 {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,},
@@ -1142,6 +1237,7 @@ static const struct of_device_id clk_gates_match[] __initconst = {
1142 {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,}, 1237 {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
1143 {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,}, 1238 {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
1144 {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,}, 1239 {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
1240 {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
1145 {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,}, 1241 {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
1146 {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,}, 1242 {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
1147 {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,}, 1243 {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
@@ -1151,7 +1247,9 @@ static const struct of_device_id clk_gates_match[] __initconst = {
1151 {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,}, 1247 {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
1152 {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,}, 1248 {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
1153 {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,}, 1249 {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
1250 {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
1154 {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,}, 1251 {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
1252 {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
1155 {.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,}, 1253 {.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,},
1156 {.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,}, 1254 {.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,},
1157 {.compatible = "allwinner,sun6i-a31-usb-clk", .data = &sun6i_a31_usb_gates_data,}, 1255 {.compatible = "allwinner,sun6i-a31-usb-clk", .data = &sun6i_a31_usb_gates_data,},
@@ -1202,6 +1300,7 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
1202 1300
1203static const char *sun4i_a10_critical_clocks[] __initdata = { 1301static const char *sun4i_a10_critical_clocks[] __initdata = {
1204 "pll5_ddr", 1302 "pll5_ddr",
1303 "ahb_sdram",
1205}; 1304};
1206 1305
1207static void __init sun4i_a10_init_clocks(struct device_node *node) 1306static void __init sun4i_a10_init_clocks(struct device_node *node)
@@ -1214,6 +1313,7 @@ CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks)
1214static const char *sun5i_critical_clocks[] __initdata = { 1313static const char *sun5i_critical_clocks[] __initdata = {
1215 "mbus", 1314 "mbus",
1216 "pll5_ddr", 1315 "pll5_ddr",
1316 "ahb_sdram",
1217}; 1317};
1218 1318
1219static void __init sun5i_init_clocks(struct device_node *node) 1319static void __init sun5i_init_clocks(struct device_node *node)
@@ -1236,3 +1336,4 @@ static void __init sun6i_init_clocks(struct device_node *node)
1236 ARRAY_SIZE(sun6i_critical_clocks)); 1336 ARRAY_SIZE(sun6i_critical_clocks));
1237} 1337}
1238CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks); 1338CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
1339CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 637b62ccc91e..c7c6d8fb32fb 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -110,6 +110,12 @@
110#define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24) 110#define XUSBIO_PLL_CFG0_SEQ_ENABLE BIT(24)
111#define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25) 111#define XUSBIO_PLL_CFG0_SEQ_START_STATE BIT(25)
112 112
113#define SATA_PLL_CFG0 0x490
114#define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
115#define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2)
116#define SATA_PLL_CFG0_SEQ_ENABLE BIT(24)
117#define SATA_PLL_CFG0_SEQ_START_STATE BIT(25)
118
113#define PLLE_MISC_PLLE_PTS BIT(8) 119#define PLLE_MISC_PLLE_PTS BIT(8)
114#define PLLE_MISC_IDDQ_SW_VALUE BIT(13) 120#define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
115#define PLLE_MISC_IDDQ_SW_CTRL BIT(14) 121#define PLLE_MISC_IDDQ_SW_CTRL BIT(14)
@@ -1361,6 +1367,19 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
1361 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; 1367 val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
1362 pll_writel(val, XUSBIO_PLL_CFG0, pll); 1368 pll_writel(val, XUSBIO_PLL_CFG0, pll);
1363 1369
1370 /* Enable hw control of SATA pll */
1371 val = pll_readl(SATA_PLL_CFG0, pll);
1372 val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
1373 val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
1374 val |= SATA_PLL_CFG0_SEQ_START_STATE;
1375 pll_writel(val, SATA_PLL_CFG0, pll);
1376
1377 udelay(1);
1378
1379 val = pll_readl(SATA_PLL_CFG0, pll);
1380 val |= SATA_PLL_CFG0_SEQ_ENABLE;
1381 pll_writel(val, SATA_PLL_CFG0, pll);
1382
1364out: 1383out:
1365 if (pll->lock) 1384 if (pll->lock)
1366 spin_unlock_irqrestore(pll->lock, flags); 1385 spin_unlock_irqrestore(pll->lock, flags);
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index adf6b814b5bc..37f32c49674e 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -469,7 +469,7 @@ static struct tegra_periph_init_data periph_clks[] = {
469 MUX("sata", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata), 469 MUX("sata", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata),
470 MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1), 470 MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1),
471 MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1), 471 MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1),
472 MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2), 472 MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2),
473 MUX8("sdmmc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC1, 14, 0, tegra_clk_sdmmc1_8), 473 MUX8("sdmmc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC1, 14, 0, tegra_clk_sdmmc1_8),
474 MUX8("sdmmc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC2, 9, 0, tegra_clk_sdmmc2_8), 474 MUX8("sdmmc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC2, 9, 0, tegra_clk_sdmmc2_8),
475 MUX8("sdmmc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC3, 69, 0, tegra_clk_sdmmc3_8), 475 MUX8("sdmmc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC3, 69, 0, tegra_clk_sdmmc3_8),
@@ -487,7 +487,7 @@ static struct tegra_periph_init_data periph_clks[] = {
487 MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, tegra_clk_extern2), 487 MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, tegra_clk_extern2),
488 MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, tegra_clk_extern3), 488 MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, tegra_clk_extern3),
489 MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm), 489 MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm),
490 MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8), 490 MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 164, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8),
491 MUX8("isp", mux_pllm_pllc_pllp_plla_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_8), 491 MUX8("isp", mux_pllm_pllc_pllp_plla_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_8),
492 MUX8("entropy", mux_pllp_clkm1, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy), 492 MUX8("entropy", mux_pllp_clkm1, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy),
493 MUX8("hdmi_audio", mux_pllp3_pllc_clkm, CLK_SOURCE_HDMI_AUDIO, 176, TEGRA_PERIPH_NO_RESET, tegra_clk_hdmi_audio), 493 MUX8("hdmi_audio", mux_pllp3_pllc_clkm, CLK_SOURCE_HDMI_AUDIO, 176, TEGRA_PERIPH_NO_RESET, tegra_clk_hdmi_audio),
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index b9c8ba258ef0..f760f31d05c4 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -151,6 +151,13 @@
151/* Tegra CPU clock and reset control regs */ 151/* Tegra CPU clock and reset control regs */
152#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 152#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
153 153
154#define MUX8(_name, _parents, _offset, \
155 _clk_num, _gate_flags, _clk_id) \
156 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
157 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
158 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\
159 NULL)
160
154#ifdef CONFIG_PM_SLEEP 161#ifdef CONFIG_PM_SLEEP
155static struct cpu_clk_suspend_context { 162static struct cpu_clk_suspend_context {
156 u32 clk_csite_src; 163 u32 clk_csite_src;
@@ -777,7 +784,6 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
777 [tegra_clk_spdif_in] = { .dt_id = TEGRA114_CLK_SPDIF_IN, .present = true }, 784 [tegra_clk_spdif_in] = { .dt_id = TEGRA114_CLK_SPDIF_IN, .present = true },
778 [tegra_clk_spdif_out] = { .dt_id = TEGRA114_CLK_SPDIF_OUT, .present = true }, 785 [tegra_clk_spdif_out] = { .dt_id = TEGRA114_CLK_SPDIF_OUT, .present = true },
779 [tegra_clk_vi_8] = { .dt_id = TEGRA114_CLK_VI, .present = true }, 786 [tegra_clk_vi_8] = { .dt_id = TEGRA114_CLK_VI, .present = true },
780 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA114_CLK_VI_SENSOR, .present = true },
781 [tegra_clk_fuse] = { .dt_id = TEGRA114_CLK_FUSE, .present = true }, 787 [tegra_clk_fuse] = { .dt_id = TEGRA114_CLK_FUSE, .present = true },
782 [tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true }, 788 [tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true },
783 [tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true }, 789 [tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true },
@@ -923,6 +929,13 @@ static struct tegra_devclk devclks[] __initdata = {
923 { .dev_id = "timer", .dt_id = TEGRA114_CLK_TIMER }, 929 { .dev_id = "timer", .dt_id = TEGRA114_CLK_TIMER },
924}; 930};
925 931
932static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = {
933 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0"
934};
935static u32 mux_pllm_pllc2_c_c3_pllp_plla_idx[] = {
936 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
937};
938
926static struct clk **clks; 939static struct clk **clks;
927 940
928static unsigned long osc_freq; 941static unsigned long osc_freq;
@@ -1178,10 +1191,18 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
1178 clks[TEGRA114_CLK_PLL_E_OUT0] = clk; 1191 clks[TEGRA114_CLK_PLL_E_OUT0] = clk;
1179} 1192}
1180 1193
1194#define CLK_SOURCE_VI_SENSOR 0x1a8
1195
1196static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1197 MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, TEGRA114_CLK_VI_SENSOR),
1198};
1199
1181static __init void tegra114_periph_clk_init(void __iomem *clk_base, 1200static __init void tegra114_periph_clk_init(void __iomem *clk_base,
1182 void __iomem *pmc_base) 1201 void __iomem *pmc_base)
1183{ 1202{
1184 struct clk *clk; 1203 struct clk *clk;
1204 struct tegra_periph_init_data *data;
1205 int i;
1185 1206
1186 /* xusb_ss_div2 */ 1207 /* xusb_ss_div2 */
1187 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, 1208 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
@@ -1209,6 +1230,14 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
1209 clk_base + CLK_SOURCE_EMC, 1230 clk_base + CLK_SOURCE_EMC,
1210 29, 3, 0, NULL); 1231 29, 3, 0, NULL);
1211 1232
1233 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1234 data = &tegra_periph_clk_list[i];
1235 clk = tegra_clk_register_periph(data->name,
1236 data->p.parent_names, data->num_parents,
1237 &data->periph, clk_base, data->offset, data->flags);
1238 clks[data->clk_id] = clk;
1239 }
1240
1212 tegra_periph_clk_init(clk_base, pmc_base, tegra114_clks, 1241 tegra_periph_clk_init(clk_base, pmc_base, tegra114_clks,
1213 &pll_p_params); 1242 &pll_p_params);
1214} 1243}
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 80efe51fdcdf..9525c684d149 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -869,7 +869,7 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
869 [tegra_clk_spdif_in] = { .dt_id = TEGRA124_CLK_SPDIF_IN, .present = true }, 869 [tegra_clk_spdif_in] = { .dt_id = TEGRA124_CLK_SPDIF_IN, .present = true },
870 [tegra_clk_spdif_out] = { .dt_id = TEGRA124_CLK_SPDIF_OUT, .present = true }, 870 [tegra_clk_spdif_out] = { .dt_id = TEGRA124_CLK_SPDIF_OUT, .present = true },
871 [tegra_clk_vi_9] = { .dt_id = TEGRA124_CLK_VI, .present = true }, 871 [tegra_clk_vi_9] = { .dt_id = TEGRA124_CLK_VI, .present = true },
872 [tegra_clk_vi_sensor] = { .dt_id = TEGRA124_CLK_VI_SENSOR, .present = true }, 872 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA124_CLK_VI_SENSOR, .present = true },
873 [tegra_clk_fuse] = { .dt_id = TEGRA124_CLK_FUSE, .present = true }, 873 [tegra_clk_fuse] = { .dt_id = TEGRA124_CLK_FUSE, .present = true },
874 [tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true }, 874 [tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true },
875 [tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true }, 875 [tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true },
@@ -1369,6 +1369,14 @@ static struct tegra_clk_init_table init_table[] __initdata = {
1369 {TEGRA124_CLK_XUSB_HS_SRC, TEGRA124_CLK_PLL_U_60M, 60000000, 0}, 1369 {TEGRA124_CLK_XUSB_HS_SRC, TEGRA124_CLK_PLL_U_60M, 60000000, 0},
1370 {TEGRA124_CLK_XUSB_FALCON_SRC, TEGRA124_CLK_PLL_RE_OUT, 224000000, 0}, 1370 {TEGRA124_CLK_XUSB_FALCON_SRC, TEGRA124_CLK_PLL_RE_OUT, 224000000, 0},
1371 {TEGRA124_CLK_XUSB_HOST_SRC, TEGRA124_CLK_PLL_RE_OUT, 112000000, 0}, 1371 {TEGRA124_CLK_XUSB_HOST_SRC, TEGRA124_CLK_PLL_RE_OUT, 112000000, 0},
1372 {TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0},
1373 {TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0},
1374 {TEGRA124_CLK_EMC, TEGRA124_CLK_CLK_MAX, 0, 1},
1375 {TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1},
1376 {TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1},
1377 {TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1},
1378 {TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0},
1379 {TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0},
1372 /* This MUST be the last entry. */ 1380 /* This MUST be the last entry. */
1373 {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0}, 1381 {TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
1374}; 1382};
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index c0a7d7723510..bf452b62beb8 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -277,6 +277,12 @@ void __init tegra_register_devclks(struct tegra_devclk *dev_clks, int num)
277 for (i = 0; i < num; i++, dev_clks++) 277 for (i = 0; i < num; i++, dev_clks++)
278 clk_register_clkdev(clks[dev_clks->dt_id], dev_clks->con_id, 278 clk_register_clkdev(clks[dev_clks->dt_id], dev_clks->con_id,
279 dev_clks->dev_id); 279 dev_clks->dev_id);
280
281 for (i = 0; i < clk_num; i++) {
282 if (!IS_ERR_OR_NULL(clks[i]))
283 clk_register_clkdev(clks[i], __clk_get_name(clks[i]),
284 "tegra-clk-debug");
285 }
280} 286}
281 287
282struct clk ** __init tegra_lookup_dt_id(int clk_id, 288struct clk ** __init tegra_lookup_dt_id(int clk_id,
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index cb8e6f14e880..62ac8f6e480c 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -18,6 +18,7 @@
18 18
19#define DRA7_DPLL_ABE_DEFFREQ 180633600 19#define DRA7_DPLL_ABE_DEFFREQ 180633600
20#define DRA7_DPLL_GMAC_DEFFREQ 1000000000 20#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
21#define DRA7_DPLL_USB_DEFFREQ 960000000
21 22
22 23
23static struct ti_dt_clk dra7xx_clks[] = { 24static struct ti_dt_clk dra7xx_clks[] = {
@@ -332,5 +333,15 @@ int __init dra7xx_dt_clk_init(void)
332 if (rc) 333 if (rc)
333 pr_err("%s: failed to configure GMAC DPLL!\n", __func__); 334 pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
334 335
336 dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
337 rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
338 if (rc)
339 pr_err("%s: failed to configure USB DPLL!\n", __func__);
340
341 dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
342 rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
343 if (rc)
344 pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
345
335 return rc; 346 return rc;
336} 347}
diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index 7c7f4b856bad..66aa83b99383 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -42,6 +42,7 @@
42#include <linux/of.h> 42#include <linux/of.h>
43#include <linux/of_device.h> 43#include <linux/of_device.h>
44#include <linux/of_irq.h> 44#include <linux/of_irq.h>
45#include <linux/clk/clk-conf.h>
45#include <linux/completion.h> 46#include <linux/completion.h>
46#include <linux/hardirq.h> 47#include <linux/hardirq.h>
47#include <linux/irqflags.h> 48#include <linux/irqflags.h>
@@ -274,6 +275,10 @@ static int i2c_device_probe(struct device *dev)
274 client->flags & I2C_CLIENT_WAKE); 275 client->flags & I2C_CLIENT_WAKE);
275 dev_dbg(dev, "probe\n"); 276 dev_dbg(dev, "probe\n");
276 277
278 status = of_clk_set_defaults(dev->of_node, false);
279 if (status < 0)
280 return status;
281
277 acpi_dev_pm_attach(&client->dev, true); 282 acpi_dev_pm_attach(&client->dev, true);
278 status = driver->probe(client, i2c_match_id(driver->id_table, client)); 283 status = driver->probe(client, i2c_match_id(driver->id_table, client));
279 if (status) 284 if (status)
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index d4f9670b51bc..22aa41cace82 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -29,6 +29,7 @@
29#include <linux/mutex.h> 29#include <linux/mutex.h>
30#include <linux/of_device.h> 30#include <linux/of_device.h>
31#include <linux/of_irq.h> 31#include <linux/of_irq.h>
32#include <linux/clk/clk-conf.h>
32#include <linux/slab.h> 33#include <linux/slab.h>
33#include <linux/mod_devicetable.h> 34#include <linux/mod_devicetable.h>
34#include <linux/spi/spi.h> 35#include <linux/spi/spi.h>
@@ -259,6 +260,10 @@ static int spi_drv_probe(struct device *dev)
259 const struct spi_driver *sdrv = to_spi_driver(dev->driver); 260 const struct spi_driver *sdrv = to_spi_driver(dev->driver);
260 int ret; 261 int ret;
261 262
263 ret = of_clk_set_defaults(dev->of_node, false);
264 if (ret)
265 return ret;
266
262 acpi_dev_pm_attach(dev, true); 267 acpi_dev_pm_attach(dev, true);
263 ret = sdrv->probe(to_spi_device(dev)); 268 ret = sdrv->probe(to_spi_device(dev));
264 if (ret) 269 if (ret)
diff --git a/include/dt-bindings/clock/clps711x-clock.h b/include/dt-bindings/clock/clps711x-clock.h
new file mode 100644
index 000000000000..0c4c80b63242
--- /dev/null
+++ b/include/dt-bindings/clock/clps711x-clock.h
@@ -0,0 +1,27 @@
1/*
2 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_CLPS711X_H
11#define __DT_BINDINGS_CLOCK_CLPS711X_H
12
13#define CLPS711X_CLK_DUMMY 0
14#define CLPS711X_CLK_CPU 1
15#define CLPS711X_CLK_BUS 2
16#define CLPS711X_CLK_PLL 3
17#define CLPS711X_CLK_TIMERREF 4
18#define CLPS711X_CLK_TIMER1 5
19#define CLPS711X_CLK_TIMER2 6
20#define CLPS711X_CLK_PWM 7
21#define CLPS711X_CLK_SPIREF 8
22#define CLPS711X_CLK_SPI 9
23#define CLPS711X_CLK_UART 10
24#define CLPS711X_CLK_TICK 11
25#define CLPS711X_CLK_MAX 12
26
27#endif
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
index 1106ca540a96..459bd2bd411f 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Author: Andrzej Haja <a.hajda@samsung.com> 3 * Author: Andrzej Hajda <a.hajda@samsung.com>
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as 6 * it under the terms of the GNU General Public License version 2 as
@@ -34,6 +34,11 @@
34#define CLK_MOUT_CORE 19 34#define CLK_MOUT_CORE 19
35#define CLK_MOUT_APLL 20 35#define CLK_MOUT_APLL 20
36#define CLK_SCLK_HDMIPHY 22 36#define CLK_SCLK_HDMIPHY 22
37#define CLK_OUT_DMC 23
38#define CLK_OUT_TOP 24
39#define CLK_OUT_LEFTBUS 25
40#define CLK_OUT_RIGHTBUS 26
41#define CLK_OUT_CPU 27
37 42
38/* gate for special clocks (sclk) */ 43/* gate for special clocks (sclk) */
39#define CLK_SCLK_FIMC0 128 44#define CLK_SCLK_FIMC0 128
@@ -230,6 +235,24 @@
230#define CLK_MOUT_G3D 394 235#define CLK_MOUT_G3D 394
231#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */ 236#define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
232 237
238/* gate clocks - ppmu */
239#define CLK_PPMULEFT 400
240#define CLK_PPMURIGHT 401
241#define CLK_PPMUCAMIF 402
242#define CLK_PPMUTV 403
243#define CLK_PPMUMFC_L 404
244#define CLK_PPMUMFC_R 405
245#define CLK_PPMUG3D 406
246#define CLK_PPMUIMAGE 407
247#define CLK_PPMULCD0 408
248#define CLK_PPMULCD1 409 /* Exynos4210 only */
249#define CLK_PPMUFILE 410
250#define CLK_PPMUGPS 411
251#define CLK_PPMUDMC0 412
252#define CLK_PPMUDMC1 413
253#define CLK_PPMUCPU 414
254#define CLK_PPMUACP 415
255
233/* div clocks */ 256/* div clocks */
234#define CLK_DIV_ISP0 450 /* Exynos4x12 only */ 257#define CLK_DIV_ISP0 450 /* Exynos4x12 only */
235#define CLK_DIV_ISP1 451 /* Exynos4x12 only */ 258#define CLK_DIV_ISP1 451 /* Exynos4x12 only */
diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h
index be6e97c54f54..4273891dc78e 100644
--- a/include/dt-bindings/clock/exynos5250.h
+++ b/include/dt-bindings/clock/exynos5250.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Author: Andrzej Haja <a.hajda@samsung.com> 3 * Author: Andrzej Hajda <a.hajda@samsung.com>
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as 6 * it under the terms of the GNU General Public License version 2 as
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 21d51ae1d242..8dc0913f1775 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Author: Andrzej Haja <a.hajda@samsung.com> 3 * Author: Andrzej Hajda <a.hajda@samsung.com>
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as 6 * it under the terms of the GNU General Public License version 2 as
diff --git a/include/dt-bindings/clock/exynos5440.h b/include/dt-bindings/clock/exynos5440.h
index 70cd85077fa9..c66fc405a79a 100644
--- a/include/dt-bindings/clock/exynos5440.h
+++ b/include/dt-bindings/clock/exynos5440.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Author: Andrzej Haja <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> 3 * Author: Andrzej Hajda <a.hajda@samsung.com>
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify 5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as 6 * it under the terms of the GNU General Public License version 2 as
diff --git a/include/dt-bindings/clock/qcom,gcc-apq8084.h b/include/dt-bindings/clock/qcom,gcc-apq8084.h
new file mode 100644
index 000000000000..2c0da566c46a
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-apq8084.h
@@ -0,0 +1,351 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_CLK_APQ_GCC_8084_H
15#define _DT_BINDINGS_CLK_APQ_GCC_8084_H
16
17#define GPLL0 0
18#define GPLL0_VOTE 1
19#define GPLL1 2
20#define GPLL1_VOTE 3
21#define GPLL2 4
22#define GPLL2_VOTE 5
23#define GPLL3 6
24#define GPLL3_VOTE 7
25#define GPLL4 8
26#define GPLL4_VOTE 9
27#define CONFIG_NOC_CLK_SRC 10
28#define PERIPH_NOC_CLK_SRC 11
29#define SYSTEM_NOC_CLK_SRC 12
30#define BLSP_UART_SIM_CLK_SRC 13
31#define QDSS_TSCTR_CLK_SRC 14
32#define UFS_AXI_CLK_SRC 15
33#define RPM_CLK_SRC 16
34#define KPSS_AHB_CLK_SRC 17
35#define QDSS_AT_CLK_SRC 18
36#define BIMC_DDR_CLK_SRC 19
37#define USB30_MASTER_CLK_SRC 20
38#define USB30_SEC_MASTER_CLK_SRC 21
39#define USB_HSIC_AHB_CLK_SRC 22
40#define MMSS_BIMC_GFX_CLK_SRC 23
41#define QDSS_STM_CLK_SRC 24
42#define ACC_CLK_SRC 25
43#define SEC_CTRL_CLK_SRC 26
44#define BLSP1_QUP1_I2C_APPS_CLK_SRC 27
45#define BLSP1_QUP1_SPI_APPS_CLK_SRC 28
46#define BLSP1_QUP2_I2C_APPS_CLK_SRC 29
47#define BLSP1_QUP2_SPI_APPS_CLK_SRC 30
48#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31
49#define BLSP1_QUP3_SPI_APPS_CLK_SRC 32
50#define BLSP1_QUP4_I2C_APPS_CLK_SRC 33
51#define BLSP1_QUP4_SPI_APPS_CLK_SRC 34
52#define BLSP1_QUP5_I2C_APPS_CLK_SRC 35
53#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36
54#define BLSP1_QUP6_I2C_APPS_CLK_SRC 37
55#define BLSP1_QUP6_SPI_APPS_CLK_SRC 38
56#define BLSP1_UART1_APPS_CLK_SRC 39
57#define BLSP1_UART2_APPS_CLK_SRC 40
58#define BLSP1_UART3_APPS_CLK_SRC 41
59#define BLSP1_UART4_APPS_CLK_SRC 42
60#define BLSP1_UART5_APPS_CLK_SRC 43
61#define BLSP1_UART6_APPS_CLK_SRC 44
62#define BLSP2_QUP1_I2C_APPS_CLK_SRC 45
63#define BLSP2_QUP1_SPI_APPS_CLK_SRC 46
64#define BLSP2_QUP2_I2C_APPS_CLK_SRC 47
65#define BLSP2_QUP2_SPI_APPS_CLK_SRC 48
66#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49
67#define BLSP2_QUP3_SPI_APPS_CLK_SRC 50
68#define BLSP2_QUP4_I2C_APPS_CLK_SRC 51
69#define BLSP2_QUP4_SPI_APPS_CLK_SRC 52
70#define BLSP2_QUP5_I2C_APPS_CLK_SRC 53
71#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54
72#define BLSP2_QUP6_I2C_APPS_CLK_SRC 55
73#define BLSP2_QUP6_SPI_APPS_CLK_SRC 56
74#define BLSP2_UART1_APPS_CLK_SRC 57
75#define BLSP2_UART2_APPS_CLK_SRC 58
76#define BLSP2_UART3_APPS_CLK_SRC 59
77#define BLSP2_UART4_APPS_CLK_SRC 60
78#define BLSP2_UART5_APPS_CLK_SRC 61
79#define BLSP2_UART6_APPS_CLK_SRC 62
80#define CE1_CLK_SRC 63
81#define CE2_CLK_SRC 64
82#define CE3_CLK_SRC 65
83#define GP1_CLK_SRC 66
84#define GP2_CLK_SRC 67
85#define GP3_CLK_SRC 68
86#define PDM2_CLK_SRC 69
87#define QDSS_TRACECLKIN_CLK_SRC 70
88#define RBCPR_CLK_SRC 71
89#define SATA_ASIC0_CLK_SRC 72
90#define SATA_PMALIVE_CLK_SRC 73
91#define SATA_RX_CLK_SRC 74
92#define SATA_RX_OOB_CLK_SRC 75
93#define SDCC1_APPS_CLK_SRC 76
94#define SDCC2_APPS_CLK_SRC 77
95#define SDCC3_APPS_CLK_SRC 78
96#define SDCC4_APPS_CLK_SRC 79
97#define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK 80
98#define SPMI_AHB_CLK_SRC 81
99#define SPMI_SER_CLK_SRC 82
100#define TSIF_REF_CLK_SRC 83
101#define USB30_MOCK_UTMI_CLK_SRC 84
102#define USB30_SEC_MOCK_UTMI_CLK_SRC 85
103#define USB_HS_SYSTEM_CLK_SRC 86
104#define USB_HSIC_CLK_SRC 87
105#define USB_HSIC_IO_CAL_CLK_SRC 88
106#define USB_HSIC_MOCK_UTMI_CLK_SRC 89
107#define USB_HSIC_SYSTEM_CLK_SRC 90
108#define GCC_BAM_DMA_AHB_CLK 91
109#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 92
110#define DDR_CLK_SRC 93
111#define GCC_BIMC_CFG_AHB_CLK 94
112#define GCC_BIMC_CLK 95
113#define GCC_BIMC_KPSS_AXI_CLK 96
114#define GCC_BIMC_SLEEP_CLK 97
115#define GCC_BIMC_SYSNOC_AXI_CLK 98
116#define GCC_BIMC_XO_CLK 99
117#define GCC_BLSP1_AHB_CLK 100
118#define GCC_BLSP1_SLEEP_CLK 101
119#define GCC_BLSP1_QUP1_I2C_APPS_CLK 102
120#define GCC_BLSP1_QUP1_SPI_APPS_CLK 103
121#define GCC_BLSP1_QUP2_I2C_APPS_CLK 104
122#define GCC_BLSP1_QUP2_SPI_APPS_CLK 105
123#define GCC_BLSP1_QUP3_I2C_APPS_CLK 106
124#define GCC_BLSP1_QUP3_SPI_APPS_CLK 107
125#define GCC_BLSP1_QUP4_I2C_APPS_CLK 108
126#define GCC_BLSP1_QUP4_SPI_APPS_CLK 109
127#define GCC_BLSP1_QUP5_I2C_APPS_CLK 110
128#define GCC_BLSP1_QUP5_SPI_APPS_CLK 111
129#define GCC_BLSP1_QUP6_I2C_APPS_CLK 112
130#define GCC_BLSP1_QUP6_SPI_APPS_CLK 113
131#define GCC_BLSP1_UART1_APPS_CLK 114
132#define GCC_BLSP1_UART1_SIM_CLK 115
133#define GCC_BLSP1_UART2_APPS_CLK 116
134#define GCC_BLSP1_UART2_SIM_CLK 117
135#define GCC_BLSP1_UART3_APPS_CLK 118
136#define GCC_BLSP1_UART3_SIM_CLK 119
137#define GCC_BLSP1_UART4_APPS_CLK 120
138#define GCC_BLSP1_UART4_SIM_CLK 121
139#define GCC_BLSP1_UART5_APPS_CLK 122
140#define GCC_BLSP1_UART5_SIM_CLK 123
141#define GCC_BLSP1_UART6_APPS_CLK 124
142#define GCC_BLSP1_UART6_SIM_CLK 125
143#define GCC_BLSP2_AHB_CLK 126
144#define GCC_BLSP2_SLEEP_CLK 127
145#define GCC_BLSP2_QUP1_I2C_APPS_CLK 128
146#define GCC_BLSP2_QUP1_SPI_APPS_CLK 129
147#define GCC_BLSP2_QUP2_I2C_APPS_CLK 130
148#define GCC_BLSP2_QUP2_SPI_APPS_CLK 131
149#define GCC_BLSP2_QUP3_I2C_APPS_CLK 132
150#define GCC_BLSP2_QUP3_SPI_APPS_CLK 133
151#define GCC_BLSP2_QUP4_I2C_APPS_CLK 134
152#define GCC_BLSP2_QUP4_SPI_APPS_CLK 135
153#define GCC_BLSP2_QUP5_I2C_APPS_CLK 136
154#define GCC_BLSP2_QUP5_SPI_APPS_CLK 137
155#define GCC_BLSP2_QUP6_I2C_APPS_CLK 138
156#define GCC_BLSP2_QUP6_SPI_APPS_CLK 139
157#define GCC_BLSP2_UART1_APPS_CLK 140
158#define GCC_BLSP2_UART1_SIM_CLK 141
159#define GCC_BLSP2_UART2_APPS_CLK 142
160#define GCC_BLSP2_UART2_SIM_CLK 143
161#define GCC_BLSP2_UART3_APPS_CLK 144
162#define GCC_BLSP2_UART3_SIM_CLK 145
163#define GCC_BLSP2_UART4_APPS_CLK 146
164#define GCC_BLSP2_UART4_SIM_CLK 147
165#define GCC_BLSP2_UART5_APPS_CLK 148
166#define GCC_BLSP2_UART5_SIM_CLK 149
167#define GCC_BLSP2_UART6_APPS_CLK 150
168#define GCC_BLSP2_UART6_SIM_CLK 151
169#define GCC_BOOT_ROM_AHB_CLK 152
170#define GCC_CE1_AHB_CLK 153
171#define GCC_CE1_AXI_CLK 154
172#define GCC_CE1_CLK 155
173#define GCC_CE2_AHB_CLK 156
174#define GCC_CE2_AXI_CLK 157
175#define GCC_CE2_CLK 158
176#define GCC_CE3_AHB_CLK 159
177#define GCC_CE3_AXI_CLK 160
178#define GCC_CE3_CLK 161
179#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 162
180#define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK 163
181#define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK 164
182#define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK 165
183#define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK 166
184#define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK 167
185#define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK 168
186#define GCC_CNOC_BUS_TIMEOUT7_AHB_CLK 169
187#define GCC_CFG_NOC_AHB_CLK 170
188#define GCC_CFG_NOC_DDR_CFG_CLK 171
189#define GCC_CFG_NOC_RPM_AHB_CLK 172
190#define GCC_COPSS_SMMU_AHB_CLK 173
191#define GCC_COPSS_SMMU_AXI_CLK 174
192#define GCC_DCD_XO_CLK 175
193#define GCC_BIMC_DDR_CH0_CLK 176
194#define GCC_BIMC_DDR_CH1_CLK 177
195#define GCC_BIMC_DDR_CPLL0_CLK 178
196#define GCC_BIMC_DDR_CPLL1_CLK 179
197#define GCC_BIMC_GFX_CLK 180
198#define GCC_DDR_DIM_CFG_CLK 181
199#define GCC_DDR_DIM_SLEEP_CLK 182
200#define GCC_DEHR_CLK 183
201#define GCC_AHB_CLK 184
202#define GCC_IM_SLEEP_CLK 185
203#define GCC_XO_CLK 186
204#define GCC_XO_DIV4_CLK 187
205#define GCC_GP1_CLK 188
206#define GCC_GP2_CLK 189
207#define GCC_GP3_CLK 190
208#define GCC_IMEM_AXI_CLK 191
209#define GCC_IMEM_CFG_AHB_CLK 192
210#define GCC_KPSS_AHB_CLK 193
211#define GCC_KPSS_AXI_CLK 194
212#define GCC_LPASS_MPORT_AXI_CLK 195
213#define GCC_LPASS_Q6_AXI_CLK 196
214#define GCC_LPASS_SWAY_CLK 197
215#define GCC_MMSS_BIMC_GFX_CLK 198
216#define GCC_MMSS_NOC_AT_CLK 199
217#define GCC_MMSS_NOC_CFG_AHB_CLK 200
218#define GCC_MMSS_VPU_MAPLE_SYS_NOC_AXI_CLK 201
219#define GCC_OCMEM_NOC_CFG_AHB_CLK 202
220#define GCC_OCMEM_SYS_NOC_AXI_CLK 203
221#define GCC_MPM_AHB_CLK 204
222#define GCC_MSG_RAM_AHB_CLK 205
223#define GCC_NOC_CONF_XPU_AHB_CLK 206
224#define GCC_PDM2_CLK 207
225#define GCC_PDM_AHB_CLK 208
226#define GCC_PDM_XO4_CLK 209
227#define GCC_PERIPH_NOC_AHB_CLK 210
228#define GCC_PERIPH_NOC_AT_CLK 211
229#define GCC_PERIPH_NOC_CFG_AHB_CLK 212
230#define GCC_PERIPH_NOC_USB_HSIC_AHB_CLK 213
231#define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK 214
232#define GCC_PERIPH_XPU_AHB_CLK 215
233#define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK 216
234#define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK 217
235#define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK 218
236#define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK 219
237#define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK 220
238#define GCC_PRNG_AHB_CLK 221
239#define GCC_QDSS_AT_CLK 222
240#define GCC_QDSS_CFG_AHB_CLK 223
241#define GCC_QDSS_DAP_AHB_CLK 224
242#define GCC_QDSS_DAP_CLK 225
243#define GCC_QDSS_ETR_USB_CLK 226
244#define GCC_QDSS_STM_CLK 227
245#define GCC_QDSS_TRACECLKIN_CLK 228
246#define GCC_QDSS_TSCTR_DIV16_CLK 229
247#define GCC_QDSS_TSCTR_DIV2_CLK 230
248#define GCC_QDSS_TSCTR_DIV3_CLK 231
249#define GCC_QDSS_TSCTR_DIV4_CLK 232
250#define GCC_QDSS_TSCTR_DIV8_CLK 233
251#define GCC_QDSS_RBCPR_XPU_AHB_CLK 234
252#define GCC_RBCPR_AHB_CLK 235
253#define GCC_RBCPR_CLK 236
254#define GCC_RPM_BUS_AHB_CLK 237
255#define GCC_RPM_PROC_HCLK 238
256#define GCC_RPM_SLEEP_CLK 239
257#define GCC_RPM_TIMER_CLK 240
258#define GCC_SATA_ASIC0_CLK 241
259#define GCC_SATA_AXI_CLK 242
260#define GCC_SATA_CFG_AHB_CLK 243
261#define GCC_SATA_PMALIVE_CLK 244
262#define GCC_SATA_RX_CLK 245
263#define GCC_SATA_RX_OOB_CLK 246
264#define GCC_SDCC1_AHB_CLK 247
265#define GCC_SDCC1_APPS_CLK 248
266#define GCC_SDCC1_CDCCAL_FF_CLK 249
267#define GCC_SDCC1_CDCCAL_SLEEP_CLK 250
268#define GCC_SDCC2_AHB_CLK 251
269#define GCC_SDCC2_APPS_CLK 252
270#define GCC_SDCC2_INACTIVITY_TIMERS_CLK 253
271#define GCC_SDCC3_AHB_CLK 254
272#define GCC_SDCC3_APPS_CLK 255
273#define GCC_SDCC3_INACTIVITY_TIMERS_CLK 256
274#define GCC_SDCC4_AHB_CLK 257
275#define GCC_SDCC4_APPS_CLK 258
276#define GCC_SDCC4_INACTIVITY_TIMERS_CLK 259
277#define GCC_SEC_CTRL_ACC_CLK 260
278#define GCC_SEC_CTRL_AHB_CLK 261
279#define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK 262
280#define GCC_SEC_CTRL_CLK 263
281#define GCC_SEC_CTRL_SENSE_CLK 264
282#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 265
283#define GCC_SNOC_BUS_TIMEOUT3_AHB_CLK 266
284#define GCC_SPDM_BIMC_CY_CLK 267
285#define GCC_SPDM_CFG_AHB_CLK 268
286#define GCC_SPDM_DEBUG_CY_CLK 269
287#define GCC_SPDM_FF_CLK 270
288#define GCC_SPDM_MSTR_AHB_CLK 271
289#define GCC_SPDM_PNOC_CY_CLK 272
290#define GCC_SPDM_RPM_CY_CLK 273
291#define GCC_SPDM_SNOC_CY_CLK 274
292#define GCC_SPMI_AHB_CLK 275
293#define GCC_SPMI_CNOC_AHB_CLK 276
294#define GCC_SPMI_SER_CLK 277
295#define GCC_SPSS_AHB_CLK 278
296#define GCC_SNOC_CNOC_AHB_CLK 279
297#define GCC_SNOC_PNOC_AHB_CLK 280
298#define GCC_SYS_NOC_AT_CLK 281
299#define GCC_SYS_NOC_AXI_CLK 282
300#define GCC_SYS_NOC_KPSS_AHB_CLK 283
301#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 284
302#define GCC_SYS_NOC_UFS_AXI_CLK 285
303#define GCC_SYS_NOC_USB3_AXI_CLK 286
304#define GCC_SYS_NOC_USB3_SEC_AXI_CLK 287
305#define GCC_TCSR_AHB_CLK 288
306#define GCC_TLMM_AHB_CLK 289
307#define GCC_TLMM_CLK 290
308#define GCC_TSIF_AHB_CLK 291
309#define GCC_TSIF_INACTIVITY_TIMERS_CLK 292
310#define GCC_TSIF_REF_CLK 293
311#define GCC_UFS_AHB_CLK 294
312#define GCC_UFS_AXI_CLK 295
313#define GCC_UFS_RX_CFG_CLK 296
314#define GCC_UFS_RX_SYMBOL_0_CLK 297
315#define GCC_UFS_RX_SYMBOL_1_CLK 298
316#define GCC_UFS_TX_CFG_CLK 299
317#define GCC_UFS_TX_SYMBOL_0_CLK 300
318#define GCC_UFS_TX_SYMBOL_1_CLK 301
319#define GCC_USB2A_PHY_SLEEP_CLK 302
320#define GCC_USB2B_PHY_SLEEP_CLK 303
321#define GCC_USB30_MASTER_CLK 304
322#define GCC_USB30_MOCK_UTMI_CLK 305
323#define GCC_USB30_SLEEP_CLK 306
324#define GCC_USB30_SEC_MASTER_CLK 307
325#define GCC_USB30_SEC_MOCK_UTMI_CLK 308
326#define GCC_USB30_SEC_SLEEP_CLK 309
327#define GCC_USB_HS_AHB_CLK 310
328#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 311
329#define GCC_USB_HS_SYSTEM_CLK 312
330#define GCC_USB_HSIC_AHB_CLK 313
331#define GCC_USB_HSIC_CLK 314
332#define GCC_USB_HSIC_IO_CAL_CLK 315
333#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 316
334#define GCC_USB_HSIC_MOCK_UTMI_CLK 317
335#define GCC_USB_HSIC_SYSTEM_CLK 318
336#define PCIE_0_AUX_CLK_SRC 319
337#define PCIE_0_PIPE_CLK_SRC 320
338#define PCIE_1_AUX_CLK_SRC 321
339#define PCIE_1_PIPE_CLK_SRC 322
340#define GCC_PCIE_0_AUX_CLK 323
341#define GCC_PCIE_0_CFG_AHB_CLK 324
342#define GCC_PCIE_0_MSTR_AXI_CLK 325
343#define GCC_PCIE_0_PIPE_CLK 326
344#define GCC_PCIE_0_SLV_AXI_CLK 327
345#define GCC_PCIE_1_AUX_CLK 328
346#define GCC_PCIE_1_CFG_AHB_CLK 329
347#define GCC_PCIE_1_MSTR_AXI_CLK 330
348#define GCC_PCIE_1_PIPE_CLK 331
349#define GCC_PCIE_1_SLV_AXI_CLK 332
350
351#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
new file mode 100644
index 000000000000..b857cadb0bd4
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
@@ -0,0 +1,293 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_CLK_GCC_IPQ806X_H
15#define _DT_BINDINGS_CLK_GCC_IPQ806X_H
16
17#define AFAB_CLK_SRC 0
18#define QDSS_STM_CLK 1
19#define SCSS_A_CLK 2
20#define SCSS_H_CLK 3
21#define AFAB_CORE_CLK 4
22#define SCSS_XO_SRC_CLK 5
23#define AFAB_EBI1_CH0_A_CLK 6
24#define AFAB_EBI1_CH1_A_CLK 7
25#define AFAB_AXI_S0_FCLK 8
26#define AFAB_AXI_S1_FCLK 9
27#define AFAB_AXI_S2_FCLK 10
28#define AFAB_AXI_S3_FCLK 11
29#define AFAB_AXI_S4_FCLK 12
30#define SFAB_CORE_CLK 13
31#define SFAB_AXI_S0_FCLK 14
32#define SFAB_AXI_S1_FCLK 15
33#define SFAB_AXI_S2_FCLK 16
34#define SFAB_AXI_S3_FCLK 17
35#define SFAB_AXI_S4_FCLK 18
36#define SFAB_AXI_S5_FCLK 19
37#define SFAB_AHB_S0_FCLK 20
38#define SFAB_AHB_S1_FCLK 21
39#define SFAB_AHB_S2_FCLK 22
40#define SFAB_AHB_S3_FCLK 23
41#define SFAB_AHB_S4_FCLK 24
42#define SFAB_AHB_S5_FCLK 25
43#define SFAB_AHB_S6_FCLK 26
44#define SFAB_AHB_S7_FCLK 27
45#define QDSS_AT_CLK_SRC 28
46#define QDSS_AT_CLK 29
47#define QDSS_TRACECLKIN_CLK_SRC 30
48#define QDSS_TRACECLKIN_CLK 31
49#define QDSS_TSCTR_CLK_SRC 32
50#define QDSS_TSCTR_CLK 33
51#define SFAB_ADM0_M0_A_CLK 34
52#define SFAB_ADM0_M1_A_CLK 35
53#define SFAB_ADM0_M2_H_CLK 36
54#define ADM0_CLK 37
55#define ADM0_PBUS_CLK 38
56#define IMEM0_A_CLK 39
57#define QDSS_H_CLK 40
58#define PCIE_A_CLK 41
59#define PCIE_AUX_CLK 42
60#define PCIE_H_CLK 43
61#define PCIE_PHY_CLK 44
62#define SFAB_CLK_SRC 45
63#define SFAB_LPASS_Q6_A_CLK 46
64#define SFAB_AFAB_M_A_CLK 47
65#define AFAB_SFAB_M0_A_CLK 48
66#define AFAB_SFAB_M1_A_CLK 49
67#define SFAB_SATA_S_H_CLK 50
68#define DFAB_CLK_SRC 51
69#define DFAB_CLK 52
70#define SFAB_DFAB_M_A_CLK 53
71#define DFAB_SFAB_M_A_CLK 54
72#define DFAB_SWAY0_H_CLK 55
73#define DFAB_SWAY1_H_CLK 56
74#define DFAB_ARB0_H_CLK 57
75#define DFAB_ARB1_H_CLK 58
76#define PPSS_H_CLK 59
77#define PPSS_PROC_CLK 60
78#define PPSS_TIMER0_CLK 61
79#define PPSS_TIMER1_CLK 62
80#define PMEM_A_CLK 63
81#define DMA_BAM_H_CLK 64
82#define SIC_H_CLK 65
83#define SPS_TIC_H_CLK 66
84#define CFPB_2X_CLK_SRC 67
85#define CFPB_CLK 68
86#define CFPB0_H_CLK 69
87#define CFPB1_H_CLK 70
88#define CFPB2_H_CLK 71
89#define SFAB_CFPB_M_H_CLK 72
90#define CFPB_MASTER_H_CLK 73
91#define SFAB_CFPB_S_H_CLK 74
92#define CFPB_SPLITTER_H_CLK 75
93#define TSIF_H_CLK 76
94#define TSIF_INACTIVITY_TIMERS_CLK 77
95#define TSIF_REF_SRC 78
96#define TSIF_REF_CLK 79
97#define CE1_H_CLK 80
98#define CE1_CORE_CLK 81
99#define CE1_SLEEP_CLK 82
100#define CE2_H_CLK 83
101#define CE2_CORE_CLK 84
102#define SFPB_H_CLK_SRC 85
103#define SFPB_H_CLK 86
104#define SFAB_SFPB_M_H_CLK 87
105#define SFAB_SFPB_S_H_CLK 88
106#define RPM_PROC_CLK 89
107#define RPM_BUS_H_CLK 90
108#define RPM_SLEEP_CLK 91
109#define RPM_TIMER_CLK 92
110#define RPM_MSG_RAM_H_CLK 93
111#define PMIC_ARB0_H_CLK 94
112#define PMIC_ARB1_H_CLK 95
113#define PMIC_SSBI2_SRC 96
114#define PMIC_SSBI2_CLK 97
115#define SDC1_H_CLK 98
116#define SDC2_H_CLK 99
117#define SDC3_H_CLK 100
118#define SDC4_H_CLK 101
119#define SDC1_SRC 102
120#define SDC1_CLK 103
121#define SDC2_SRC 104
122#define SDC2_CLK 105
123#define SDC3_SRC 106
124#define SDC3_CLK 107
125#define SDC4_SRC 108
126#define SDC4_CLK 109
127#define USB_HS1_H_CLK 110
128#define USB_HS1_XCVR_SRC 111
129#define USB_HS1_XCVR_CLK 112
130#define USB_HSIC_H_CLK 113
131#define USB_HSIC_XCVR_SRC 114
132#define USB_HSIC_XCVR_CLK 115
133#define USB_HSIC_SYSTEM_CLK_SRC 116
134#define USB_HSIC_SYSTEM_CLK 117
135#define CFPB0_C0_H_CLK 118
136#define CFPB0_D0_H_CLK 119
137#define CFPB0_C1_H_CLK 120
138#define CFPB0_D1_H_CLK 121
139#define USB_FS1_H_CLK 122
140#define USB_FS1_XCVR_SRC 123
141#define USB_FS1_XCVR_CLK 124
142#define USB_FS1_SYSTEM_CLK 125
143#define GSBI_COMMON_SIM_SRC 126
144#define GSBI1_H_CLK 127
145#define GSBI2_H_CLK 128
146#define GSBI3_H_CLK 129
147#define GSBI4_H_CLK 130
148#define GSBI5_H_CLK 131
149#define GSBI6_H_CLK 132
150#define GSBI7_H_CLK 133
151#define GSBI1_QUP_SRC 134
152#define GSBI1_QUP_CLK 135
153#define GSBI2_QUP_SRC 136
154#define GSBI2_QUP_CLK 137
155#define GSBI3_QUP_SRC 138
156#define GSBI3_QUP_CLK 139
157#define GSBI4_QUP_SRC 140
158#define GSBI4_QUP_CLK 141
159#define GSBI5_QUP_SRC 142
160#define GSBI5_QUP_CLK 143
161#define GSBI6_QUP_SRC 144
162#define GSBI6_QUP_CLK 145
163#define GSBI7_QUP_SRC 146
164#define GSBI7_QUP_CLK 147
165#define GSBI1_UART_SRC 148
166#define GSBI1_UART_CLK 149
167#define GSBI2_UART_SRC 150
168#define GSBI2_UART_CLK 151
169#define GSBI3_UART_SRC 152
170#define GSBI3_UART_CLK 153
171#define GSBI4_UART_SRC 154
172#define GSBI4_UART_CLK 155
173#define GSBI5_UART_SRC 156
174#define GSBI5_UART_CLK 157
175#define GSBI6_UART_SRC 158
176#define GSBI6_UART_CLK 159
177#define GSBI7_UART_SRC 160
178#define GSBI7_UART_CLK 161
179#define GSBI1_SIM_CLK 162
180#define GSBI2_SIM_CLK 163
181#define GSBI3_SIM_CLK 164
182#define GSBI4_SIM_CLK 165
183#define GSBI5_SIM_CLK 166
184#define GSBI6_SIM_CLK 167
185#define GSBI7_SIM_CLK 168
186#define USB_HSIC_HSIC_CLK_SRC 169
187#define USB_HSIC_HSIC_CLK 170
188#define USB_HSIC_HSIO_CAL_CLK 171
189#define SPDM_CFG_H_CLK 172
190#define SPDM_MSTR_H_CLK 173
191#define SPDM_FF_CLK_SRC 174
192#define SPDM_FF_CLK 175
193#define SEC_CTRL_CLK 176
194#define SEC_CTRL_ACC_CLK_SRC 177
195#define SEC_CTRL_ACC_CLK 178
196#define TLMM_H_CLK 179
197#define TLMM_CLK 180
198#define SATA_H_CLK 181
199#define SATA_CLK_SRC 182
200#define SATA_RXOOB_CLK 183
201#define SATA_PMALIVE_CLK 184
202#define SATA_PHY_REF_CLK 185
203#define SATA_A_CLK 186
204#define SATA_PHY_CFG_CLK 187
205#define TSSC_CLK_SRC 188
206#define TSSC_CLK 189
207#define PDM_SRC 190
208#define PDM_CLK 191
209#define GP0_SRC 192
210#define GP0_CLK 193
211#define GP1_SRC 194
212#define GP1_CLK 195
213#define GP2_SRC 196
214#define GP2_CLK 197
215#define MPM_CLK 198
216#define EBI1_CLK_SRC 199
217#define EBI1_CH0_CLK 200
218#define EBI1_CH1_CLK 201
219#define EBI1_2X_CLK 202
220#define EBI1_CH0_DQ_CLK 203
221#define EBI1_CH1_DQ_CLK 204
222#define EBI1_CH0_CA_CLK 205
223#define EBI1_CH1_CA_CLK 206
224#define EBI1_XO_CLK 207
225#define SFAB_SMPSS_S_H_CLK 208
226#define PRNG_SRC 209
227#define PRNG_CLK 210
228#define PXO_SRC 211
229#define SPDM_CY_PORT0_CLK 212
230#define SPDM_CY_PORT1_CLK 213
231#define SPDM_CY_PORT2_CLK 214
232#define SPDM_CY_PORT3_CLK 215
233#define SPDM_CY_PORT4_CLK 216
234#define SPDM_CY_PORT5_CLK 217
235#define SPDM_CY_PORT6_CLK 218
236#define SPDM_CY_PORT7_CLK 219
237#define PLL0 220
238#define PLL0_VOTE 221
239#define PLL3 222
240#define PLL3_VOTE 223
241#define PLL4 224
242#define PLL4_VOTE 225
243#define PLL8 226
244#define PLL8_VOTE 227
245#define PLL9 228
246#define PLL10 229
247#define PLL11 230
248#define PLL12 231
249#define PLL14 232
250#define PLL14_VOTE 233
251#define PLL18 234
252#define CE5_SRC 235
253#define CE5_H_CLK 236
254#define CE5_CORE_CLK 237
255#define CE3_SLEEP_CLK 238
256#define SFAB_AHB_S8_FCLK 239
257#define SPDM_CY_PORT8_CLK 246
258#define PCIE_ALT_REF_SRC 247
259#define PCIE_ALT_REF_CLK 248
260#define PCIE_1_A_CLK 249
261#define PCIE_1_AUX_CLK 250
262#define PCIE_1_H_CLK 251
263#define PCIE_1_PHY_CLK 252
264#define PCIE_1_ALT_REF_SRC 253
265#define PCIE_1_ALT_REF_CLK 254
266#define PCIE_2_A_CLK 255
267#define PCIE_2_AUX_CLK 256
268#define PCIE_2_H_CLK 257
269#define PCIE_2_PHY_CLK 258
270#define PCIE_2_ALT_REF_SRC 259
271#define PCIE_2_ALT_REF_CLK 260
272#define EBI2_CLK 261
273#define USB30_SLEEP_CLK 262
274#define USB30_UTMI_SRC 263
275#define USB30_0_UTMI_CLK 264
276#define USB30_1_UTMI_CLK 265
277#define USB30_MASTER_SRC 266
278#define USB30_0_MASTER_CLK 267
279#define USB30_1_MASTER_CLK 268
280#define GMAC_CORE1_CLK_SRC 269
281#define GMAC_CORE2_CLK_SRC 270
282#define GMAC_CORE3_CLK_SRC 271
283#define GMAC_CORE4_CLK_SRC 272
284#define GMAC_CORE1_CLK 273
285#define GMAC_CORE2_CLK 274
286#define GMAC_CORE3_CLK 275
287#define GMAC_CORE4_CLK 276
288#define UBI32_CORE1_CLK_SRC 277
289#define UBI32_CORE2_CLK_SRC 278
290#define UBI32_CORE1_CLK 279
291#define UBI32_CORE2_CLK 280
292
293#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8960.h b/include/dt-bindings/clock/qcom,gcc-msm8960.h
index f9f547146a15..7d20eedfee98 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8960.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8960.h
@@ -308,5 +308,16 @@
308#define PLL13 292 308#define PLL13 292
309#define PLL14 293 309#define PLL14 293
310#define PLL14_VOTE 294 310#define PLL14_VOTE 294
311#define USB_HS3_H_CLK 295
312#define USB_HS3_XCVR_SRC 296
313#define USB_HS3_XCVR_CLK 297
314#define USB_HS4_H_CLK 298
315#define USB_HS4_XCVR_SRC 299
316#define USB_HS4_XCVR_CLK 300
317#define SATA_PHY_CFG_CLK 301
318#define SATA_A_CLK 302
319#define CE3_SRC 303
320#define CE3_CORE_CLK 304
321#define CE3_H_CLK 305
311 322
312#endif 323#endif
diff --git a/include/dt-bindings/clock/qcom,mmcc-apq8084.h b/include/dt-bindings/clock/qcom,mmcc-apq8084.h
new file mode 100644
index 000000000000..a929f86d0ddd
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,mmcc-apq8084.h
@@ -0,0 +1,183 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_CLK_APQ_MMCC_8084_H
15#define _DT_BINDINGS_CLK_APQ_MMCC_8084_H
16
17#define MMSS_AHB_CLK_SRC 0
18#define MMSS_AXI_CLK_SRC 1
19#define MMPLL0 2
20#define MMPLL0_VOTE 3
21#define MMPLL1 4
22#define MMPLL1_VOTE 5
23#define MMPLL2 6
24#define MMPLL3 7
25#define MMPLL4 8
26#define CSI0_CLK_SRC 9
27#define CSI1_CLK_SRC 10
28#define CSI2_CLK_SRC 11
29#define CSI3_CLK_SRC 12
30#define VCODEC0_CLK_SRC 13
31#define VFE0_CLK_SRC 14
32#define VFE1_CLK_SRC 15
33#define MDP_CLK_SRC 16
34#define PCLK0_CLK_SRC 17
35#define PCLK1_CLK_SRC 18
36#define OCMEMNOC_CLK_SRC 19
37#define GFX3D_CLK_SRC 20
38#define JPEG0_CLK_SRC 21
39#define JPEG1_CLK_SRC 22
40#define JPEG2_CLK_SRC 23
41#define EDPPIXEL_CLK_SRC 24
42#define EXTPCLK_CLK_SRC 25
43#define VP_CLK_SRC 26
44#define CCI_CLK_SRC 27
45#define CAMSS_GP0_CLK_SRC 28
46#define CAMSS_GP1_CLK_SRC 29
47#define MCLK0_CLK_SRC 30
48#define MCLK1_CLK_SRC 31
49#define MCLK2_CLK_SRC 32
50#define MCLK3_CLK_SRC 33
51#define CSI0PHYTIMER_CLK_SRC 34
52#define CSI1PHYTIMER_CLK_SRC 35
53#define CSI2PHYTIMER_CLK_SRC 36
54#define CPP_CLK_SRC 37
55#define BYTE0_CLK_SRC 38
56#define BYTE1_CLK_SRC 39
57#define EDPAUX_CLK_SRC 40
58#define EDPLINK_CLK_SRC 41
59#define ESC0_CLK_SRC 42
60#define ESC1_CLK_SRC 43
61#define HDMI_CLK_SRC 44
62#define VSYNC_CLK_SRC 45
63#define RBCPR_CLK_SRC 46
64#define RBBMTIMER_CLK_SRC 47
65#define MAPLE_CLK_SRC 48
66#define VDP_CLK_SRC 49
67#define VPU_BUS_CLK_SRC 50
68#define MMSS_CXO_CLK 51
69#define MMSS_SLEEPCLK_CLK 52
70#define AVSYNC_AHB_CLK 53
71#define AVSYNC_EDPPIXEL_CLK 54
72#define AVSYNC_EXTPCLK_CLK 55
73#define AVSYNC_PCLK0_CLK 56
74#define AVSYNC_PCLK1_CLK 57
75#define AVSYNC_VP_CLK 58
76#define CAMSS_AHB_CLK 59
77#define CAMSS_CCI_CCI_AHB_CLK 60
78#define CAMSS_CCI_CCI_CLK 61
79#define CAMSS_CSI0_AHB_CLK 62
80#define CAMSS_CSI0_CLK 63
81#define CAMSS_CSI0PHY_CLK 64
82#define CAMSS_CSI0PIX_CLK 65
83#define CAMSS_CSI0RDI_CLK 66
84#define CAMSS_CSI1_AHB_CLK 67
85#define CAMSS_CSI1_CLK 68
86#define CAMSS_CSI1PHY_CLK 69
87#define CAMSS_CSI1PIX_CLK 70
88#define CAMSS_CSI1RDI_CLK 71
89#define CAMSS_CSI2_AHB_CLK 72
90#define CAMSS_CSI2_CLK 73
91#define CAMSS_CSI2PHY_CLK 74
92#define CAMSS_CSI2PIX_CLK 75
93#define CAMSS_CSI2RDI_CLK 76
94#define CAMSS_CSI3_AHB_CLK 77
95#define CAMSS_CSI3_CLK 78
96#define CAMSS_CSI3PHY_CLK 79
97#define CAMSS_CSI3PIX_CLK 80
98#define CAMSS_CSI3RDI_CLK 81
99#define CAMSS_CSI_VFE0_CLK 82
100#define CAMSS_CSI_VFE1_CLK 83
101#define CAMSS_GP0_CLK 84
102#define CAMSS_GP1_CLK 85
103#define CAMSS_ISPIF_AHB_CLK 86
104#define CAMSS_JPEG_JPEG0_CLK 87
105#define CAMSS_JPEG_JPEG1_CLK 88
106#define CAMSS_JPEG_JPEG2_CLK 89
107#define CAMSS_JPEG_JPEG_AHB_CLK 90
108#define CAMSS_JPEG_JPEG_AXI_CLK 91
109#define CAMSS_MCLK0_CLK 92
110#define CAMSS_MCLK1_CLK 93
111#define CAMSS_MCLK2_CLK 94
112#define CAMSS_MCLK3_CLK 95
113#define CAMSS_MICRO_AHB_CLK 96
114#define CAMSS_PHY0_CSI0PHYTIMER_CLK 97
115#define CAMSS_PHY1_CSI1PHYTIMER_CLK 98
116#define CAMSS_PHY2_CSI2PHYTIMER_CLK 99
117#define CAMSS_TOP_AHB_CLK 100
118#define CAMSS_VFE_CPP_AHB_CLK 101
119#define CAMSS_VFE_CPP_CLK 102
120#define CAMSS_VFE_VFE0_CLK 103
121#define CAMSS_VFE_VFE1_CLK 104
122#define CAMSS_VFE_VFE_AHB_CLK 105
123#define CAMSS_VFE_VFE_AXI_CLK 106
124#define MDSS_AHB_CLK 107
125#define MDSS_AXI_CLK 108
126#define MDSS_BYTE0_CLK 109
127#define MDSS_BYTE1_CLK 110
128#define MDSS_EDPAUX_CLK 111
129#define MDSS_EDPLINK_CLK 112
130#define MDSS_EDPPIXEL_CLK 113
131#define MDSS_ESC0_CLK 114
132#define MDSS_ESC1_CLK 115
133#define MDSS_EXTPCLK_CLK 116
134#define MDSS_HDMI_AHB_CLK 117
135#define MDSS_HDMI_CLK 118
136#define MDSS_MDP_CLK 119
137#define MDSS_MDP_LUT_CLK 120
138#define MDSS_PCLK0_CLK 121
139#define MDSS_PCLK1_CLK 122
140#define MDSS_VSYNC_CLK 123
141#define MMSS_RBCPR_AHB_CLK 124
142#define MMSS_RBCPR_CLK 125
143#define MMSS_SPDM_AHB_CLK 126
144#define MMSS_SPDM_AXI_CLK 127
145#define MMSS_SPDM_CSI0_CLK 128
146#define MMSS_SPDM_GFX3D_CLK 129
147#define MMSS_SPDM_JPEG0_CLK 130
148#define MMSS_SPDM_JPEG1_CLK 131
149#define MMSS_SPDM_JPEG2_CLK 132
150#define MMSS_SPDM_MDP_CLK 133
151#define MMSS_SPDM_PCLK0_CLK 134
152#define MMSS_SPDM_PCLK1_CLK 135
153#define MMSS_SPDM_VCODEC0_CLK 136
154#define MMSS_SPDM_VFE0_CLK 137
155#define MMSS_SPDM_VFE1_CLK 138
156#define MMSS_SPDM_RM_AXI_CLK 139
157#define MMSS_SPDM_RM_OCMEMNOC_CLK 140
158#define MMSS_MISC_AHB_CLK 141
159#define MMSS_MMSSNOC_AHB_CLK 142
160#define MMSS_MMSSNOC_BTO_AHB_CLK 143
161#define MMSS_MMSSNOC_AXI_CLK 144
162#define MMSS_S0_AXI_CLK 145
163#define OCMEMCX_AHB_CLK 146
164#define OCMEMCX_OCMEMNOC_CLK 147
165#define OXILI_OCMEMGX_CLK 148
166#define OXILI_GFX3D_CLK 149
167#define OXILI_RBBMTIMER_CLK 150
168#define OXILICX_AHB_CLK 151
169#define VENUS0_AHB_CLK 152
170#define VENUS0_AXI_CLK 153
171#define VENUS0_CORE0_VCODEC_CLK 154
172#define VENUS0_CORE1_VCODEC_CLK 155
173#define VENUS0_OCMEMNOC_CLK 156
174#define VENUS0_VCODEC0_CLK 157
175#define VPU_AHB_CLK 158
176#define VPU_AXI_CLK 159
177#define VPU_BUS_CLK 160
178#define VPU_CXO_CLK 161
179#define VPU_MAPLE_CLK 162
180#define VPU_SLEEP_CLK 163
181#define VPU_VDP_CLK 164
182
183#endif
diff --git a/include/dt-bindings/clock/qcom,mmcc-msm8960.h b/include/dt-bindings/clock/qcom,mmcc-msm8960.h
index 5868ef14a777..85041b28f97f 100644
--- a/include/dt-bindings/clock/qcom,mmcc-msm8960.h
+++ b/include/dt-bindings/clock/qcom,mmcc-msm8960.h
@@ -133,5 +133,13 @@
133#define CSIPHY0_TIMER_CLK 116 133#define CSIPHY0_TIMER_CLK 116
134#define PLL1 117 134#define PLL1 117
135#define PLL2 118 135#define PLL2 118
136#define RGB_TV_CLK 119
137#define NPL_TV_CLK 120
138#define VCAP_AHB_CLK 121
139#define VCAP_AXI_CLK 122
140#define VCAP_SRC 123
141#define VCAP_CLK 124
142#define VCAP_NPL_CLK 125
143#define PLL15 126
136 144
137#endif 145#endif
diff --git a/include/dt-bindings/clock/rk3066a-cru.h b/include/dt-bindings/clock/rk3066a-cru.h
new file mode 100644
index 000000000000..bc1ed1dbd855
--- /dev/null
+++ b/include/dt-bindings/clock/rk3066a-cru.h
@@ -0,0 +1,35 @@
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <dt-bindings/clock/rk3188-cru-common.h>
17
18/* soft-reset indices */
19#define SRST_SRST1 0
20#define SRST_SRST2 1
21
22#define SRST_L2MEM 18
23#define SRST_I2S0 23
24#define SRST_I2S1 24
25#define SRST_I2S2 25
26#define SRST_TIMER2 29
27
28#define SRST_GPIO4 36
29#define SRST_GPIO6 38
30
31#define SRST_TSADC 92
32
33#define SRST_HDMI 96
34#define SRST_HDMI_APB 97
35#define SRST_CIF1 111
diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h
new file mode 100644
index 000000000000..750ee60e75fb
--- /dev/null
+++ b/include/dt-bindings/clock/rk3188-cru-common.h
@@ -0,0 +1,249 @@
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16/* core clocks from */
17#define PLL_APLL 1
18#define PLL_DPLL 2
19#define PLL_CPLL 3
20#define PLL_GPLL 4
21#define CORE_PERI 5
22#define CORE_L2C 6
23
24/* sclk gates (special clocks) */
25#define SCLK_UART0 64
26#define SCLK_UART1 65
27#define SCLK_UART2 66
28#define SCLK_UART3 67
29#define SCLK_MAC 68
30#define SCLK_SPI0 69
31#define SCLK_SPI1 70
32#define SCLK_SARADC 71
33#define SCLK_SDMMC 72
34#define SCLK_SDIO 73
35#define SCLK_EMMC 74
36#define SCLK_I2S0 75
37#define SCLK_I2S1 76
38#define SCLK_I2S2 77
39#define SCLK_SPDIF 78
40#define SCLK_CIF0 79
41#define SCLK_CIF1 80
42#define SCLK_OTGPHY0 81
43#define SCLK_OTGPHY1 82
44#define SCLK_HSADC 83
45#define SCLK_TIMER0 84
46#define SCLK_TIMER1 85
47#define SCLK_TIMER2 86
48#define SCLK_TIMER3 87
49#define SCLK_TIMER4 88
50#define SCLK_TIMER5 89
51#define SCLK_TIMER6 90
52#define SCLK_JTAG 91
53#define SCLK_SMC 92
54
55#define DCLK_LCDC0 190
56#define DCLK_LCDC1 191
57
58/* aclk gates */
59#define ACLK_DMA1 192
60#define ACLK_DMA2 193
61#define ACLK_GPS 194
62#define ACLK_LCDC0 195
63#define ACLK_LCDC1 196
64#define ACLK_GPU 197
65#define ACLK_SMC 198
66#define ACLK_CIF 199
67#define ACLK_IPP 200
68#define ACLK_RGA 201
69#define ACLK_CIF0 202
70
71/* pclk gates */
72#define PCLK_GRF 320
73#define PCLK_PMU 321
74#define PCLK_TIMER0 322
75#define PCLK_TIMER1 323
76#define PCLK_TIMER2 324
77#define PCLK_TIMER3 325
78#define PCLK_PWM01 326
79#define PCLK_PWM23 327
80#define PCLK_SPI0 328
81#define PCLK_SPI1 329
82#define PCLK_SARADC 330
83#define PCLK_WDT 331
84#define PCLK_UART0 332
85#define PCLK_UART1 333
86#define PCLK_UART2 334
87#define PCLK_UART3 335
88#define PCLK_I2C0 336
89#define PCLK_I2C1 337
90#define PCLK_I2C2 338
91#define PCLK_I2C3 339
92#define PCLK_I2C4 340
93#define PCLK_GPIO0 341
94#define PCLK_GPIO1 342
95#define PCLK_GPIO2 343
96#define PCLK_GPIO3 344
97#define PCLK_GPIO4 345
98#define PCLK_GPIO6 346
99#define PCLK_EFUSE 347
100#define PCLK_TZPC 348
101#define PCLK_TSADC 349
102
103/* hclk gates */
104#define HCLK_SDMMC 448
105#define HCLK_SDIO 449
106#define HCLK_EMMC 450
107#define HCLK_OTG0 451
108#define HCLK_EMAC 452
109#define HCLK_SPDIF 453
110#define HCLK_I2S0 454
111#define HCLK_I2S1 455
112#define HCLK_I2S2 456
113#define HCLK_OTG1 457
114#define HCLK_HSIC 458
115#define HCLK_HSADC 459
116#define HCLK_PIDF 460
117#define HCLK_LCDC0 461
118#define HCLK_LCDC1 462
119#define HCLK_ROM 463
120#define HCLK_CIF0 464
121#define HCLK_IPP 465
122#define HCLK_RGA 466
123#define HCLK_NANDC0 467
124
125#define CLK_NR_CLKS (HCLK_NANDC0 + 1)
126
127/* soft-reset indices */
128#define SRST_MCORE 2
129#define SRST_CORE0 3
130#define SRST_CORE1 4
131#define SRST_MCORE_DBG 7
132#define SRST_CORE0_DBG 8
133#define SRST_CORE1_DBG 9
134#define SRST_CORE0_WDT 12
135#define SRST_CORE1_WDT 13
136#define SRST_STRC_SYS 14
137#define SRST_L2C 15
138
139#define SRST_CPU_AHB 17
140#define SRST_AHB2APB 19
141#define SRST_DMA1 20
142#define SRST_INTMEM 21
143#define SRST_ROM 22
144#define SRST_SPDIF 26
145#define SRST_TIMER0 27
146#define SRST_TIMER1 28
147#define SRST_EFUSE 30
148
149#define SRST_GPIO0 32
150#define SRST_GPIO1 33
151#define SRST_GPIO2 34
152#define SRST_GPIO3 35
153
154#define SRST_UART0 39
155#define SRST_UART1 40
156#define SRST_UART2 41
157#define SRST_UART3 42
158#define SRST_I2C0 43
159#define SRST_I2C1 44
160#define SRST_I2C2 45
161#define SRST_I2C3 46
162#define SRST_I2C4 47
163
164#define SRST_PWM0 48
165#define SRST_PWM1 49
166#define SRST_DAP_PO 50
167#define SRST_DAP 51
168#define SRST_DAP_SYS 52
169#define SRST_TPIU_ATB 53
170#define SRST_PMU_APB 54
171#define SRST_GRF 55
172#define SRST_PMU 56
173#define SRST_PERI_AXI 57
174#define SRST_PERI_AHB 58
175#define SRST_PERI_APB 59
176#define SRST_PERI_NIU 60
177#define SRST_CPU_PERI 61
178#define SRST_EMEM_PERI 62
179#define SRST_USB_PERI 63
180
181#define SRST_DMA2 64
182#define SRST_SMC 65
183#define SRST_MAC 66
184#define SRST_NANC0 68
185#define SRST_USBOTG0 69
186#define SRST_USBPHY0 70
187#define SRST_OTGC0 71
188#define SRST_USBOTG1 72
189#define SRST_USBPHY1 73
190#define SRST_OTGC1 74
191#define SRST_HSADC 76
192#define SRST_PIDFILTER 77
193#define SRST_DDR_MSCH 79
194
195#define SRST_TZPC 80
196#define SRST_SDMMC 81
197#define SRST_SDIO 82
198#define SRST_EMMC 83
199#define SRST_SPI0 84
200#define SRST_SPI1 85
201#define SRST_WDT 86
202#define SRST_SARADC 87
203#define SRST_DDRPHY 88
204#define SRST_DDRPHY_APB 89
205#define SRST_DDRCTL 90
206#define SRST_DDRCTL_APB 91
207#define SRST_DDRPUB 93
208
209#define SRST_VIO0_AXI 98
210#define SRST_VIO0_AHB 99
211#define SRST_LCDC0_AXI 100
212#define SRST_LCDC0_AHB 101
213#define SRST_LCDC0_DCLK 102
214#define SRST_LCDC1_AXI 103
215#define SRST_LCDC1_AHB 104
216#define SRST_LCDC1_DCLK 105
217#define SRST_IPP_AXI 106
218#define SRST_IPP_AHB 107
219#define SRST_RGA_AXI 108
220#define SRST_RGA_AHB 109
221#define SRST_CIF0 110
222
223#define SRST_VCODEC_AXI 112
224#define SRST_VCODEC_AHB 113
225#define SRST_VIO1_AXI 114
226#define SRST_VCODEC_CPU 115
227#define SRST_VCODEC_NIU 116
228#define SRST_GPU 120
229#define SRST_GPU_NIU 122
230#define SRST_TFUN_ATB 125
231#define SRST_TFUN_APB 126
232#define SRST_CTI4_APB 127
233
234#define SRST_TPIU_APB 128
235#define SRST_TRACE 129
236#define SRST_CORE_DBG 130
237#define SRST_DBG_APB 131
238#define SRST_CTI0 132
239#define SRST_CTI0_APB 133
240#define SRST_CTI1 134
241#define SRST_CTI1_APB 135
242#define SRST_PTM_CORE0 136
243#define SRST_PTM_CORE1 137
244#define SRST_PTM0 138
245#define SRST_PTM0_ATB 139
246#define SRST_PTM1 140
247#define SRST_PTM1_ATB 141
248#define SRST_CTM 142
249#define SRST_TS 143
diff --git a/include/dt-bindings/clock/rk3188-cru.h b/include/dt-bindings/clock/rk3188-cru.h
new file mode 100644
index 000000000000..9fac8edd3f9d
--- /dev/null
+++ b/include/dt-bindings/clock/rk3188-cru.h
@@ -0,0 +1,51 @@
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <dt-bindings/clock/rk3188-cru-common.h>
17
18/* soft-reset indices */
19#define SRST_PTM_CORE2 0
20#define SRST_PTM_CORE3 1
21#define SRST_CORE2 5
22#define SRST_CORE3 6
23#define SRST_CORE2_DBG 10
24#define SRST_CORE3_DBG 11
25
26#define SRST_TIMER2 16
27#define SRST_TIMER4 23
28#define SRST_I2S0 24
29#define SRST_TIMER5 25
30#define SRST_TIMER3 29
31#define SRST_TIMER6 31
32
33#define SRST_PTM3 36
34#define SRST_PTM3_ATB 37
35
36#define SRST_GPS 67
37#define SRST_HSICPHY 75
38#define SRST_TIMER 78
39
40#define SRST_PTM2 92
41#define SRST_CORE2_WDT 94
42#define SRST_CORE3_WDT 95
43
44#define SRST_PTM2_ATB 111
45
46#define SRST_HSIC 117
47#define SRST_CTI2 118
48#define SRST_CTI2_APB 119
49#define SRST_GPU_BRIDGE 121
50#define SRST_CTI3 123
51#define SRST_CTI3_APB 124
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h
new file mode 100644
index 000000000000..ebcb460ea4ad
--- /dev/null
+++ b/include/dt-bindings/clock/rk3288-cru.h
@@ -0,0 +1,278 @@
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16/* core clocks */
17#define PLL_APLL 1
18#define PLL_DPLL 2
19#define PLL_CPLL 3
20#define PLL_GPLL 4
21#define PLL_NPLL 5
22
23/* sclk gates (special clocks) */
24#define SCLK_GPU 64
25#define SCLK_SPI0 65
26#define SCLK_SPI1 66
27#define SCLK_SPI2 67
28#define SCLK_SDMMC 68
29#define SCLK_SDIO0 69
30#define SCLK_SDIO1 70
31#define SCLK_EMMC 71
32#define SCLK_TSADC 72
33#define SCLK_SARADC 73
34#define SCLK_PS2C 74
35#define SCLK_NANDC0 75
36#define SCLK_NANDC1 76
37#define SCLK_UART0 77
38#define SCLK_UART1 78
39#define SCLK_UART2 79
40#define SCLK_UART3 80
41#define SCLK_UART4 81
42#define SCLK_I2S0 82
43#define SCLK_SPDIF 83
44#define SCLK_SPDIF8CH 84
45#define SCLK_TIMER0 85
46#define SCLK_TIMER1 86
47#define SCLK_TIMER2 87
48#define SCLK_TIMER3 88
49#define SCLK_TIMER4 89
50#define SCLK_TIMER5 90
51#define SCLK_TIMER6 91
52#define SCLK_HSADC 92
53#define SCLK_OTGPHY0 93
54#define SCLK_OTGPHY1 94
55#define SCLK_OTGPHY2 95
56#define SCLK_OTG_ADP 96
57#define SCLK_HSICPHY480M 97
58#define SCLK_HSICPHY12M 98
59#define SCLK_MACREF 99
60#define SCLK_LCDC_PWM0 100
61#define SCLK_LCDC_PWM1 101
62#define SCLK_MAC_RX 102
63#define SCLK_MAC_TX 103
64
65#define DCLK_VOP0 190
66#define DCLK_VOP1 191
67
68/* aclk gates */
69#define ACLK_GPU 192
70#define ACLK_DMAC1 193
71#define ACLK_DMAC2 194
72#define ACLK_MMU 195
73#define ACLK_GMAC 196
74#define ACLK_VOP0 197
75#define ACLK_VOP1 198
76#define ACLK_CRYPTO 199
77#define ACLK_RGA 200
78
79/* pclk gates */
80#define PCLK_GPIO0 320
81#define PCLK_GPIO1 321
82#define PCLK_GPIO2 322
83#define PCLK_GPIO3 323
84#define PCLK_GPIO4 324
85#define PCLK_GPIO5 325
86#define PCLK_GPIO6 326
87#define PCLK_GPIO7 327
88#define PCLK_GPIO8 328
89#define PCLK_GRF 329
90#define PCLK_SGRF 330
91#define PCLK_PMU 331
92#define PCLK_I2C0 332
93#define PCLK_I2C1 333
94#define PCLK_I2C2 334
95#define PCLK_I2C3 335
96#define PCLK_I2C4 336
97#define PCLK_I2C5 337
98#define PCLK_SPI0 338
99#define PCLK_SPI1 339
100#define PCLK_SPI2 340
101#define PCLK_UART0 341
102#define PCLK_UART1 342
103#define PCLK_UART2 343
104#define PCLK_UART3 344
105#define PCLK_UART4 345
106#define PCLK_TSADC 346
107#define PCLK_SARADC 347
108#define PCLK_SIM 348
109#define PCLK_GMAC 349
110#define PCLK_PWM 350
111#define PCLK_RKPWM 351
112#define PCLK_PS2C 352
113#define PCLK_TIMER 353
114#define PCLK_TZPC 354
115
116/* hclk gates */
117#define HCLK_GPS 448
118#define HCLK_OTG0 449
119#define HCLK_USBHOST0 450
120#define HCLK_USBHOST1 451
121#define HCLK_HSIC 452
122#define HCLK_NANDC0 453
123#define HCLK_NANDC1 454
124#define HCLK_TSP 455
125#define HCLK_SDMMC 456
126#define HCLK_SDIO0 457
127#define HCLK_SDIO1 458
128#define HCLK_EMMC 459
129#define HCLK_HSADC 460
130#define HCLK_CRYPTO 461
131#define HCLK_I2S0 462
132#define HCLK_SPDIF 463
133#define HCLK_SPDIF8CH 464
134#define HCLK_VOP0 465
135#define HCLK_VOP1 466
136#define HCLK_ROM 467
137#define HCLK_IEP 468
138#define HCLK_ISP 469
139#define HCLK_RGA 470
140
141#define CLK_NR_CLKS (HCLK_RGA + 1)
142
143/* soft-reset indices */
144#define SRST_CORE0 0
145#define SRST_CORE1 1
146#define SRST_CORE2 2
147#define SRST_CORE3 3
148#define SRST_CORE0_PO 4
149#define SRST_CORE1_PO 5
150#define SRST_CORE2_PO 6
151#define SRST_CORE3_PO 7
152#define SRST_PDCORE_STRSYS 8
153#define SRST_PDBUS_STRSYS 9
154#define SRST_L2C 10
155#define SRST_TOPDBG 11
156#define SRST_CORE0_DBG 12
157#define SRST_CORE1_DBG 13
158#define SRST_CORE2_DBG 14
159#define SRST_CORE3_DBG 15
160
161#define SRST_PDBUG_AHB_ARBITOR 16
162#define SRST_EFUSE256 17
163#define SRST_DMAC1 18
164#define SRST_INTMEM 19
165#define SRST_ROM 20
166#define SRST_SPDIF8CH 21
167#define SRST_TIMER 22
168#define SRST_I2S0 23
169#define SRST_SPDIF 24
170#define SRST_TIMER0 25
171#define SRST_TIMER1 26
172#define SRST_TIMER2 27
173#define SRST_TIMER3 28
174#define SRST_TIMER4 29
175#define SRST_TIMER5 30
176#define SRST_EFUSE 31
177
178#define SRST_GPIO0 32
179#define SRST_GPIO1 33
180#define SRST_GPIO2 34
181#define SRST_GPIO3 35
182#define SRST_GPIO4 36
183#define SRST_GPIO5 37
184#define SRST_GPIO6 38
185#define SRST_GPIO7 39
186#define SRST_GPIO8 40
187#define SRST_I2C0 42
188#define SRST_I2C1 43
189#define SRST_I2C2 44
190#define SRST_I2C3 45
191#define SRST_I2C4 46
192#define SRST_I2C5 47
193
194#define SRST_DWPWM 48
195#define SRST_MMC_PERI 49
196#define SRST_PERIPH_MMU 50
197#define SRST_DAP 51
198#define SRST_DAP_SYS 52
199#define SRST_TPIU 53
200#define SRST_PMU_APB 54
201#define SRST_GRF 55
202#define SRST_PMU 56
203#define SRST_PERIPH_AXI 57
204#define SRST_PERIPH_AHB 58
205#define SRST_PERIPH_APB 59
206#define SRST_PERIPH_NIU 60
207#define SRST_PDPERI_AHB_ARBI 61
208#define SRST_EMEM 62
209#define SRST_USB_PERI 63
210
211#define SRST_DMAC2 64
212#define SRST_MAC 66
213#define SRST_GPS 67
214#define SRST_RKPWM 69
215#define SRST_CCP 71
216#define SRST_USBHOST0 72
217#define SRST_HSIC 73
218#define SRST_HSIC_AUX 74
219#define SRST_HSIC_PHY 75
220#define SRST_HSADC 76
221#define SRST_NANDC0 77
222#define SRST_NANDC1 78
223
224#define SRST_TZPC 80
225#define SRST_SPI0 83
226#define SRST_SPI1 84
227#define SRST_SPI2 85
228#define SRST_SARADC 87
229#define SRST_PDALIVE_NIU 88
230#define SRST_PDPMU_INTMEM 89
231#define SRST_PDPMU_NIU 90
232#define SRST_SGRF 91
233
234#define SRST_VIO_ARBI 96
235#define SRST_RGA_NIU 97
236#define SRST_VIO0_NIU_AXI 98
237#define SRST_VIO_NIU_AHB 99
238#define SRST_LCDC0_AXI 100
239#define SRST_LCDC0_AHB 101
240#define SRST_LCDC0_DCLK 102
241#define SRST_VIO1_NIU_AXI 103
242#define SRST_VIP 104
243#define SRST_RGA_CORE 105
244#define SRST_IEP_AXI 106
245#define SRST_IEP_AHB 107
246#define SRST_RGA_AXI 108
247#define SRST_RGA_AHB 109
248#define SRST_ISP 110
249#define SRST_EDP 111
250
251#define SRST_VCODEC_AXI 112
252#define SRST_VCODEC_AHB 113
253#define SRST_VIO_H2P 114
254#define SRST_MIPIDSI0 115
255#define SRST_MIPIDSI1 116
256#define SRST_MIPICSI 117
257#define SRST_LVDS_PHY 118
258#define SRST_LVDS_CON 119
259#define SRST_GPU 120
260#define SRST_HDMI 121
261#define SRST_CORE_PVTM 124
262#define SRST_GPU_PVTM 125
263
264#define SRST_MMC0 128
265#define SRST_SDIO0 129
266#define SRST_SDIO1 130
267#define SRST_EMMC 131
268#define SRST_USBOTG_AHB 132
269#define SRST_USBOTG_PHY 133
270#define SRST_USBOTG_CON 134
271#define SRST_USBHOST0_AHB 135
272#define SRST_USBHOST0_PHY 136
273#define SRST_USBHOST0_CON 137
274#define SRST_USBHOST1_AHB 138
275#define SRST_USBHOST1_PHY 139
276#define SRST_USBHOST1_CON 140
277#define SRST_USB_ADP 141
278#define SRST_ACC_EFUSE 142
diff --git a/include/dt-bindings/mfd/palmas.h b/include/dt-bindings/mfd/palmas.h
new file mode 100644
index 000000000000..2c8ac4841385
--- /dev/null
+++ b/include/dt-bindings/mfd/palmas.h
@@ -0,0 +1,18 @@
1/*
2 * This header provides macros for Palmas device bindings.
3 *
4 * Copyright (c) 2013, NVIDIA Corporation.
5 *
6 * Author: Laxman Dewangan <ldewangan@nvidia.com>
7 *
8 */
9
10#ifndef __DT_BINDINGS_PALMAS_H__
11#define __DT_BINDINGS_PALMAS_H
12
13/* External control pins */
14#define PALMAS_EXT_CONTROL_PIN_ENABLE1 1
15#define PALMAS_EXT_CONTROL_PIN_ENABLE2 2
16#define PALMAS_EXT_CONTROL_PIN_NSLEEP 3
17
18#endif /* __DT_BINDINGS_PALMAS_H */
diff --git a/include/dt-bindings/reset/qcom,gcc-apq8084.h b/include/dt-bindings/reset/qcom,gcc-apq8084.h
new file mode 100644
index 000000000000..527caaf48e3d
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,gcc-apq8084.h
@@ -0,0 +1,109 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_RESET_APQ_GCC_8084_H
15#define _DT_BINDINGS_RESET_APQ_GCC_8084_H
16
17#define GCC_SYSTEM_NOC_BCR 0
18#define GCC_CONFIG_NOC_BCR 1
19#define GCC_PERIPH_NOC_BCR 2
20#define GCC_IMEM_BCR 3
21#define GCC_MMSS_BCR 4
22#define GCC_QDSS_BCR 5
23#define GCC_USB_30_BCR 6
24#define GCC_USB3_PHY_BCR 7
25#define GCC_USB_HS_HSIC_BCR 8
26#define GCC_USB_HS_BCR 9
27#define GCC_USB2A_PHY_BCR 10
28#define GCC_USB2B_PHY_BCR 11
29#define GCC_SDCC1_BCR 12
30#define GCC_SDCC2_BCR 13
31#define GCC_SDCC3_BCR 14
32#define GCC_SDCC4_BCR 15
33#define GCC_BLSP1_BCR 16
34#define GCC_BLSP1_QUP1_BCR 17
35#define GCC_BLSP1_UART1_BCR 18
36#define GCC_BLSP1_QUP2_BCR 19
37#define GCC_BLSP1_UART2_BCR 20
38#define GCC_BLSP1_QUP3_BCR 21
39#define GCC_BLSP1_UART3_BCR 22
40#define GCC_BLSP1_QUP4_BCR 23
41#define GCC_BLSP1_UART4_BCR 24
42#define GCC_BLSP1_QUP5_BCR 25
43#define GCC_BLSP1_UART5_BCR 26
44#define GCC_BLSP1_QUP6_BCR 27
45#define GCC_BLSP1_UART6_BCR 28
46#define GCC_BLSP2_BCR 29
47#define GCC_BLSP2_QUP1_BCR 30
48#define GCC_BLSP2_UART1_BCR 31
49#define GCC_BLSP2_QUP2_BCR 32
50#define GCC_BLSP2_UART2_BCR 33
51#define GCC_BLSP2_QUP3_BCR 34
52#define GCC_BLSP2_UART3_BCR 35
53#define GCC_BLSP2_QUP4_BCR 36
54#define GCC_BLSP2_UART4_BCR 37
55#define GCC_BLSP2_QUP5_BCR 38
56#define GCC_BLSP2_UART5_BCR 39
57#define GCC_BLSP2_QUP6_BCR 40
58#define GCC_BLSP2_UART6_BCR 41
59#define GCC_PDM_BCR 42
60#define GCC_PRNG_BCR 43
61#define GCC_BAM_DMA_BCR 44
62#define GCC_TSIF_BCR 45
63#define GCC_TCSR_BCR 46
64#define GCC_BOOT_ROM_BCR 47
65#define GCC_MSG_RAM_BCR 48
66#define GCC_TLMM_BCR 49
67#define GCC_MPM_BCR 50
68#define GCC_MPM_AHB_RESET 51
69#define GCC_MPM_NON_AHB_RESET 52
70#define GCC_SEC_CTRL_BCR 53
71#define GCC_SPMI_BCR 54
72#define GCC_SPDM_BCR 55
73#define GCC_CE1_BCR 56
74#define GCC_CE2_BCR 57
75#define GCC_BIMC_BCR 58
76#define GCC_SNOC_BUS_TIMEOUT0_BCR 59
77#define GCC_SNOC_BUS_TIMEOUT2_BCR 60
78#define GCC_PNOC_BUS_TIMEOUT0_BCR 61
79#define GCC_PNOC_BUS_TIMEOUT1_BCR 62
80#define GCC_PNOC_BUS_TIMEOUT2_BCR 63
81#define GCC_PNOC_BUS_TIMEOUT3_BCR 64
82#define GCC_PNOC_BUS_TIMEOUT4_BCR 65
83#define GCC_CNOC_BUS_TIMEOUT0_BCR 66
84#define GCC_CNOC_BUS_TIMEOUT1_BCR 67
85#define GCC_CNOC_BUS_TIMEOUT2_BCR 68
86#define GCC_CNOC_BUS_TIMEOUT3_BCR 69
87#define GCC_CNOC_BUS_TIMEOUT4_BCR 70
88#define GCC_CNOC_BUS_TIMEOUT5_BCR 71
89#define GCC_CNOC_BUS_TIMEOUT6_BCR 72
90#define GCC_DEHR_BCR 73
91#define GCC_RBCPR_BCR 74
92#define GCC_MSS_RESTART 75
93#define GCC_LPASS_RESTART 76
94#define GCC_WCSS_RESTART 77
95#define GCC_VENUS_RESTART 78
96#define GCC_COPSS_SMMU_BCR 79
97#define GCC_SPSS_BCR 80
98#define GCC_PCIE_0_BCR 81
99#define GCC_PCIE_0_PHY_BCR 82
100#define GCC_PCIE_1_BCR 83
101#define GCC_PCIE_1_PHY_BCR 84
102#define GCC_USB_30_SEC_BCR 85
103#define GCC_USB3_SEC_PHY_BCR 86
104#define GCC_SATA_BCR 87
105#define GCC_CE3_BCR 88
106#define GCC_UFS_BCR 89
107#define GCC_USB30_PHY_COM_BCR 90
108
109#endif
diff --git a/include/dt-bindings/reset/qcom,gcc-ipq806x.h b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
new file mode 100644
index 000000000000..0ad5ef930b5d
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
@@ -0,0 +1,132 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_RESET_IPQ_806X_H
15#define _DT_BINDINGS_RESET_IPQ_806X_H
16
17#define QDSS_STM_RESET 0
18#define AFAB_SMPSS_S_RESET 1
19#define AFAB_SMPSS_M1_RESET 2
20#define AFAB_SMPSS_M0_RESET 3
21#define AFAB_EBI1_CH0_RESET 4
22#define AFAB_EBI1_CH1_RESET 5
23#define SFAB_ADM0_M0_RESET 6
24#define SFAB_ADM0_M1_RESET 7
25#define SFAB_ADM0_M2_RESET 8
26#define ADM0_C2_RESET 9
27#define ADM0_C1_RESET 10
28#define ADM0_C0_RESET 11
29#define ADM0_PBUS_RESET 12
30#define ADM0_RESET 13
31#define QDSS_CLKS_SW_RESET 14
32#define QDSS_POR_RESET 15
33#define QDSS_TSCTR_RESET 16
34#define QDSS_HRESET_RESET 17
35#define QDSS_AXI_RESET 18
36#define QDSS_DBG_RESET 19
37#define SFAB_PCIE_M_RESET 20
38#define SFAB_PCIE_S_RESET 21
39#define PCIE_EXT_RESET 22
40#define PCIE_PHY_RESET 23
41#define PCIE_PCI_RESET 24
42#define PCIE_POR_RESET 25
43#define PCIE_HCLK_RESET 26
44#define PCIE_ACLK_RESET 27
45#define SFAB_LPASS_RESET 28
46#define SFAB_AFAB_M_RESET 29
47#define AFAB_SFAB_M0_RESET 30
48#define AFAB_SFAB_M1_RESET 31
49#define SFAB_SATA_S_RESET 32
50#define SFAB_DFAB_M_RESET 33
51#define DFAB_SFAB_M_RESET 34
52#define DFAB_SWAY0_RESET 35
53#define DFAB_SWAY1_RESET 36
54#define DFAB_ARB0_RESET 37
55#define DFAB_ARB1_RESET 38
56#define PPSS_PROC_RESET 39
57#define PPSS_RESET 40
58#define DMA_BAM_RESET 41
59#define SPS_TIC_H_RESET 42
60#define SFAB_CFPB_M_RESET 43
61#define SFAB_CFPB_S_RESET 44
62#define TSIF_H_RESET 45
63#define CE1_H_RESET 46
64#define CE1_CORE_RESET 47
65#define CE1_SLEEP_RESET 48
66#define CE2_H_RESET 49
67#define CE2_CORE_RESET 50
68#define SFAB_SFPB_M_RESET 51
69#define SFAB_SFPB_S_RESET 52
70#define RPM_PROC_RESET 53
71#define PMIC_SSBI2_RESET 54
72#define SDC1_RESET 55
73#define SDC2_RESET 56
74#define SDC3_RESET 57
75#define SDC4_RESET 58
76#define USB_HS1_RESET 59
77#define USB_HSIC_RESET 60
78#define USB_FS1_XCVR_RESET 61
79#define USB_FS1_RESET 62
80#define GSBI1_RESET 63
81#define GSBI2_RESET 64
82#define GSBI3_RESET 65
83#define GSBI4_RESET 66
84#define GSBI5_RESET 67
85#define GSBI6_RESET 68
86#define GSBI7_RESET 69
87#define SPDM_RESET 70
88#define SEC_CTRL_RESET 71
89#define TLMM_H_RESET 72
90#define SFAB_SATA_M_RESET 73
91#define SATA_RESET 74
92#define TSSC_RESET 75
93#define PDM_RESET 76
94#define MPM_H_RESET 77
95#define MPM_RESET 78
96#define SFAB_SMPSS_S_RESET 79
97#define PRNG_RESET 80
98#define SFAB_CE3_M_RESET 81
99#define SFAB_CE3_S_RESET 82
100#define CE3_SLEEP_RESET 83
101#define PCIE_1_M_RESET 84
102#define PCIE_1_S_RESET 85
103#define PCIE_1_EXT_RESET 86
104#define PCIE_1_PHY_RESET 87
105#define PCIE_1_PCI_RESET 88
106#define PCIE_1_POR_RESET 89
107#define PCIE_1_HCLK_RESET 90
108#define PCIE_1_ACLK_RESET 91
109#define PCIE_2_M_RESET 92
110#define PCIE_2_S_RESET 93
111#define PCIE_2_EXT_RESET 94
112#define PCIE_2_PHY_RESET 95
113#define PCIE_2_PCI_RESET 96
114#define PCIE_2_POR_RESET 97
115#define PCIE_2_HCLK_RESET 98
116#define PCIE_2_ACLK_RESET 99
117#define SFAB_USB30_S_RESET 100
118#define SFAB_USB30_M_RESET 101
119#define USB30_0_PORT2_HS_PHY_RESET 102
120#define USB30_0_MASTER_RESET 103
121#define USB30_0_SLEEP_RESET 104
122#define USB30_0_UTMI_PHY_RESET 105
123#define USB30_0_POWERON_RESET 106
124#define USB30_0_PHY_RESET 107
125#define USB30_1_MASTER_RESET 108
126#define USB30_1_SLEEP_RESET 109
127#define USB30_1_UTMI_PHY_RESET 110
128#define USB30_1_POWERON_RESET 111
129#define USB30_1_PHY_RESET 112
130#define NSSFB0_RESET 113
131#define NSSFB1_RESET 114
132#endif
diff --git a/include/dt-bindings/reset/qcom,gcc-msm8960.h b/include/dt-bindings/reset/qcom,gcc-msm8960.h
index 07edd0e65eed..47c8686955da 100644
--- a/include/dt-bindings/reset/qcom,gcc-msm8960.h
+++ b/include/dt-bindings/reset/qcom,gcc-msm8960.h
@@ -114,5 +114,21 @@
114#define SFAB_SMPSS_S_RESET 97 114#define SFAB_SMPSS_S_RESET 97
115#define PRNG_RESET 98 115#define PRNG_RESET 98
116#define RIVA_RESET 99 116#define RIVA_RESET 99
117#define USB_HS3_RESET 100
118#define USB_HS4_RESET 101
119#define CE3_RESET 102
120#define PCIE_EXT_PCI_RESET 103
121#define PCIE_PHY_RESET 104
122#define PCIE_PCI_RESET 105
123#define PCIE_POR_RESET 106
124#define PCIE_HCLK_RESET 107
125#define PCIE_ACLK_RESET 108
126#define CE3_H_RESET 109
127#define SFAB_CE3_M_RESET 110
128#define SFAB_CE3_S_RESET 111
129#define SATA_RESET 112
130#define CE3_SLEEP_RESET 113
131#define GSS_SLP_RESET 114
132#define GSS_RESET 115
117 133
118#endif 134#endif
diff --git a/include/dt-bindings/reset/qcom,mmcc-apq8084.h b/include/dt-bindings/reset/qcom,mmcc-apq8084.h
new file mode 100644
index 000000000000..c1671396531d
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,mmcc-apq8084.h
@@ -0,0 +1,64 @@
1/*
2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_RESET_APQ_MMCC_8084_H
15#define _DT_BINDINGS_RESET_APQ_MMCC_8084_H
16
17#define MMSS_SPDM_RESET 0
18#define MMSS_SPDM_RM_RESET 1
19#define VENUS0_RESET 2
20#define VPU_RESET 3
21#define MDSS_RESET 4
22#define AVSYNC_RESET 5
23#define CAMSS_PHY0_RESET 6
24#define CAMSS_PHY1_RESET 7
25#define CAMSS_PHY2_RESET 8
26#define CAMSS_CSI0_RESET 9
27#define CAMSS_CSI0PHY_RESET 10
28#define CAMSS_CSI0RDI_RESET 11
29#define CAMSS_CSI0PIX_RESET 12
30#define CAMSS_CSI1_RESET 13
31#define CAMSS_CSI1PHY_RESET 14
32#define CAMSS_CSI1RDI_RESET 15
33#define CAMSS_CSI1PIX_RESET 16
34#define CAMSS_CSI2_RESET 17
35#define CAMSS_CSI2PHY_RESET 18
36#define CAMSS_CSI2RDI_RESET 19
37#define CAMSS_CSI2PIX_RESET 20
38#define CAMSS_CSI3_RESET 21
39#define CAMSS_CSI3PHY_RESET 22
40#define CAMSS_CSI3RDI_RESET 23
41#define CAMSS_CSI3PIX_RESET 24
42#define CAMSS_ISPIF_RESET 25
43#define CAMSS_CCI_RESET 26
44#define CAMSS_MCLK0_RESET 27
45#define CAMSS_MCLK1_RESET 28
46#define CAMSS_MCLK2_RESET 29
47#define CAMSS_MCLK3_RESET 30
48#define CAMSS_GP0_RESET 31
49#define CAMSS_GP1_RESET 32
50#define CAMSS_TOP_RESET 33
51#define CAMSS_AHB_RESET 34
52#define CAMSS_MICRO_RESET 35
53#define CAMSS_JPEG_RESET 36
54#define CAMSS_VFE_RESET 37
55#define CAMSS_CSI_VFE0_RESET 38
56#define CAMSS_CSI_VFE1_RESET 39
57#define OXILI_RESET 40
58#define OXILICX_RESET 41
59#define OCMEMCX_RESET 42
60#define MMSS_RBCRP_RESET 43
61#define MMSSNOCAHB_RESET 44
62#define MMSSNOCAXI_RESET 45
63
64#endif
diff --git a/include/dt-bindings/reset/qcom,mmcc-msm8960.h b/include/dt-bindings/reset/qcom,mmcc-msm8960.h
index ba36ec680118..11741113a841 100644
--- a/include/dt-bindings/reset/qcom,mmcc-msm8960.h
+++ b/include/dt-bindings/reset/qcom,mmcc-msm8960.h
@@ -89,5 +89,13 @@
89#define CSI2_RESET 72 89#define CSI2_RESET 72
90#define CSI_RDI1_RESET 73 90#define CSI_RDI1_RESET 73
91#define CSI_RDI2_RESET 74 91#define CSI_RDI2_RESET 74
92#define GFX3D_AXI_RESET 75
93#define VCAP_AXI_RESET 76
94#define SMMU_VCAP_AHB_RESET 77
95#define VCAP_AHB_RESET 78
96#define CSI_RDI_RESET 79
97#define CSI_PIX_RESET 80
98#define VCAP_NPL_RESET 81
99#define VCAP_RESET 82
92 100
93#endif 101#endif
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 0c287dbbb144..411dd7eb2653 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -619,5 +619,10 @@ static inline void clk_writel(u32 val, u32 __iomem *reg)
619 619
620#endif /* platform dependent I/O accessors */ 620#endif /* platform dependent I/O accessors */
621 621
622#ifdef CONFIG_DEBUG_FS
623struct dentry *clk_debugfs_add_file(struct clk *clk, char *name, umode_t mode,
624 void *data, const struct file_operations *fops);
625#endif
626
622#endif /* CONFIG_COMMON_CLK */ 627#endif /* CONFIG_COMMON_CLK */
623#endif /* CLK_PROVIDER_H */ 628#endif /* CLK_PROVIDER_H */
diff --git a/include/linux/clk/clk-conf.h b/include/linux/clk/clk-conf.h
new file mode 100644
index 000000000000..f3050e15f833
--- /dev/null
+++ b/include/linux/clk/clk-conf.h
@@ -0,0 +1,20 @@
1/*
2 * Copyright (C) 2014 Samsung Electronics Co., Ltd.
3 * Sylwester Nawrocki <s.nawrocki@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10struct device_node;
11
12#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK)
13int of_clk_set_defaults(struct device_node *node, bool clk_supplier);
14#else
15static inline int of_clk_set_defaults(struct device_node *node,
16 bool clk_supplier)
17{
18 return 0;
19}
20#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-24 22:38:29 -0400