diff options
author | Mike Turquette <mturquette@linaro.org> | 2014-07-31 12:32:18 -0400 |
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committer | Mike Turquette <mturquette@linaro.org> | 2014-07-31 12:32:18 -0400 |
commit | d7d3d26fa5446fc74e2c52504d827bda89b7b03e (patch) | |
tree | 209f3a0fe71af5a97ece45cee40c7e1a4f5495f3 /drivers/clk/samsung/clk-s3c64xx.c | |
parent | abeab450bfe823079c8a3abf5123f41a0da62392 (diff) | |
parent | f65d518942325d4bfa74b5c9d42ea5a89e4f6943 (diff) |
Merge tag 'for_3.17/samsung-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-next-samsung
Samsung clock patches for 3.17
1) non-critical fixes (without need to push to stable):
d5e136a clk: samsung: Register clk provider only after registering its all clocks
305cfab clk: samsung: Make of_device_id array const
e9d5295 clk: samsung: exynos5420: Setup clocks before system suspend
f65d518 clk: samsung: trivial: Correct typo in author's name
2) Exynos CLKOUT driver:
800c979 clk: samsung: exynos4: Add missing CPU/DMC clock hierarchy
01f7ec2 clk: samsung: exynos4: Add CLKOUT clock hierarchy
1e832e5 clk: samsung: Add driver to control CLKOUT line on Exynos SoCs
d19bb39 ARM: dts: exynos: Update PMU node with CLKOUT related data
3) Clock hierarchy extensions:
17d3f1d clk: exynos4: Add PPMU IP block source clocks.
ca5b402 clk: samsung: register exynos5420 apll/kpll configuration data
4) ARM CLKDOWN functionality enablement for Exynos4 and 3250:
42773b2 clk: samsung: exynos4: Enable ARMCLK down feature
45c5b0a clk: samsung: exynos3250: Enable ARMCLK down feature
Diffstat (limited to 'drivers/clk/samsung/clk-s3c64xx.c')
-rw-r--r-- | drivers/clk/samsung/clk-s3c64xx.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-s3c64xx.c b/drivers/clk/samsung/clk-s3c64xx.c index 8889ff1c10fc..0f590e5550cb 100644 --- a/drivers/clk/samsung/clk-s3c64xx.c +++ b/drivers/clk/samsung/clk-s3c64xx.c | |||
@@ -518,6 +518,8 @@ void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f, | |||
518 | ARRAY_SIZE(s3c64xx_clock_aliases)); | 518 | ARRAY_SIZE(s3c64xx_clock_aliases)); |
519 | s3c64xx_clk_sleep_init(); | 519 | s3c64xx_clk_sleep_init(); |
520 | 520 | ||
521 | samsung_clk_of_add_provider(np, ctx); | ||
522 | |||
521 | pr_info("%s clocks: apll = %lu, mpll = %lu\n" | 523 | pr_info("%s clocks: apll = %lu, mpll = %lu\n" |
522 | "\tepll = %lu, arm_clk = %lu\n", | 524 | "\tepll = %lu, arm_clk = %lu\n", |
523 | is_s3c6400 ? "S3C6400" : "S3C6410", | 525 | is_s3c6400 ? "S3C6400" : "S3C6410", |