aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/clk/qcom/gcc-msm8974.c
diff options
context:
space:
mode:
authorGeorgi Djakov <georgi.djakov@linaro.org>2015-03-20 12:30:26 -0400
committerStephen Boyd <sboyd@codeaurora.org>2015-03-23 19:09:19 -0400
commit293d2e97b37f545bb36aef78cd549d9e6cd66e7f (patch)
tree4b8ba1c40d681b198dd67696087cf03531f03ca0 /drivers/clk/qcom/gcc-msm8974.c
parentfae507afbdf3384227ced662c51c5b6cbff223c8 (diff)
clk: qcom: Introduce parent_map tables
In the current parent mapping code, we can get duplicate or inconsistent indexes, which leads to discrepancy between the number of elements in the array and the number of parents. Until now, this was solved with some reordering but this is not always possible. This patch introduces index tables that are used to define the relations between the PLL source and the hardware mux configuration value. To accomplish this, here we do the following: - Define a parent_map struct to map the relations between PLL source index and register configuration value. - Add a qcom_find_src_index() function for finding the index of a clock matching the specific PLL configuration. - Update the {set,get}_parent RCG functions use the newly introduced parent_map struct. - Convert all existing drivers to the new parent_map tables. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/qcom/gcc-msm8974.c')
-rw-r--r--drivers/clk/qcom/gcc-msm8974.c30
1 files changed, 16 insertions, 14 deletions
diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
index a6937fe78d8a..c39d09874e74 100644
--- a/drivers/clk/qcom/gcc-msm8974.c
+++ b/drivers/clk/qcom/gcc-msm8974.c
@@ -32,14 +32,16 @@
32#include "clk-branch.h" 32#include "clk-branch.h"
33#include "reset.h" 33#include "reset.h"
34 34
35#define P_XO 0 35enum {
36#define P_GPLL0 1 36 P_XO,
37#define P_GPLL1 1 37 P_GPLL0,
38#define P_GPLL4 2 38 P_GPLL1,
39 P_GPLL4,
40};
39 41
40static const u8 gcc_xo_gpll0_map[] = { 42static const struct parent_map gcc_xo_gpll0_map[] = {
41 [P_XO] = 0, 43 { P_XO, 0 },
42 [P_GPLL0] = 1, 44 { P_GPLL0, 1 }
43}; 45};
44 46
45static const char *gcc_xo_gpll0[] = { 47static const char *gcc_xo_gpll0[] = {
@@ -47,10 +49,10 @@ static const char *gcc_xo_gpll0[] = {
47 "gpll0_vote", 49 "gpll0_vote",
48}; 50};
49 51
50static const u8 gcc_xo_gpll0_gpll4_map[] = { 52static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
51 [P_XO] = 0, 53 { P_XO, 0 },
52 [P_GPLL0] = 1, 54 { P_GPLL0, 1 },
53 [P_GPLL4] = 5, 55 { P_GPLL4, 5 }
54}; 56};
55 57
56static const char *gcc_xo_gpll0_gpll4[] = { 58static const char *gcc_xo_gpll0_gpll4[] = {
@@ -984,9 +986,9 @@ static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
984 { } 986 { }
985}; 987};
986 988
987static u8 usb_hsic_clk_src_map[] = { 989static const struct parent_map usb_hsic_clk_src_map[] = {
988 [P_XO] = 0, 990 { P_XO, 0 },
989 [P_GPLL1] = 4, 991 { P_GPLL1, 4 }
990}; 992};
991 993
992static struct clk_rcg2 usb_hsic_clk_src = { 994static struct clk_rcg2 usb_hsic_clk_src = {