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-rw-r--r--drivers/clk/qcom/clk-rcg.c13
-rw-r--r--drivers/clk/qcom/clk-rcg.h14
-rw-r--r--drivers/clk/qcom/clk-rcg2.c14
-rw-r--r--drivers/clk/qcom/common.c12
-rw-r--r--drivers/clk/qcom/common.h4
-rw-r--r--drivers/clk/qcom/gcc-apq8084.c62
-rw-r--r--drivers/clk/qcom/gcc-ipq806x.c46
-rw-r--r--drivers/clk/qcom/gcc-msm8660.c22
-rw-r--r--drivers/clk/qcom/gcc-msm8960.c32
-rw-r--r--drivers/clk/qcom/gcc-msm8974.c30
-rw-r--r--drivers/clk/qcom/lcc-ipq806x.c12
-rw-r--r--drivers/clk/qcom/lcc-msm8960.c12
-rw-r--r--drivers/clk/qcom/mmcc-apq8084.c168
-rw-r--r--drivers/clk/qcom/mmcc-msm8960.c49
-rw-r--r--drivers/clk/qcom/mmcc-msm8974.c134
15 files changed, 338 insertions, 286 deletions
diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c
index 2c5d85961f54..8f2f48071a7a 100644
--- a/drivers/clk/qcom/clk-rcg.c
+++ b/drivers/clk/qcom/clk-rcg.c
@@ -54,7 +54,7 @@ static u8 clk_rcg_get_parent(struct clk_hw *hw)
54 goto err; 54 goto err;
55 ns = ns_to_src(&rcg->s, ns); 55 ns = ns_to_src(&rcg->s, ns);
56 for (i = 0; i < num_parents; i++) 56 for (i = 0; i < num_parents; i++)
57 if (ns == rcg->s.parent_map[i]) 57 if (ns == rcg->s.parent_map[i].cfg)
58 return i; 58 return i;
59 59
60err: 60err:
@@ -90,7 +90,7 @@ static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
90 ns = ns_to_src(s, ns); 90 ns = ns_to_src(s, ns);
91 91
92 for (i = 0; i < num_parents; i++) 92 for (i = 0; i < num_parents; i++)
93 if (ns == s->parent_map[i]) 93 if (ns == s->parent_map[i].cfg)
94 return i; 94 return i;
95 95
96err: 96err:
@@ -105,7 +105,7 @@ static int clk_rcg_set_parent(struct clk_hw *hw, u8 index)
105 u32 ns; 105 u32 ns;
106 106
107 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); 107 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
108 ns = src_to_ns(&rcg->s, rcg->s.parent_map[index], ns); 108 ns = src_to_ns(&rcg->s, rcg->s.parent_map[index].cfg, ns);
109 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns); 109 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
110 110
111 return 0; 111 return 0;
@@ -206,7 +206,7 @@ static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val)
206static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f) 206static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
207{ 207{
208 u32 ns, md, reg; 208 u32 ns, md, reg;
209 int bank, new_bank, ret; 209 int bank, new_bank, ret, index;
210 struct mn *mn; 210 struct mn *mn;
211 struct pre_div *p; 211 struct pre_div *p;
212 struct src_sel *s; 212 struct src_sel *s;
@@ -276,7 +276,10 @@ static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
276 } 276 }
277 277
278 s = &rcg->s[new_bank]; 278 s = &rcg->s[new_bank];
279 ns = src_to_ns(s, s->parent_map[f->src], ns); 279 index = qcom_find_src_index(hw, s->parent_map, f->src);
280 if (index < 0)
281 return index;
282 ns = src_to_ns(s, s->parent_map[index].cfg, ns);
280 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns); 283 ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
281 if (ret) 284 if (ret)
282 return ret; 285 return ret;
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index d09d06ba278e..56028bb31d87 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -26,6 +26,16 @@ struct freq_tbl {
26}; 26};
27 27
28/** 28/**
29 * struct parent_map - map table for PLL source select configuration values
30 * @src: source PLL
31 * @cfg: configuration value
32 */
33struct parent_map {
34 u8 src;
35 u8 cfg;
36};
37
38/**
29 * struct mn - M/N:D counter 39 * struct mn - M/N:D counter
30 * @mnctr_en_bit: bit to enable mn counter 40 * @mnctr_en_bit: bit to enable mn counter
31 * @mnctr_reset_bit: bit to assert mn counter reset 41 * @mnctr_reset_bit: bit to assert mn counter reset
@@ -65,7 +75,7 @@ struct pre_div {
65struct src_sel { 75struct src_sel {
66 u8 src_sel_shift; 76 u8 src_sel_shift;
67#define SRC_SEL_MASK 0x7 77#define SRC_SEL_MASK 0x7
68 const u8 *parent_map; 78 const struct parent_map *parent_map;
69}; 79};
70 80
71/** 81/**
@@ -151,7 +161,7 @@ struct clk_rcg2 {
151 u32 cmd_rcgr; 161 u32 cmd_rcgr;
152 u8 mnd_width; 162 u8 mnd_width;
153 u8 hid_width; 163 u8 hid_width;
154 const u8 *parent_map; 164 const struct parent_map *parent_map;
155 const struct freq_tbl *freq_tbl; 165 const struct freq_tbl *freq_tbl;
156 struct clk_regmap clkr; 166 struct clk_regmap clkr;
157}; 167};
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 10c2e45832b8..416becce4170 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -75,7 +75,7 @@ static u8 clk_rcg2_get_parent(struct clk_hw *hw)
75 cfg >>= CFG_SRC_SEL_SHIFT; 75 cfg >>= CFG_SRC_SEL_SHIFT;
76 76
77 for (i = 0; i < num_parents; i++) 77 for (i = 0; i < num_parents; i++)
78 if (cfg == rcg->parent_map[i]) 78 if (cfg == rcg->parent_map[i].cfg)
79 return i; 79 return i;
80 80
81err: 81err:
@@ -114,10 +114,10 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
114{ 114{
115 struct clk_rcg2 *rcg = to_clk_rcg2(hw); 115 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
116 int ret; 116 int ret;
117 u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
117 118
118 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, 119 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
119 CFG_SRC_SEL_MASK, 120 CFG_SRC_SEL_MASK, cfg);
120 rcg->parent_map[index] << CFG_SRC_SEL_SHIFT);
121 if (ret) 121 if (ret)
122 return ret; 122 return ret;
123 123
@@ -222,7 +222,11 @@ static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate,
222static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) 222static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
223{ 223{
224 u32 cfg, mask; 224 u32 cfg, mask;
225 int ret; 225 struct clk_hw *hw = &rcg->clkr.hw;
226 int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
227
228 if (index < 0)
229 return index;
226 230
227 if (rcg->mnd_width && f->n) { 231 if (rcg->mnd_width && f->n) {
228 mask = BIT(rcg->mnd_width) - 1; 232 mask = BIT(rcg->mnd_width) - 1;
@@ -245,7 +249,7 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
245 mask = BIT(rcg->hid_width) - 1; 249 mask = BIT(rcg->hid_width) - 1;
246 mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK; 250 mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
247 cfg = f->pre_div << CFG_SRC_DIV_SHIFT; 251 cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
248 cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT; 252 cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
249 if (rcg->mnd_width && f->n && (f->m != f->n)) 253 if (rcg->mnd_width && f->n && (f->m != f->n))
250 cfg |= CFG_MODE_DUAL_EDGE; 254 cfg |= CFG_MODE_DUAL_EDGE;
251 ret = regmap_update_bits(rcg->clkr.regmap, 255 ret = regmap_update_bits(rcg->clkr.regmap,
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index e20d947db3e5..f7101e330b1d 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -43,6 +43,18 @@ struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate)
43} 43}
44EXPORT_SYMBOL_GPL(qcom_find_freq); 44EXPORT_SYMBOL_GPL(qcom_find_freq);
45 45
46int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src)
47{
48 int i, num_parents = __clk_get_num_parents(hw->clk);
49
50 for (i = 0; i < num_parents; i++)
51 if (src == map[i].src)
52 return i;
53
54 return -ENOENT;
55}
56EXPORT_SYMBOL_GPL(qcom_find_src_index);
57
46struct regmap * 58struct regmap *
47qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc) 59qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc)
48{ 60{
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
index f519322acdf3..7a0e73713063 100644
--- a/drivers/clk/qcom/common.h
+++ b/drivers/clk/qcom/common.h
@@ -19,6 +19,8 @@ struct clk_regmap;
19struct qcom_reset_map; 19struct qcom_reset_map;
20struct regmap; 20struct regmap;
21struct freq_tbl; 21struct freq_tbl;
22struct clk_hw;
23struct parent_map;
22 24
23struct qcom_cc_desc { 25struct qcom_cc_desc {
24 const struct regmap_config *config; 26 const struct regmap_config *config;
@@ -30,6 +32,8 @@ struct qcom_cc_desc {
30 32
31extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, 33extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,
32 unsigned long rate); 34 unsigned long rate);
35extern int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map,
36 u8 src);
33 37
34extern struct regmap *qcom_cc_map(struct platform_device *pdev, 38extern struct regmap *qcom_cc_map(struct platform_device *pdev,
35 const struct qcom_cc_desc *desc); 39 const struct qcom_cc_desc *desc);
diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
index e3ef90264214..54a756b90a37 100644
--- a/drivers/clk/qcom/gcc-apq8084.c
+++ b/drivers/clk/qcom/gcc-apq8084.c
@@ -32,18 +32,20 @@
32#include "clk-branch.h" 32#include "clk-branch.h"
33#include "reset.h" 33#include "reset.h"
34 34
35#define P_XO 0 35enum {
36#define P_GPLL0 1 36 P_XO,
37#define P_GPLL1 1 37 P_GPLL0,
38#define P_GPLL4 2 38 P_GPLL1,
39#define P_PCIE_0_1_PIPE_CLK 1 39 P_GPLL4,
40#define P_SATA_ASIC0_CLK 1 40 P_PCIE_0_1_PIPE_CLK,
41#define P_SATA_RX_CLK 1 41 P_SATA_ASIC0_CLK,
42#define P_SLEEP_CLK 1 42 P_SATA_RX_CLK,
43 P_SLEEP_CLK,
44};
43 45
44static const u8 gcc_xo_gpll0_map[] = { 46static const struct parent_map gcc_xo_gpll0_map[] = {
45 [P_XO] = 0, 47 { P_XO, 0 },
46 [P_GPLL0] = 1, 48 { P_GPLL0, 1 }
47}; 49};
48 50
49static const char *gcc_xo_gpll0[] = { 51static const char *gcc_xo_gpll0[] = {
@@ -51,10 +53,10 @@ static const char *gcc_xo_gpll0[] = {
51 "gpll0_vote", 53 "gpll0_vote",
52}; 54};
53 55
54static const u8 gcc_xo_gpll0_gpll4_map[] = { 56static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
55 [P_XO] = 0, 57 { P_XO, 0 },
56 [P_GPLL0] = 1, 58 { P_GPLL0, 1 },
57 [P_GPLL4] = 5, 59 { P_GPLL4, 5 }
58}; 60};
59 61
60static const char *gcc_xo_gpll0_gpll4[] = { 62static const char *gcc_xo_gpll0_gpll4[] = {
@@ -63,9 +65,9 @@ static const char *gcc_xo_gpll0_gpll4[] = {
63 "gpll4_vote", 65 "gpll4_vote",
64}; 66};
65 67
66static const u8 gcc_xo_sata_asic0_map[] = { 68static const struct parent_map gcc_xo_sata_asic0_map[] = {
67 [P_XO] = 0, 69 { P_XO, 0 },
68 [P_SATA_ASIC0_CLK] = 2, 70 { P_SATA_ASIC0_CLK, 2 }
69}; 71};
70 72
71static const char *gcc_xo_sata_asic0[] = { 73static const char *gcc_xo_sata_asic0[] = {
@@ -73,9 +75,9 @@ static const char *gcc_xo_sata_asic0[] = {
73 "sata_asic0_clk", 75 "sata_asic0_clk",
74}; 76};
75 77
76static const u8 gcc_xo_sata_rx_map[] = { 78static const struct parent_map gcc_xo_sata_rx_map[] = {
77 [P_XO] = 0, 79 { P_XO, 0 },
78 [P_SATA_RX_CLK] = 2, 80 { P_SATA_RX_CLK, 2}
79}; 81};
80 82
81static const char *gcc_xo_sata_rx[] = { 83static const char *gcc_xo_sata_rx[] = {
@@ -83,9 +85,9 @@ static const char *gcc_xo_sata_rx[] = {
83 "sata_rx_clk", 85 "sata_rx_clk",
84}; 86};
85 87
86static const u8 gcc_xo_pcie_map[] = { 88static const struct parent_map gcc_xo_pcie_map[] = {
87 [P_XO] = 0, 89 { P_XO, 0 },
88 [P_PCIE_0_1_PIPE_CLK] = 2, 90 { P_PCIE_0_1_PIPE_CLK, 2 }
89}; 91};
90 92
91static const char *gcc_xo_pcie[] = { 93static const char *gcc_xo_pcie[] = {
@@ -93,9 +95,9 @@ static const char *gcc_xo_pcie[] = {
93 "pcie_pipe", 95 "pcie_pipe",
94}; 96};
95 97
96static const u8 gcc_xo_pcie_sleep_map[] = { 98static const struct parent_map gcc_xo_pcie_sleep_map[] = {
97 [P_XO] = 0, 99 { P_XO, 0 },
98 [P_SLEEP_CLK] = 6, 100 { P_SLEEP_CLK, 6 }
99}; 101};
100 102
101static const char *gcc_xo_pcie_sleep[] = { 103static const char *gcc_xo_pcie_sleep[] = {
@@ -1263,9 +1265,9 @@ static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
1263 { } 1265 { }
1264}; 1266};
1265 1267
1266static u8 usb_hsic_clk_src_map[] = { 1268static const struct parent_map usb_hsic_clk_src_map[] = {
1267 [P_XO] = 0, 1269 { P_XO, 0 },
1268 [P_GPLL1] = 4, 1270 { P_GPLL1, 4 }
1269}; 1271};
1270 1272
1271static struct clk_rcg2 usb_hsic_clk_src = { 1273static struct clk_rcg2 usb_hsic_clk_src = {
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index a015bb06c09b..ee73cc7f6e55 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -140,15 +140,17 @@ static struct clk_regmap pll14_vote = {
140 }, 140 },
141}; 141};
142 142
143#define P_PXO 0 143enum {
144#define P_PLL8 1 144 P_PXO,
145#define P_PLL3 1 145 P_PLL8,
146#define P_PLL0 2 146 P_PLL3,
147#define P_CXO 2 147 P_PLL0,
148 P_CXO,
149};
148 150
149static const u8 gcc_pxo_pll8_map[] = { 151static const struct parent_map gcc_pxo_pll8_map[] = {
150 [P_PXO] = 0, 152 { P_PXO, 0 },
151 [P_PLL8] = 3, 153 { P_PLL8, 3 }
152}; 154};
153 155
154static const char *gcc_pxo_pll8[] = { 156static const char *gcc_pxo_pll8[] = {
@@ -156,10 +158,10 @@ static const char *gcc_pxo_pll8[] = {
156 "pll8_vote", 158 "pll8_vote",
157}; 159};
158 160
159static const u8 gcc_pxo_pll8_cxo_map[] = { 161static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
160 [P_PXO] = 0, 162 { P_PXO, 0 },
161 [P_PLL8] = 3, 163 { P_PLL8, 3 },
162 [P_CXO] = 5, 164 { P_CXO, 5 }
163}; 165};
164 166
165static const char *gcc_pxo_pll8_cxo[] = { 167static const char *gcc_pxo_pll8_cxo[] = {
@@ -168,14 +170,14 @@ static const char *gcc_pxo_pll8_cxo[] = {
168 "cxo", 170 "cxo",
169}; 171};
170 172
171static const u8 gcc_pxo_pll3_map[] = { 173static const struct parent_map gcc_pxo_pll3_map[] = {
172 [P_PXO] = 0, 174 { P_PXO, 0 },
173 [P_PLL3] = 1, 175 { P_PLL3, 1 }
174}; 176};
175 177
176static const u8 gcc_pxo_pll3_sata_map[] = { 178static const struct parent_map gcc_pxo_pll3_sata_map[] = {
177 [P_PXO] = 0, 179 { P_PXO, 0 },
178 [P_PLL3] = 6, 180 { P_PLL3, 6 }
179}; 181};
180 182
181static const char *gcc_pxo_pll3[] = { 183static const char *gcc_pxo_pll3[] = {
@@ -183,10 +185,10 @@ static const char *gcc_pxo_pll3[] = {
183 "pll3", 185 "pll3",
184}; 186};
185 187
186static const u8 gcc_pxo_pll8_pll0[] = { 188static const struct parent_map gcc_pxo_pll8_pll0[] = {
187 [P_PXO] = 0, 189 { P_PXO, 0 },
188 [P_PLL8] = 3, 190 { P_PLL8, 3 },
189 [P_PLL0] = 2, 191 { P_PLL0, 2 }
190}; 192};
191 193
192static const char *gcc_pxo_pll8_pll0_map[] = { 194static const char *gcc_pxo_pll8_pll0_map[] = {
diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm8660.c
index f366e68f7316..fc6b12da5b30 100644
--- a/drivers/clk/qcom/gcc-msm8660.c
+++ b/drivers/clk/qcom/gcc-msm8660.c
@@ -59,13 +59,15 @@ static struct clk_regmap pll8_vote = {
59 }, 59 },
60}; 60};
61 61
62#define P_PXO 0 62enum {
63#define P_PLL8 1 63 P_PXO,
64#define P_CXO 2 64 P_PLL8,
65 P_CXO,
66};
65 67
66static const u8 gcc_pxo_pll8_map[] = { 68static const struct parent_map gcc_pxo_pll8_map[] = {
67 [P_PXO] = 0, 69 { P_PXO, 0 },
68 [P_PLL8] = 3, 70 { P_PLL8, 3 }
69}; 71};
70 72
71static const char *gcc_pxo_pll8[] = { 73static const char *gcc_pxo_pll8[] = {
@@ -73,10 +75,10 @@ static const char *gcc_pxo_pll8[] = {
73 "pll8_vote", 75 "pll8_vote",
74}; 76};
75 77
76static const u8 gcc_pxo_pll8_cxo_map[] = { 78static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
77 [P_PXO] = 0, 79 { P_PXO, 0 },
78 [P_PLL8] = 3, 80 { P_PLL8, 3 },
79 [P_CXO] = 5, 81 { P_CXO, 5 }
80}; 82};
81 83
82static const char *gcc_pxo_pll8_cxo[] = { 84static const char *gcc_pxo_pll8_cxo[] = {
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index e60feffc10a1..eb6a4f9fa107 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -113,14 +113,16 @@ static struct clk_regmap pll14_vote = {
113 }, 113 },
114}; 114};
115 115
116#define P_PXO 0 116enum {
117#define P_PLL8 1 117 P_PXO,
118#define P_PLL3 2 118 P_PLL8,
119#define P_CXO 2 119 P_PLL3,
120 P_CXO,
121};
120 122
121static const u8 gcc_pxo_pll8_map[] = { 123static const struct parent_map gcc_pxo_pll8_map[] = {
122 [P_PXO] = 0, 124 { P_PXO, 0 },
123 [P_PLL8] = 3, 125 { P_PLL8, 3 }
124}; 126};
125 127
126static const char *gcc_pxo_pll8[] = { 128static const char *gcc_pxo_pll8[] = {
@@ -128,10 +130,10 @@ static const char *gcc_pxo_pll8[] = {
128 "pll8_vote", 130 "pll8_vote",
129}; 131};
130 132
131static const u8 gcc_pxo_pll8_cxo_map[] = { 133static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
132 [P_PXO] = 0, 134 { P_PXO, 0 },
133 [P_PLL8] = 3, 135 { P_PLL8, 3 },
134 [P_CXO] = 5, 136 { P_CXO, 5 }
135}; 137};
136 138
137static const char *gcc_pxo_pll8_cxo[] = { 139static const char *gcc_pxo_pll8_cxo[] = {
@@ -140,10 +142,10 @@ static const char *gcc_pxo_pll8_cxo[] = {
140 "cxo", 142 "cxo",
141}; 143};
142 144
143static const u8 gcc_pxo_pll8_pll3_map[] = { 145static const struct parent_map gcc_pxo_pll8_pll3_map[] = {
144 [P_PXO] = 0, 146 { P_PXO, 0 },
145 [P_PLL8] = 3, 147 { P_PLL8, 3 },
146 [P_PLL3] = 6, 148 { P_PLL3, 6 }
147}; 149};
148 150
149static const char *gcc_pxo_pll8_pll3[] = { 151static const char *gcc_pxo_pll8_pll3[] = {
diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
index a6937fe78d8a..c39d09874e74 100644
--- a/drivers/clk/qcom/gcc-msm8974.c
+++ b/drivers/clk/qcom/gcc-msm8974.c
@@ -32,14 +32,16 @@
32#include "clk-branch.h" 32#include "clk-branch.h"
33#include "reset.h" 33#include "reset.h"
34 34
35#define P_XO 0 35enum {
36#define P_GPLL0 1 36 P_XO,
37#define P_GPLL1 1 37 P_GPLL0,
38#define P_GPLL4 2 38 P_GPLL1,
39 P_GPLL4,
40};
39 41
40static const u8 gcc_xo_gpll0_map[] = { 42static const struct parent_map gcc_xo_gpll0_map[] = {
41 [P_XO] = 0, 43 { P_XO, 0 },
42 [P_GPLL0] = 1, 44 { P_GPLL0, 1 }
43}; 45};
44 46
45static const char *gcc_xo_gpll0[] = { 47static const char *gcc_xo_gpll0[] = {
@@ -47,10 +49,10 @@ static const char *gcc_xo_gpll0[] = {
47 "gpll0_vote", 49 "gpll0_vote",
48}; 50};
49 51
50static const u8 gcc_xo_gpll0_gpll4_map[] = { 52static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
51 [P_XO] = 0, 53 { P_XO, 0 },
52 [P_GPLL0] = 1, 54 { P_GPLL0, 1 },
53 [P_GPLL4] = 5, 55 { P_GPLL4, 5 }
54}; 56};
55 57
56static const char *gcc_xo_gpll0_gpll4[] = { 58static const char *gcc_xo_gpll0_gpll4[] = {
@@ -984,9 +986,9 @@ static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
984 { } 986 { }
985}; 987};
986 988
987static u8 usb_hsic_clk_src_map[] = { 989static const struct parent_map usb_hsic_clk_src_map[] = {
988 [P_XO] = 0, 990 { P_XO, 0 },
989 [P_GPLL1] = 4, 991 { P_GPLL1, 4 }
990}; 992};
991 993
992static struct clk_rcg2 usb_hsic_clk_src = { 994static struct clk_rcg2 usb_hsic_clk_src = {
diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c
index 19378b080dd7..e4ac699666d5 100644
--- a/drivers/clk/qcom/lcc-ipq806x.c
+++ b/drivers/clk/qcom/lcc-ipq806x.c
@@ -61,12 +61,14 @@ static const struct pll_config pll4_config = {
61 .main_output_mask = BIT(23), 61 .main_output_mask = BIT(23),
62}; 62};
63 63
64#define P_PXO 0 64enum {
65#define P_PLL4 1 65 P_PXO,
66 P_PLL4,
67};
66 68
67static const u8 lcc_pxo_pll4_map[] = { 69static const struct parent_map lcc_pxo_pll4_map[] = {
68 [P_PXO] = 0, 70 { P_PXO, 0 },
69 [P_PLL4] = 2, 71 { P_PLL4, 2 }
70}; 72};
71 73
72static const char *lcc_pxo_pll4[] = { 74static const char *lcc_pxo_pll4[] = {
diff --git a/drivers/clk/qcom/lcc-msm8960.c b/drivers/clk/qcom/lcc-msm8960.c
index e2c863295f00..d0df9d5fc3af 100644
--- a/drivers/clk/qcom/lcc-msm8960.c
+++ b/drivers/clk/qcom/lcc-msm8960.c
@@ -47,12 +47,14 @@ static struct clk_pll pll4 = {
47 }, 47 },
48}; 48};
49 49
50#define P_PXO 0 50enum {
51#define P_PLL4 1 51 P_PXO,
52 P_PLL4,
53};
52 54
53static const u8 lcc_pxo_pll4_map[] = { 55static const struct parent_map lcc_pxo_pll4_map[] = {
54 [P_PXO] = 0, 56 { P_PXO, 0 },
55 [P_PLL4] = 2, 57 { P_PLL4, 2 }
56}; 58};
57 59
58static const char *lcc_pxo_pll4[] = { 60static const char *lcc_pxo_pll4[] = {
diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
index 157139a5c1ca..1b17df2cb0af 100644
--- a/drivers/clk/qcom/mmcc-apq8084.c
+++ b/drivers/clk/qcom/mmcc-apq8084.c
@@ -27,28 +27,30 @@
27#include "clk-branch.h" 27#include "clk-branch.h"
28#include "reset.h" 28#include "reset.h"
29 29
30#define P_XO 0 30enum {
31#define P_MMPLL0 1 31 P_XO,
32#define P_EDPLINK 1 32 P_MMPLL0,
33#define P_MMPLL1 2 33 P_EDPLINK,
34#define P_HDMIPLL 2 34 P_MMPLL1,
35#define P_GPLL0 3 35 P_HDMIPLL,
36#define P_EDPVCO 3 36 P_GPLL0,
37#define P_MMPLL4 4 37 P_EDPVCO,
38#define P_DSI0PLL 4 38 P_MMPLL4,
39#define P_DSI0PLL_BYTE 4 39 P_DSI0PLL,
40#define P_MMPLL2 4 40 P_DSI0PLL_BYTE,
41#define P_MMPLL3 4 41 P_MMPLL2,
42#define P_GPLL1 5 42 P_MMPLL3,
43#define P_DSI1PLL 5 43 P_GPLL1,
44#define P_DSI1PLL_BYTE 5 44 P_DSI1PLL,
45#define P_MMSLEEP 6 45 P_DSI1PLL_BYTE,
46 46 P_MMSLEEP,
47static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = { 47};
48 [P_XO] = 0, 48
49 [P_MMPLL0] = 1, 49static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
50 [P_MMPLL1] = 2, 50 { P_XO, 0 },
51 [P_GPLL0] = 5, 51 { P_MMPLL0, 1 },
52 { P_MMPLL1, 2 },
53 { P_GPLL0, 5 }
52}; 54};
53 55
54static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = { 56static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
@@ -58,13 +60,13 @@ static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
58 "mmss_gpll0_vote", 60 "mmss_gpll0_vote",
59}; 61};
60 62
61static const u8 mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = { 63static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
62 [P_XO] = 0, 64 { P_XO, 0 },
63 [P_MMPLL0] = 1, 65 { P_MMPLL0, 1 },
64 [P_HDMIPLL] = 4, 66 { P_HDMIPLL, 4 },
65 [P_GPLL0] = 5, 67 { P_GPLL0, 5 },
66 [P_DSI0PLL] = 2, 68 { P_DSI0PLL, 2 },
67 [P_DSI1PLL] = 3, 69 { P_DSI1PLL, 3 }
68}; 70};
69 71
70static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = { 72static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
@@ -76,12 +78,12 @@ static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
76 "dsi1pll", 78 "dsi1pll",
77}; 79};
78 80
79static const u8 mmcc_xo_mmpll0_1_2_gpll0_map[] = { 81static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
80 [P_XO] = 0, 82 { P_XO, 0 },
81 [P_MMPLL0] = 1, 83 { P_MMPLL0, 1 },
82 [P_MMPLL1] = 2, 84 { P_MMPLL1, 2 },
83 [P_GPLL0] = 5, 85 { P_GPLL0, 5 },
84 [P_MMPLL2] = 3, 86 { P_MMPLL2, 3 }
85}; 87};
86 88
87static const char *mmcc_xo_mmpll0_1_2_gpll0[] = { 89static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
@@ -92,12 +94,12 @@ static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
92 "mmpll2", 94 "mmpll2",
93}; 95};
94 96
95static const u8 mmcc_xo_mmpll0_1_3_gpll0_map[] = { 97static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
96 [P_XO] = 0, 98 { P_XO, 0 },
97 [P_MMPLL0] = 1, 99 { P_MMPLL0, 1 },
98 [P_MMPLL1] = 2, 100 { P_MMPLL1, 2 },
99 [P_GPLL0] = 5, 101 { P_GPLL0, 5 },
100 [P_MMPLL3] = 3, 102 { P_MMPLL3, 3 }
101}; 103};
102 104
103static const char *mmcc_xo_mmpll0_1_3_gpll0[] = { 105static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
@@ -108,13 +110,13 @@ static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
108 "mmpll3", 110 "mmpll3",
109}; 111};
110 112
111static const u8 mmcc_xo_dsi_hdmi_edp_map[] = { 113static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
112 [P_XO] = 0, 114 { P_XO, 0 },
113 [P_EDPLINK] = 4, 115 { P_EDPLINK, 4 },
114 [P_HDMIPLL] = 3, 116 { P_HDMIPLL, 3 },
115 [P_EDPVCO] = 5, 117 { P_EDPVCO, 5 },
116 [P_DSI0PLL] = 1, 118 { P_DSI0PLL, 1 },
117 [P_DSI1PLL] = 2, 119 { P_DSI1PLL, 2 }
118}; 120};
119 121
120static const char *mmcc_xo_dsi_hdmi_edp[] = { 122static const char *mmcc_xo_dsi_hdmi_edp[] = {
@@ -126,13 +128,13 @@ static const char *mmcc_xo_dsi_hdmi_edp[] = {
126 "dsi1pll", 128 "dsi1pll",
127}; 129};
128 130
129static const u8 mmcc_xo_dsi_hdmi_edp_gpll0_map[] = { 131static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
130 [P_XO] = 0, 132 { P_XO, 0 },
131 [P_EDPLINK] = 4, 133 { P_EDPLINK, 4 },
132 [P_HDMIPLL] = 3, 134 { P_HDMIPLL, 3 },
133 [P_GPLL0] = 5, 135 { P_GPLL0, 5 },
134 [P_DSI0PLL] = 1, 136 { P_DSI0PLL, 1 },
135 [P_DSI1PLL] = 2, 137 { P_DSI1PLL, 2 }
136}; 138};
137 139
138static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = { 140static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
@@ -144,13 +146,13 @@ static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
144 "dsi1pll", 146 "dsi1pll",
145}; 147};
146 148
147static const u8 mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = { 149static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
148 [P_XO] = 0, 150 { P_XO, 0 },
149 [P_EDPLINK] = 4, 151 { P_EDPLINK, 4 },
150 [P_HDMIPLL] = 3, 152 { P_HDMIPLL, 3 },
151 [P_GPLL0] = 5, 153 { P_GPLL0, 5 },
152 [P_DSI0PLL_BYTE] = 1, 154 { P_DSI0PLL_BYTE, 1 },
153 [P_DSI1PLL_BYTE] = 2, 155 { P_DSI1PLL_BYTE, 2 }
154}; 156};
155 157
156static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = { 158static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
@@ -162,12 +164,12 @@ static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
162 "dsi1pllbyte", 164 "dsi1pllbyte",
163}; 165};
164 166
165static const u8 mmcc_xo_mmpll0_1_4_gpll0_map[] = { 167static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = {
166 [P_XO] = 0, 168 { P_XO, 0 },
167 [P_MMPLL0] = 1, 169 { P_MMPLL0, 1 },
168 [P_MMPLL1] = 2, 170 { P_MMPLL1, 2 },
169 [P_GPLL0] = 5, 171 { P_GPLL0, 5 },
170 [P_MMPLL4] = 3, 172 { P_MMPLL4, 3 }
171}; 173};
172 174
173static const char *mmcc_xo_mmpll0_1_4_gpll0[] = { 175static const char *mmcc_xo_mmpll0_1_4_gpll0[] = {
@@ -178,13 +180,13 @@ static const char *mmcc_xo_mmpll0_1_4_gpll0[] = {
178 "gpll0", 180 "gpll0",
179}; 181};
180 182
181static const u8 mmcc_xo_mmpll0_1_4_gpll1_0_map[] = { 183static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
182 [P_XO] = 0, 184 { P_XO, 0 },
183 [P_MMPLL0] = 1, 185 { P_MMPLL0, 1 },
184 [P_MMPLL1] = 2, 186 { P_MMPLL1, 2 },
185 [P_MMPLL4] = 3, 187 { P_MMPLL4, 3 },
186 [P_GPLL0] = 5, 188 { P_GPLL0, 5 },
187 [P_GPLL1] = 4, 189 { P_GPLL1, 4 }
188}; 190};
189 191
190static const char *mmcc_xo_mmpll0_1_4_gpll1_0[] = { 192static const char *mmcc_xo_mmpll0_1_4_gpll1_0[] = {
@@ -196,14 +198,14 @@ static const char *mmcc_xo_mmpll0_1_4_gpll1_0[] = {
196 "gpll0", 198 "gpll0",
197}; 199};
198 200
199static const u8 mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = { 201static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
200 [P_XO] = 0, 202 { P_XO, 0 },
201 [P_MMPLL0] = 1, 203 { P_MMPLL0, 1 },
202 [P_MMPLL1] = 2, 204 { P_MMPLL1, 2 },
203 [P_MMPLL4] = 3, 205 { P_MMPLL4, 3 },
204 [P_GPLL0] = 5, 206 { P_GPLL0, 5 },
205 [P_GPLL1] = 4, 207 { P_GPLL1, 4 },
206 [P_MMSLEEP] = 6, 208 { P_MMSLEEP, 6 }
207}; 209};
208 210
209static const char *mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = { 211static const char *mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c
index e8b33bbc362f..9711bca9cc06 100644
--- a/drivers/clk/qcom/mmcc-msm8960.c
+++ b/drivers/clk/qcom/mmcc-msm8960.c
@@ -33,18 +33,21 @@
33#include "clk-branch.h" 33#include "clk-branch.h"
34#include "reset.h" 34#include "reset.h"
35 35
36#define P_PXO 0 36enum {
37#define P_PLL8 1 37 P_PXO,
38#define P_PLL2 2 38 P_PLL8,
39#define P_PLL3 3 39 P_PLL2,
40#define P_PLL15 3 40 P_PLL3,
41 P_PLL15,
42 P_HDMI_PLL,
43};
41 44
42#define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n } 45#define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
43 46
44static u8 mmcc_pxo_pll8_pll2_map[] = { 47static const struct parent_map mmcc_pxo_pll8_pll2_map[] = {
45 [P_PXO] = 0, 48 { P_PXO, 0 },
46 [P_PLL8] = 2, 49 { P_PLL8, 2 },
47 [P_PLL2] = 1, 50 { P_PLL2, 1 }
48}; 51};
49 52
50static const char *mmcc_pxo_pll8_pll2[] = { 53static const char *mmcc_pxo_pll8_pll2[] = {
@@ -53,11 +56,11 @@ static const char *mmcc_pxo_pll8_pll2[] = {
53 "pll2", 56 "pll2",
54}; 57};
55 58
56static u8 mmcc_pxo_pll8_pll2_pll3_map[] = { 59static const struct parent_map mmcc_pxo_pll8_pll2_pll3_map[] = {
57 [P_PXO] = 0, 60 { P_PXO, 0 },
58 [P_PLL8] = 2, 61 { P_PLL8, 2 },
59 [P_PLL2] = 1, 62 { P_PLL2, 1 },
60 [P_PLL3] = 3, 63 { P_PLL3, 3 }
61}; 64};
62 65
63static const char *mmcc_pxo_pll8_pll2_pll15[] = { 66static const char *mmcc_pxo_pll8_pll2_pll15[] = {
@@ -67,11 +70,11 @@ static const char *mmcc_pxo_pll8_pll2_pll15[] = {
67 "pll15", 70 "pll15",
68}; 71};
69 72
70static u8 mmcc_pxo_pll8_pll2_pll15_map[] = { 73static const struct parent_map mmcc_pxo_pll8_pll2_pll15_map[] = {
71 [P_PXO] = 0, 74 { P_PXO, 0 },
72 [P_PLL8] = 2, 75 { P_PLL8, 2 },
73 [P_PLL2] = 1, 76 { P_PLL2, 1 },
74 [P_PLL15] = 3, 77 { P_PLL15, 3 }
75}; 78};
76 79
77static const char *mmcc_pxo_pll8_pll2_pll3[] = { 80static const char *mmcc_pxo_pll8_pll2_pll3[] = {
@@ -1377,11 +1380,9 @@ static struct clk_branch rot_clk = {
1377 }, 1380 },
1378}; 1381};
1379 1382
1380#define P_HDMI_PLL 1 1383static const struct parent_map mmcc_pxo_hdmi_map[] = {
1381 1384 { P_PXO, 0 },
1382static u8 mmcc_pxo_hdmi_map[] = { 1385 { P_HDMI_PLL, 3 }
1383 [P_PXO] = 0,
1384 [P_HDMI_PLL] = 3,
1385}; 1386};
1386 1387
1387static const char *mmcc_pxo_hdmi[] = { 1388static const char *mmcc_pxo_hdmi[] = {
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index be94c54a9a4f..07f4cc159ad3 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -32,26 +32,28 @@
32#include "clk-branch.h" 32#include "clk-branch.h"
33#include "reset.h" 33#include "reset.h"
34 34
35#define P_XO 0 35enum {
36#define P_MMPLL0 1 36 P_XO,
37#define P_EDPLINK 1 37 P_MMPLL0,
38#define P_MMPLL1 2 38 P_EDPLINK,
39#define P_HDMIPLL 2 39 P_MMPLL1,
40#define P_GPLL0 3 40 P_HDMIPLL,
41#define P_EDPVCO 3 41 P_GPLL0,
42#define P_GPLL1 4 42 P_EDPVCO,
43#define P_DSI0PLL 4 43 P_GPLL1,
44#define P_DSI0PLL_BYTE 4 44 P_DSI0PLL,
45#define P_MMPLL2 4 45 P_DSI0PLL_BYTE,
46#define P_MMPLL3 4 46 P_MMPLL2,
47#define P_DSI1PLL 5 47 P_MMPLL3,
48#define P_DSI1PLL_BYTE 5 48 P_DSI1PLL,
49 49 P_DSI1PLL_BYTE,
50static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = { 50};
51 [P_XO] = 0, 51
52 [P_MMPLL0] = 1, 52static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
53 [P_MMPLL1] = 2, 53 { P_XO, 0 },
54 [P_GPLL0] = 5, 54 { P_MMPLL0, 1 },
55 { P_MMPLL1, 2 },
56 { P_GPLL0, 5 }
55}; 57};
56 58
57static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = { 59static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
@@ -61,13 +63,13 @@ static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
61 "mmss_gpll0_vote", 63 "mmss_gpll0_vote",
62}; 64};
63 65
64static const u8 mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = { 66static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
65 [P_XO] = 0, 67 { P_XO, 0 },
66 [P_MMPLL0] = 1, 68 { P_MMPLL0, 1 },
67 [P_HDMIPLL] = 4, 69 { P_HDMIPLL, 4 },
68 [P_GPLL0] = 5, 70 { P_GPLL0, 5 },
69 [P_DSI0PLL] = 2, 71 { P_DSI0PLL, 2 },
70 [P_DSI1PLL] = 3, 72 { P_DSI1PLL, 3 }
71}; 73};
72 74
73static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = { 75static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
@@ -79,12 +81,12 @@ static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
79 "dsi1pll", 81 "dsi1pll",
80}; 82};
81 83
82static const u8 mmcc_xo_mmpll0_1_2_gpll0_map[] = { 84static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
83 [P_XO] = 0, 85 { P_XO, 0 },
84 [P_MMPLL0] = 1, 86 { P_MMPLL0, 1 },
85 [P_MMPLL1] = 2, 87 { P_MMPLL1, 2 },
86 [P_GPLL0] = 5, 88 { P_GPLL0, 5 },
87 [P_MMPLL2] = 3, 89 { P_MMPLL2, 3 }
88}; 90};
89 91
90static const char *mmcc_xo_mmpll0_1_2_gpll0[] = { 92static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
@@ -95,12 +97,12 @@ static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
95 "mmpll2", 97 "mmpll2",
96}; 98};
97 99
98static const u8 mmcc_xo_mmpll0_1_3_gpll0_map[] = { 100static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
99 [P_XO] = 0, 101 { P_XO, 0 },
100 [P_MMPLL0] = 1, 102 { P_MMPLL0, 1 },
101 [P_MMPLL1] = 2, 103 { P_MMPLL1, 2 },
102 [P_GPLL0] = 5, 104 { P_GPLL0, 5 },
103 [P_MMPLL3] = 3, 105 { P_MMPLL3, 3 }
104}; 106};
105 107
106static const char *mmcc_xo_mmpll0_1_3_gpll0[] = { 108static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
@@ -111,12 +113,12 @@ static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
111 "mmpll3", 113 "mmpll3",
112}; 114};
113 115
114static const u8 mmcc_xo_mmpll0_1_gpll1_0_map[] = { 116static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
115 [P_XO] = 0, 117 { P_XO, 0 },
116 [P_MMPLL0] = 1, 118 { P_MMPLL0, 1 },
117 [P_MMPLL1] = 2, 119 { P_MMPLL1, 2 },
118 [P_GPLL0] = 5, 120 { P_GPLL0, 5 },
119 [P_GPLL1] = 4, 121 { P_GPLL1, 4 }
120}; 122};
121 123
122static const char *mmcc_xo_mmpll0_1_gpll1_0[] = { 124static const char *mmcc_xo_mmpll0_1_gpll1_0[] = {
@@ -127,13 +129,13 @@ static const char *mmcc_xo_mmpll0_1_gpll1_0[] = {
127 "gpll1_vote", 129 "gpll1_vote",
128}; 130};
129 131
130static const u8 mmcc_xo_dsi_hdmi_edp_map[] = { 132static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
131 [P_XO] = 0, 133 { P_XO, 0 },
132 [P_EDPLINK] = 4, 134 { P_EDPLINK, 4 },
133 [P_HDMIPLL] = 3, 135 { P_HDMIPLL, 3 },
134 [P_EDPVCO] = 5, 136 { P_EDPVCO, 5 },
135 [P_DSI0PLL] = 1, 137 { P_DSI0PLL, 1 },
136 [P_DSI1PLL] = 2, 138 { P_DSI1PLL, 2 }
137}; 139};
138 140
139static const char *mmcc_xo_dsi_hdmi_edp[] = { 141static const char *mmcc_xo_dsi_hdmi_edp[] = {
@@ -145,13 +147,13 @@ static const char *mmcc_xo_dsi_hdmi_edp[] = {
145 "dsi1pll", 147 "dsi1pll",
146}; 148};
147 149
148static const u8 mmcc_xo_dsi_hdmi_edp_gpll0_map[] = { 150static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
149 [P_XO] = 0, 151 { P_XO, 0 },
150 [P_EDPLINK] = 4, 152 { P_EDPLINK, 4 },
151 [P_HDMIPLL] = 3, 153 { P_HDMIPLL, 3 },
152 [P_GPLL0] = 5, 154 { P_GPLL0, 5 },
153 [P_DSI0PLL] = 1, 155 { P_DSI0PLL, 1 },
154 [P_DSI1PLL] = 2, 156 { P_DSI1PLL, 2 }
155}; 157};
156 158
157static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = { 159static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
@@ -163,13 +165,13 @@ static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
163 "dsi1pll", 165 "dsi1pll",
164}; 166};
165 167
166static const u8 mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = { 168static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
167 [P_XO] = 0, 169 { P_XO, 0 },
168 [P_EDPLINK] = 4, 170 { P_EDPLINK, 4 },
169 [P_HDMIPLL] = 3, 171 { P_HDMIPLL, 3 },
170 [P_GPLL0] = 5, 172 { P_GPLL0, 5 },
171 [P_DSI0PLL_BYTE] = 1, 173 { P_DSI0PLL_BYTE, 1 },
172 [P_DSI1PLL_BYTE] = 2, 174 { P_DSI1PLL_BYTE, 2 }
173}; 175};
174 176
175static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = { 177static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-02 16:01:24 -0400