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authorJesse Barnes <jbarnes@nietzche.virtuousgeek.org>2008-02-19 18:39:58 -0500
committerDave Airlie <airlied@redhat.com>2008-02-19 18:39:58 -0500
commit0da3ea12fc2607beb67c2d54d0347807ea615573 (patch)
tree661fbfd1bd8e81481b45bdaebf72e1c1b00db470 /drivers/char/drm/i915_drv.c
parentca0b07d9a969c6561e5d6f69c861fbedf8d09e5d (diff)
drm/i915: save/restore interrupt state
On resume, if the interrupt state isn't restored correctly, we may end up with a flood of unexpected or ill-timed interrupts, which could cause the kernel to disable the interrupt or vblank events to happen at the wrong time. So save/restore them properly. Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'drivers/char/drm/i915_drv.c')
-rw-r--r--drivers/char/drm/i915_drv.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/char/drm/i915_drv.c b/drivers/char/drm/i915_drv.c
index 52e51033d32c..0f525ad536a4 100644
--- a/drivers/char/drm/i915_drv.c
+++ b/drivers/char/drm/i915_drv.c
@@ -276,6 +276,7 @@ static int i915_suspend(struct drm_device *dev)
276 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF); 276 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
277 } 277 }
278 i915_save_palette(dev, PIPE_A); 278 i915_save_palette(dev, PIPE_A);
279 dev_priv->savePIPEASTAT = I915_READ(I915REG_PIPEASTAT);
279 280
280 /* Pipe & plane B info */ 281 /* Pipe & plane B info */
281 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF); 282 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
@@ -303,6 +304,7 @@ static int i915_suspend(struct drm_device *dev)
303 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF); 304 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
304 } 305 }
305 i915_save_palette(dev, PIPE_B); 306 i915_save_palette(dev, PIPE_B);
307 dev_priv->savePIPEBSTAT = I915_READ(I915REG_PIPEBSTAT);
306 308
307 /* CRT state */ 309 /* CRT state */
308 dev_priv->saveADPA = I915_READ(ADPA); 310 dev_priv->saveADPA = I915_READ(ADPA);
@@ -329,6 +331,11 @@ static int i915_suspend(struct drm_device *dev)
329 dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2); 331 dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
330 dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL); 332 dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
331 333
334 /* Interrupt state */
335 dev_priv->saveIIR = I915_READ(I915REG_INT_IDENTITY_R);
336 dev_priv->saveIER = I915_READ(I915REG_INT_ENABLE_R);
337 dev_priv->saveIMR = I915_READ(I915REG_INT_MASK_R);
338
332 /* VGA state */ 339 /* VGA state */
333 dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0); 340 dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
334 dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1); 341 dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);