diff options
author | Jesse Barnes <jbarnes@nietzche.virtuousgeek.org> | 2008-02-19 18:39:58 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2008-02-19 18:39:58 -0500 |
commit | 0da3ea12fc2607beb67c2d54d0347807ea615573 (patch) | |
tree | 661fbfd1bd8e81481b45bdaebf72e1c1b00db470 | |
parent | ca0b07d9a969c6561e5d6f69c861fbedf8d09e5d (diff) |
drm/i915: save/restore interrupt state
On resume, if the interrupt state isn't restored correctly, we may end
up with a flood of unexpected or ill-timed interrupts, which could cause
the kernel to disable the interrupt or vblank events to happen at the
wrong time. So save/restore them properly.
Signed-off-by: Dave Airlie <airlied@linux.ie>
-rw-r--r-- | drivers/char/drm/i915_drv.c | 7 | ||||
-rw-r--r-- | drivers/char/drm/i915_drv.h | 5 |
2 files changed, 12 insertions, 0 deletions
diff --git a/drivers/char/drm/i915_drv.c b/drivers/char/drm/i915_drv.c index 52e51033d32c..0f525ad536a4 100644 --- a/drivers/char/drm/i915_drv.c +++ b/drivers/char/drm/i915_drv.c | |||
@@ -276,6 +276,7 @@ static int i915_suspend(struct drm_device *dev) | |||
276 | dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF); | 276 | dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF); |
277 | } | 277 | } |
278 | i915_save_palette(dev, PIPE_A); | 278 | i915_save_palette(dev, PIPE_A); |
279 | dev_priv->savePIPEASTAT = I915_READ(I915REG_PIPEASTAT); | ||
279 | 280 | ||
280 | /* Pipe & plane B info */ | 281 | /* Pipe & plane B info */ |
281 | dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF); | 282 | dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF); |
@@ -303,6 +304,7 @@ static int i915_suspend(struct drm_device *dev) | |||
303 | dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF); | 304 | dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF); |
304 | } | 305 | } |
305 | i915_save_palette(dev, PIPE_B); | 306 | i915_save_palette(dev, PIPE_B); |
307 | dev_priv->savePIPEBSTAT = I915_READ(I915REG_PIPEBSTAT); | ||
306 | 308 | ||
307 | /* CRT state */ | 309 | /* CRT state */ |
308 | dev_priv->saveADPA = I915_READ(ADPA); | 310 | dev_priv->saveADPA = I915_READ(ADPA); |
@@ -329,6 +331,11 @@ static int i915_suspend(struct drm_device *dev) | |||
329 | dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2); | 331 | dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2); |
330 | dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL); | 332 | dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL); |
331 | 333 | ||
334 | /* Interrupt state */ | ||
335 | dev_priv->saveIIR = I915_READ(I915REG_INT_IDENTITY_R); | ||
336 | dev_priv->saveIER = I915_READ(I915REG_INT_ENABLE_R); | ||
337 | dev_priv->saveIMR = I915_READ(I915REG_INT_MASK_R); | ||
338 | |||
332 | /* VGA state */ | 339 | /* VGA state */ |
333 | dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0); | 340 | dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0); |
334 | dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1); | 341 | dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1); |
diff --git a/drivers/char/drm/i915_drv.h b/drivers/char/drm/i915_drv.h index 786460d6b1a3..360f6600427b 100644 --- a/drivers/char/drm/i915_drv.h +++ b/drivers/char/drm/i915_drv.h | |||
@@ -134,6 +134,7 @@ typedef struct drm_i915_private { | |||
134 | u32 saveVBLANK_A; | 134 | u32 saveVBLANK_A; |
135 | u32 saveVSYNC_A; | 135 | u32 saveVSYNC_A; |
136 | u32 saveBCLRPAT_A; | 136 | u32 saveBCLRPAT_A; |
137 | u32 savePIPEASTAT; | ||
137 | u32 saveDSPASTRIDE; | 138 | u32 saveDSPASTRIDE; |
138 | u32 saveDSPASIZE; | 139 | u32 saveDSPASIZE; |
139 | u32 saveDSPAPOS; | 140 | u32 saveDSPAPOS; |
@@ -154,6 +155,7 @@ typedef struct drm_i915_private { | |||
154 | u32 saveVBLANK_B; | 155 | u32 saveVBLANK_B; |
155 | u32 saveVSYNC_B; | 156 | u32 saveVSYNC_B; |
156 | u32 saveBCLRPAT_B; | 157 | u32 saveBCLRPAT_B; |
158 | u32 savePIPEBSTAT; | ||
157 | u32 saveDSPBSTRIDE; | 159 | u32 saveDSPBSTRIDE; |
158 | u32 saveDSPBSIZE; | 160 | u32 saveDSPBSIZE; |
159 | u32 saveDSPBPOS; | 161 | u32 saveDSPBPOS; |
@@ -182,6 +184,9 @@ typedef struct drm_i915_private { | |||
182 | u32 saveFBC_LL_BASE; | 184 | u32 saveFBC_LL_BASE; |
183 | u32 saveFBC_CONTROL; | 185 | u32 saveFBC_CONTROL; |
184 | u32 saveFBC_CONTROL2; | 186 | u32 saveFBC_CONTROL2; |
187 | u32 saveIER; | ||
188 | u32 saveIIR; | ||
189 | u32 saveIMR; | ||
185 | u32 saveSWF0[16]; | 190 | u32 saveSWF0[16]; |
186 | u32 saveSWF1[16]; | 191 | u32 saveSWF1[16]; |
187 | u32 saveSWF2[3]; | 192 | u32 saveSWF2[3]; |