MIPS: Handle MIPS IV, V and R2 FPU instructions on MIPS R6 as well

MIPS R2 FPU instructions are also present in MIPS R6 so amend the
preprocessor definitions to take MIPS R6 into consideration.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>

2 files changed, 6 insertions, 5 deletions

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index e686131ff995..0d8208de9a3f 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -220,7 +220,8 @@
 #define cpu_has_mips_4_5_r      (cpu_has_mips_4 | cpu_has_mips_5_r)
 #define cpu_has_mips_5_r        (cpu_has_mips_5 | cpu_has_mips_r)
 
-#define cpu_has_mips_4_5_r2     (cpu_has_mips_4_5 | cpu_has_mips_r2)
+#define cpu_has_mips_4_5_r2_r6  (cpu_has_mips_4_5 | cpu_has_mips_r2 | \
+                                 cpu_has_mips_r6)
 
 #define cpu_has_mips32  (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6)
 #define cpu_has_mips64  (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6)
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 3c341b08d120..b30bf65c7d7d 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -1561,14 +1561,14 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                  * achieve full IEEE-754 accuracy - however this emulator does.
                  */
                 case frsqrt_op:
-                        if (!cpu_has_mips_4_5_r2)
+                        if (!cpu_has_mips_4_5_r2_r6)
                                 return SIGILL;
 
                         handler.u = fpemu_sp_rsqrt;
                         goto scopuop;
 
                 case frecip_op:
-                        if (!cpu_has_mips_4_5_r2)
+                        if (!cpu_has_mips_4_5_r2_r6)
                                 return SIGILL;
 
                         handler.u = fpemu_sp_recip;
@@ -1763,13 +1763,13 @@ copcsr:
                  * achieve full IEEE-754 accuracy - however this emulator does.
                  */
                 case frsqrt_op:
-                        if (!cpu_has_mips_4_5_r2)
+                        if (!cpu_has_mips_4_5_r2_r6)
                                 return SIGILL;
 
                         handler.u = fpemu_dp_rsqrt;
                         goto dcopuop;
                 case frecip_op:
-                        if (!cpu_has_mips_4_5_r2)
+                        if (!cpu_has_mips_4_5_r2_r6)
                                 return SIGILL;
 
                         handler.u = fpemu_dp_recip;